CN116819280A - Chip abnormality identification method and device based on ZPAT algorithm - Google Patents
Chip abnormality identification method and device based on ZPAT algorithm Download PDFInfo
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Abstract
The application provides a chip abnormality identification method and device based on a ZPAT algorithm, wherein the chip abnormality identification method based on the ZPAT algorithm comprises the following steps: obtaining target detection data corresponding to each target chip of a batch to be detected; aiming at target test key indexes of each target chip of the batch to be detected in different test stages, determining target test parameters corresponding to each target chip of the batch to be detected; determining a dynamic qualification rate proportion range of a specific target chip in a batch to be detected based on the target test parameters and a preset ZPAT algorithm; and determining the qualification rate of the specific target chip based on the dynamic qualification rate limit range and the labeling qualification rate ratio of the specific target chip so as to realize the completion of the abnormal identification of each target chip of the batch to be detected. The application shortens the test period and greatly improves the test efficiency and the test accuracy.
Description
Technical Field
The application relates to the technical field of chip detection, in particular to a method and a device for identifying abnormality of a chip based on a ZPAT algorithm.
Background
With the development of society and the progress of technology, more and more fields begin to use semiconductor materials, and in the field of chip testing, whether chips for mobile phones, notebooks and other devices or chips for automobiles, household appliances, heavy machinery and the like, the quality and qualification rate of semiconductor components are directly related to the overall quality of finished products and related electronic parts thereof, so how to detect the qualification rate of chips, and reducing various problems caused by chip failure are great problems facing each large chip manufacturer. The chip testing is complicated, and how to quickly and accurately determine the defect of the chip is a problem to be solved in various factories facing various related test projects.
The traditional judgment of whether the chip is abnormal mainly depends on an experienced operator to carry out data statistics processing and make sorting decisions in a post-processing mode, and the advantages and disadvantages of the chip on the wafer are judged in a mode of drawing a data distribution diagram for the data after statistics, so that abnormal products are removed, however, the determination mode of the abnormal chip for post-processing the data wastes a great amount of time and resources, the test period is prolonged, the test efficiency is reduced, and the test accuracy is greatly influenced.
Disclosure of Invention
Therefore, the application aims to provide the abnormality identification method and the abnormality identification device for the chip based on the ZPAT algorithm, which not only shortens the test period, but also greatly improves the test efficiency and the test accuracy.
The embodiment of the application provides a chip abnormality identification method based on a ZPAT algorithm, which comprises the following steps:
acquiring target detection data corresponding to each target chip of a batch to be detected, wherein each target detection data comprises horizontal plane position coordinate information of the target chip;
determining target test parameters corresponding to the target chips of the batch to be detected aiming at target test key points of the target chips of the batch to be detected in different test stages;
determining a dynamic qualification rate proportion range of the specific target chips in the batch to be detected based on the target test parameters and a preset ZPAT algorithm for any batch of specific target chips, wherein the specific target chips are used for representing target chips with the same horizontal plane position coordinate information in the batch to be detected, and any one of the target chips belongs to the specific target chips in any batch;
and determining the qualification rate of the specific target chip based on the dynamic qualification rate limit range and the labeling qualification rate ratio of the specific target chip so as to realize the completion of the abnormal identification of each target chip of the batch to be detected, wherein the labeling qualification rate is used for representing the original test qualification rate corresponding to the specific target chip in any batch.
Further, target detection data corresponding to each target chip of the batch to be detected is obtained by the following method:
acquiring initial detection data corresponding to each target chip of a batch to be detected;
and screening the initial detection data according to a preset test standard and a preset test item to determine target detection data corresponding to each target chip of the batch to be detected.
Further, the target test key indexes comprise target test programs, target test factory information and target test equipment information, and the target test parameters comprise target dispersion degree, target dispersion coefficient and target test center position.
Further, the determining, for any batch of specific target chips, the dynamic qualification rate ratio range of the specific target chips in the batch to be detected based on the target test parameters and a preset ZPAT algorithm includes:
and aiming at any batch of specific target chips, determining the dynamic qualification rate proportion range of any specific target chip in the batch to be detected according to the target dispersion degree, the target dispersion coefficient, the target test center position and a preset ZPAT algorithm.
Further, the formula for determining the dynamic qualification rate ratio range of any specific target chip in the batch to be detected is specifically as follows:
A＝Center ± Spread*Multiple；
wherein, A is used for representing dynamic qualification rate proportion range, center is used for representing target test Center position, space is used for representing target dispersion degree, multiple is used for representing target dispersion coefficient.
Further, the determining the qualification rate of the specific target chip based on the dynamic qualification rate limit range and the labeled qualification rate ratio of the specific target chip includes:
judging whether the marked qualification rate proportion is in the dynamic qualification rate proportion limit range or not according to the dynamic qualification rate proportion limit range and the marked qualification rate proportion of the specific target chip;
if yes, determining that the qualification rate of the specific target chip is qualified;
if not, determining that the qualification rate of the specific target chip is unqualified.
The embodiment of the application also provides an abnormality recognition device of the chip based on the ZPAT algorithm, which comprises:
the acquisition module is used for acquiring target detection data corresponding to each target chip of the batch to be detected, wherein each target detection data comprises horizontal plane position coordinate information of the target chip;
the first determining module is used for determining target test parameters corresponding to the target chips of the batch to be detected aiming at target test key indexes of the target chips of the batch to be detected in different test stages;
the second determining module is used for determining a dynamic qualification rate proportion range of the specific target chips in the batch to be detected based on the target test parameters and a preset ZPAT algorithm for the specific target chips in any batch, wherein the specific target chips are used for representing the target chips with the same horizontal plane position coordinate information in the batch to be detected, and any target chip belongs to the specific target chip in any batch;
and the third determining module is used for determining the qualification rate of the specific target chip based on the dynamic qualification rate limit range and the labeling qualification rate ratio of the specific target chip so as to realize the completion of the abnormal identification of each target chip of the batch to be detected, wherein the labeling qualification rate is used for representing the original test qualification rate corresponding to the specific target chip in any batch.
Further, the target test key indexes in the first determining module comprise target test programs, target test factory information and target test equipment information, and the target test parameters comprise target dispersion degree, target dispersion coefficient and target test center position.
The embodiment of the application also provides electronic equipment, which comprises: the device comprises a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, the processor and the memory are communicated through the bus when the electronic device runs, and the machine-readable instructions are executed by the processor to execute the steps of the abnormality identification method of the chip based on the ZPAT algorithm.
The embodiment of the application also provides a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to execute the steps of the anomaly identification method of the chip based on the ZPAT algorithm.
Compared with the chip anomaly identification method in the prior art, the chip anomaly identification method and device based on the ZPAT algorithm provided by the embodiment of the application have the advantages that the target test key indexes of all target chips of the batch to be detected in different test stages are aimed at, the target test parameters corresponding to all target chips of the batch to be detected are determined, the dynamic qualification rate proportion range of the specific target chips in the batch to be detected is determined based on the target test parameters and the preset ZPAT algorithm aiming at any batch of specific target chips, and the qualification rate of the specific target chips is determined based on the dynamic qualification rate limit range and the labeling qualification rate proportion of the specific target chips so as to realize the anomaly identification of all target chips of the batch to be detected.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 shows one of flowcharts of a method for identifying anomalies in a chip based on a ZPAT algorithm according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a specific target chip in a method for identifying an abnormality of a chip based on ZPAT algorithm according to an embodiment of the present application;
FIG. 3 is a second flowchart of a method for identifying anomalies in a chip based on the ZPAT algorithm according to an embodiment of the present application;
fig. 4 shows a schematic structural diagram of an abnormality recognition device of a chip based on ZPAT algorithm according to an embodiment of the present application;
fig. 5 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
In the figure:
400-abnormality recognition device of the chip based on ZPAT algorithm; 410-an acquisition module; 420-a first determination module; 430-a second determination module; 440-a third determination module; 500-an electronic device; 510-a processor; 520-memory; 530-bus.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments of the present application, every other embodiment obtained by a person skilled in the art without making any inventive effort falls within the scope of protection of the present application.
First, an application scenario to which the present application is applicable will be described. The application can be applied to the technical field of chip detection.
The research shows that the traditional judgment on whether the chip is abnormal mainly depends on an experienced operator to perform data statistics processing and make sorting decisions in a post-processing mode, and the quality of the chip on the wafer is judged in a mode of drawing a data distribution diagram on the data after statistics, so that abnormal products are removed, however, the determination mode of the abnormal chip for post-processing the data wastes a great amount of time and resources, not only prolongs the test period and reduces the test efficiency, but also greatly influences the test accuracy.
In the prior art, a general part average test (Part Average Testing, PAT) method is generally adopted, a PAT limit threshold is set for a test standard of screening conditions through calculation of a correlation algorithm by testing a plurality of batches and collecting data, the PAT limit threshold is used as a specification lower limit (Lower Specification Limit, LSL) and a specification upper limit (Upper Specification Limit, USL), a specification lower limit (Lower Specification Limit, LSL) and a specification upper limit (Upper Specification Limit, USL) are set in a test program, any test result outside the PAT limit threshold is regarded as unqualified, and the unqualified test result is removed from the total number of parts, so that the quality and reliability of related components are improved, and the overall qualification rate is improved.
In the prior art, the abnormal chip is usually determined by adopting the static PAT, so that a great amount of time and resources are wasted, the test period is prolonged, the test efficiency is reduced, and the test accuracy is greatly influenced.
Based on the method and the device, the embodiment of the application provides the chip abnormality identification method and the device based on the ZPAT algorithm, which shortens the test period and greatly improves the test efficiency and the test accuracy.
Referring to fig. 1, fig. 1 is a flowchart of a method for identifying an abnormality of a chip based on ZPAT algorithm according to an embodiment of the present application. As shown in fig. 1, the method for identifying the abnormality of the chip based on the ZPAT algorithm provided by the embodiment of the application comprises the following steps:
s101, obtaining target detection data corresponding to each target chip of a batch to be detected, wherein each target detection data comprises horizontal plane position coordinate information of the target chip.
In this step, the target detection data in the embodiment provided by the application are various types of test data of each target chip of the batch to be detected in different test stages, wherein the data types in the target detection data include, but are not limited to, horizontal plane position coordinate information of the target chip.
Thus, the anomaly identification method of the chip based on the ZPAT algorithm in the embodiment provided by the application is an advanced version of dynamic PAT in nature.
The ZPAT algorithm is a dynamic PAT applied to ATE to improve the quality and reliability of components.
The dynamic PAT refers to that each target chip of a batch to be detected is tested, target detection data are counted, a new criterion suitable for the current batch to be detected is selected according to the result, and then mass production testing is carried out, so that each target chip of the batch to be detected can be dynamically screened and classified during the mass production testing.
S102, determining target test parameters corresponding to the target chips of the batch to be detected according to target test key indexes of the target chips of the batch to be detected in different test stages.
In this step, before determining the target test key indexes of each target chip in different test stages, the embodiment of the application firstly selects test data corresponding to some sample batches of chips to perform test parameter configuration of verification test (test run), then performs parameter adjustment based on the test run result, and then determines the adjusted parameters as target test parameters.
And then determining target test parameters according to the test running result and target test key indexes in different test stages, and finally using the adjusted parameters in the identification of each target chip to realize the real-time monitoring and control of each target chip in the detection batch.
In the above, the embodiment provided by the application supports the resetting of the target test parameters, and can simulate the influence condition of different target test parameters on the abnormal recognition of the target chip in real time under the condition that the authenticity of the target detection data of the target chip is not influenced, so that the flexibility and the instantaneity are improved.
Optionally, the target test key indicator includes a target test program, target test factory information and target test equipment information, and the target test parameter includes a target dispersion degree, a target dispersion coefficient and a target test center position.
The target test center position supports indexes such as a calculated mean value, a median value and the like; the target dispersion degree supports the indexes such as standard deviation, reinforced standard deviation and quartile range; the target dispersion coefficient in the embodiment provided by the application is subjected to self-defined dynamic adjustment according to the running condition/experience value.
S103, determining a dynamic qualification rate proportion range of the specific target chips in the batch to be detected based on the target test parameters and a preset ZPAT algorithm for the specific target chips in any batch, wherein the specific target chips are used for representing the target chips with the same horizontal plane position coordinate information in the batch to be detected, and any target chip belongs to the specific target chip in any batch.
In this step, since the specific target chip is used to represent the target chips with the same horizontal plane position coordinate information in the batch to be detected, each target chip in the batch to be detected may be attributed to a specific target chip in a certain batch, refer to fig. 2, fig. 2 shows a schematic structural diagram of a specific target chip in the method for identifying a chip abnormality based on the ZPAT algorithm provided in the embodiment of the present application, and as shown in fig. 2, the ZPAT algorithm may implement comparison in a similar vertical direction for a specific target chip in a certain batch.
The method for identifying the abnormality of the chip based on the ZPAT algorithm in the embodiment provided by the application is to count the test difference of the Z coordinates of each target chip of the batch to be detected.
Optionally, the step S103 includes the following substeps:
in the substep 1031, for any batch of specific target chips, determining a dynamic qualification rate ratio range of any specific target chip in the batch to be detected according to the target dispersion degree, the target dispersion coefficient, the target test center position and a preset ZPAT algorithm.
In the step, a formula for determining the dynamic qualification rate proportion range of any specific target chip in the batch to be detected is specifically as follows:
A＝Center±Spread*Multiple；
wherein, A is used for representing dynamic qualification rate proportion range, center is used for representing target test Center position, space is used for representing target dispersion degree, multiple is used for representing target dispersion coefficient.
S104, determining the qualification rate of the specific target chip based on the dynamic qualification rate limit range and the labeling qualification rate ratio of the specific target chip so as to realize the completion of the abnormal identification of each target chip of the batch to be detected, wherein the labeling qualification rate is used for representing the original test qualification rate corresponding to the specific target chip in any batch.
In the step, when target detection data corresponding to each target chip of a batch to be detected is obtained, namely, original test qualification rates (marked qualification rates) corresponding to specific target chips in different batches are marked at the same time, at the moment, a dynamic qualification rate proportion limit range calculated according to the formula is compared with the marked qualification rate proportion of the specific target chips, and finally, the qualification rate of the target chips and whether the target chips are abnormal are determined.
The dynamic qualification rate proportion range of the specific target chip is used for representing the ratio range of the specific target chip which is still qualified in the vertical direction under the condition that the horizontal plane position coordinate information is the same.
Optionally, the step S104 includes the following substeps:
and step 1041, judging whether the marked qualification rate is within the dynamic qualification rate limit range according to the dynamic qualification rate limit range and the marked qualification rate of the specific target chip.
In this step, the dynamic qualification rate ratio limit range in the embodiment provided by the present application includes a dynamic qualification rate ratio upper limit and a dynamic qualification rate ratio lower limit, and the dynamic qualification rate ratio upper limit may specifically be:
A1＝Center+Spread*Multiple；
the dynamic qualification rate ratio offline may be specifically:
A2＝Center-Spread*Multiple；
the embodiment provided by the application can specifically judge whether the labeling qualification rate ratio of the specific target chip is greater than A=center-space Multiple or less than center+space Multiple.
And step 1042, if yes, determining that the qualification rate of the specific target chip is qualified.
In this step, if the labeled yield ratio of the specific target chip is greater than a=center-space Multiple or less than center+space Multiple, the yield of the specific target chip is determined to be acceptable.
Sub-step 1043, if not, determining that the qualification rate of the specific target chip is unqualified.
In the step, if the labeling qualification rate ratio of the specific target chip is not greater than a=center-space Multiple or not less than center+space Multiple, determining that the qualification rate of the specific target chip is unqualified, then applying the qualification rate of the specific target chip to each target wafer, and marking the target chip of each target wafer to realize the redistribution of the target chip state.
Compared with the chip anomaly identification method in the prior art, the chip anomaly identification method based on the ZPAT algorithm provided by the embodiment of the application has the advantages that the target test key indexes of all target chips of the batch to be detected in different test stages are aimed at, the target test parameters corresponding to all target chips of the batch to be detected are determined, the dynamic qualification rate proportion range of the specific target chips in the batch to be detected is determined based on the target test parameters and the preset ZPAT algorithm aiming at any batch specific target chips, and the qualification rate of the specific target chips is determined based on the dynamic qualification rate proportion limit range and the labeling qualification rate proportion of the specific target chips, so that the anomaly identification of all target chips of the batch to be detected is realized.
Referring to fig. 3, fig. 3 is a flowchart illustrating a second flowchart of a method for identifying an abnormality of a chip based on ZPAT algorithm according to an embodiment of the present application. As shown in fig. 3, the method for identifying the abnormality of the chip based on the ZPAT algorithm provided by the embodiment of the application comprises the following steps:
s301, initial detection data corresponding to each target chip of the batch to be detected are obtained.
Here, the source of the initial Test Data corresponding to each target chip of the lot to be tested in the embodiment of the present application may be specifically but not limited to the original Data (Test Raw Data) and the MES Data (MES Data).
S302, screening the initial detection data according to a preset test standard and a preset test item, and determining target detection data corresponding to each target chip of the batch to be detected.
In this step, after initial detection data corresponding to each target chip of the batch to be detected is determined, virtual data set is first constructed according to a preset test standard (a test point of interest) and a preset test item, and target detection data corresponding to each target chip of the batch to be detected is determined.
Here, the preset test items in the embodiment provided by the present application may also include the target test program, the target test factory information, and the target test equipment information, so as to perform targeted screening on the initial detection data.
The plurality of VDSs are configured according to different preset test items, and only the corresponding VDS is selected from the preset test standards.
S303, determining target test parameters corresponding to the target chips of the batch to be detected according to target test key points of the target chips of the batch to be detected in different test stages.
S304, determining a dynamic qualification rate proportion range of the specific target chips in the batch to be detected based on the target test parameters and a preset ZPAT algorithm for the specific target chips in any batch, wherein the specific target chips are used for representing the target chips with the same horizontal plane position coordinate information in the batch to be detected, and any target chip belongs to the specific target chip in any batch.
S305, determining the qualification rate of the specific target chip based on the dynamic qualification rate limit range and the labeling qualification rate ratio of the specific target chip so as to realize the completion of the abnormal identification of each target chip of the batch to be detected, wherein the labeling qualification rate is used for representing the original test qualification rate corresponding to the specific target chip in any batch.
The descriptions of S303 to S305 may refer to the descriptions of S102 to S104, and the same technical effects can be achieved, which will not be described in detail.
Compared with the chip anomaly identification method in the prior art, the chip anomaly identification method based on the ZPAT algorithm provided by the embodiment of the application has the advantages that the target test key indexes of all target chips of the batch to be detected in different test stages are aimed at, the target test parameters corresponding to all target chips of the batch to be detected are determined, the dynamic qualification rate proportion range of the specific target chips in the batch to be detected is determined based on the target test parameters and the preset ZPAT algorithm aiming at any batch specific target chips, and the qualification rate of the specific target chips is determined based on the dynamic qualification rate proportion limit range and the labeling qualification rate proportion of the specific target chips, so that the anomaly identification of all target chips of the batch to be detected is realized.
Referring to fig. 4, fig. 4 is a schematic structural diagram of abnormality recognition of a chip based on ZPAT algorithm according to an embodiment of the present application. As shown in fig. 4, the abnormality recognition device 400 of the ZPAT algorithm-based chip includes:
the obtaining module 410 is configured to obtain target detection data corresponding to each target chip of the batch to be detected, where each target detection data includes horizontal plane position coordinate information of the target chip.
The first determining module 420 is configured to determine, for target test key indicators of each target chip of the batch to be tested in different test phases, target test parameters corresponding to each target chip of the batch to be tested.
Optionally, the first determining module 420 obtains the target detection data corresponding to each target chip of the batch to be detected by:
initial detection data corresponding to each target chip of the batch to be detected are obtained.
And screening the initial detection data according to a preset test standard and a preset test item to determine target detection data corresponding to each target chip of the batch to be detected.
Optionally, the target test key indicators in the first determining module 420 include a target test program, target test factory information and target test equipment information, and the target test parameters include a target dispersion degree, a target dispersion coefficient and a target test center position.
The second determining module 430 is configured to determine, for any lot of specific target chips, a dynamic qualification rate ratio range of the specific target chips in the lot to be detected based on the target test parameters and a preset ZPAT algorithm, where the specific target chips are used to characterize target chips with the same horizontal plane position coordinate information in the lot to be detected, and any one of the target chips belongs to the specific target chips in any lot.
Optionally, the second determining module 430 is specifically configured to:
and aiming at any batch of specific target chips, determining the dynamic qualification rate proportion range of any specific target chip in the batch to be detected according to the target dispersion degree, the target dispersion coefficient, the target test center position and a preset ZPAT algorithm.
Optionally, the formula for determining the dynamic qualification rate ratio range of any specific target chip in the batch to be detected is specifically:
A＝Center±Spread*Multiple；
wherein, A is used for representing dynamic qualification rate proportion range, center is used for representing target test Center position, space is used for representing target dispersion degree, multiple is used for representing target dispersion coefficient.
And a third determining module 440, configured to determine a qualification rate of the specific target chip based on the dynamic qualification rate limit range and a labeled qualification rate ratio of the specific target chip, so as to implement the completion of the anomaly identification of each target chip of the batch to be detected, where the labeled qualification rate is used to characterize the original test qualification rate corresponding to the specific target chip in any batch.
Optionally, the third determining module 440 is specifically configured to:
and judging whether the marked qualification rate proportion is within the dynamic qualification rate proportion limit range according to the dynamic qualification rate proportion limit range and the marked qualification rate proportion of the specific target chip.
If yes, determining that the qualification rate of the specific target chip is qualified.
If not, determining that the qualification rate of the specific target chip is unqualified.
Compared with the chip anomaly identification device in the prior art, the chip anomaly identification device 400 based on the ZPAT algorithm provided by the embodiment of the application determines the target test parameters corresponding to each target chip of the batch to be detected by aiming at the target test key indexes of each target chip of the batch to be detected in different test stages, determines the dynamic qualification rate proportion range of the specific target chip in the batch to be detected based on the target test parameters and the preset ZPAT algorithm and determines the qualification rate of the specific target chip based on the dynamic qualification rate proportion limit range and the labeling qualification rate proportion of the specific target chip, so as to realize the anomaly identification of each target chip of the batch to be detected.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the application. As shown in fig. 5, the electronic device 500 includes a processor 510, a memory 520, and a bus 530.
The memory 520 stores machine-readable instructions executable by the processor 510, and when the electronic device 500 is running, the processor 510 communicates with the memory 520 through the bus 530, and when the machine-readable instructions are executed by the processor 510, the steps of the method for identifying an abnormality of a chip based on ZPAT algorithm in the method embodiments shown in fig. 1 and fig. 3 may be executed, and detailed implementation manners may refer to method embodiments and are not repeated herein.
The embodiment of the present application further provides a computer readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the method for identifying an abnormality of a chip based on ZPAT algorithm in the method embodiments shown in fig. 1 and fig. 3 may be executed, and specific implementation manners may refer to the method embodiments and will not be repeated herein.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Finally, it should be noted that: the above examples are only specific embodiments of the present application, and are not intended to limit the scope of the present application, but it should be understood by those skilled in the art that the present application is not limited thereto, and that the present application is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. The chip abnormality identification method based on the ZPAT algorithm is characterized by comprising the following steps of:
acquiring target detection data corresponding to each target chip of a batch to be detected, wherein each target detection data comprises horizontal plane position coordinate information of the target chip;
determining target test parameters corresponding to the target chips of the batch to be detected aiming at target test key points of the target chips of the batch to be detected in different test stages;
determining a dynamic qualification rate proportion range of the specific target chips in the batch to be detected based on the target test parameters and a preset ZPAT algorithm for any batch of specific target chips, wherein the specific target chips are used for representing target chips with the same horizontal plane position coordinate information in the batch to be detected, and any one of the target chips belongs to the specific target chips in any batch;
and determining the qualification rate of the specific target chip based on the dynamic qualification rate limit range and the labeling qualification rate ratio of the specific target chip so as to realize the completion of the abnormal identification of each target chip of the batch to be detected, wherein the labeling qualification rate is used for representing the original test qualification rate corresponding to the specific target chip in any batch.
2. The abnormality identification method of chips based on ZPAT algorithm according to claim 1, wherein the target detection data corresponding to each target chip of the lot to be detected is obtained by:
acquiring initial detection data corresponding to each target chip of a batch to be detected;
and screening the initial detection data according to a preset test standard and a preset test item to determine target detection data corresponding to each target chip of the batch to be detected.
3. The method for identifying anomalies on a chip based on the ZPAT algorithm according to claim 1, wherein the target test key indicators comprise a target test program, target test factory information and target test equipment information, and the target test parameters comprise a target dispersion degree, a target dispersion coefficient and a target test center position.
4. The method for identifying the abnormality of the chips based on the ZPAT algorithm according to claim 3, wherein the determining the dynamic qualification rate ratio range of the specific target chips in the batch to be detected based on the target test parameters and the preset ZPAT algorithm for any batch of specific target chips comprises:
and aiming at any batch of specific target chips, determining the dynamic qualification rate proportion range of any specific target chip in the batch to be detected according to the target dispersion degree, the target dispersion coefficient, the target test center position and a preset ZPAT algorithm.
5. The method for identifying anomalies in chips based on ZPAT algorithm according to claim 4, wherein the formula for determining the dynamic qualification rate ratio range of any specific target chip in the batch to be tested is specifically:
A＝Center ± Spread*Multiple；
wherein, A is used for representing dynamic qualification rate proportion range, center is used for representing target test Center position, space is used for representing target dispersion degree, multiple is used for representing target dispersion coefficient.
6. The ZPAT algorithm-based chip anomaly identification method according to claim 1, wherein the determining the yield of the specific target chip based on the dynamic yield ratio limit range and the labeled yield ratio of the specific target chip comprises:
judging whether the marked qualification rate proportion is in the dynamic qualification rate proportion limit range or not according to the dynamic qualification rate proportion limit range and the marked qualification rate proportion of the specific target chip;
if yes, determining that the qualification rate of the specific target chip is qualified;
if not, determining that the qualification rate of the specific target chip is unqualified.
7. An abnormality recognition device of a ZPAT algorithm-based chip, characterized in that the abnormality recognition device of a ZPAT algorithm-based chip includes:
the acquisition module is used for acquiring target detection data corresponding to each target chip of the batch to be detected, wherein each target detection data comprises horizontal plane position coordinate information of the target chip;
the first determining module is used for determining target test parameters corresponding to the target chips of the batch to be detected aiming at target test key indexes of the target chips of the batch to be detected in different test stages;
the second determining module is used for determining a dynamic qualification rate proportion range of the specific target chips in the batch to be detected based on the target test parameters and a preset ZPAT algorithm for the specific target chips in any batch, wherein the specific target chips are used for representing the target chips with the same horizontal plane position coordinate information in the batch to be detected, and any target chip belongs to the specific target chip in any batch;
and the third determining module is used for determining the qualification rate of the specific target chip based on the dynamic qualification rate limit range and the labeling qualification rate ratio of the specific target chip so as to realize the completion of the abnormal identification of each target chip of the batch to be detected, wherein the labeling qualification rate is used for representing the original test qualification rate corresponding to the specific target chip in any batch.
8. The ZPAT algorithm-based chip anomaly identification device according to claim 7, wherein the target test key indicators in the first determination module include a target test program, target test factory information, and target test equipment information, and the target test parameters include a target dispersion degree, a target dispersion coefficient, and a target test center position.
9. An electronic device, comprising: a processor, a memory and a bus, the memory storing machine readable instructions executable by the processor, the processor and the memory communicating over the bus when the electronic device is running, the machine readable instructions when executed by the processor performing the steps of the ZPAT algorithm-based chip anomaly identification method according to any one of claims 1 to 6.
10. A computer-readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, performs the steps of the method for identifying anomalies of a chip based on the ZPAT algorithm as claimed in any one of the preceding claims 1 to 6.
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