CN116819278A

CN116819278A - Super capacitor charging circuit testing method, device, equipment, computer and medium

Info

Publication number: CN116819278A
Application number: CN202310728806.1A
Authority: CN
Inventors: 吕泽华
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-06-19
Filing date: 2023-06-19
Publication date: 2023-09-29

Abstract

The invention provides a method, a device, equipment, a computer and a medium for testing a super capacitor charging circuit, wherein the method comprises the following steps: testing a first target signal under a first test scene to obtain first test data; acquiring a first test result of the target super capacitor charging circuit in a first test scene based on the first test data; the target super capacitor is converted from a power-off state to a power-on state in a first test scene, and the power-on state is kept for a first preset time period; the first test data includes actual values of a first target parameter of the first target signal in a first test scenario. The method, the device, the equipment, the computer and the medium for testing the super-capacitor charging circuit can test the working state of the super-capacitor charging circuit in the charging stage more comprehensively and accurately, and can provide more accurate and more comprehensive data support for the design and improvement of the super-capacitor charging circuit.

Description

Super capacitor charging circuit testing method, device, equipment, computer and medium

Technical Field

The invention relates to the technical field of electronic information, in particular to a method, a device, equipment, a computer and a medium for testing a super capacitor charging circuit.

Background

The super capacitor charging circuit is a backup power supply widely applied to various electronic devices, and can provide power-off protection for key components in the electronic devices under the condition that the electronic devices are abnormally powered off. Therefore, the performance of the super capacitor charging circuit has important significance for guaranteeing the high availability and stability of the electronic equipment.

According to the testing method of the super-capacitor charging circuit in the prior art, whether the super-capacitor charging circuit triggers power-off protection under the condition that abnormal power-off occurs to the electronic equipment can be judged only by checking the operation log of the electronic equipment, the operation state of the super-capacitor charging circuit is difficult to comprehensively test, and further data support is difficult to provide for design and improvement of the super-capacitor charging circuit. Therefore, how to more fully test the operation state of the super capacitor charging circuit is a technical problem to be solved in the field.

Disclosure of Invention

The invention provides a method, a device, equipment, a computer and a medium for testing a super-capacitor charging circuit, which are used for solving the defect that the operation state of the super-capacitor charging circuit is difficult to comprehensively test in the prior art and realizing the more comprehensive test on the operation state of the super-capacitor charging circuit.

The invention provides a testing method of a super capacitor charging circuit, which is used for testing a target super capacitor charging circuit; the target super capacitor charging circuit comprises a protection circuit, a first MOS tube, a power supply circuit, a driving circuit, a second MOS tube, a monitoring circuit and a super capacitor; the source electrode of the first MOS tube is connected with the first end of the protection circuit, the grid electrode of the first MOS tube is connected with the controller, and the drain electrode of the first MOS tube is respectively connected with the first end of the power supply circuit and the first end of the driving circuit; the grid electrode of the second MOS tube is connected with the second end of the driving circuit, the source electrode of the second MOS tube is connected with the second end of the power supply circuit, and the drain electrode of the second MOS tube is connected with the first end of the monitoring circuit; the second end of the monitoring circuit is connected with the super capacitor;

the method comprises the following steps:

testing a first target signal in a first test scene to obtain first test data;

acquiring a first test result of the target super capacitor charging circuit in the first test scene based on the first test data;

the target super capacitor is converted from a power-off state to a power-on state in the first test scene, and the power-on state is kept for a first preset time period;

The first test data comprises actual values of first target parameters of the first target signal in the first test scene;

the first target signal includes at least two of a first signal, a second signal, and a third signal; the first signal is a signal input to the grid electrode of the first MOS tube by the controller; the second signal is a signal input to the grid electrode of the second MOS tube from the second end of the driving circuit; the third signal is a signal input to the first end of the protection circuit from the drain electrode of the second MOS tube; the first target parameter includes an on time.

According to the method for testing the super capacitor charging circuit provided by the invention, the first test result of the target super capacitor charging circuit in the first test scene is obtained based on the first test data, and the method comprises the following steps:

based on the first test data, judging whether the type of at least one of the first MOS tube, the second MOS tube and the components in the driving circuit is proper, and determining the judging result as a first test result of the target super capacitor charging circuit in the first test scene.

According to the testing method for the super capacitor charging circuit provided by the invention, the step of judging whether the type selection of at least one of the first MOS tube, the second MOS tube and the components in the driving circuit is proper based on the first testing data comprises the following steps:

under the condition that the first target signal comprises the first signal and the second signal, based on the difference value between the actual value of the on time of the second signal in the first test scene and the actual value of the on time of the first signal in the first test scene, judging whether the types of the components in the first MOS tube and the driving circuit are proper or not,

under the condition that the first target signal comprises the second signal and the third signal, based on the difference value between the actual value of the opening time of the third signal in the first test scene and the actual value of the opening time of the second signal in the first test scene, judging whether the type selection of the second MOS tube is proper or not,

and under the condition that the first target signal only comprises the first signal and the third signal, judging whether the types of the first MOS tube, the second MOS tube and the components in the driving circuit are proper or not based on the difference value between the actual value of the opening time of the third signal in the first test scene and the actual value of the opening time of the first signal in the first test scene.

According to the testing method for the super capacitor charging circuit provided by the invention, after judging whether the types of the components in the first MOS tube and the driving circuit are proper or not based on the difference value between the actual value of the on time of the second signal in the first testing scene and the actual value of the on time of the first signal in the first testing scene, the method further comprises:

under the condition that the selection of components in the first MOS tube and/or the driving circuit is not proper, determining a target value of a third target parameter of the first MOS tube based on the first test data;

determining whether the type selection of the first MOS tube is proper or not based on the target value of the third target parameter of the first MOS tube and the actual value of the third target parameter of the first MOS tube;

determining that the type of the component in the driving circuit is unsuitable under the condition that the type of the first MOS tube is determined to be suitable, and determining the type of the MOS tube used for replacing the first MOS tube based on the actual value of the third target parameter of the first MOS tube under the condition that the type of the first MOS tube is determined to be unsuitable;

wherein the third target parameter includes at least one of gate charge, threshold voltage, on-delay time, and off-delay time.

According to the testing method for the super capacitor charging circuit provided by the invention, after judging whether the second MOS tube is suitable for the type selection based on the difference value between the actual value of the on time of the third signal in the first testing scene and the actual value of the on time of the second signal in the first testing scene, the method further comprises:

under the condition that the second MOS tube is not proper in type selection, determining a target value of a third target parameter of the second MOS tube based on the first test data;

determining a model of the MOS tube for replacing the second MOS tube based on a target value of a third target parameter of the second MOS tube;

and determining the working state grade of the target super capacitor charging circuit in a first test scene based on at least one of the difference value between the actual value of the second signal on time and the actual value of the first signal on time, the difference value between the actual value of the third signal on time and the actual value of the first signal on time and the difference value between the actual value of the third signal on time and the actual value of the second signal on time, and taking the working state grade as a first test result of the target super capacitor charging circuit in the first test scene.

The method for testing the super capacitor charging circuit provided by the invention further comprises the following steps:

under a second test scene, testing a second target signal and the super capacitor to obtain second test data;

based on the second test data, a test result of the target super capacitor charging circuit in a second test scene is obtained;

the target component in the second test scene is converted from a power-on state to a power-off state, and the power-off state is kept for a second preset time period; the target component is provided with power-off protection by the target super capacitor charging circuit;

the second test data comprise actual values of a second target parameter of the second target signal in the second test scene and actual values of a third target parameter of the supercapacitor in the second test scene;

the second target signal comprises a circuit switching signal and a complete machine power-down signal, and the circuit switching signal and the complete machine power-down signal are output by the target component; the second target parameter includes a level; the third target parameter includes voltage and current.

Under the first test scene, testing the second target signal and the super capacitor to obtain third test data;

acquiring a second test result of the target super capacitor charging circuit in the first test scene based on the third test data;

the third test data comprise an actual value of a second target parameter of the second target signal in the first test scene and an actual value of a third target parameter of the supercapacitor in the first test scene.

According to the method for testing the super capacitor charging circuit provided by the invention, after a first test result of the target super capacitor charging circuit in the first test scene, a second test result of the target super capacitor charging circuit in the first test scene and a test result of the target super capacitor charging circuit in the second test scene are obtained, the method further comprises:

and combining a first test result of the target super-capacitor charging circuit in the first test scene, acquiring a second test result of the target super-capacitor charging circuit in the first test scene and a test result of the target super-capacitor charging circuit in the second test scene to acquire a test result of the target super-capacitor charging circuit.

The invention also provides a super capacitor charging circuit testing device which is used for testing the target super capacitor charging circuit; the target super capacitor charging circuit comprises a protection circuit, a first MOS tube, a power supply circuit, a driving circuit, a second MOS tube, a monitoring circuit and a super capacitor; the source electrode of the first MOS tube is connected with the first end of the protection circuit, the grid electrode of the first MOS tube is connected with the controller, and the drain electrode of the first MOS tube is respectively connected with the first end of the power supply circuit and the first end of the driving circuit; the grid electrode of the second MOS tube is connected with the second end of the driving circuit, the source electrode of the second MOS tube is connected with the second end of the power supply circuit, and the drain electrode of the second MOS tube is connected with the first end of the monitoring circuit; the second end of the monitoring circuit is connected with the super capacitor;

the device comprises:

the data acquisition module is used for testing the first target signal under a first test scene to acquire the first test data;

the circuit testing module is used for acquiring a first testing result of the target super capacitor charging circuit in the first testing scene based on the first testing data;

The invention also provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the super capacitor charging circuit testing method according to any one of the above when executing the program.

The invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method of testing a supercapacitor charge circuit as described in any one of the above.

The invention also provides a computer program product comprising a computer program which when executed by a processor implements a method of testing a supercapacitor charge circuit as described in any one of the above.

According to the method, the device, the equipment, the computer and the medium for testing the super-capacitor charging circuit, the first target signal is tested in the first test scene, after the first test data are obtained, the test result of the target super-capacitor charging circuit in the first test scene is obtained based on the first test data, the working state of the super-capacitor charging circuit in the charging stage can be tested more comprehensively and accurately, and more accurate and more comprehensive data support can be provided for design and improvement of the super-capacitor charging circuit.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a circuit diagram of a target super-capacitor charging circuit in a super-capacitor charging circuit test method provided by the invention;

FIG. 2 is a schematic flow chart of a testing method of a super capacitor charging circuit according to the present invention;

FIG. 3 is a second flow chart of the testing method of the super capacitor charging circuit according to the present invention;

fig. 4 is a schematic structural diagram of a testing device for a super capacitor charging circuit provided by the invention;

fig. 5 is a schematic structural diagram of an electronic device provided by the present invention.

Reference numerals:

101: a target super capacitor charging circuit; 102: a protection circuit; 103: a power supply circuit; 104: a driving circuit; 105: a monitoring circuit; 106: a super capacitor; 107: a first end of the protection circuit; 108: a controller; 109: a first end of the charging circuit; 110: a first end of the driving circuit; 111: a second end of the driving circuit; 112: a second terminal of the charging circuit; 113: a first end of the monitoring circuit; 114: a second end of the monitoring circuit; 115: a current monitoring circuit; 116: a health detection circuit; 117: a first MOS tube; 118: a second MOS tube; 119: a first diode; 120: a first resistor; 121: a first capacitor; 122: an inductance; 123: a second diode; 124: a second resistor; 125: and a second capacitor.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

It should be noted that, the redundant array of independent disks (Redundant Array of Independent Disks, RAID) is a technology of combining multiple independent hard disks (physical hard disks) in different manners to form a hard disk group (logical hard disk), so as to provide higher storage performance than a single hard disk and provide data backup, and the RAID card can store data in an unstable environment.

Under the condition that abnormal power failure occurs to a RAID card in the electronic equipment, a backup power supply system in the electronic equipment can supply power to the RAID card, so that the RAID card can brush dirty data (data which is transmitted to the RAID card when power is cut off and is not written into a hard disk) generated after abnormal power failure into a flash memory chip in the electronic equipment for storage.

The backup power system in the electronic device may include a super capacitor charging circuit and a DC/DC conversion chip (Direct Current Direct Current Converter DC/DC conversion chip), among others. The super capacitor charging circuit has the storage capacity (typically on the order of tens of farads) required to support one complete data transfer. The DC/DC conversion chip is responsible for obtaining the output of the super capacitor charging circuit and providing a constant voltage for the data recovery electronic circuit. The data transfer must be completed before the voltage across the supercapacitor charge circuit drops to the minimum input operating voltage (UVLO) of the DC/DC converter chip.

Therefore, the storage capacity of the super capacitor charging circuit needs to be large enough, and it is generally required to be able to satisfy the power-off protection 2 to 3 times in connection with the protection. The performance of the super capacitor charging circuit has important significance for guaranteeing high availability and stability of electronic equipment.

However, the test method of the super capacitor charging circuit in the related art has fewer measured signals, the obtained state information of the super capacitor charging circuit is limited, and only whether the super capacitor charging circuit triggers power-off protection under the condition that the electronic equipment fails abnormally can be judged, the operation state of the super capacitor charging circuit is difficult to comprehensively test, and further whether the circuit design of the super capacitor charging circuit has enough margin is difficult to judge.

In contrast, the invention provides a testing method for a super capacitor charging circuit. The testing method of the super capacitor charging circuit can comprehensively detect the working states of the super capacitor charging circuit in the charging stage and the power-off protection stage, can more comprehensively and accurately acquire the testing result of the working states of the super capacitor charging circuit in each stage, and can provide more accurate and comprehensive data support for the design and improvement of the super capacitor charging circuit.

Fig. 1 is a circuit diagram of a target super capacitor charging circuit in the test method of the super capacitor charging circuit provided by the invention. As shown in fig. 1, the target super capacitor charging circuit 101 includes a protection circuit 102, a first MOS transistor 117, a power supply circuit 103, a driving circuit 104, a second MOS transistor 118, a monitoring circuit 105, and a super capacitor 106; the source electrode of the first MOS tube 117 is connected with the first end 107 of the protection circuit, the grid electrode of the first MOS tube 117 is connected with the controller 108, and the drain electrode of the first MOS tube 117 is respectively connected with the first end 109 of the charging circuit and the first end 110 of the driving circuit; the grid electrode of the second MOS tube 118 is connected with the second end 111 of the driving circuit, the source electrode of the second MOS tube 118 is connected with the second end 112 of the charging circuit, and the drain electrode of the second MOS tube 118 is connected with the first end 113 of the monitoring circuit; a second terminal 114 of the monitoring circuit is connected to the supercapacitor 106.

Note that MOS is an abbreviation of MOSFET. MOSFET Metal-Oxide-semiconductor field effect transistor (MOSFET) is abbreviated as Metal-Oxide-Semiconductor Field-Effect Transistor.

As shown in fig. 1, the power supply circuit 103 includes a first diode 119, a first resistor 120, and a first capacitor 121.

The input of the power supply circuit 103 is the input of the first diode 119.

The input voltage is connected with the input end of the first diode 119, the output end of the first diode 119 is respectively connected with one end of the first capacitor 121 and one end of the first resistor 120, and the other end of the first capacitor 121 is grounded;

one end of the first resistor 120 is the first end 109 of the power supply circuit, and the output end of the first diode 119 is the second end 112 of the power supply circuit.

The other end of the first resistor 120 is connected to the first end 110 of the driving circuit and the drain of the first MOS transistor 117, and the second end 111 of the driving circuit is connected to the gate of the second MOS transistor 118.

A second terminal of the protection circuit 102 is connected to a power supply (VCC), and a third terminal of the protection circuit 102 is grounded.

The third terminal of the driving circuit is connected to a power supply (VCC), and the fourth terminal of the driving circuit 104 is grounded.

As shown in fig. 1, the monitoring circuit 105 includes an inductor 122, a second diode 123, a capacitor C2, a current monitoring circuit 115, a resistor R2, and a health detection circuit 116.

One end of the inductor 122 is connected to the drain of the second MOS transistor 118 and the input end of the second diode 123, and the input end of the second diode 123 is the first end 113 of the monitoring circuit.

The output of the second diode 123 is grounded.

The other end of the inductor 122, one end of the second resistor 124, and the first end of the current monitoring circuit 115 are connected to one end of the second capacitor 125, and the other end of the second capacitor 125 is grounded.

The other end of the second resistor 124 is connected to the second end of the current monitoring circuit 115, the supercapacitor 106, and the first end of the monitoring detection circuit, the third end of the current monitoring circuit 115 is connected to a power supply (VCC), and the fourth end of the current monitoring circuit 115 is grounded.

The other end of the second resistor 124 is the second end 114 of the monitoring circuit.

A second terminal of the health detection circuit 116 is connected to a power supply (VCC), and a third terminal of the health detection circuit 116 is grounded.

It should be noted that, the target super capacitor charging circuit 101 in the embodiment of the present invention is a general super capacitor charging circuit, and is widely applied to various electronic devices, and can provide power-off protection for key components in the electronic devices when the electronic devices are abnormally powered off. The circuit structure of the target supercapacitor charge circuit 101 shown in fig. 1 is a general circuit structure of the supercapacitor charge circuit.

It should be noted that, in the embodiment of the present invention, the target supercapacitor charge circuit 101 is disposed in the target electronic device, so as to provide power-off protection for the target component in the target electronic device.

The actions of the target supercapacitor charge circuit 101 during the charging phase include: in the case of the RAID card being powered on, if it is detected that the target super capacitor charging circuit 101 is in place, charging of the target super capacitor charging circuit 101 is started.

The controller 108 in the target electronic device acquires the voltage of the supercapacitor 106 in the target supercapacitor charge circuit 101, and inputs a PWM signal to the gate of the first MOS transistor 117 according to a preset initial duty cycle and frequency based on the voltage.

The target supercapacitor charge circuit 101 in the charging stage may be regarded as a BUCK (BUCK) circuit, the second MOS transistor 118 is an upper switch MOS transistor, the second diode 123 is a freewheeling diode, the inductor 122 is an output inductor, C1 is an input capacitor, C2 is an output capacitor, and after the input voltage (P12V) is input to the target supercapacitor charge circuit 101 from the input end of the second diode 123, the supercapacitor 106 in the target supercapacitor charge circuit 101 may be charged.

The charging principle of the target supercapacitor charge circuit 101 includes: after passing through the first MOS transistor 117 and the driving circuit 104, the PWM signal is amplified into a pwm_gate signal;

The PWM_GATE signal is input to the grid electrode of the second MOS tube 118, the on-off state of the second MOS tube 118 is controlled, and the drain electrode of the second MOS tube 118 outputs a Phase signal;

after rectifying and filtering the Phase signal by the inductor 122 and the second capacitor 125, the output voltage v_super-cap charges the super-capacitor.

During the charging phase, the controller 108 may modulate the duty cycle and frequency of the PWM signal according to the real-time voltage of the supercapacitor 106, thereby gradually increasing the voltage v_super cap, maintaining the charging of the supercapacitor 106.

In the charging stage, the charging current passes through the first resistor 120 to convert the current signal into a voltage signal, the voltage signal is amplified by the signal amplifier in the current monitoring circuit 105 and is input into the protection circuit 102, and when the charging current is overlarge, the first MOS tube 117 is immediately closed to stop charging; if the charging current is normal, the voltage that continues to charge the super capacitor 106 reaches the target voltage.

When the voltage of the super capacitor 106 reaches the target voltage, the controller 108 stops outputting the PWM signal, the charging phase is ended, the first MOS transistor 117 is turned off, and the health detection circuit is started.

The health detection circuit discharges the super capacitor 106 with a constant current I, and detects the variation DeltaV of the voltage of the super capacitor 106 after a fixed period of time t, using the formula And calculating the capacitance capacity of the super capacitor 106 to finish the health detection of the super capacitor 106.

After 2-3 times of cyclic charge and discharge, the target super capacitor charging circuit 101 is charged and enters a protectable state.

Fig. 2 is a schematic flow chart of a testing method of a super capacitor charging circuit according to the present invention. The test method of the super capacitor charging circuit provided by the invention is used for testing the target super capacitor charging circuit 101. The method for testing the super capacitor charging circuit of the present invention is described below with reference to fig. 2. As shown in fig. 2, the method includes: step 201, testing a first target signal in a first test scene to obtain first test data;

the target supercapacitor 106 is converted from a power-off state to a power-on state in the first test scene, and the power-on state is kept for a first preset time period;

the first test data comprises actual values of first target parameters of the first target signal in a first test scene;

the first target signal includes at least two of a first signal, a second signal, and a third signal; the first signal is a signal input to the gate of the first MOS transistor 117 by the controller 108; the second signal is a signal input to the gate of the second MOS transistor 118 from the second end 111 of the driving circuit; the third signal is a signal input to the first end 107 of the protection circuit from the drain of the second MOS transistor 118; the first target parameter includes an on time.

It should be noted that, the execution body of the embodiment of the invention is a super capacitor charging circuit testing device.

Specifically, the target super capacitor charging circuit 101 is a test object of the super capacitor charging circuit test method provided by the invention.

It can be understood that, because the circuit structure of the target super capacitor charging circuit 101 in the embodiment of the invention is a general super capacitor power supply circuit 103 widely applied to various electronic devices, the testing method of the super capacitor charging circuit provided by the invention has universality.

It should be noted that, before the test method for the super capacitor charging circuit provided by the invention tests the target super capacitor charging circuit 101, a test environment is established.

In the method for testing the super capacitor charging circuit provided by the invention, the target super capacitor charging circuit 101 can be tested in a plurality of test scenes, and test results of the target super capacitor charging circuit 101 in different test scenes can be obtained.

In the first test scenario in the embodiment of the present invention, the working state of the target supercapacitor 106 in the charging stage is tested, so that the target supercapacitor 106 is converted from the power-off state to the power-on state in the first test scenario, and the power-on state is maintained for a first preset period.

It should be noted that the first preset duration may be predefined according to actual situations and/or a priori knowledge. The first preset duration is not specifically limited in the embodiment of the present invention.

It should be noted that, the first signal in the embodiment of the present invention is the PWM signal above; the second signal is the pwm_gate signal above; the third signal is the Phase signal above.

It should be noted that, since the second signal is a signal obtained by amplifying the first signal by the first MOS transistor 117 stage driving circuit 104; the third signal is a signal output by the second MOS transistor 118 after being controlled by the first signal, and the first signal, the second signal and the third signal are amplified step by step through the first MOS transistor 117, the driving circuit 104 and the second MOS transistor 118, so that the actual values of the first target parameters of the first signal, the second signal and the third signal have stronger correlation with the selection of the components in the first MOS transistor 117, the second MOS transistor 118 and the driving circuit 104.

The first target signal in the embodiment of the present invention includes at least one of the first signal, the second signal and the third signal, and the working state of the target supercapacitor 106 in the charging stage may be evaluated by testing at least one of the first signal, the second signal and the third signal in the first test scenario, and at least one of the type selection of the first MOS transistor 117, the type selection of the second MOS transistor 118 and the type selection of the component in the driving circuit 104 may also be evaluated.

It can be appreciated that, in the case where the first target signal includes the first signal, the second signal, and the third signal, the working state of the target supercapacitor 106 in the charging stage can be more comprehensively and accurately estimated, and the selection of the components in the first MOS transistor 117, the second MOS transistor 118, and the driving circuit 104 can be simultaneously estimated.

It should be noted that, in the embodiment of the present invention, the first target parameter includes a time To Open (TON), and the first target parameter may also include other parameters. The first target parameter is predefined based on a priori knowledge and/or actual conditions.

In the case that the first target signal includes the first signal, a test point may be set between the controller 108 and the gate of the first MOS transistor 117, and then an oscilloscope may be used to collect a waveform diagram of the first signal under the first test scene at the test point; based on the waveform diagram of the first signal in the first test scene, the actual value of the first target parameter of the first signal in the first test scene can be obtained as the first test data.

In the case that the first target signal includes the second signal, a test point may be set between the second end 111 of the driving circuit and the gate of the second MOS transistor 118, and then an oscillograph may be used to collect a waveform of the second signal in the first test scene at the test point, and then an actual value of the first target parameter of the second signal in the first test scene may be obtained as the first test data based on the waveform of the second signal in the first test scene.

In the case that the first target signal includes the third signal, a test point may be set between the drain of the second MOS transistor 118 and one end of the inductor 122, and then an oscilloscope may be used to collect a waveform diagram of the third signal in the first test scene at the test point; based on the waveform diagram of the third signal in the first test scene, the actual value of the first target parameter of the third signal in the first test scene can be obtained and used as the first test data.

It will be appreciated that the actual values in embodiments of the present invention are dynamically changing over time.

Step 202, based on the first test data, a first test result of the target supercapacitor charge circuit 101 under the first test scene is obtained.

Specifically, after the first test data is obtained, the test result of the target supercapacitor charging circuit 101 in the first test scene may be obtained by means of condition judgment, numerical calculation, mathematical statistics, model processing and the like based on the first test data.

Optionally, the test result of the target supercapacitor charge circuit 101 in the first test scenario may include a working state level of the target supercapacitor charge circuit 101 in the first test scenario, and may further include electronic components with unsuitable types in the target supercapacitor charge circuit 101.

The working state level of the target super capacitor charging circuit 101 in the first test scene can be used for describing the working state of the target super capacitor charging circuit 101 in the charging stage; the higher the working state level of the target super capacitor charging circuit 101 in the first test scenario, the better the working state of the target super capacitor charging circuit 101 in the charging stage.

According to the embodiment of the invention, the first target signal is tested in the first test scene, after the first test data are obtained, the test result of the target super capacitor charging circuit in the first test scene is obtained based on the first test data, so that the working state of the super capacitor charging circuit in the charging stage can be tested more comprehensively and accurately, and more accurate and more comprehensive data support can be provided for the design and improvement of the super capacitor charging circuit.

As an alternative embodiment, based on the first test data, acquiring a first test result of the target supercapacitor charge circuit 101 in the first test scenario includes: based on the first test data, it is determined whether the selection of at least one of the first MOS transistor 117, the second MOS transistor 118, and the components in the driving circuit 104 is appropriate, and the determination result is determined as a first test result of the target supercapacitor charge circuit 101 in the first test scenario.

It should be noted that, as shown in the control logic from the first signal (PWM signal) to the second signal (pwm_gate signal) and then to the third signal (Phase signal), after the first signal is amplified by the first MOS transistor 117 and the driving circuit 104, the on time of the second signal is longer than the on time of the first signal, and the second signal will have a certain distortion compared with the first signal. After the second signal is amplified by the second MOS transistor 118, the on time of the third signal is longer than the on time of the second signal, and the third signal will have a distortion to a certain extent compared with the first signal and the second signal.

However, if the distortion of the second signal and/or the third signal is serious, the performance of the target supercapacitor charge circuit 101 may be affected.

In the embodiment of the invention, whether the type of the first MOS transistor 117 and the type of the component in the driving circuit 104 are appropriate or not can be determined based on the actual value of the on time of the first signal in the first test scene and the actual value of the on time of the second signal in the first test scene.

In the embodiment of the invention, whether the second MOS transistor 118 is suitable for the type selection can be determined based on the actual value of the on time of the second signal in the first test scene and the actual value of the on time of the third signal in the first test scene.

In the embodiment of the invention, whether the type of the second MOS transistor 118, the type of the first MOS transistor 117 and the type of the components in the driving circuit 104 are appropriate or not can be determined based on the actual value of the on time of the first signal in the first test scene and the actual value of the on time of the third signal in the first test scene.

In the embodiment of the invention, whether the type of the second MOS transistor 118, the type of the first MOS transistor 117 and the type of the component in the driving circuit 104 are appropriate or not can be determined based on the actual value of the on time of the first signal in the first test scene, the actual value of the on time of the second signal in the first test scene and the actual value of the on time of the third signal in the first test scene.

It can be appreciated that, based on the actual value of the on time of the first signal in the first test scenario, the actual value of the on time of the second signal in the first test scenario, and the actual value of the on time of the third signal in the first test scenario, whether the type of the second MOS transistor 118, the type of the first MOS transistor 117, and the type of the components in the driving circuit 104 are appropriate may be more accurately selected.

As an alternative embodiment, determining whether the type of at least one of the first MOS transistor 117, the second MOS transistor 118, and the component in the driving circuit 104 is suitable based on the first test data includes: in the case where the first target signal includes the first signal and the second signal, based on a difference between an actual value of the on time of the second signal in the first test scene and an actual value of the on time of the first signal in the first test scene, it is determined whether the types of the components in the first MOS transistor 117 and the driving circuit 104 are appropriate.

In the case that the first target signal includes the first signal and the second signal, a difference between an actual value of the on time of the second signal in the first test scene and an actual value of the on time of the first signal in the first test scene may be calculated.

If the difference is not greater than the first threshold, it may be indicated that the distortion of the second signal compared with the first signal is in a normal range, so that the selection of the components in the first MOS transistor 117 and the driving circuit 104 may be suitable as the test result of the target super capacitor charging circuit 101 in the first test scenario;

if the difference is greater than the first threshold, it may be indicated that the distortion of the second signal compared with the first signal exceeds the normal range, and thus the type of the components in the first MOS transistor 117 and/or the driving circuit 104 may be selected improperly, which may be used as a test result of the target super capacitor charging circuit 101 in the first test scenario.

In the case that the first target signal includes the second signal and the third signal, based on a difference between an actual value of the on time of the third signal in the first test scene and an actual value of the on time of the second signal in the first test scene, it is determined whether the second MOS transistor 118 is suitable for the type selection.

And under the condition that the first target signal comprises the second signal and the third signal, calculating to obtain the actual value of the on time of the third signal in the first test scene and the difference value between the actual value of the on time of the second signal in the first test scene.

If the difference is not greater than the second threshold, it may be indicated that the distortion of the third signal compared with the second signal is in the normal range, so that the second MOS transistor 118 may be selected appropriately, and the selected second MOS transistor may be used as a test result of the target supercapacitor charge circuit 101 in the first test scenario;

if the difference is greater than the second threshold, it may be indicated that the distortion of the third signal compared with the second signal exceeds the normal range, and thus the second MOS transistor 118 may be selected improperly as the test result of the target supercapacitor charge circuit 101 under the first test scenario.

In the case where the first target signal includes only the first signal and the third signal, based on a difference between an actual value of the on time of the third signal in the first test scene and an actual value of the on time of the first signal in the first test scene, it is determined whether the types of the first MOS transistor 117, the second MOS transistor 118, and the components in the driving circuit 104 are appropriate.

Specifically, in the case that the first target signal includes the first signal and the third signal, a difference between an actual value of the on time of the third signal in the first test scene and an actual value of the on time of the first signal in the first test scene may be calculated.

If the difference is not greater than the third threshold, it may be indicated that the distortion of the third signal compared with the first signal is in the normal range, so that the second MOS transistor 118, the first MOS transistor 117 and the components in the driving circuit 104 may be determined to be suitable for selecting as the test result of the target super capacitor charging circuit 101 in the first test scenario;

if the difference is greater than the third threshold, it may be indicated that the distortion of the third signal compared with the first signal exceeds the normal range, and it may be further determined that at least one of the second MOS transistor 118, the first MOS transistor 117, and the components in the driving circuit 104 is not suitable for selecting as the test result of the target supercapacitor charging circuit 101 under the first test scenario.

It should be noted that, when the first target signal includes the first signal, the second signal, and the third signal, the condition judgment may be performed based on the first threshold, the second threshold, and the third threshold, or based on only the first threshold and the second threshold, so as to determine whether the types of the components in the second MOS transistor 118, the first MOS transistor 117, and the driving circuit 104 are appropriate.

It should be noted that, in the embodiment of the present invention, the first threshold, the second threshold, and the third threshold may be predefined according to actual situations and/or priori knowledge, for example, the first threshold, the second threshold, and the third threshold may be determined based on a critical value of the target supercapacitor charge circuit 101 triggering the overcurrent protection. In the embodiment of the invention, specific values of the first threshold, the second threshold and the third threshold are not limited.

As an alternative embodiment, after determining whether the types of the components in the first MOS transistor 117 and the driving circuit 104 are suitable based on the difference between the actual value of the on time of the second signal in the first test scene and the actual value of the on time of the first signal in the first test scene, the method further includes: in the case that the selection of the components in the first MOS transistor 117 and/or the driving circuit 104 is determined to be inappropriate, determining a target value of a third target parameter of the first MOS transistor 117 based on the first test data;

determining whether the model of the first MOS transistor 117 is proper or not based on the target value of the third target parameter of the first MOS transistor 117 and the actual value of the third target parameter of the first MOS transistor 117;

determining that the type of the component in the driving circuit 104 is unsuitable when the type of the first MOS transistor 117 is determined to be suitable, and determining the type of the MOS transistor for replacing the first MOS transistor 117 based on the actual value of the third target parameter of the first MOS transistor 117 when the type of the first MOS transistor 117 is determined to be unsuitable;

The gate charge (Q _g ) The method refers to the quantity of electric charges injected into the grid electrode for conducting (driving) the MOS tube, and the driving characteristic of the MOS tube can be measured by the grid electric charges.

Threshold voltage (V) _GS(th) ) The gate-source voltage is the voltage when the drain electrode starts to have current or the current disappears when the MOS tube is turned off.

Conduction delay time (T) _d(on) ) Refers to the time from the gate-source voltage rising by more than 10% of VGS to the drain-source voltage reaching 90% of VDS.

Off delay time (T) _d(off) ) Refers to the time from the gate-source voltage falling below 90% of VGS to the drain-source voltage reaching 10% of VDS.

The actual values of the parameters of the first MOS transistor 117 may affect the distortion degree of the second signal compared to the first signal. Therefore, at least one of the above parameters may be determined as the third target parameter in the embodiment of the present invention.

In the case that the selection of the components in the first MOS transistor 117 and/or the driving circuit 104 is determined to be inappropriate, the target value of the third target parameter of the first MOS transistor 117 may be determined by means of numerical calculation, condition judgment, model processing, and the like, based on the difference between the actual value of the on time of the second signal in the first test scene and the actual value of the on time of the first signal in the first test scene.

After determining the target value of the third target parameter of the first MOS transistor 117, a difference between the target value of the third target parameter of the first MOS transistor 117 and the actual value of the third target parameter of the first MOS transistor 117 may be calculated.

In the case that the difference is not greater than the fourth threshold, it may be determined that the selection of the first MOS transistor 117 is appropriate, and the distortion of the second signal compared with the first signal is out of the normal range due to the inappropriate selection of the components in the driving circuit 104;

in the case that the difference is greater than the fourth threshold, it may be determined that the selection of the first MOS transistor 117 is not appropriate, and the distortion of the second signal compared with the first signal is beyond the normal range, which may be caused by the inappropriate selection of the first MOS transistor 117, or may be caused by the inappropriate selection of the components in the first MOS transistor 117 and the driving circuit 104.

The fourth threshold in embodiments of the present invention may be predefined based on actual conditions and/or a priori knowledge. The specific value of the fourth threshold in the embodiment of the present invention is not limited.

It can be appreciated that in the case where the selection of the first MOS transistor 117 is determined to be appropriate, it may be determined that the selection of the components in the driving circuit 104 is not appropriate.

It should be noted that, when determining that the type selection of the first MOS transistor 117 is not appropriate, the MOS transistor for replacing the first MOS transistor 117 may be determined based on the target value of the third target parameter of the first MOS transistor 117.

As an alternative embodiment, after determining whether the type of the second MOS transistor 118 is suitable based on the difference between the actual value of the on time of the third signal in the first test scenario and the actual value of the on time of the second signal in the first test scenario, the method further includes: in the case where it is determined that the selection of the second MOS transistor 118 is not appropriate, a target value of the third target parameter of the second MOS transistor 118 is determined based on the first test data.

Determining a MOS tube model for replacing the second MOS tube 118 based on the target value of the third target parameter of the second MOS tube 118;

Specifically, in the case that the selection of the second MOS transistor 118 is determined to be inappropriate, the target value of the third target parameter of the second MOS transistor 118 may be determined by means of numerical calculation, condition judgment, model processing, and the like, based on the difference between the actual value of the on time of the third signal in the first test scene and the actual value of the on time of the second signal in the first test scene.

After determining the target value of the third target parameter of the second MOS transistor 118, a MOS transistor for replacing the second MOS transistor 118 may be determined based on the target value of the third target parameter of the second MOS transistor 118.

According to the embodiment of the invention, based on the first test data, whether the type selection of at least one of the first MOS tube 117, the second MOS tube 118 and the components in the driving circuit is proper or not is judged, and the judgment result is determined to be the first test result of the target super capacitor charging circuit in the first test scene, so that the components with improper type selection in the super capacitor charging circuit can be more accurately and more efficiently determined, and the efficiency and the accuracy of designing or improving the super capacitor charging circuit can be improved.

As an alternative embodiment, based on the first test data, acquiring a first test result of the target supercapacitor charge circuit 101 in the first test scenario includes: and determining the working state level of the target super-capacitor charging circuit 101 in the first test scene based on at least one of the difference value between the actual value of the second signal on time and the actual value of the first signal on time, the difference value between the actual value of the third signal on time and the actual value of the first signal on time and the difference value between the actual value of the third signal on time and the actual value of the second signal on time, and taking the working state level of the target super-capacitor charging circuit 101 in the first test scene as a first test result of the target super-capacitor charging circuit 101 in the first test scene.

Specifically, in the case that the first target signal includes the first signal and the second signal, the operating state level of the target supercapacitor charge circuit 101 in the first test scene is determined based on the difference between the actual value of the turn-on time of the second signal in the first test scene and the actual value of the turn-on time of the first signal in the first test scene, and the first preset condition.

In the case that the first target signal includes the second signal and the third signal, the working state level of the target supercapacitor charge circuit 101 in the first test scene is determined based on the difference between the actual value of the turn-on time of the third signal in the first test scene and the actual value of the turn-on time of the second signal in the first test scene, and the second preset condition.

In the case that the first target signal includes the first signal and the third signal, the working state level of the target supercapacitor charge circuit 101 in the first test scene is determined based on a difference value between an actual value of the turn-on time of the third signal in the first test scene and an actual value of the turn-on time of the first signal in the first test scene, and a third preset condition.

In the case that the first target signal includes the first signal, the second signal, and the third signal, the operating state level of the target supercapacitor charging circuit 101 under the first test scenario may be determined based on a difference between an actual value of the on-time of the second signal under the first test scenario and an actual value of the on-time of the first signal under the first test scenario, a difference between an actual value of the on-time of the third signal under the first test scenario and an actual value of the on-time of the first signal under the first test scenario, and a first preset condition, a second preset volume, and a third preset condition.

It should be noted that, in the embodiment of the present invention, the first preset condition, the second preset condition, and the third preset condition are used to describe the correspondence between different differences and different working state levels. The first preset condition, the second preset condition and the third preset condition may be predefined based on a priori knowledge and/or actual conditions. In the embodiment of the present invention, the first preset condition, the second preset condition, and the third preset condition are not specifically limited.

If a plurality of different operating state levels are determined based on the first preset condition, the second preset condition, and the third preset condition, the operating state level with a higher duty ratio among the plurality of operating state levels may be determined as the operating state level of the target supercapacitor charging circuit 101 in the first test scene, or the level located in the middle among the plurality of operating state levels may be determined as the operating state level of the target supercapacitor charging circuit 101 in the first test scene.

According to the embodiment of the invention, the working state grade of the target super-capacitor charging circuit in the first test scene is determined based on the first test data, and the working state of the super-capacitor charging circuit in the charging stage can be more intuitively and comprehensively described as the first test result of the target super-capacitor charging circuit in the first test scene.

Based on the above content of each embodiment, the method for testing the super capacitor charging circuit further includes: under a second test scene, testing a second target signal and the super capacitor 106 to obtain second test data;

the target component in the second test scene is converted from a power-on state to a power-off state, and the power-off state is kept for a second preset time period; the target component is provided with power-off protection by the target super capacitor charging circuit 101;

the second test data includes an actual value of a second target parameter of the second target signal in the second test scenario, and an actual value of a third target parameter of the supercapacitor 106 in the second test scenario;

the second target signal comprises a circuit switching signal and a complete machine power-down signal, and the circuit switching signal and the complete machine power-down signal are output by the target component; the second target parameter includes a level; the third target parameters include voltage and current.

It should be noted that, in the second test scenario in the embodiment of the present invention, the working state of the target supercapacitor 106 in the power-off protection stage is tested, so that the target component in the second test scenario is converted from the power-on state to the power-off state, and the power-off state is maintained for a second preset period of time.

It should be noted that the second preset duration may be predefined according to actual situations and/or a priori knowledge. The second preset duration is not specifically limited in the embodiment of the present invention.

Optionally, the target component in the embodiment of the present invention may be a RAID card in the target electronic device.

It should be noted that, the circuit switching signal and the complete machine power-off signal output by the target component, and the voltage and the current of the supercapacitor 106 may be used to determine whether the power-off protection instruction triggering the target supercapacitor charging circuit 101 to perform the power-off protection on the target component is correctly sent and whether the target supercapacitor charging circuit 101 triggers the power-off protection when the target component is converted from the power-on state to the power-off state, or may be used to test the working state of the target supercapacitor charging circuit 101 in the power-off protection stage on the target component when the target component is in the power-off state.

According to the embodiment of the invention, the oscillograph of the second target signal in the second test scene can be obtained by using the oscillograph, and then the actual value of the level of the second target signal in the second test scene can be obtained as second test data based on the oscillograph.

In the embodiment of the invention, the actual values of the voltage and the current of the supercapacitor 106 in the second test scene can be obtained by using the ammeter and the voltmeter and used as the second test data.

Based on the second test data, a test result of the target super capacitor charging circuit 101 under a second test scene is obtained;

specifically, after the second test data is obtained, whether the power-off protection instruction triggering the target supercapacitor charging circuit 101 to perform power-off protection on the target component is correctly sent out and whether the target supercapacitor charging circuit 101 triggers power-off protection can be determined based on the change condition of the level of the second target signal in the second test scene and the change condition of the voltage and the current of the supercapacitor 106 in the second test scene, and the determination result is determined as the test result of the target supercapacitor charging circuit 101 in the second test scene.

Based on the change condition of the level of the second target signal in the second test scene and the change condition of the voltage and the current of the supercapacitor 106 in the second test scene, the successful power-off protection of the target supercapacitor charging circuit 101 to the target component in the second test scene can be obtained, and the power-off protection is used as the test result of the target supercapacitor charging circuit 101 in the second test scene.

Specifically, under the condition that the target component is converted from the power-on state to the power-off state, the level of the power-off signal of the whole machine is pulled up, the RAID card judges that dirty data which is not written into a hard disk exists in DDR particles, the RAID card triggers the power-off protection of the target super capacitor 106, the circuit switching signal is maintained to be high level, at the moment, the power supply voltage of the RAID card is switched to the power supply (4.5V) of the charging section of the target super capacitor by the power supply (3.3V) of the system, the power supply voltage of the RAID card is consistent with the voltage of the super capacitor 106 in the power-off protection process, after a period of time, the level of the circuit switching signal is lowered, the power supply voltage of the RAID card drops to 0V, and the power-off protection of the target super capacitor 106 is proved to be normally completed.

It should be noted that, if it is determined, based on the second test data, that the power-off protection instruction triggering the target supercapacitor charging circuit 101 to perform power-off protection on the target component is not correctly issued, the target supercapacitor charging circuit 101 does not trigger power-off protection, or the power-off protection of the target component by the target supercapacitor charging circuit 101 in the second test scenario is unsuccessful, then based on the second test data, a component that may fail and/or a component with improper type selection may be further determined in the target supercapacitor charging circuit 101.

As an alternative embodiment, in a second test scenario, the second target signal and the supercapacitor 106 are tested, and before the second test data is obtained, the method further includes: it is determined that the hard disk in the system in which the target capacitive powering circuit 103 and the target element are located has passed the IO test.

According to the embodiment of the invention, the second target signal and the super capacitor are tested in the second test scene, after the second test data are obtained, the test result of the target super capacitor charging circuit in the second test scene is obtained based on the second test data, the working state of the super capacitor charging circuit in the power-off protection stage can be comprehensively detected, the test result of the working state of the super capacitor charging circuit in the power-off protection stage can be more comprehensively and accurately obtained, and more accurate and more comprehensive data support can be provided for the design and improvement of the super capacitor charging circuit.

Based on the above content of each embodiment, the method for testing the super capacitor charging circuit further includes: under the first test scene, testing the second target signal and the super capacitor 106 to obtain third test data;

wherein the third test data includes an actual value of the second target parameter of the second target signal in the first test scenario and an actual value of the third target parameter of the supercapacitor 106 in the first test scenario.

Specifically, in the embodiment of the invention, an oscillograph of the second target signal under the first test scene can be obtained, and then based on the oscillograph, the actual value of the level of the second target signal under the first test scene can be obtained as the third test data.

In the embodiment of the invention, the actual value of the voltage and/or the current of the supercapacitor 106 in the first test scene can be obtained by using the ammeter and the voltmeter and used as the third test data.

Based on the third test data, a second test result of the target supercapacitor charge circuit 101 under the first test scene is obtained.

Specifically, after the third test data is obtained, the working state level of the target supercapacitor charging circuit 101 in the first test scene may be obtained as the second test result of the target supercapacitor charging circuit 101 in the first test scene based on the change condition of the level of the second target signal in the first test scene and/or the change condition of the voltage and/or the current of the supercapacitor 106 in the first test scene.

Optionally, a third test result of the target supercapacitor charge circuit 101 in the first test scenario is obtained by combining the first test result and the second test result of the target supercapacitor charge circuit 101 in the first test scenario.

Specifically, after the first test result and the second test result of the target supercapacitor charge circuit 101 in the first test scenario are obtained, the first test result and the second test result may be combined to obtain the third test result of the target supercapacitor charge circuit 101 in the first test scenario.

Optionally, when the first test result and the second test result both include the working state level of the target supercapacitor charging circuit 101 in the first test scene, if the working state levels of the target supercapacitor charging circuit 101 in the first test scene in the first test result and the second test result are the same, determining the working state level as a third test result of the target supercapacitor charging circuit 101 in the first test scene; if the working state grades of the target super capacitor charging circuit 101 in the first test result and the second test result are different in the first test scene, determining the working state grade with the lower grade as a third test result of the target super capacitor charging circuit 101 in the first test scene.

According to the embodiment of the invention, the second target signal and/or the super capacitor is tested in the first test scene, and then the second test result of the target super capacitor charging circuit in the first test scene is obtained based on the third test data after the third test data is obtained, so that the third test result of the target super capacitor charging circuit 101 in the first test scene can be obtained by combining the first test result and the second test result of the target super capacitor charging circuit in the first test scene, the working state of the super capacitor charging circuit in the charging stage can be detected more comprehensively, and the test accuracy and the comprehensiveness of the super capacitor charging circuit in the charging stage can be further improved.

Based on the foregoing content of each embodiment, after obtaining the first test result of the target supercapacitor charge circuit 101 in the first test scenario, obtaining the second test result of the target supercapacitor charge circuit 101 in the first test scenario, and obtaining the test result of the target supercapacitor charge circuit 101 in the second test scenario, the method further includes: and combining the first test result of the target super-capacitor charging circuit 101 under the first test scene, the second test result of the target super-capacitor charging circuit 101 under the first test scene and the test result of the target super-capacitor charging circuit 101 under the second test scene to obtain the test result of the target super-capacitor charging circuit 101.

It should be noted that, in the embodiment of the present invention, the test result of the target supercapacitor charge circuit 101, including the test result in the charging stage and the power-off protection stage of the target supercapacitor charge circuit 101, may be used to describe the overall performance of the target supercapacitor charge circuit 101.

In order to facilitate understanding of the method for testing the super capacitor charging circuit provided by the invention, the method for testing the super capacitor charging circuit provided by the invention is described by way of an example. FIG. 3 is a second flow chart of the testing method of the super capacitor charging circuit according to the present invention.

The first target signal in this example includes a first signal, a second signal, and a third signal.

As shown in fig. 3, the step of testing the target super capacitor charging circuit 101 based on the super capacitor charging circuit testing method provided by the present invention includes: building a test environment;

test points are selected, and the test points are respectively located between the controller 108 and the gate of the first MOS transistor 117, between the second end 111 of the driving circuit and the gate of the second MOS transistor 118, and between the drain of the second MOS transistor 118 and one end of the inductor 122.

And under the first test scene, acquiring actual values of the opening time of the first signal, the second signal and the third signal under the first test scene as first test data.

In the first test scenario, the actual values of the levels of the circuit switching signal and the complete machine power-down signal in the first test scenario and the actual values of the voltages and the currents of the super capacitor 106 in the first test scenario are obtained and used as second test data.

After the hard disk Full IO test is operated, in a second test scene, the actual values of the level of the circuit switching signal and the complete machine power-down signal in the second test scene and the actual values of the voltage and the current of the supercapacitor 106 in the second test scene are obtained and used as third test data.

Based on the first test data, the second test data, and the third test data, a test result of the target supercapacitor charge circuit 101 is obtained.

Fig. 4 is a schematic structural diagram of the testing device for the super capacitor charging circuit provided by the invention. The super capacitor charging circuit testing device provided by the invention is described below with reference to fig. 4, and the super capacitor charging circuit testing device described below and the super capacitor charging circuit testing method provided by the invention described above can be referred to correspondingly. The super capacitor charging circuit testing device provided by the invention is used for the target super capacitor charging circuit 101. The target super capacitor charging circuit 101 comprises a protection circuit 102, a first MOS tube 117, a power supply circuit 103, a driving circuit 104, a second MOS tube 118, a monitoring circuit 105 and a super capacitor 106; the source electrode of the first MOS tube 117 is connected with the first end 107 of the protection circuit, the grid electrode of the first MOS tube 117 is connected with the controller 108, and the drain electrode of the first MOS tube 117 is respectively connected with the first end 109 of the power supply circuit and the first end 110 of the driving circuit; the grid electrode of the second MOS tube 118 is connected with the second end 111 of the driving circuit, the source electrode of the second MOS tube 118 is connected with the second end 112 of the power supply circuit, and the drain electrode of the second MOS tube 118 is connected with the first end 113 of the monitoring circuit; a second terminal 114 of the monitoring circuit is connected to the supercapacitor 106.

As shown in fig. 4, the super capacitor charging circuit testing device includes: a data acquisition module 401 and a circuit test module 402.

The data acquisition module 401 is configured to test a first target signal in a first test scenario to acquire first test data;

the circuit testing module 402 is configured to obtain a first test result of the target supercapacitor charging circuit under a first test scenario based on the first test data;

the target super capacitor is converted from a power-off state to a power-on state in a first test scene, and the power-on state is kept for a first preset time period;

the first target signal includes at least two of a first signal, a second signal, and a third signal; the first signal is a signal input to the gate of the first MOS transistor 117 by the controller; the second signal is a signal input to the gate of the second MOS transistor 118 from the second end of the driving circuit; the third signal is a signal input to the first end of the protection circuit from the drain of the second MOS transistor 118; the first target parameter includes an on time.

Specifically, the data acquisition module 401 and the circuit test module 402 are electrically connected.

According to the super capacitor charging circuit testing device, the first target signal is tested in the first testing scene, after the first testing data are obtained, the testing result of the target super capacitor charging circuit in the first testing scene is obtained based on the first testing data, the working state of the super capacitor charging circuit in the charging stage can be tested more comprehensively and accurately, and more accurate and more comprehensive data support can be provided for design and improvement of the super capacitor charging circuit.

Fig. 5 illustrates a physical schematic diagram of an electronic device, as shown in fig. 5, which may include: processor 510, communication interface (Communications Interface) 520, memory 530, and communication bus 540, wherein processor 510, communication interface 520, memory 530 complete communication with each other through communication bus 540. Processor 510 may invoke logic instructions in memory 530 to perform a supercapacitor charge circuit test method comprising: testing a first target signal under a first test scene to obtain first test data; acquiring a first test result of the target super capacitor charging circuit in a first test scene based on the first test data; the target super capacitor is converted from a power-off state to a power-on state in a first test scene, and the power-on state is kept for a first preset time period; the first test data comprises actual values of first target parameters of the first target signal in a first test scene; the first target signal includes at least two of a first signal, a second signal, and a third signal; the first signal is a signal input to the gate of the first MOS transistor 117 by the controller; the second signal is a signal input to the gate of the second MOS transistor 118 from the second end of the driving circuit; the third signal is a signal input to the first end of the protection circuit from the drain of the second MOS transistor 118; the first target parameter includes an on time.

Further, the logic instructions in the memory 530 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Based on the content of the above embodiments, a computer includes: the electronic equipment, the controller, the target super capacitor charging circuit and the target components are as described above.

The computer in the embodiment of the invention can utilize the electronic equipment to realize the self-detection of the target hen capacitor charging circuit, can detect the working state of the target super capacitor charging circuit in each node more comprehensively, and can improve the running stability and the high availability of the computer.

In another aspect, the present invention also provides a computer program product, where the computer program product includes a computer program, where the computer program can be stored on a non-transitory computer readable storage medium, and when the computer program is executed by a processor, the computer can execute the method for testing the super capacitor charging circuit provided by the above methods, and the method includes: testing a first target signal under a first test scene to obtain first test data; acquiring a first test result of the target super capacitor charging circuit in a first test scene based on the first test data; the target super capacitor is converted from a power-off state to a power-on state in a first test scene, and the power-on state is kept for a first preset time period; the first test data comprises actual values of first target parameters of the first target signal in a first test scene; the first target signal includes at least two of a first signal, a second signal, and a third signal; the first signal is a signal input to the gate of the first MOS transistor 117 by the controller; the second signal is a signal input to the gate of the second MOS transistor 118 from the second end of the driving circuit; the third signal is a signal input to the first end of the protection circuit from the drain of the second MOS transistor 118; the first target parameter includes an on time.

In yet another aspect, the present invention further provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the method for testing a supercapacitor charge circuit provided by the above methods, the method comprising: testing a first target signal under a first test scene to obtain first test data; acquiring a first test result of the target super capacitor charging circuit in a first test scene based on the first test data; the target super capacitor is converted from a power-off state to a power-on state in a first test scene, and the power-on state is kept for a first preset time period; the first test data comprises actual values of first target parameters of the first target signal in a first test scene; the first target signal includes at least two of a first signal, a second signal, and a third signal; the first signal is a signal input to the gate of the first MOS transistor 117 by the controller; the second signal is a signal input to the gate of the second MOS transistor 118 from the second end of the driving circuit; the third signal is a signal input to the first end of the protection circuit from the drain of the second MOS transistor 118; the first target parameter includes an on time.

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. The test method of the super capacitor charging circuit is characterized by being used for testing a target super capacitor charging circuit; the target super capacitor charging circuit comprises a protection circuit, a first MOS tube, a power supply circuit, a driving circuit, a second MOS tube, a monitoring circuit and a super capacitor; the source electrode of the first MOS tube is connected with the first end of the protection circuit, the grid electrode of the first MOS tube is connected with the controller, and the drain electrode of the first MOS tube is respectively connected with the first end of the power supply circuit and the first end of the driving circuit; the grid electrode of the second MOS tube is connected with the second end of the driving circuit, the source electrode of the second MOS tube is connected with the second end of the power supply circuit, and the drain electrode of the second MOS tube is connected with the first end of the monitoring circuit; the second end of the monitoring circuit is connected with the super capacitor;

The method comprises the following steps:

testing a first target signal in a first test scene to obtain first test data;

the target super capacitor charging circuit is converted into a power-on state from a power-off state in the first test scene, and the power-on state is kept for a first preset time period;

2. The method of claim 1, wherein the obtaining, based on the first test data, a first test result of the target supercapacitor charging circuit in the first test scenario includes:

3. The method according to claim 2, wherein determining whether the type of at least one of the first MOS transistor, the second MOS transistor, and the component in the driving circuit is suitable based on the first test data, comprises:

4. The method for testing a supercapacitor charge circuit according to claim 3, wherein after determining whether the types of the first MOS transistor and the components in the driving circuit are suitable based on a difference between an actual value of the turn-on time of the second signal in the first test scene and an actual value of the turn-on time of the first signal in the first test scene, the method further comprises:

5. The method for testing a supercapacitor charge circuit according to claim 3, wherein after determining whether the model selection of the second MOS transistor is appropriate based on a difference between an actual value of the turn-on time of the third signal in the first test scene and an actual value of the turn-on time of the second signal in the first test scene, the method further comprises:

6. The method of claim 1, wherein the obtaining, based on the first test data, a first test result of the target supercapacitor charging circuit in the first test scenario includes:

7. The method of any one of claims 1 to 6, further comprising:

8. The method of testing a supercapacitor charge circuit according to claim 7, further comprising:

9. The method of claim 8, wherein after obtaining a first test result of the target supercapacitor charge circuit in the first test scenario, obtaining a second test result of the target supercapacitor charge circuit in the first test scenario, and obtaining a test result of the target supercapacitor charge circuit in the second test scenario, the method further comprises:

10. The super capacitor charging circuit testing device is characterized by being used for testing a target super capacitor charging circuit; the target super capacitor charging circuit comprises a protection circuit, a first MOS tube, a power supply circuit, a driving circuit, a second MOS tube, a monitoring circuit and a super capacitor; the source electrode of the first MOS tube is connected with the first end of the protection circuit, the grid electrode of the first MOS tube is connected with the controller, and the drain electrode of the first MOS tube is respectively connected with the first end of the power supply circuit and the first end of the driving circuit; the grid electrode of the second MOS tube is connected with the second end of the driving circuit, the source electrode of the second MOS tube is connected with the second end of the power supply circuit, and the drain electrode of the second MOS tube is connected with the first end of the monitoring circuit; the second end of the monitoring circuit is connected with the super capacitor;

The device comprises:

11. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the supercapacitor charge circuit testing method according to any one of claims 1 to 9 when the program is executed by the processor.

12. A computer, comprising: the electronic device, controller, target supercapacitor charge circuit, and target component of claim 11.

13. A non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the supercapacitor charge circuit testing method according to any one of claims 1 to 9.