CN116805841A - Miniature high-gain quasi-resonant flyback converter - Google Patents

Abstract

The application provides a miniature high-gain quasi-resonant flyback converter, which comprises a transformer, an electronic switching tube and a phase-dislocation voltage doubling circuit; the transformer comprises a primary winding L1, a primary winding L2, a secondary winding L3 and a secondary winding L4; the same-name ends of the primary winding L1 and the primary winding L2 are connected to the positive electrode of the direct-current power supply, the different-name ends of the primary winding L1 and the primary winding L2 are connected to the input end of an electronic switching tube, the output end of the electronic switching tube is grounded through a resistor R5, and the control end of the electronic switching tube is connected to a controller; the error phase voltage doubling circuit is provided with a first input end and a second input end, the first input end of the error phase voltage doubling circuit is connected to the homonymous end of the secondary winding L3, the heteronymous end of the secondary winding L3 is grounded through a resistor R7, the second input end of the error phase voltage doubling circuit is connected to the heteronymous end of the secondary winding L4, the homonymous end of the secondary winding L4 is grounded, and the output end of the error phase voltage doubling circuit supplies power to a load.

Description

Miniature high-gain quasi-resonant flyback converter

Technical Field

The application relates to a flyback converter, in particular to a miniature high-gain quasi-resonant flyback converter.

Background

Quasi-resonant converters refer to power electronic converter technology that utilizes the resonance effect between the inductance and the junction capacitance of the power semiconductor device under DCM to realize soft switching, and are widely used in power supply structures such as PFC, flyback converters, and the like. Particularly in flyback converters, how to achieve higher voltage gain and lower losses at a small size and low cost is a challenge in recent years.

The flyback converter is usually realized with high gain by adopting schemes such as serial-parallel connection with other converters, multi-inductance coupling, embedded voltage doubling structure and the like; however, in the existing scheme, in order to realize the high-gain flyback converter topology, the multi-stage serial-parallel connection form of other converters is complex in structure and inconvenient to control; the form of multi-inductance coupling requires more magnetic elements to perform multi-winding coupling, but can be optimized from the angle of inductance utilization rate, and meanwhile, the current capacity is improved; the embedded voltage doubling structure is usually in a form of gain amplification by adopting a charge pump voltage doubling circuit, the traditional single-end charge pump circuit has higher requirements on the voltage withstand of a transformer to the ground and has slower charging speed, and the multi-end charge pump circuit needs a plurality of capacitors and diodes, so that the cost is higher. Meanwhile, in the aspect of control, a flyback converter is often designed by adopting a mode based on a QR (quick-response) quasi-resonant soft switch, and the existing scheme often has the problems of inaccurate resonant voltage valley detection and peak (saturation) exciting current detection or complex detection means and higher cost, so that the soft switch is invalid, and steady-state loss is increased; there is also a problem of CCM charging boost overheating during start-up, making it impossible to further integrate its overall converter size.

Therefore, in order to solve the above-mentioned technical problems, a new technical means is needed.

Disclosure of Invention

Therefore, the application aims to provide a miniature high-gain quasi-resonant flyback converter, which can effectively improve voltage gain, reduce the voltage-withstanding level of a transformer to the ground, reduce the number of diodes and capacitors used in a voltage-multiplying structure of a charge pump, reduce cost and the volume of the whole converter, be beneficial to miniaturization and integration, improve the utilization rate of inductance and reduce electromagnetic interference; the device can charge and boost rapidly, enter a quasi-resonance soft switching mode, and reduce CCM boosting, charging, heating and loss in the starting process.

The application provides a miniature high-gain quasi-resonant flyback converter, which comprises a transformer, an electronic switching tube and a phase-dislocation voltage doubling circuit;

the transformer comprises a primary winding L1, a primary winding L2, a secondary winding L3 and a secondary winding L4;

the same-name ends of the primary winding L1 and the primary winding L2 are connected to the positive electrode of the direct-current power supply, the different-name ends of the primary winding L1 and the primary winding L2 are connected to the input end of an electronic switching tube, the output end of the electronic switching tube is grounded through a resistor R5, and the control end of the electronic switching tube is connected to a controller;

the error phase voltage doubling circuit is provided with a first input end and a second input end, the first input end of the error phase voltage doubling circuit is connected to the homonymous end of the secondary winding L3, the heteronymous end of the secondary winding L3 is grounded through a resistor R7, the second input end of the error phase voltage doubling circuit is connected to the heteronymous end of the secondary winding L4, the homonymous end of the secondary winding L4 is grounded, and the output end of the error phase voltage doubling circuit supplies power to a load.

Further, the phase-dislocation voltage doubling circuit comprises a capacitor C6, a capacitor C7, a diode D1, a diode D2, a diode D3, a diode D4, a capacitor C8 and a capacitor C9;

one end of a capacitor C6 is used as a first input end of the phase-error voltage doubling circuit and is connected with the same-name end of the secondary winding L3, the other end of the capacitor C6 is connected with the anode of a diode D4 through a capacitor C7, and the cathode of the diode D4 is used as an output end of the phase-error voltage doubling circuit;

the anode of the diode D4 is connected with the cathode of the diode D3, the anode of the diode D3 is connected with the cathode of the diode D2, the anode of the diode D2 is connected with the cathode of the diode D1, and the anode of the diode D1 is grounded;

the common connection point between the capacitor C7 and the capacitor C6 is connected to the anode of the diode D2, one end of the capacitor C9 is used as a second input end of the phase-dislocation voltage doubling circuit to be connected to the synonym end of the secondary winding L4, the capacitor C9 is connected to the cathode of the diode D4 through the capacitor C8, and the common connection point between the capacitor C8 and the capacitor C9 is connected to the anode of the diode D3.

Further, the circuit also comprises a first sampling circuit, wherein the first sampling circuit comprises a capacitor C4, a capacitor C5, a resistor R6 and a resistor R8;

one end of a resistor R6 is connected to the output end of the electronic switch tube, the other end of the resistor R6 is connected to the synonym end of the secondary winding L3 through a resistor R8, a common connection point between the resistor R8 and the resistor R6 is grounded through a capacitor C5, the common connection point between the resistor R8 and the resistor R6 is connected to one end of a capacitor C4, and the other end of the capacitor C4 is used as the output end of the sampling circuit.

Further, the self-adaptive direct-current bias circuit comprises a NOT gate circuit A1, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a capacitor C12 and a capacitor C13;

the input end of the NOT gate circuit A1 is connected to the input pin of the controller, the NOT gate circuit is connected to the output pin of the controller, the output end of the NOT gate circuit A1 is connected to one end of a capacitor C12 through a resistor R12, the other end of the capacitor C12 is grounded, a common connection point between the capacitor C12 and the resistor R12 is connected to the input end of the NOT gate circuit A1, one end of a resistor R13 is connected to the common connection point between the resistor R12 and the capacitor C12, the other end of the resistor R13 is grounded through a capacitor C13, the common connection point between the capacitor C13 and the resistor R13 is grounded after being connected in series through a resistor R14 and a resistor R15, and the common connection point between the resistor R14 and the resistor R15 is used as the output end of the self-adaptive DC bias circuit to be connected to one end of the capacitor C4 as the output end of the sampling circuit.

Further, the circuit also comprises a second sampling circuit, wherein the second sampling circuit comprises a capacitor C14, a resistor R16, a capacitor C15 and a resistor R17;

one end of the capacitor C14 is used as the input end of the second sampling circuit and is connected with the input end of the electronic switching tube, the other end of the capacitor C14 is connected with one end of the resistor R17 through the resistor R16, the other end of the resistor R17 is grounded, the common connection point between the resistor R16 and the resistor R17 is grounded through the capacitor C15, and the common connection point between the resistor R16 and the resistor R17 is used as the output end QR of the second sampling circuit _{_Detect} 。

Further, the power supply circuit further comprises a clamp absorption circuit, wherein the clamp absorption circuit comprises a capacitor C3, a resistor R4 and a voltage stabilizing tube ZD1;

one end of the capacitor C3 and one end of the resistor R4 are connected in parallel and then connected to the homonymous end of the primary winding L1, the other end of the capacitor C3 and the resistor R4 are connected to the cathode of the voltage stabilizing tube ZD1, and the anode of the voltage stabilizing tube ZD1 is connected to the heteronymous end of the primary winding L1.

The filter voltage stabilizing circuit comprises a resistor R1, a resistor R2, a resistor R3, a capacitor C1 and a capacitor C2;

one end of the resistor R1 is connected to the output end of the direct current power supply, the other end of the resistor R1 is grounded through the capacitor C1, a common connection point between the resistor R1 and the direct current power supply is grounded through the capacitor C2, the common connection point between the resistor R1 and the capacitor C2 is grounded after being connected in series through the resistor R3 and the resistor R2, and the common connection point between the resistor R2 and the resistor R3 is connected to the detection input end of the controller.

Further, the circuit comprises an output circuit, wherein the output circuit comprises a diode D5, a capacitor C10, a capacitor C11, a resistor R9, a resistor R10 and a resistor R11;

the anode of the diode D5 is used as an input end of the output circuit, the cathode of the diode D5 is connected to one end of the resistor R9, the other end of the resistor R9 is grounded through the capacitor C11, and a common connection point between the capacitor C11 and the resistor R9 is used as an output end of the output circuit;

the common connection point between the resistor R9 and the cathode of the diode D5 is grounded through a capacitor C10, one end of the resistor R10 is connected to the common connection point between the capacitor C11 and the resistor R9, the other end of the resistor R10 is grounded through a resistor R11, and the common connection point between the resistor R10 and the resistor R11 is connected to the detection input end of the controller.

The application has the beneficial effects that: according to the application, the voltage gain can be effectively improved, the voltage-withstanding grade of the transformer to the ground is reduced, the number of diodes and capacitors used in the charge pump voltage-multiplying structure is reduced, the cost and the volume of the whole converter are reduced, the miniaturization and integration are facilitated, the inductance utilization rate can be improved, and the electromagnetic interference is reduced; the device can charge and boost rapidly, enter a quasi-resonance soft switching mode, and reduce CCM boosting, charging, heating and loss in the starting process.

Drawings

The application is further described below with reference to the accompanying drawings and examples:

fig. 1 is a schematic diagram of the present application.

Fig. 2 is a schematic diagram of a second sampling circuit according to the present application.

Fig. 3 is a schematic diagram of a dc bias circuit of the present application.

Fig. 4 is a waveform diagram of an embodiment of the present application.

Detailed Description

The present application is further described in detail below:

the application provides a miniature high-gain quasi-resonant flyback converter, which comprises a transformer, an electronic switching tube and a phase-dislocation voltage doubling circuit;

the transformer comprises a primary winding L1, a primary winding L2, a secondary winding L3 and a secondary winding L4;

the same-name ends of the primary winding L1 and the primary winding L2 are connected to a direct-current power supply, the different-name ends of the primary winding L1 and the primary winding L2 are connected to the input end of an electronic switching tube, the output end of the electronic switching tube is grounded through a resistor R5, and the control end of the electronic switching tube is connected to a controller;

the error phase voltage doubling circuit is provided with a first input end and a second input end, the first input end of the error phase voltage doubling circuit is connected to the homonymous end of the secondary winding L3, the heteronymous end of the secondary winding L3 is grounded through a resistor R7, the second input end of the error phase voltage doubling circuit is connected to the heteronymous end of the secondary winding L4, the homonymous end of the secondary winding L4 is grounded, and the output end of the error phase voltage doubling circuit supplies power to a load; through the structure, the voltage gain can be effectively improved, the voltage-withstanding level of the transformer to the ground is reduced, the number of diodes and capacitors used in the charge pump voltage-multiplying structure is reduced, the cost and the size of the whole converter are reduced, the miniaturization and integration are facilitated, the inductance utilization rate can be improved, and the electromagnetic interference is reduced; the device can charge and boost rapidly, enter a quasi-resonance soft switching mode, and reduce CCM boosting, charging, heating and loss in the starting process.

The electronic switch tube is preferably an NMOS tube, and of course, the electronic switch tube can also be realized by a triode or an IGBT.

In this embodiment, the phase-error voltage doubling circuit includes a capacitor C6, a capacitor C7, a diode D1, a diode D2, a diode D3, a diode D4, a capacitor C8, and a capacitor C9;

one end of a capacitor C6 is used as a first input end of the phase-error voltage doubling circuit and is connected with the same-name end of the secondary winding L3, the other end of the capacitor C6 is connected with the anode of a diode D4 through a capacitor C7, and the cathode of the diode D4 is used as an output end of the phase-error voltage doubling circuit;

the anode of the diode D4 is connected with the cathode of the diode D3, the anode of the diode D3 is connected with the cathode of the diode D2, the anode of the diode D2 is connected with the cathode of the diode D1, and the anode of the diode D1 is grounded;

the common connection point between the capacitor C7 and the capacitor C6 is connected to the anode of the diode D2, one end of the capacitor C9 is used as a second input end of the phase-failure voltage doubling circuit to be connected to the different-name end of the secondary winding L4, the capacitor C9 is connected to the cathode of the diode D4 through the capacitor C8, the common connection point between the capacitor C8 and the capacitor C9 is connected to the anode of the diode D3, and through the structure and combining the connection relation of the parallel connection of the double primary windings and the equivalent series connection of the double secondary windings, the current capacity and the voltage doubling capacity of the phase-failure voltage doubling circuit can be effectively improved, and the load capacity of the whole converter is improved.

Taking fig. 1 as an example: when the electronic switching tube is turned on, the voltage of the primary winding of the transformer is positive and negative from top to bottom and is equal to the input voltage, the voltage of the secondary winding L3 is positive and negative from top to bottom, and the voltage of the secondary winding L4 is positive and negative from bottom, at the moment, D1, D3 and D5 are turned off, D2 and D4 are turned on, at the moment, the input voltage is converted from the primary winding of the transformer to the secondary winding (the turns ratio is set to be n), and flows through the voltage doubling circuit capacitor to form a loop 1: r7- & gt L3- & gt C6- & gt D2- & gt C9- & gt L4; loop 2: R7-L3-C6-C7-D4-C8-C9-L4.

When the electronic switching tube is turned off, exciting current of the primary winding of the transformer flows to the secondary side through the primary side winding of the ideal transformer, back voltage Vr on the primary windings L1 and L2 of the transformer is reflected by the secondary windings L3 and L4, current commutations are carried out at the moment, D1, D3 and D5 are conducted, D2 and D4 are turned off, and a loop circuit 3 is formed: d1→c6→l3→r7; loop 4: l4→c9→d3→c7→c6→l3→r7 and loop 5: l4→c9→c8→d5→output side.

The number of turns of the transformer is n, the directions of voltages of L1, L2, L3, C6, C7, C8 and C9 are positive and negative, L4 is positive and negative, and the direction of the reflected voltage Vr at the primary winding side of the transformer is opposite to the direction of the input voltage Vin; the drop in the sense resistor R7 is negligible here, and for loop 1 there is equation (1) according to KVL's law, equivalent to twice the input voltage converted to the secondary winding side voltage, C9 charge, C6 reverse discharge,

V _C9 ＝ V _C6 +2n·Vin (1)

for loop 2, having equation (2), equivalent to doubling the input voltage to the secondary winding side voltage, charge C9 and C8, where C6 and C7 discharge in opposite directions,

V _C8 +V _C9 ＝ 2n·Vin + V _C6 +V _C7 (2)

for the loop 3 with the formula (3), the freewheel current converted from the exciting inductance to the secondary side charges C6 through D1, so as to prepare for voltage superposition and C6 external discharge when the switch electronic switching tube is conducted,

V _C6 ＝n·Vr (3)

for loop 4, of formula (4), this corresponds to a double back pressure superimposed on C9, charging C6 and C7, discharging C9 in reverse,

V _C6 +V _C7 ＝ 2n·Vr+V _C9 (4)

for the loop 5 with the formula (5), the exciting current is converted into the follow current of the exciting current, the secondary side is charged to the output side through the loop, the voltage doubling process is completed, and the output voltage can be obtained by KVL

Vo ＝ n*Vr + V _C9 +V _C8 (5)

The solving step for each element voltage on the secondary winding side is as follows: loop 3 (electronic switching tube off) →loop 1 (electronic switching tube on) →loop 4 (electronic switching tube off) →loop 2 (electronic switching tube on) →loop 5 (electronic switching tube off) are substituted in order to solve the available formulas (6) to (10)

V _C6 ＝ n·Vr (6)

V _C9 ＝ n·Vr+2·Vin/n (7)

V _C7 ＝ 2n·Vr+2·Vin/n (8)

V _C8 ＝ 2n·Vr+2·Vin/n (9)

Vo ＝ 4n·(Vr+Vin) (10)

By the structure of the phase-dislocation charging, the side voltage of the secondary winding is greatly raised, and the overall voltage gain of the converter is improved; compared with the prior art, the charging speed is obviously improved, which is twice that of the prior single-ended charge pump, so that the time of the converter in the CCM charging boosting stage in the starting process is reduced, the heating and the loss are effectively reduced, and the size integration is facilitated; the voltage of the secondary winding of the transformer to the ground is reduced to half of the voltage of the existing single-ended charge pump (single-ended voltage doubling circuit), so that the withstand voltage of the transformer is reduced; the whole circuit has simple structure, reduces the number of diodes and capacitors used in the voltage doubling structure of the charge pump, reduces the volume and the cost, and simultaneously reduces the working loss in the reverse recovery process of the conduction and the voltage resistance of the diode.

In this embodiment, the circuit further includes a first sampling circuit, where the first sampling circuit includes a capacitor C4, a capacitor C5, a resistor R6, and a resistor R8;

one end of a resistor R6 is connected between the output end of the electronic switching tube and a sampling resistor R5, the other end of the resistor R6 is connected to the synonym end of a secondary winding L3 through a resistor R8, a common connection point between the resistor R8 and the resistor R6 is grounded through a capacitor C5, the common connection point between the resistor R8 and the resistor R6 is connected to one end of a capacitor C4, the other end of the capacitor C4 is used as the output end of a sampling circuit, a collected current signal of the sampling circuit is input into a controller, and the controller controls to turn off the electronic switching tube according to the sampling signal.

Wherein: the first sampling circuit is used for accurately sampling peak (saturation) current of a transformer, the sampling detection of exciting current of a traditional flyback converter usually adopts a primary winding side series sampling resistor, as shown in fig. 1, a resistor R5 is a sampling resistor, and in order to improve gain and charging boosting performance, a charge pump-based phase-dislocation voltage doubling structure is added at a secondary winding side of the flyback converter in the topology structure; due to the working characteristics of the charge pump, the pump capacitor is repeatedly charged and discharged according to the on/off state, so that voltage superposition is realized; at the moment of switching on/off state, an equivalent RC charging current of a pump capacitor charging and discharging voltage difference flows through the secondary winding and is coupled to the primary winding, a waveform (shown as a fourth waveform chart in fig. 4) of superposition of two parts of current of a real exciting current (triangular wave) and an equivalent RC charging current (steamed bread wave) is observed at a Vp node above a current detection resistor R5, if the current waveform is directly sampled by using the existing scheme, the aliasing phenomenon of the current waveform directly influences the accuracy of peak exciting current detection, thereby influencing an integral control loop and causing the system breakdown of the converter. Therefore, the first sampling circuit structure is adopted, current sampling is carried out by simultaneously connecting current detection resistors R5 and R6 in series in the primary winding and the secondary winding, and the distortion waves at the primary winding side and the secondary winding side are cancelled through the addition of the resistors R6 and R8, so that a real exciting current rising peak waveform is obtained, and accurate sampling feedback and control are realized.

In this embodiment, the self-adaptive dc bias circuit further includes a not gate circuit A1, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a capacitor C12, and a capacitor C13;

the input end of the NOT gate circuit A1 is connected to the input pin of the controller, the NOT gate circuit is connected to the output pin of the controller, the output end of the NOT gate circuit A1 is connected to one end of a capacitor C12 through a resistor R12, the other end of the capacitor C12 is grounded, a common connection point between the capacitor C12 and the resistor R12 is connected to the input end of the NOT gate circuit A1, one end of a resistor R13 is connected to the common connection point between the resistor R12 and the capacitor C12, the other end of the resistor R13 is grounded through a capacitor C13, the common connection point between the capacitor C13 and the resistor R13 is grounded after being connected in series through a resistor R14 and a resistor R15, and the common connection point between the resistor R14 and the resistor R15 is used as the output end of a direct current bias circuit to be connected to one end of a capacitor C4 as the output end of the sampling circuit. Through the structure, the adaptability of the application can be enhanced, a miniature analog chip can be used as a controller to control the operation of the whole system, the cost is reduced, under the structure, the self-adaptive direct current bias voltage synchronously changes along with the triggering threshold value of the actual digital input mode, meanwhile, the input pin can be further configured with a LVD (Low Voltage Digital) digital input mode according to the actual application requirement, the input pin has a very small and stable hysteresis range, the gain relation between the input pin and the fluctuation of the power supply voltage is smaller or does not change along with the fluctuation of the power supply voltage, the absolute and relative stability of the direct current bias voltage is synchronously ensured, the node TFB is connected with the input pin of the analog control chip and is configured into a digital input mode (nanosecond delay and lower hysteresis range), A1 is a logic NOT gate in the chip, and TIO is the output pin of the analog control chip and is used for carrying out high-low level pulse jump. When the TIO output is at a high level, a low-pass filter is formed by R12 and C12 for charging, the TFB node voltage VTFB is approximately linearly increased in a TIO change period, when the VTFB is increased to the chip digital input hysteresis upper threshold value, the trigger logic judges that the signal is high, the signal is low after being inverted through A1, the pin TIO outputs a low level, the R12 and the C12 start discharging, the TFB node voltage VTFB is approximately linearly decreased, when the VTFB is reduced to the chip digital input hysteresis lower threshold value, the trigger logic judges that the signal is low, the signal is high after being inverted through A1, and the TIO pin outputs a high level, so that the trigger logic reciprocates. The average value of the voltage VTFB of the TFB node is equal to the midpoint of the threshold value (consistency of IO characteristics of a control chip) of the digital input mode logic judgment of each pin of the chip, and the self-adaptive accurate tracking can be performed according to the individual differences of different chips. Meanwhile, the charging and discharging time of the equivalent RC can be adjusted by adjusting the values of R12 and C12, the frequency of the VTFB voltage ripple can be adjusted, and the response bandwidth of the system can be adjusted; r13 and C13 form an RC low-pass filter, the resistor R14 and the resistor R15 form a resistor divider, and the direct-current bias voltage output to IDC is regulated by regulating the voltage dividing ratio; the peak exciting current alternating current signal sampled at IAC is overlapped on the direct current component of IDC (namely the midpoint of the threshold value of the digital input mode self-adaptive tracking of the control chip) through a direct-isolation coupling capacitor C4, and a node IDC is connected to the input pin of the control chip and is configured to be of the same digital input type as the TFB pin (the IO characteristic of the control chip keeps consistent); the IAC alternating current signal amplitude and sampling signal-to-noise ratio adjustment is realized by adjusting the resistors R5, R6, R8 and R7, the direct current bias voltage injected by the IDC node is matched, the matching with the digital input trigger threshold hysteresis range can be realized, the digital input mode of the pins of the analog control chip can be optimized and improved into a self-adaptive high-speed comparator, the self-adaptive high-speed comparator can achieve the high-speed sampling and comparator response level of the high-precision digital control chip, the peak exciting current sampling signal is accurately judged in nanosecond delay, the MOS tube is turned off, the sampling and control loop performance of the MOS tube is greatly improved under the low-cost design, and the self-adaptive high-speed comparator has the anti-interference capability on voltage fluctuation. The control chip (i.e. the controller) adopts the existing analog chip, such as GreenPAK SLG 46855.

In this embodiment, the second sampling circuit further includes a capacitor C14, a resistor R16, a capacitor C15, and a resistor R17;

one end of the capacitor C14 is used as the input end of the second sampling circuit and is connected with the input end of the electronic switching tube, the other end of the capacitor C14 is connected with one end of the resistor R17 through the resistor R16, the other end of the resistor R17 is grounded, the common connection point between the resistor R16 and the resistor R17 is grounded through the capacitor C15, and the common connection point between the resistor R16 and the resistor R17 is used as the output end QR of the second sampling circuit _{_Detect} . The QR resonance valley voltage detection principle is that a flyback converter works under DCM, an MOS transistor junction capacitor forms main resonance with an excitation inductor after the current at the secondary winding side is reduced to zero, and when the MOS transistor end voltage is detected to resonate to a valley point, a MOS transistor turn-on signal is triggered to realize QR quasi-resonance soft switching, therefore, through the structure, a dynamic voltage division network is formed by C14 and C15 to sample Vds and regulate and input the Vds into a control chip, wherein the core detection principle is a high-pass filter structure formed by C14 and R17, and the high-pass filter structure can represent the voltage slope change of the switching transistor end voltage Vds at the moment of upward anti-picking after passing through the valley point of the QR resonance voltage, so that the QR resonance valley voltage detection triggering is realized; wherein C15 and C14 form a dynamic voltage divider to adjust sampling inversionThe feed signal amplitude, R16, acts as a current limiting function.

In this embodiment, the voltage regulator further includes a clamp absorption circuit, where the clamp absorption circuit includes a capacitor C3, a resistor R4, and a voltage regulator ZD1;

one end of the capacitor C3 and one end of the resistor R4 are connected in parallel to the homonymous end of the primary winding L1, the other end of the capacitor C3 and the resistor R4 are connected to the cathode and the anode of the voltage stabilizing tube ZD1, and the anode of the voltage stabilizing tube ZD1 is connected to the heteronymous end of the primary winding L1.

In this embodiment, the voltage stabilizing circuit further includes a filtering voltage stabilizing circuit, where the filtering voltage stabilizing circuit includes a resistor R1, a resistor R2, a resistor R3, a capacitor C1, and a capacitor C2;

one end of the resistor R1 is connected to the output end of the direct current power supply, the other end of the resistor R1 is grounded through the capacitor C1, a common connection point between the resistor R1 and the direct current power supply is grounded through the capacitor C2, the common connection point between the resistor R1 and the capacitor C2 is grounded after being connected in series through the resistor R3 and the resistor R2, the common connection point between the resistor R2 and the resistor R3 is connected to the detection input end of the controller, through the structure, the stability and decoupling of the direct current bus voltage connected with the direct current power supply when the converter is in working states such as charge and discharge of a phase-failure voltage doubling circuit and circuit resonance can be ensured, the resistor R2 and the resistor R3 form a voltage division detection circuit, the common point connection point VIS outputs detection voltage to the control chip, and the electronic switch tube is controlled to be turned off when under voltage is reduced, so that protection is realized.

In this embodiment, the output circuit further includes a diode D5, a capacitor C10, a capacitor C11, a resistor R9, a resistor R10, and a resistor R11;

the anode of the diode D5 is used as an input end of the output circuit, the cathode of the diode D5 is connected to one end of the resistor R9, the other end of the resistor R9 is grounded through the capacitor C11, and a common connection point between the capacitor C11 and the resistor R9 is used as an output end of the output circuit;

the common connection point between the resistor R9 and the cathode of the diode D5 is grounded through a capacitor C10, one end of the resistor R10 is connected to the common connection point between the capacitor C11 and the resistor R9, the other end of the resistor R10 is grounded through a resistor R11, and the common connection point VOS between the resistor R10 and the resistor R11 is connected to the detection input end of the controller. The control chip controls the MOS tube to be turned off according to the feedback voltage of the VOS point, so that the peak voltage control of the outer ring is realized, and the C10, C11 and the resistor R9 form a pi-type filter.

The following is further described in one specific example:

for example, when the application is applied to a high-voltage power supply, 12V direct-current voltage is increased to 1600V and output, and the turns ratio of the primary winding and the secondary winding of the transformer is set as 1:12, the upper limit Im of excitation saturation detection is 5A, the input pin of a control chip for detecting the QR resonance valley voltage and peak excitation current is configured into a digital input mode (low cost and high response speed), and other elements perform reasonable device type selection and parameter setting on the converter according to the technical scheme of the application.

Configuring digital input for QR valley voltage detection into Schmitt trigger mode (trigger decision threshold hysteresis range: 1.5V-3V), performing QR resonance voltage valley detection according to the characteristic of the input pin shown in FIG. 2, when C15 is not counted, C14 and R17 form a standard high-pass filter structure, performing differential operation equivalent to C14 on the signal, and performing QR _{_Detect} The node obtains the slope of the Vds resonance voltage; based on the method, the equivalent dynamic voltage division is carried out on the signal amplitude from Vds to ground by using C15, and the matching adjustment can be carried out according to the digital input mode trigger threshold of the control chip. The frequency of the Vds resonance voltage is set to be 2M, and the resonance amplitude of the Vds resonance voltage reaches the ZVS soft switching requirement; to set C14 to 50pF, R17 can be realized by the control chip input pull-down resistor to be set to 10kΩ, C15 can be realized by the parasitic capacitance of the input pin itself to be set to 2.5pF; meanwhile, in order to avoid overcurrent of an input pin, a 100 omega current-limiting resistor R16 is connected in series in the circuit, so that QR is achieved _{_Detect} Node and V _ds The equivalent signal transfer function between can be expressed as M=1/[ SR16 C15+1/(SR 17C 14) + (R16/R17+C15/C14+1)]＝1/[0.00000025S+1/(0.0005S)+1.06]. When the Vds resonance voltage passes through the valley value and is reversely chosen instantly, the transfer function will be positively increased along with the slope of the Vds resonance voltage, so that the QR is enabled to be _{_Detect} The node feedback signal reaches the upper limit (3V) of the trigger threshold of the digital input mode of the input pin of the control chip, and the trigger signal is enabled to be turned on. At the same time byDuring the turn-off period of the switch MOS Guan Gang, the leakage inductance of the transformer and the junction capacitance of the switch tube generate high-frequency small-amplitude resonance, and the digital input mode with a larger trigger judgment hysteresis range is selected to have a certain filtering effect on the interference resonance, but a certain margin (the quantitative analysis can be carried out according to the resonance frequency, the amplitude and the threshold trigger signal strength when necessary) is still needed to be remained for blanking treatment on the QR valley voltage detection in a certain time just after turn-off, so that false triggering is prevented.

Value exciting current detection parameter design

The digital input for peak exciting current detection is to be configured into an LVD trigger mode, the judging threshold hysteresis range is 808 mV-812 mV, the threshold midpoint (810 mV) can be obtained by the bias voltage generating circuit of the high-speed self-adaptive comparator shown in fig. 2, wherein the system ripple response between the low-pass filter formed by R12 and C12 and the control chip can be designed in a compromise manner between the system response and the stability according to actual selection, and the system ripple response is to be set as MHz level ripple; the second stage filter circuit formed by R13 and C13 filters out response ripple as much as possible, and further enables the signal to form direct current bias voltage at the node IDC after passing through the resistor divider formed by R14 and R15.

Assuming that the primary winding side current detecting resistor R5 is 20 milliohms, assuming that x=3 expands the signal to noise ratio, and the relation between the IAC node voltage amplitude and the primary winding side resistance current detecting resistor R5 is V _IAC ＝R5·(2·Im)·[2x/(x+1)]＝20·(2·5)·[(2·3)/(3+1)]=300 mV. The voltage spacing between the dc bias voltage and the upper limit of the digital input mode trigger threshold should be set to be half of the ac signal, i.e., 150mV (node IAC is equal to IDC ac component); the dc bias voltage should be set to 812mV-150mV = 662mV; therefore, the ratio of the voltage dividing resistors of the direct current bias voltage generating circuit is (R12+R13+R14)/R15=150 mV/662mV, and the model selection design can be carried out according to the actual resistance value.

As shown in fig. 4, the converter works under the steady-state DCM, and the voltage waveform at the time of resonance of the switch MOS tube end voltage Vds (such as the first waveform diagram in fig. 4) is accurately captured by the reverse-picking instantaneous slope change after passing through the valley, the conduction signal is triggered, and the MOS tube gate driving signal (such as the second waveform diagram in fig. 4) is set high by the QR valley voltage detection parameter design; meanwhile, by means of the scheme, the peak exciting current detection circuit accurately samples the upper limit of exciting current of the transformer (IDC node voltage is a curve above a third waveform diagram in FIG. 4), timely logic judgment is carried out through the design of the high-speed self-adaptive comparator, a turn-off signal is triggered, and a MOS tube grid driving signal is set to be low. In fig. 4, the lower curve in the third waveform chart is a node IAC voltage waveform, which characterizes the transformer exciting current waveform, and in fig. 4 is an equal-proportion transformed sampling waveform (the transformation ratio can be adjusted according to the comparator threshold and the signal-to-noise ratio requirement) of the current detection resistor of the primary winding side Vp (the fourth waveform chart in fig. 4) and the secondary winding side Vs (the fifth waveform chart in fig. 4) nodes; according to graph and text, the exciting current extraction circuit based on primary winding side and secondary winding side abnormal wave cancellation can effectively offset current distortion waveforms (equivalent RC charging) caused by a secondary winding side charge pump, and accurately extract peak exciting current to obtain IAC, and then the IAC alternating current signal is lifted to a threshold midpoint of digital input mode self-adaptive tracking of a control chip through the self-adaptive bias voltage generation circuit, high-speed comparator logic judgment is further carried out on IDC, and peak exciting current accuracy is greatly improved.

Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present application, which is intended to be covered by the scope of the claims of the present application.

Claims (8)

1. A miniature high-gain quasi-resonant flyback converter is characterized in that: the device comprises a transformer, an electronic switching tube and a phase-error voltage doubling circuit;

the transformer comprises a primary winding L1, a primary winding L2, a secondary winding L3 and a secondary winding L4;

the same-name ends of the primary winding L1 and the primary winding L2 are connected to the positive electrode of the direct-current power supply, the different-name ends of the primary winding L1 and the primary winding L2 are connected to the input end of an electronic switching tube, the output end of the electronic switching tube is grounded through a resistor R5, and the control end of the electronic switching tube is connected to a controller;

the error phase voltage doubling circuit is provided with a first input end and a second input end, the first input end of the error phase voltage doubling circuit is connected to the homonymous end of the secondary winding L3, the heteronymous end of the secondary winding L3 is grounded through a resistor R7, the second input end of the error phase voltage doubling circuit is connected to the heteronymous end of the secondary winding L4, the homonymous end of the secondary winding L4 is grounded, and the output end of the error phase voltage doubling circuit supplies power to a load.

2. The miniature high gain quasi-resonant flyback converter of claim 1 wherein: the phase-shifting voltage doubling circuit comprises a capacitor C6, a capacitor C7, a diode D1, a diode D2, a diode D3, a diode D4, a capacitor C8 and a capacitor C9;

one end of a capacitor C6 is used as a first input end of the phase-error voltage doubling circuit and is connected with the same-name end of the secondary winding L3, the other end of the capacitor C6 is connected with the anode of a diode D4 through a capacitor C7, and the cathode of the diode D4 is used as an output end of the phase-error voltage doubling circuit;

the anode of the diode D4 is connected with the cathode of the diode D3, the anode of the diode D3 is connected with the cathode of the diode D2, the anode of the diode D2 is connected with the cathode of the diode D1, and the anode of the diode D1 is grounded;

the common connection point between the capacitor C7 and the capacitor C6 is connected to the anode of the diode D2, one end of the capacitor C9 is used as a second input end of the phase-dislocation voltage doubling circuit to be connected to the synonym end of the secondary winding L4, the capacitor C9 is connected to the cathode of the diode D4 through the capacitor C8, and the common connection point between the capacitor C8 and the capacitor C9 is connected to the anode of the diode D3.

3. The miniature high gain quasi-resonant flyback converter of claim 2 wherein: the circuit also comprises a first sampling circuit, wherein the first sampling circuit comprises a capacitor C4, a capacitor C5, a resistor R6 and a resistor R8;

one end of a resistor R6 is connected to the output end of the electronic switch tube, the other end of the resistor R6 is connected to the synonym end of the secondary winding L3 through a resistor R8, a common connection point between the resistor R8 and the resistor R6 is grounded through a capacitor C5, the common connection point between the resistor R8 and the resistor R6 is connected to one end of a capacitor C4, and the other end of the capacitor C4 is used as the output end of the sampling circuit.

4. A miniature high gain quasi-resonant flyback converter according to claim 3 wherein: the self-adaptive direct-current bias circuit comprises a NOT gate circuit A1, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a capacitor C12 and a capacitor C13;

the input end of the NOT gate circuit A1 is connected to the input pin of the controller, the NOT gate circuit is connected to the output pin of the controller, the output end of the NOT gate circuit A1 is connected to one end of a capacitor C12 through a resistor R12, the other end of the capacitor C12 is grounded, a common connection point between the capacitor C12 and the resistor R12 is connected to the input end of the NOT gate circuit A1, one end of a resistor R13 is connected to the common connection point between the resistor R12 and the capacitor C12, the other end of the resistor R13 is grounded through a capacitor C13, the common connection point between the capacitor C13 and the resistor R13 is grounded after being connected in series through a resistor R14 and a resistor R15, and the common connection point between the resistor R14 and the resistor R15 is used as the output end of the self-adaptive DC bias circuit to be connected to one end of the capacitor C4 as the output end of the sampling circuit.

5. The miniature high gain quasi-resonant flyback converter of claim 1 wherein: the second sampling circuit comprises a capacitor C14, a resistor R16, a capacitor C15 and a resistor R17;

one end of the capacitor C14 is used as the input end of the second sampling circuit and is connected with the input end of the electronic switching tube, the other end of the capacitor C14 is connected with one end of the resistor R17 through the resistor R16, the other end of the resistor R17 is grounded, the common connection point between the resistor R16 and the resistor R17 is grounded through the capacitor C15, and the common connection point between the resistor R16 and the resistor R17 is used as the output end QR of the second sampling circuit _{_Detect} 。

6. The miniature high gain quasi-resonant flyback converter of claim 1 wherein: the power supply circuit further comprises a clamp absorption circuit, wherein the clamp absorption circuit comprises a capacitor C3, a resistor R4 and a voltage stabilizing tube ZD1;

one end of the capacitor C3 and one end of the resistor R4 are connected in parallel and then connected to the homonymous end of the primary winding L1, the other end of the capacitor C3 and the resistor R4 are connected to the cathode of the voltage stabilizing tube ZD1, and the anode of the voltage stabilizing tube ZD1 is connected to the heteronymous end of the primary winding L1.

7. The miniature high gain quasi-resonant flyback converter of claim 1 wherein: the filter voltage stabilizing circuit comprises a resistor R1, a resistor R2, a resistor R3, a capacitor C1 and a capacitor C2;

one end of the resistor R1 is connected to the output end of the direct current power supply, the other end of the resistor R1 is grounded through the capacitor C1, a common connection point between the resistor R1 and the direct current power supply is grounded through the capacitor C2, the common connection point between the resistor R1 and the capacitor C2 is grounded after being connected in series through the resistor R3 and the resistor R2, and the common connection point between the resistor R2 and the resistor R3 is connected to the detection input end of the controller.

8. The miniature high gain quasi-resonant flyback converter of claim 1 wherein: the output circuit comprises a diode D5, a capacitor C10, a capacitor C11, a resistor R9, a resistor R10 and a resistor R11;

the anode of the diode D5 is used as an input end of the output circuit, the cathode of the diode D5 is connected to one end of the resistor R9, the other end of the resistor R9 is grounded through the capacitor C11, and a common connection point between the capacitor C11 and the resistor R9 is used as an output end of the output circuit;

the common connection point between the resistor R9 and the cathode of the diode D5 is grounded through a capacitor C10, one end of the resistor R10 is connected to the common connection point between the capacitor C11 and the resistor R9, the other end of the resistor R10 is grounded through a resistor R11, and the common connection point between the resistor R10 and the resistor R11 is connected to the detection input end of the controller.