CN116805652A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDF

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Publication number
CN116805652A
CN116805652A CN202310105330.6A CN202310105330A CN116805652A CN 116805652 A CN116805652 A CN 116805652A CN 202310105330 A CN202310105330 A CN 202310105330A CN 116805652 A CN116805652 A CN 116805652A
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China
Prior art keywords
layer
semiconductor region
gate
semiconductor device
electrode
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Inventor
中村研贵
塚田能成
小堀俊光
前田康宏
米田真也
根来佑树
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Honda Motor Co Ltd
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Honda Motor Co Ltd
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Publication of CN116805652A publication Critical patent/CN116805652A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a semiconductor device. A semiconductor device (10) is provided with: n is n + A source layer (18) and a source electrode (12); n is n ‑ A drift layer (16) and a drain electrode (11); having the following n + Source layers (18) and n ‑ And a p base layer (17) of a channel section (17 b) separated by the drift layer (16). A semiconductor device (10) is provided with a gate oxide film (15) and n + Source layer (18), channel portion (17 b), and n ‑ Grid electrodes n adjacent to each other in the drift layer (16) ‑ Layer (19) and gate p layer (20). Grid n ‑ Layer (19) and gate p layer (20) are along n + Source layer (18), channel portion (17 b)n ‑ The drift layers (16) are adjacent to each other in the direction in which they are arranged in sequence. A semiconductor device (10) is provided with a first gate electrode (13) bonded to a gate p layer (20) and a gate n ‑ And a second gate electrode (14) to which the layer (19) is bonded.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips
Technical Field
The present invention relates to a semiconductor device.
Background
Conventionally, a semiconductor device having a so-called superjunction structure in which n-type columnar regions and p-type columnar regions are alternately arranged in parallel in a drift region is known (for example, refer to japanese patent application laid-open No. 2000-40822).
Disclosure of Invention
In the above-described conventional semiconductor device, it is desirable to ensure a desired withstand voltage between the drain electrode and the source electrode and to reduce on-resistance at the same time. For example, it is desirable to increase the current density by increasing the impurity concentration of the drift region, and to secure a desired depletion region (for example, depletion of the entire region of the columnar region) by decreasing the width (length in the arrangement direction) of the columnar region of different conductivity types formed in the drift region, thereby securing a desired withstand voltage and increasing the current density. However, for example, the aspect ratio of the columnar region is limited by a manufacturing process such as a deep trench, and thus, it is difficult to secure a desired withstand voltage and to increase the current density.
An object of an embodiment of the present invention is to provide a semiconductor device capable of improving current density while ensuring a desired withstand voltage, and improving energy efficiency.
The semiconductor device according to the first aspect of the present invention includes: a first semiconductor region of a first conductivity type; a first electrode bonded to the first semiconductor region; a second semiconductor region of the first conductivity type; a second electrode bonded to the second semiconductor region; a third semiconductor region of a second conductivity type having a channel portion separating the first semiconductor region from the second semiconductor region; an insulator adjacent to the first semiconductor region, the second semiconductor region, and the channel portion, respectively; a gate semiconductor region adjacent to the first semiconductor region, the second semiconductor region, and the channel portion, respectively, with the insulator interposed therebetween; and a first gate electrode and a second gate electrode bonded to both ends of the gate semiconductor region in a direction along which the first semiconductor region, the channel portion, and the second semiconductor region are sequentially arranged, wherein the gate semiconductor region includes: a fourth semiconductor region of the second conductivity type bonded to the first gate electrode arranged on the first semiconductor region side in the arrangement direction; and a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and bonded to the second gate electrode arranged on the second semiconductor region side in the arrangement direction.
A second aspect of the present invention provides the semiconductor device according to the first aspect, wherein the semiconductor device includes a rectifying portion having a rectifying function between the second electrode and the second gate electrode.
In a third aspect of the present invention, in the semiconductor device according to the second aspect, the rectifying unit may include: a sixth semiconductor region of the first conductivity type bonded to the second gate electrode; and a seventh semiconductor region of the second conductivity type adjacent to the sixth semiconductor region and bonded to the second electrode, wherein the second gate electrode, the sixth semiconductor region, and the seventh semiconductor region are adjacent to the second semiconductor region via the insulator.
A fourth aspect of the present invention provides the semiconductor device according to any one of the first to third aspects, wherein an interface between the second semiconductor region and the third semiconductor region and an interface between the fourth semiconductor region and the fifth semiconductor region are included in the same plane.
A fifth aspect of the present invention provides the semiconductor device according to any one of the first to fourth aspects, wherein the semiconductor device includes an eighth semiconductor region of the second conductivity type, the eighth semiconductor region being adjacent to the third semiconductor region in the arrangement direction, and the eighth semiconductor region being adjacent to the second semiconductor region in a direction in which the gate semiconductor region and the second semiconductor region are adjacent to each other with the insulator interposed therebetween.
A sixth aspect of the present invention provides the semiconductor device according to the fifth aspect, wherein the impurity concentrations of the second semiconductor region and the eighth semiconductor region are set according to the ratio of the sizes of the second semiconductor region and the eighth semiconductor region.
According to the first aspect, since the gate semiconductor region is provided adjacent to the second semiconductor region and the channel region via the insulator, the accumulation layer can be formed in the second semiconductor region by applying a voltage to the gate semiconductor region at the time of conduction, and the current density can be increased.
By providing the first gate electrode and the second gate electrode bonded to both end portions of the gate semiconductor region, the respective potentials on the first gate electrode side and the second gate electrode side of the gate semiconductor region can be appropriately set at the time of voltage withstand or the like. The fourth semiconductor region of the second conductivity type and the fifth semiconductor region of the first conductivity type are arranged along the direction in which the third semiconductor region of the second conductivity type (channel portion) and the second semiconductor region of the first conductivity type are arranged, whereby a depletion layer can be formed in the gate semiconductor region in addition to the third semiconductor region and the second semiconductor region at the time of voltage resistance. Depletion layers are formed on both sides of the insulator in a direction in which the third semiconductor region and the second semiconductor region are adjacent to the gate semiconductor region with the insulator interposed therebetween, whereby it is possible to suppress the occurrence of an excessive electric field acting on the insulator.
In the case of the second aspect, the rectifying portion is provided between the second electrode and the second gate electrode, so that connection to the outside such as a load can be facilitated. The desired potential of each of the second electrode and the second gate electrode can be appropriately set at the time of conduction, the time of withstand voltage, and the like.
In the case of the third aspect, the rectifying portion may be integrally provided with the gate semiconductor region via the second gate electrode, and the second electrode may be disposed so as to extend to both sides of the insulator in a direction in which the sixth semiconductor region and the seventh semiconductor region are adjacent to the second semiconductor region with the insulator interposed therebetween. For example, compared with the case where different electrodes are arranged on both sides of the insulator, the case where the first electrode side is the front surface side, that is, the second electrode side does not require separate fabrication of the different electrodes, and thus the process of fabricating the electrodes can be suppressed from becoming complicated.
In the case of the fourth aspect, the potential distribution in the depletion layer formed in the third semiconductor region and the second semiconductor region can be made equal to the potential distribution in the depletion layer formed in the gate semiconductor region at the time of voltage withstand, and the situation in which an electric field acts on the insulator can be suppressed.
In the case of the fifth aspect, the so-called superjunction structure in which the second semiconductor region of the first conductivity type is arranged adjacent to the eighth semiconductor region of the second conductivity type can ensure a desired withstand voltage, and the impurity concentration of the second semiconductor region can be increased to increase the current density.
In the case of the sixth aspect, even when the ratio of the sizes of the second semiconductor region and the eighth semiconductor region is appropriately set in accordance with, for example, ensuring a desired current density, the impurity concentrations of the second semiconductor region and the eighth semiconductor region can be appropriately set so as to maintain a desired charge compensation, and a desired withstand voltage can be easily ensured.
Drawings
Fig. 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a cross-sectional view of a half cell showing a state of the semiconductor device in the on state in the embodiment of the present invention.
Fig. 3 is a diagram showing an example of a relationship between drain voltage and drain current at the time of conduction in each of the semiconductor device according to the embodiment of the present invention and the semiconductor device of the comparative example.
Fig. 4 is a diagram showing an example of a relationship between a position at an A-A line of a cross section of the semiconductor device and electron density at the time of conduction in the embodiment of the present invention.
Fig. 5 is a cross-sectional view of a half cell showing a state in which the semiconductor device is voltage-resistant in the embodiment of the present invention.
Fig. 6 is a cross-sectional view of a half cell showing a state of the semiconductor device in the on state in the first modification of the embodiment of the present invention.
Fig. 7 is a cross-sectional view of a half cell showing a state at the time of on of the semiconductor device in the second modification of the embodiment of the present invention.
Fig. 8 is a diagram showing an example of the relationship between the drain voltage and the drain current at the time of conduction in each of the semiconductor device of the second modification example and the semiconductor device of the comparative example according to the embodiment of the present invention.
Fig. 9 is a cross-sectional view of a half cell showing a state at the time of on of the semiconductor device in the third modification of the embodiment of the present invention.
Fig. 10 is a perspective view showing a state of the semiconductor device in the fourth modification of the embodiment of the present invention when the semiconductor device is turned on.
Fig. 11 is a cross-sectional view of a half cell showing a state at the time of on of the semiconductor device in the fifth modification of the embodiment of the present invention.
Detailed Description
Hereinafter, a semiconductor device 10 according to an embodiment of the present invention will be described with reference to the drawings.
Fig. 1 is a cross-sectional view showing the structure of a semiconductor device 10 according to the embodiment.
As shown in fig. 1, a semiconductor device 10 according to an embodiment includes, for example, a MOSFET (Metal Oxide semiconductor field effect transistor) formed on a substrate.
The substrate being composed of Si, siC, gaN or Ga 2 O 3 Etc. Is required toThe semiconductor material is not limited. The semiconductor device 10 is, for example, a so-called vertical n-channel semiconductor device.
Hereinafter, each axis direction of the X axis, the Y axis, and the Z axis orthogonal to each other in the three-dimensional space is a direction parallel to each axis. For example, the X-axis direction is parallel to the width direction (so-called lateral direction) of the semiconductor device 10, the Y-axis direction is parallel to the thickness direction (so-called longitudinal direction) of the semiconductor device 10, and the Z-axis direction is parallel to the orthogonal direction (so-called depth direction) of the X-axis direction and the Y-axis direction.
The semiconductor device 10 of the embodiment includes a drain electrode 11 (second electrode), a source electrode 12 (first electrode), a first gate electrode 13, a second gate electrode 14, a gate oxide film 15 (insulator), and n - A drift layer 16 (second semiconductor region), a p base layer 17 (third semiconductor region), n + Source layer 18 (first semiconductor region), gate n - Layer 19 (gate semiconductor region, fifth semiconductor region) and gate p layer 20 (gate semiconductor region, fourth semiconductor region).
The drain electrode 11 is disposed at a first end portion of the semiconductor device 10, out of both end portions along the Y-axis direction. Drain electrode 11 is aligned with n along the Y-axis direction - The drift layer 16 is bonded.
The source electrode 12 is disposed at a second end portion of the semiconductor device 10, out of the two end portions along the Y-axis direction. The source electrode 12 is connected to the p base layer 17 and the n along the Y-axis direction + The source layers 18 are bonded respectively.
The first gate electrode 13 is arranged at a second end portion of the semiconductor device 10, out of the two end portions along the Y-axis direction. The first gate electrode 13 is arranged apart from the source electrode 12 along the X-axis direction. The first gate electrode 13 is bonded to the gate p layer 20 along the Y-axis direction.
The second gate electrode 14 is arranged at a first end portion of the two end portions of the semiconductor device 10 in the Y-axis direction. The second gate electrode 14 is arranged apart from the drain electrode 11 along the X-axis direction. The second gate electrode 14 is connected to the gate n along the Y-axis direction - The layers 19 are joined.
Gate oxide films 15 and n - Drift layer 16, p base layer 17, n + Source layer 18, gate n - Layer 1The 9 and gate p layers 20 are adjacent, respectively. The gate oxide film 15 will n - Drift layer 16, p base layer 17 and n + Source layer 18 and gate n - Layer 19 and gate p layer 20 are separated.
n - The drift layer 16 is formed of an n-type (n-type) semiconductor having a relatively small carrier concentration. n is n - The drift layer 16 is bonded to the drain electrode 11 along the Y-axis direction. n is n - The drift layer 16 is formed along the X-axis direction with the gate oxide film 15 and the gate n interposed therebetween - Layer 19 is adjacent.
The p base layer 17 is formed of a p-type (p-type) semiconductor. p base layer 17 to follow along the Y-axis direction and n - The drift layer 16 is laminated with n - The drift layer 16 is adjacent.
The p base layer 17 includes, for example, a contact portion 17a and a channel portion 17b. The contact portion 17a is joined to the source electrode 12 along the Y-axis direction. The channel portion 17b is formed by n along the Y-axis direction - Drift layers 16 and n + The source layer 18 is sandwiched from both sides. Channel portions 17b and n - Drift layer 16 and n + Source layer 18 is adjacent to form n - Drift layers 16 and n + The source layers 18 are separated. The channel portion 17b is adjacent to the gate p layer 20 along the X-axis direction with the gate oxide film 15 interposed therebetween.
n + The source layer 18 is formed of an n-type (n-type) semiconductor having a relatively large carrier concentration. n is n + The source layer 18 is adjacent to the channel portion 17b of the p base layer 17 so as to be stacked with the channel portion 17b along the Y axis direction. n is n + The source layer 18 is bonded to the source electrode 12 along the Y-axis direction.
Grid n - The layer 19 is formed of an n-type (n-type) semiconductor having a relatively small carrier concentration. For example, grid n - Carrier concentration of layer 19 with n - The carrier concentration of the drift layer 16 is the same. Grid n - Layer 19 is bonded to second gate electrode 14 along the Y-axis direction and is adjacent to gate p-layer 20. Grid n - Layer 19 is formed along the X-axis direction with gate oxide film 15 and n interposed therebetween - The drift layer 16 is adjacent.
The gate p layer 20 is formed of a p-type (p-type) semiconductor. For example, the carrier concentration of the gate p layer 20 is the same as that of the p base layer 17. The gate p layer 20 is bonded to the first gate electrode 13 along the Y-axis direction and to the gate n - Layer 19 is adjacent. The gate p layer 20 is formed along the X-axis direction with the gate oxide film 15 interposed between the channel portions 17b and n of the p base layer 17 + The source layers 18 are respectively adjacent.
For example, gates n adjacent along the Y-axis direction - The interface of layer 19 with gate p layer 20 and n adjacent along the Y-axis direction - The interface between the drift layer 16 and the p base layer 17 is contained in the same plane.
Fig. 2 is a cross-sectional view of half cell H showing a state of semiconductor device 10 in the embodiment at the time of conduction. As shown in fig. 1, the half cell H is one of a pair of symmetrical portions of the semiconductor device 10 having a symmetrical shape with respect to the Y-Z plane. Fig. 3 is a diagram showing an example (an example of simulation) of the relationship between the drain voltage and the drain current at the time of conduction in each of the semiconductor device 10 of the embodiment and the semiconductor device of the comparative example. Fig. 4 is a diagram showing an example (simulated example) of a relationship between a position at an A-A line of a cross section of the semiconductor device 10 and electron density at the time of conduction in the embodiment.
As shown in fig. 2, the semiconductor device 10 of the embodiment includes a first power source 31, a second power source 32, a load 33, and a diode 34 (rectifying unit). The first power supply 31 and the second power supply 32 are, for example, power supply circuits that switch the presence or absence of output, polarity inversion, and the like. The first power supply 31 and the second power supply 32 are power supply circuits for direct current, respectively.
The load 33 is connected between the first power supply 31 and the drain electrode 11.
The diode 34 is connected between the drain electrode 11 and the second gate electrode 14.
The diode 34 has an anode connected to the drain electrode 11 and a cathode connected to the second gate electrode 14. The forward direction of the diode 34 is the direction from the drain electrode 11 toward the second gate electrode 14.
When the semiconductor device 10 is turned on (i.e., turned on in the forward direction), the positive electrode of the first power supply 31 is connected to the load 33, and is connected to the drain electrode 11 via the load 33. The negative electrode of the first power supply 31 is connected to the source electrode 12 and the negative electrode of the second power supply 32. The positive electrode of the second power supply 32 is connected to the first gate electrode 13.
By a second electricity at the time of conduction of the semiconductor device 10Source 32 is directed to gate n - Layer 19 and gate p layer 20 are applied with a predetermined positive voltage to n adjacent to gate oxide film 15 - The drift layer 16 is formed with n + The accumulation layer 21 is formed with an n inversion layer 22 in the channel portion 17b adjacent to the gate oxide film 15.
n + The accumulation layer 21 accumulates n at the interface of the gate oxide film 15 - An n-type (n-type) semiconductor region having a relatively large carrier concentration formed by majority carriers in the drift layer 16.
The n inversion layer 22 is a region of an n-type (n-type) semiconductor formed by drawing minority carriers of the channel portion 17b toward the interface of the gate oxide film 15.
By forming n inversion layer 22 and n + An accumulation layer 21, whereby electron current EC1 flows from drain electrode 11 via n + Accumulation layer 21, n inversion layer 22 and n + The source layer 18 flows toward the source electrode 12.
When the semiconductor device 10 is turned on, for example, when the output voltage of the first power supply 31 is 1000V, the output voltage of the second power supply 32 is 15V, and the voltage drop of the load 33 is 998V, the potential of the drain electrode 11 is 2V, the potential of the source electrode 12 is 0V, the potentials of the first gate electrode 13 and the second gate electrode 14 are 15V, the voltages Vgs of the respective gate electrodes 13 and 14 with respect to the source electrode 12 are 15V, and the voltage Vds of the drain electrode 11 with respect to the source electrode 12 is 2V. In this case, the forward direction of the diode 34 is set in the direction from the drain electrode 11 toward the second gate electrode 14, and thus the current (reverse current) from the second gate electrode 14 toward the drain electrode 11 can be suppressed.
The comparative example shown in fig. 3 is, for example, a semiconductor device 10 of the embodiment without the first gate electrode 13, the second gate electrode 14, and the gate n - Super junction MOSFET of gate structure of layer 19 and gate p layer 20, semiconductor device of comparative example does not have n when turned on + Layer 21 is built up.
As shown in fig. 3, it is considered that drain currents Id (V1), id (V2), and Id (V3) at the time of conduction in the semiconductor device 10 of the embodiment are due to n + The accumulation layer 21 is larger than the drain current Ic at the time of conduction in the semiconductor device of the comparative example. The drain of the embodimentThe pole currents Id (V1), id (V2), id (V3) and the voltage Vgs of each gate electrode 13, 14 relative to the source electrode 12 are the first voltage V1, the second voltage V2 #>V1), third voltage V3>V2) corresponds to the case. For example, the first voltage V1 is 15V, the second voltage V2 is 20V, and the third voltage V3 is 30V. It is considered that the drain current Id increases as the voltage Vgs applied to each gate electrode 13, 14 increases.
As shown in fig. 4, n at the time of conduction in the semiconductor device 10 of the embodiment is considered to be - Electron density ratio n of the portion adjacent to the gate oxide film 15 in the drift layer 16 - The electron density of the other portion of the drift layer 16 is relatively high, and n is formed at a portion adjacent to the gate oxide film 15 + Layer 21 is built up.
Fig. 5 is a cross-sectional view of half cell H showing a state in the withstand voltage of semiconductor device 10 according to the embodiment.
As shown in fig. 5, when the semiconductor device 10 is voltage-resistant, the output voltage of the second power supply 32 is 0V, which is obtained by passing n - The barrier of the depletion layer 40a expanding by the drift layer 16 and the p base layer 17 cuts off the gap between the drain electrode 11 and the source electrode 12. By extending through the gate n - The barrier of the depletion layer 40b expanding by the layer 19 and the gate p layer 20 cuts off the gap between the first gate electrode 13 and the second gate electrode 14. Grid n - Interface of layer 19 with gate p-layer 20 and n - The interface between the drift layer 16 and the p base layer 17 is contained in the same plane, and therefore the potential distribution along the Y axis direction in the depletion layer 40a is the same as the potential distribution along the Y axis direction in the depletion layer 40 b. Thereby, both sides of the gate oxide film 15 along the X-axis direction are at the same potential.
In the withstand voltage of the semiconductor device 10, for example, when the output voltage of the first power supply 31 is 1000V, the output voltage of the second power supply 32 is 0V, and the voltage drop of the load 33 is 1V, the potentials of the drain electrode 11 and the second gate electrode 14 are 999V, the potentials of the source electrode 12 and the first gate electrode 13 are 0V, the voltage Vgs of the first gate electrode 13 with respect to the source electrode 12 is 0V, and the voltages Vds of the drain electrode 11 and the second gate electrode 14 with respect to the source electrode 12 are 999V. In this case, since the two sides of the gate oxide film 15 along the X-axis direction have the same potential, the application of an electric field to the gate oxide film 15 can be suppressed.
As described above, according to the semiconductor device 10 of the embodiment, the gate n is formed by - Voltage application at turn-on of layer 19 and gate p layer 20, thereby forming n - The drift layer 16 can form n + The accumulation layer 21 can increase the current density. In addition, by the opposite grid electrode n - By applying a voltage at the time of turning on the layer 19 and the gate p layer 20, an n-inversion layer 22 can be formed in the channel portion 17b, and switching between switching off and on of the device can be performed.
By having the gate n - First gate electrode 13 and second gate electrode 14 bonded to layer 19 and gate p layer 20, and thus gate n can be appropriately changed in withstand voltage or the like - The potential of each of layer 19 and gate p layer 20.
Grid n - Layer 19 and gate p layer 20 pass along n - The drift layer 16 is arranged in a direction (Y-axis direction) adjacent to the p base layer 17, and thus, when withstand voltage, except n - Outside the drift layer 16 and the p base layer 17, a gate n - The layer 19 and the gate p layer 20 can also form a depletion layer 40b. Depletion layers 40a and 40b are formed on both sides of the gate oxide film 15 along the X-axis direction, and thus, an excessive electric field can be prevented from being applied to the gate oxide film 15.
Grid n - Interface of layer 19 with gate p-layer 20 and n - The interface between the drift layer 16 and the p base layer 17 is contained in the same plane, and therefore the potential distribution along the Y axis direction in the depletion layer 40a is the same as the potential distribution along the Y axis direction in the depletion layer 40b. Thus, the same potential is applied to both sides of the gate oxide film 15 along the X-axis direction, and the application of an electric field to the gate oxide film 15 can be suppressed.
By providing the diode 34 connected between the drain electrode 11 and the second gate electrode 14, connection to the outside such as the load 33 can be facilitated. The desired potential of each of the drain electrode 11 and the second gate electrode 14 at the time of conduction, the time of withstand voltage, and the like can be appropriately set.
(modification)
A modification of the embodiment will be described below. The same reference numerals are given to the same parts as those of the above-described embodiments, and the description thereof is omitted or simplified.
In the above embodiment, the semiconductor device 10 includes the diode 34, but is not limited thereto.
Fig. 6 is a cross-sectional view of a half cell H showing a state of the semiconductor device 10A in the first modification of the embodiment at the time of conduction.
As shown in fig. 6, the semiconductor device 10A according to the first modification replaces the diode 34 according to the above-described embodiment, and includes the gate oxide film 15 and n along the X-axis direction - A part of the region adjacent to the drift layer 16 includes a p layer 51 (rectifying portion, seventh semiconductor region) and an n layer 52 (rectifying portion, sixth semiconductor region) adjacent to each other.
The semiconductor device 10A of the first modification replaces the second gate electrode 14 of the above-described embodiment, and includes the gate oxide film 15 and n along the X-axis direction - A part of the region adjacent to the drift layer 16 includes an n layer 52 and a gate n - The layer 19 sandwiches the second gate electrode 53 of the first modification from both sides in the Y-axis direction.
In the semiconductor device 10A of the first modification, the drain electrodes 11 are sequentially arranged in the Y-axis direction and in the X-axis direction, respectively - The drift layer 16, the gate oxide film 15, and the p layer 51 are adjacent to each other.
The p-layer 51 is formed of a p-type (p-type) semiconductor. The p-layer 51 is bonded to the drain electrode 11 along the Y-axis direction. The p layer 51 is formed along the X-axis direction with the gate oxide film 15 and n interposed therebetween - The drift layer 16 is adjacent.
The n layer 52 is formed of an n-type (n-type) semiconductor. The n layer 52 is adjacent to the p layer 51 so as to be laminated with the p layer 51 along the Y axis direction. n layer 52 is formed along the X-axis direction with gate oxide film 15 and n - The drift layer 16 is adjacent.
The second gate electrode 53 of the first modification is formed of an n-type (n-type) semiconductor or metal having a relatively large carrier concentration. A second gate electrode 53 along the Y-axis direction and n-layer 52 and gate n - Layer 19 is laminated with n layers 52 and gate n, respectively - Layer 19 is adjacent. The second gate electrode 53 is formed along the X-axis direction with the gate oxide film 15 and n interposed therebetween - The drift layer 16 is adjacent.
When the semiconductor device 10A of the first modification is turned on, the second power supply 32 supplies power to the gate n - Layer 19 and gate p layer 20 apply a predetermined positive voltage, thereby sandwiching gate oxide film 15 and gate n along the X-axis direction - N adjacent to layer 19 and second gate electrode 53 - A part of the drift layer 16 is formed with n + Layer 21 is built up. In addition, an n inversion layer 22 is formed in the channel portion 17b adjacent to the gate oxide film 15.
At n inversion layer 22 and n - A part of the drift layer 16 is formed with n + An accumulation layer 21, whereby electron current EC1 flows from drain electrode 11 via n - Drift layers 16, n + Accumulation layer 21, n inversion layer 22 and n + The source layer 18 flows toward the source electrode 12.
In the on state of the semiconductor device 10A according to the first modification, the forward direction of the p-layer 51 and the n-layer 52 is set to the direction from the drain electrode 11 toward the second gate electrode 53, and thus the current (reverse current) from the second gate electrode 53 toward the drain electrode 11 can be suppressed.
According to the first modification, the p-layer 51 and the n-layer 52 functioning as diodes can be connected to the gate n via the second gate electrode 53 - Layer 19 is integrally built in. The p layer 51 is bonded to the drain electrode 11, and thus the drain electrode 11 can be disposed so as to extend to both sides of the gate oxide film 15 in the X-axis direction. For example, compared with the case where different electrodes are arranged on both sides of the gate oxide film 15, the case where the source electrode 12 side is the front surface side, that is, the drain electrode 11 side does not require separate fabrication of the different electrodes, and thus the process for fabricating the electrodes can be prevented from being complicated.
In the above embodiment, the semiconductor device 10 is a MOSFET, but the present invention is not limited thereto, and a semiconductor device having a so-called superjunction structure may be used.
Fig. 7 is a cross-sectional view of a half cell H showing a state of the semiconductor device 10B in the second modification of the embodiment at the time of conduction. Fig. 8 is a diagram showing an example (simulated example) of the relationship between the drain voltage and the drain current at the time of conduction in each of the semiconductor device 10B of the second modification example and the semiconductor device of the comparative example of the embodiment.
As shown in fig. 7, the semiconductor device 10B of the second modification is a combined Bipolar and MOS (so-called BiMOS) having a superjunction structure. The combined Bipolar-and-MOS (so-called BiMOS) is a semiconductor device formed by combining a BJT (Bipolar Junction Transistor: bipolar junction transistor) and a MOS, which are integrally formed on a single substrate.
The semiconductor device 10B of the second modification includes the drain electrode 11, the source electrode 12, the first gate electrode 13, the second gate electrode 14, the gate oxide film 15, and n - Drift layer 16, p base layer 17, n + Source layer 18, gate n - Layer 19 and gate p-layer 20, first power supply 31, second power supply 32, load 33, diode 34, base electrode 61, at least one p-pillar layer 62 (eighth semiconductor region), and current source 63.
The drain electrode 11 and the second gate electrode 14 of the second modification are disposed at a first end portion of the semiconductor device 10B, out of both end portions along the Y-axis direction.
The source electrode 12, the first gate electrode 13, and the base electrode 61 of the second modification are disposed at a second end portion of the semiconductor device 10B, out of both end portions along the Y-axis direction. The source electrode 12 of the second modification is bonded to the n+ source layer 18 along the Y-axis direction. The base electrode 61 is bonded to the contact portion 17a of the p base layer 17 along the Y-axis direction.
Each p-pillar layer 62 is formed of a p-type (p-type) semiconductor. Each p-pillar layer 62 is provided, for example, at n - A portion of the drift layer 16. For example, the plurality of p-pillar layers 62 are arranged in order with appropriate intervals therebetween along the X-axis direction, so as to be aligned with n along the X-axis direction - The drift layers 16 are alternately arranged. Each p-pillar layer 62 is adjacent to the contact portion 17a of the p-base layer 17 along the Y-axis direction. N of the second modification - The drift layer 16 is adjacent to the channel portion 17b of the p base layer 17 along the Y-axis direction.
In the semiconductor device 10B of the second modification, n - Impurity concentration N of drift layer 16 D And impurity concentration N of p-pillar layer 62 A May be set according to the ratio of the sizes of the layers 16, 62 to each other. For example, n is a main current path according to the ratio of the widths of the layers 16 and 62 along the X-axis direction - Drift layer 16 is p-pillarIn the case where layer 62 is relatively large, the impurity concentration N of p-pillar layer 62 is adjusted to maintain desired charge compensation A Set to be a ratio of n - Impurity concentration N of drift layer 16 D Relatively large (N D <N A )。
The current source 63 is, for example, a power supply circuit that switches the presence or absence of output, polarity inversion, and the like. The current source 63 is a power supply circuit that outputs a constant current.
In the on state (i.e., in the forward direction) of the semiconductor device 10B according to the second modification example, the negative electrode of the first power supply 31 is connected to the negative electrodes of the source electrode 12, the second power supply 32, and the current source 63. The positive electrode of the current source 63 is connected to the base electrode 61.
In the on state of the semiconductor device 10B according to the second modification example, a predetermined positive voltage is applied to the gate electrodes 13 and 14 with respect to the source electrode 12 by the second power supply 32, and thereby the electron current EC1 passes from the drain electrode 11 through n + Accumulation layer 21, n inversion layer 22 and n + The source layer 18 flows toward the source electrode 12.
When the semiconductor device 10B of the second modification is turned on, a predetermined current is supplied to the base electrode 61 by the current source 63, and the electron current EC2 passes from the drain electrode 11 through n - Drift layer 16, channel portion 17b of p base layer 17, and n + The source layer 18 flows toward the source electrode 12. Further, a hole current HC1 relatively smaller than the electron currents EC1 and EC2 goes from the contact portion 17a of the p base layer 17 toward n - The drift layer 16 flows.
The comparative example shown in fig. 8 is, for example, a semiconductor device 10B not including the first gate electrode 13 and the second gate electrode 14 and the gate n corresponding to the second modification example - Semiconductor device of super junction structure of gate structure of layer 19 and gate p layer 20, semiconductor device of comparative example does not have n when turned on + Layer 21 is built up.
As shown in fig. 8, it is considered that drain currents Id (V1) and Id (V3) at the time of conduction in the semiconductor device 10B of the second modification are due to n + The accumulation layer 21 is larger than the drain current Ic at the time of conduction in the semiconductor device of the comparative example. The drain currents Id (V1) and Id (V3) and the gate electrodes 13 and 14 according to the embodiment are set to be equal to each other with respect to the sourceThe voltage Vgs of the electrode 12 is the first voltage V1 and the third voltage V3%>V1) corresponds to the case. For example, the first voltage V1 is 15V, and the third voltage V3 is 30V. It is considered that the drain current Id increases with an increase in the voltage Vgs applied to each gate electrode 13, 14.
According to the second modification, the so-called superjunction structure can ensure a desired withstand voltage, and at the same time, n is set to - The impurity concentration of the drift layer 16 increases, and the current density can be increased.
Even if n is set appropriately, for example, in accordance with the securing of a desired current density or the like - Even in the case of the ratio of the sizes of the drift layer 16 and the p-pillar layer 62, n can be appropriately set so as to maintain desired charge compensation - The impurity concentrations of the drift layer 16 and the p-pillar layer 62 can easily ensure a desired withstand voltage.
In the second modification of the embodiment described above, the gate n of the semiconductor device 10B - Layer 19 is formed along the X-axis direction with gate oxide film 15 and n interposed therebetween - The drift layer 16 is adjacent, but is not limited thereto. For example, the first gate electrode 13, the second gate electrode 14 and the gate n - The gate structure formed by the layer 19 and the gate p layer 20 may be arranged at any position along the X-axis direction in the semiconductor device of the superjunction structure.
Fig. 9 is a cross-sectional view of a half cell H showing a state of the semiconductor device 10C in the third modification of the embodiment at the time of conduction.
As shown in fig. 9, a semiconductor device 10C according to a third modification includes a first gate electrode 13, a second gate electrode 14, and a gate n - The gate structure formed by the layer 19 and the gate p layer 20 is sandwiched between two device structures from both sides in the X-axis direction. The two device structures are combined Bipolar-and-MOS (so-called BiMOS) having a superjunction structure, and have substantially the same structure as each other.
The first device structure includes a first drain electrode 11a (second electrode), a first source electrode 12a (first electrode), and a first n - A drift layer 16a (second semiconductor region), a first p base layer 17A (corresponding to the p base layer 17, third semiconductor region), and a first n + Source layer 18a (first halfA conductor region), a first base electrode 61a, and at least one first p-pillar layer 62a (eighth semiconductor region).
The second device structure comprises a second drain electrode 11b, a second source electrode 12b, and a second n - A drift layer 16B, a second p base layer 17B, and a second n + A source layer 18b, a second base electrode 61b, and at least one second p-pillar layer 62b (eighth semiconductor region).
First device structure, first gate electrode 13, second gate electrode 14, first gate oxide film 15a (insulator), gate n - The layer 19 and the gate p layer 20 correspond to the structure of the semiconductor device 10B of the second modification example described above.
In the on state (i.e., in the forward direction) of the semiconductor device 10C according to the third modification example, the negative electrode of the first power supply 31 is connected to the negative electrodes of the source electrodes 12a and 12b, the second power supply 32, and the current source 63. The positive electrode of the current source 63 is connected to the respective base electrodes 61a and 61 b.
The load 33 is connected between the first power supply 31 and each drain electrode 11a, 11 b. The diode 34 is connected between each of the drain electrodes 11a and 11b and the second gate electrode 14.
In the semiconductor device 10C of the third modification, the first device structure and the second device structure sandwich the first gate oxide film 15a and the second gate oxide film 15b and the gate n along the X-axis direction - Layer 19 and gate p layer 20 are adjacent.
In the second device structure, the contact portion 17c of the second p-base layer 17B is adjacent to the gate p layer 20 along the X-axis direction with the second gate oxide film 15B interposed therebetween, in the contact portion 17c and the channel portion 17 d. The second p-pillar layer 62b of the second device structure is formed along the X-axis direction with the gate n through the second gate oxide film 15b - Layer 19 is adjacent.
In the semiconductor device 10C of the third modification, n is each, as in the semiconductor device 10B of the second modification - Impurity concentration N of drift layers 16a and 16b D And impurity concentration N of each p column layer 62a, 62b A Can be according to each n - The ratio of the sizes of the drift layers 16a and 16b and the p-pillar layers 62a and 62b is set.
Conduction of the semiconductor device 10C of the third modificationIn this case, a predetermined positive voltage is applied to each of the gate electrodes 13 and 14 from the second power supply 32 with respect to the first source electrode 12a, and thereby the electron current EC1 passes from the first drain electrode 11a through n + Accumulation layer 21, n inversion layer 22 and first n + The source layer 18a flows toward the first source electrode 12 a.
When the semiconductor device 10C of the third modification is turned on, a predetermined current is supplied to the base electrodes 61a and 61b by the current source 63, and thereby the electron currents EC2 and EC3 pass from the drain electrodes 11a and 11b through the n electrodes - Drift layers 16a and 16B, channel portions 17B and 17d of p base layers 17A and 17B, and n + The source layers 18a and 18b flow toward the source electrodes 12a and 12 b. Further, hole currents HC1 and HC2 relatively smaller than electron currents EC1, EC2 and EC3 are directed from contact portions 17A and 17c of p base layers 17A and 17B toward n - The drift layers 16a and 16b flow.
According to the third modification, the first gate electrode 13, the second gate electrode 14 and the gate n can be used at the same time while ensuring desired charge compensation and withstand voltage - The gate structure formed by the layer 19 and the gate p layer 20 is arranged at an appropriate position, and the degree of freedom of the device structure can be increased.
In the above-described embodiment, the semiconductor device 10 is formed as a so-called vertical semiconductor device, but is not limited thereto, and may be formed as a so-called horizontal semiconductor device.
Fig. 10 is a perspective view showing a state of the semiconductor device 10D in the fourth modification of the embodiment at the time of conduction.
As shown in fig. 10, the semiconductor device 10D of the fourth modification includes a drain electrode 71 (second electrode), a source electrode 72, first and second gate electrodes 73 and 74, and gate oxide films 75, n - A drift layer 76 (second semiconductor region), a p base layer 77 (third semiconductor region), n + Source layer 78 (first semiconductor region), gate n - Layer 79 (gate semiconductor region, fifth semiconductor region) and gate p layer 80 (gate semiconductor region, fourth semiconductor region), first and second power supplies 31 and 32, load 33, and diode 34.
The drain electrode 71 is arranged in the Y-axis direction of the semiconductor device 10DA first one of the two ends. The drain electrode 71 is connected to n in the Z-axis direction on one (first end surface) side of both end surfaces of the semiconductor device 10D in the Z-axis direction - The drift layer 76 is bonded.
The source electrode 72 is disposed at a second end portion of the semiconductor device 10D, out of the two end portions along the Y-axis direction. The source electrode 72 is connected to n in the Z-axis direction on one (first end surface) side of the two end surfaces of the semiconductor device 10D in the Z-axis direction + The source layer 78 is bonded.
The first gate electrode 73 is arranged at a second end portion of the semiconductor device 10D, out of the two end portions along the Y-axis direction. The first gate electrode 73 is arranged apart from the source electrode 72 along the X-axis direction. The first gate electrode 73 is bonded to the gate p layer 80 along the Z-axis direction on one (first end) side of both end surfaces of the semiconductor device 10D along the Z-axis direction.
The second gate electrode 74 is disposed at a first end portion of the semiconductor device 10D, out of the two end portions along the Y-axis direction. The second gate electrode 74 is arranged apart from the drain electrode 71 along the X-axis direction. The second gate electrode 74 is connected to the gate n along the Z-axis direction on one (the first end surface) side of the two end surfaces of the semiconductor device 10D along the Z-axis direction - Layer 79 is bonded.
Gate oxide films 75 and n - Drift layer 76, p base layer 77, n + Source layer 78, gate n - Layer 79 and gate p layer 80 are adjacent, respectively. Gate oxide film 75 will n - Drift layer 76, p base layer 77 and n + Source layer 78 and gate n - Layer 79 and gate p layer 80 are separated.
n - Drift layer 76, p base layer 77 and n + The source layers 78 are adjacent to each other in a sequential manner along the Y-axis direction. Grid n - The layer 79 and the gate p layer 80 are adjacent to each other so as to be stacked in the Y-axis direction. n is n - Drift layer 76 and gate n - The layers 79 are adjacent to each other along the X-axis direction with the gate oxide film 75 interposed therebetween. p base layer 77 and n + The source layer 78 and the gate p layer 80 are adjacent to each other along the X-axis direction with the gate oxide film 75 interposed therebetween.
For example, gates n adjacent along the Y-axis direction - The interface of layer 79 with gate p layer 80 and n adjacent along the Y-axis direction - Drift layer 7The interface of 6 and p-base layer 77 is contained in the same plane.
When the semiconductor device 10D is turned on (i.e., turned on in the forward direction), the positive electrode of the first power supply 31 is connected to the load 33, and is connected to the drain electrode 71 via the load 33. The negative electrode of the first power supply 31 is connected to the source electrode 72 and the negative electrode of the second power supply 32. The positive electrode of the second power supply 32 is connected to the first gate electrode 73. The diode 34 has an anode connected to the drain electrode 71 and a cathode connected to the second gate electrode 74.
During the conduction of the semiconductor device 10D, the second power source 32 is used to supply power to the gate n - Layer 79 and gate p layer 80 are applied with a predetermined positive voltage to n adjacent to gate oxide film 75 - The drift layer 76 is formed with n + An accumulation layer and an n-inversion layer are formed on the p-base layer 77 adjacent to the gate oxide film 75.
In the above embodiment, the semiconductor device 10 is of an n-channel type, but the present invention is not limited thereto, and may be of a p-channel type.
Fig. 11 is a cross-sectional view of a half cell H showing a state of the semiconductor device 10E in the fifth modification of the embodiment at the time of conduction.
As shown in fig. 11, a semiconductor device 10E according to a fifth modification includes a drain electrode 11, a source electrode 12, first and second gate electrodes 13 and 14, a gate oxide film 15, and p - A drift layer 81 (second semiconductor region), an n base layer 82, and p + Source layer 83 (first semiconductor region), gate electrode p - Layer 84 (gate semiconductor region, fifth semiconductor region) and gate n layer 85 (gate semiconductor region, fourth semiconductor region), first and second power supplies 31 and 32, load 33, and diode 34.
The drain electrode 11 is connected to the p-type semiconductor device 10E along the Y-axis direction at the first end in the Y-axis direction - The drift layer 81 is bonded.
The source electrode 12 is bonded to the n base layer 82 and the p+ source layer 83 along the Y axis direction at the second end portion of the semiconductor device 10E in the Y axis direction.
The first gate electrode 13 is bonded to the gate n layer 85 along the Y-axis direction at the second end portion of the semiconductor device 10E in the Y-axis direction.
The second gate electrode 14 is connected to the gate electrode p along the Y-axis direction at the first end portion of the semiconductor device 10E in the Y-axis direction - Layer 84 is bonded.
Gate oxide film 15 and p - Drift layer 81, n base layer 82, p + Source layer 83, gate p - Layer 84 and gate n layer 85 are adjacent, respectively. The gate oxide film 15 will p - Drift layer 81, n base layer 82 and p + Source layer 83 and gate p - Layer 84 and gate n layer 85 are separated.
p - The drift layer 81 is formed of a p-type (p-type) semiconductor having a relatively small carrier concentration. P is p - The drift layer 81 is bonded to the drain electrode 11 along the Y-axis direction. P is p - The drift layer 81 is formed along the X-axis direction with the gate electrode p through the gate oxide film 15 - Layer 84 is adjacent.
The n base layer 82 is formed of an n-type (n-type) semiconductor. n base layer 82 to follow the Y-axis direction and p - The drift layer 81 is laminated with p - The drift layer 81 is adjacent.
The n base layer 82 includes, for example, a contact portion 82a and a channel portion 82b. The contact portion 82a is joined to the source electrode 12 along the Y-axis direction. Channel 82b extends from p along the Y-axis - Drift layer 81 and p + The source layer 83 is sandwiched from both sides. Channel portions 82b and p - Drift layer 81 and p + Source layer 83 is adjacent to p - Drift layers 81 and p + The source layers 83 are separated. The channel 82b is adjacent to the gate n layer 85 along the X-axis direction with the gate oxide film 15 interposed therebetween.
p + The source layer 83 is formed of a p-type (p-type) semiconductor having a relatively large carrier concentration. P is p + The source layer 83 is adjacent to the channel portion 82b so as to be laminated with the channel portion 82b of the n-base layer 82 along the Y-axis direction. P is p + The source layer 83 is bonded to the source electrode 12 along the Y-axis direction.
Grid electrode p - Layer 84 is formed of a p-type semiconductor having a relatively small carrier concentration. For example, gate p - Carrier concentration and p of layer 84 - The carrier concentration of the drift layer 81 is the same. Grid electrode p - Layer 84 is bonded to second gate electrode 14 along the Y-axis direction and is adjacent to gate n-layer 85. Grid electrode p - Layer 84 is formed along the X-axis direction with gate oxide film 15 and p therebetween - The drift layer 81 is adjacent.
The gate n layer 85 is formed of an n-type (n-type) semiconductor. For example, the carrier concentration of the gate n layer 85 is the same as the carrier concentration of the n base layer 82. The gate n layer 85 is bonded to the first gate electrode 13 along the Y-axis direction and to the gate p - Layer 84 is adjacent. Gate n layer 85 is formed along the X-axis direction with gate oxide film 15 and channel portion 82b and p of n base layer 82 interposed therebetween + The source layers 83 are adjacent to each other.
For example, gates p adjacent in the Y-axis direction - The interface of layer 84 and gate n layer 85 and p adjacent along the Y-axis direction - The interface between the drift layer 81 and the n base layer 82 is contained in the same plane.
When the semiconductor device 10E is turned on (i.e., turned on in the forward direction), the negative electrode of the first power supply 31 is connected to the load 33, and is connected to the drain electrode 11 via the load 33. The positive electrode of the first power source 31 is connected to the source electrode 12 and the positive electrode of the second power source 32. The negative electrode of the second power supply 32 is connected to the first gate electrode 13. The diode 34 has an anode connected to the second gate electrode 14 and a cathode connected to the drain electrode 11.
During the conduction of the semiconductor device 10D, the second power source 32 is used to supply power to the gate p - Layer 84 and gate n layer 85 apply a predetermined negative voltage to p adjacent to gate oxide film 75 - The drift layer 81 is formed with p + The accumulation layer 86 and a p inversion layer 87 are formed in the channel portion 82b adjacent to the gate oxide film 75.
p + The accumulation layer 86 accumulates p at the interface of the gate oxide film 15 - A region of a p-type (p-type) semiconductor having a relatively large carrier concentration formed by majority carriers of the drift layer 81.
The p inversion layer 87 is a region of a p-type (p-type) semiconductor formed by drawing minority carriers of the channel portion 82b toward the interface of the gate oxide film 15.
By forming p-inversion layer 87 and p + An accumulation layer 86 whereby hole current HC3 flows from the source electrode 12 via p + Source layer 83, p inversion layer 87 and p + The accumulation layer 86 flows toward the drain electrode 11.
In the above embodiment, the semiconductor device 10 is a MOSFET, but is not limited thereto. The semiconductor device 10 may have a structure corresponding to at least a MOSFET.
For example, the semiconductor device 10 may be a combination type bipolarand-MOS (so-called BiMOS), a combination type bipolarand-MOS (so-called BiMOS) having a superjunction structure, a MOSFET having a superjunction structure, or the like.
The embodiments of the present invention are presented as examples, and are not intended to limit the scope of the invention. These embodiments can be implemented in various other modes, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications are included in the invention described in the claims and the equivalent scope thereof, as are included in the scope and gist of the invention.

Claims (8)

1. A semiconductor device, wherein,
the semiconductor device includes:
a first semiconductor region of a first conductivity type;
a first electrode bonded to the first semiconductor region;
A second semiconductor region of the first conductivity type;
a second electrode bonded to the second semiconductor region;
a third semiconductor region of a second conductivity type having a channel portion separating the first semiconductor region from the second semiconductor region;
an insulator adjacent to the first semiconductor region, the second semiconductor region, and the channel portion, respectively;
a gate semiconductor region adjacent to the first semiconductor region, the second semiconductor region, and the channel portion, respectively, with the insulator interposed therebetween; and
a first gate electrode and a second gate electrode which are bonded to both end portions of the gate semiconductor region in a direction along which the first semiconductor region, the channel portion, and the second semiconductor region are sequentially arranged,
the gate semiconductor region includes:
a fourth semiconductor region of the second conductivity type bonded to the first gate electrode arranged on the first semiconductor region side in the arrangement direction; and
and a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and bonded to the second gate electrode arranged on the second semiconductor region side in the arrangement direction.
2. The semiconductor device according to claim 1, wherein,
the semiconductor device includes a rectifying portion having a rectifying function between the second electrode and the second gate electrode.
3. The semiconductor device according to claim 2, wherein,
the rectifying unit includes:
a sixth semiconductor region of the first conductivity type bonded to the second gate electrode; and
a seventh semiconductor region of the second conductivity type adjacent to the sixth semiconductor region and bonded to the second electrode,
the second gate electrode, the sixth semiconductor region, and the seventh semiconductor region are adjacent to the second semiconductor region via the insulator.
4. The semiconductor device according to any one of claim 1 to 3, wherein,
the interface between the second semiconductor region and the third semiconductor region and the interface between the fourth semiconductor region and the fifth semiconductor region are contained in the same plane.
5. The semiconductor device according to any one of claim 1 to 3, wherein,
the semiconductor device includes an eighth semiconductor region of the second conductivity type, the eighth semiconductor region being adjacent to the third semiconductor region in the direction of the arrangement, and the eighth semiconductor region being adjacent to the second semiconductor region in a direction in which the gate semiconductor region and the second semiconductor region are adjacent to each other with the insulator interposed therebetween.
6. The semiconductor device according to claim 5, wherein,
the impurity concentrations of the second semiconductor region and the eighth semiconductor region are set according to the ratio of the sizes of the second semiconductor region and the eighth semiconductor region.
7. The semiconductor device according to claim 4, wherein,
the semiconductor device includes an eighth semiconductor region of the second conductivity type, the eighth semiconductor region being adjacent to the third semiconductor region in the direction of the arrangement, and the eighth semiconductor region being adjacent to the second semiconductor region in a direction in which the gate semiconductor region and the second semiconductor region are adjacent to each other with the insulator interposed therebetween.
8. The semiconductor device according to claim 7, wherein,
the impurity concentrations of the second semiconductor region and the eighth semiconductor region are set according to the ratio of the sizes of the second semiconductor region and the eighth semiconductor region.
CN202310105330.6A 2022-03-23 2023-02-13 Semiconductor device with a semiconductor device having a plurality of semiconductor chips Pending CN116805652A (en)

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