CN116805649A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Abstract

The invention provides a semiconductor device. A semiconductor device (10) is provided with: n is n ⁺ A source layer (20) and a source electrode (12); n is n ⁺ Drain electrode layer (16), n ^‑ A drift layer (17) and a drain electrode (11); and a p base layer (19) and a base electrode (13). The p base layer (19) has a structure in which n is equal to ⁺ Source layers (20) and n ^‑ Channel portions (19 c) separated by the drift layer (17). The semiconductor device (10) is provided with a second contact portion (19 b), wherein the second contact portion (19 b) is adjacent to the base electrode (13) and has an impurity concentration that is relatively higher than the impurity concentration of other portions of the p base layer (19).

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Technical Field

The present invention relates to a semiconductor device.

Background

Conventionally, a semiconductor device including a MOSFET (Metal Oxide semiconductor field effect transistor) and a BJT (Bipolar Junction Transistor: bipolar junction transistor) integrally formed on a single substrate and connected in parallel is known (for example, refer to japanese patent application laid-open (jp) No. 61-180472 and japanese patent application laid-open (jp) No. 61-225854).

Disclosure of Invention

In the above-described conventional semiconductor device, it is desirable to ensure a desired withstand voltage between the drain electrode and the source electrode and to reduce the loss of on-resistance and the like. For example, in a structure corresponding to a BJT, it is desirable to suppress the inflow of minority carriers to the base electrode to improve the current density and current amplification factor.

An object of an embodiment of the present invention is to provide a semiconductor device capable of improving a current density and a current amplification factor while securing a desired withstand voltage, and improving energy efficiency.

The semiconductor device according to the first aspect of the present invention includes: a first semiconductor region of a first conductivity type; a first electrode bonded to the first semiconductor region; a second semiconductor region of the first conductivity type; a second electrode bonded to the second semiconductor region; a third semiconductor region of a second conductivity type having a channel portion separating the first semiconductor region from the second semiconductor region; and a third electrode bonded to the third semiconductor region, wherein the third semiconductor region includes a contact portion, the contact portion is adjacent to the third electrode, and an impurity concentration of the contact portion is relatively higher than an impurity concentration of other portions of the third semiconductor region.

A second aspect of the present invention provides the semiconductor device according to the first aspect, wherein the semiconductor device includes a fourth semiconductor region of the second conductivity type, the fourth semiconductor region being adjacent to the third semiconductor region in a direction in which the first semiconductor region, the channel portion, and the second semiconductor region are sequentially arranged, and being adjacent to the second semiconductor region in a direction orthogonal to the arrangement direction.

In the third aspect, in the semiconductor device according to the first or second aspect, the contact portion may have a size larger than a diffusion length of minority carriers corresponding to an impurity concentration of the contact portion.

According to the first aspect, the contact portion is provided adjacent to the third electrode, and the impurity concentration is relatively higher than the impurity concentration at other portions of the third semiconductor region, so that the recombination of minority carriers at the contact portion can be promoted, and the inflow of minority carriers to the third electrode can be suppressed. By increasing the ratio of the carrier component in the current flowing to the third electrode, it is possible to improve the current density and the current amplification factor while ensuring a desired withstand voltage.

In the case of the second embodiment, the second semiconductor region of the first conductivity type and the fourth semiconductor region of the second conductivity type are arranged adjacent to each other in a so-called superjunction structure, whereby a desired withstand voltage is ensured, and the impurity concentration of the second semiconductor region is increased to thereby increase the current density.

By providing the contact portion, minority carriers can be prevented from flowing into the third electrode through the fourth semiconductor region of the second conductivity type in the superjunction structure, and the current density and the current amplification factor can be improved.

In the case of the third aspect, the size of the contact portion is larger than the diffusion length of the minority carrier corresponding to the impurity concentration of the contact portion, whereby the recombination of the minority carrier at the contact portion can be promoted.

Drawings

Fig. 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.

Fig. 2 is a sectional view taken through a Y-Z plane at the position of the line A-A shown in fig. 1.

Fig. 3 is a cross-sectional view of a half cell showing a state of the semiconductor device in the on state in the embodiment of the present invention.

Fig. 4 is a graph showing an example of the relationship between the drain voltage and the drain current at the time of conduction in each of the semiconductor device according to the embodiment of the present invention and the semiconductor device of the comparative example.

Fig. 5 is a graph showing an example of the relationship between the electronic components of the drain voltage and the base current at the time of conduction in each of the semiconductor device according to the embodiment of the present invention and the semiconductor device of the comparative example.

Fig. 6 is a cross-sectional view of a half cell showing a state in reverse conduction of the semiconductor device in the embodiment of the present invention.

Fig. 7 is a graph showing an example of the relationship between the drain voltage and the drain current at the time of reverse conduction in each of the semiconductor device according to the embodiment of the present invention and the semiconductor device of the comparative example.

Fig. 8 is a cross-sectional view of a half cell showing a state of the semiconductor device in the on state in the first modification of the embodiment of the present invention.

Detailed Description

Hereinafter, a semiconductor device 10 according to an embodiment of the present invention will be described with reference to the drawings.

Fig. 1 is a cross-sectional view showing the structure of a semiconductor device 10 according to the embodiment. Fig. 2 is a sectional view taken through a Y-Z plane at the position of the line A-A shown in fig. 1.

As shown in fig. 1 and 2, the semiconductor device 10 according to the embodiment is, for example, a combined bipolarand MOS (so-called BiMOS) having a superjunction structure. The semiconductor device of the super junction structure includes, for example, n-type columnar regions and p-type columnar regions alternately arranged in parallel in the drift region. A combined Bipolar-and-MOS (so-called BiMOS) is a semiconductor device formed by combining a BJT and a MOS integrally formed on a single substrate. The substrate being composed of Si, siC, gaN or Ga ₂ O ₃ And semiconductor materials. The semiconductor material is not limited. The semiconductor device 10 is, for example, a so-called vertical n-channel semiconductor device.

Hereinafter, the directions of the axes X, Y, and Z orthogonal to each other in the three-dimensional space are directions parallel to the axes. For example, the X-axis direction is parallel to the width direction (so-called lateral direction) of the semiconductor device 10, the Y-axis direction is parallel to the thickness direction (so-called longitudinal direction) of the semiconductor device 10, and the Z-axis direction is parallel to the orthogonal direction (so-called depth direction) of the X-axis direction and the Y-axis direction.

The semiconductor device 10 of the embodiment includes a drain electrode 11 (second electrode), a source electrode 12 (first electrode), a base electrode 13 (third electrode), a gate electrode 14, and gate oxide films 15, n ⁺ Drain layer 16 (second semiconductor region), n ^- A drift layer 17 (second semiconductor region), at least one p-pillar layer 18 (fourth semiconductor region), a p-base layer 19 (third semiconductor region), and n ⁺ Source layer 20 (first semiconductor region).

The drain electrode 11 is disposed at a first end portion of the semiconductor device 10, out of both end portions along the Y-axis direction. Drain electrode 11 is aligned with n along the Y-axis direction ⁺ The drain layer 16 is bonded.

The source electrode 12 is disposed at a second end portion of the semiconductor device 10, out of the two end portions along the Y-axis direction. The source electrode 12 is aligned with n along the Y-axis direction ⁺ The source layer 20 is bonded.

The base electrode 13 is disposed at a second end portion of the semiconductor device 10, out of the two end portions along the Y-axis direction. The base electrode 13 is arranged apart from the source electrode 12 along the X-axis direction. The base electrode 13 is bonded to the p base layer 19 along the Y-axis direction.

The gate electrode 14 and the gate oxide film 15 are formed in a so-called trench-type gate structure having a shape buried in the substrate along the Y-axis direction, for example. The gate electrode 14 is covered with a gate oxide film 15. Gate oxide film 15 and source electrode 12, n ^- Drift layer 17, p base layer 19 and n ⁺ The source layers 20 are respectively adjacent. The gate electrode 14 is connected to the source electrodes 12, n via a gate oxide film 15 ^- Drift layer 17, p base layer 19 and n ⁺ The source layers 20 are respectively adjacent.

n ⁺ The drain layer 16 is formed of an n-type (n-type) semiconductor having a relatively large carrier concentration. n is n ⁺ The drain layer 16 is bonded to the drain electrode 11 along the Y-axis direction。

n ^- The drift layer 17 is formed of an n-type (n-type) semiconductor having a relatively small carrier concentration. n is n ^- A drift layer 17 for forming a pair of n-well regions along the Y-axis direction ⁺ The drain layer 16 is laminated with n ⁺ The drain layer 16 is adjacent.

Each p-pillar layer 18 is formed of a p-type (p-type) semiconductor. Each p-pillar layer 18 is provided, for example, at n ^- A portion of the drift layer 17. For example, the plurality of p-pillar layers 18 are arranged in order with an appropriate interval therebetween along the X-axis direction, so as to be aligned with n along the X-axis direction ^- The drift layers 17 are alternately arranged. Each p-pillar layer 18 is aligned with n along the Y-axis direction ⁺ The drain layer 16 is laminated with n ⁺ The drain layer 16 is adjacent.

The p base layer 19 is formed of a p-type (p-type) semiconductor. A p base layer 19 for a border along the Y-axis direction and n ^- Drift layer 17 and p-pillar layer 18 are stacked with n ^- The drift layer 17 and the p-pillar layer 18 are adjacent. The p base layer 19 includes, for example, a first contact portion 19a and a second contact portion 19b (contact portion), and a channel portion 19c.

The first contact portion 19a is sandwiched by the p-pillar layer 18 and the second contact portion 19b from both sides along the Y-axis direction. The first contact portion 19a is adjacent to the p-pillar layer 18 and the second contact portion 19b along the Y-axis direction, and separates the p-pillar layer 18 from the second contact portion 19b.

The second contact portion 19b is joined to the base electrode 13 along the Y-axis direction. The second contact portion 19b is adjacent to the first contact portion 19a so as to be laminated with the first contact portion 19a along the Y-axis direction. The second contact portion 19b is provided so as to cover the entire area of the interface between the base electrodes 13 adjacent to the p base layer 19.

The channel portion 19c is formed by n along the Y-axis direction ^- Drift layer 17 and n ⁺ The source layer 20 is sandwiched from both sides. Channel portions 19c and n ^- Drift layer 17 and n ⁺ Source layers 20 are adjacent to each other to form n ^- Drift layers 17 and n ⁺ The source layers 20 are separated. The channel portion 19c is adjacent to the gate electrode 14 along the X-axis direction with the gate oxide film 15 interposed therebetween.

The impurity concentration of the second contact portion 19b is set to be relatively higher than the impurity concentration of other portions of the p base layer 19, for example, the impurity concentrations of the first contact portion 19a and the channel portion 19c.

For example, the impurity concentration of the second contact portion 19b is 1×10 ²⁰ (cm ^-3 ) And the like, the impurity concentration of the first contact portion 19a and the channel portion 19c is 1×10 ¹⁸ (cm ^-3 ) Etc. The thickness of the second contact portion 19b along the Y-axis direction is, for example, a thickness sufficiently long with respect to the diffusion length of minority carriers (electrons) corresponding to the impurity concentration of the second contact portion 19b, and the impurity concentration is 1×10 ²⁰ (cm ^-3 ) The thickness of (2) is 1 μm or the like.

n ⁺ The source layer 20 is formed of an n-type (n-type) semiconductor having a relatively large carrier concentration. n is n ⁺ The source layer 20 is adjacent to the channel portion 19c of the p base layer 19 so as to be stacked with the channel portion 19c along the Y-axis direction. n is n ⁺ The source layer 20 is bonded to the source electrode 12 along the Y-axis direction.

Fig. 3 is a cross-sectional view of half cell H showing a state of semiconductor device 10 in the embodiment at the time of conduction. As shown in fig. 1, the half cell H is one of a pair of symmetrical portions of the semiconductor device 10 having a symmetrical shape with respect to the Y-Z plane. Fig. 4 is a graph showing an example (simulated example) of the relationship between the drain voltage and the drain current at the time of conduction in each of the semiconductor device 10 of the embodiment and the semiconductor device of the comparative example. Fig. 5 is a graph showing an example (simulated example) of the relationship between the drain voltage and the electronic component of the base current at the time of conduction in each of the semiconductor device 10 of the embodiment and the semiconductor device of the comparative example.

As shown in fig. 3, the semiconductor device 10 of the embodiment includes a first power source 31, a second power source 32, and a current source 33. The first power supply 31, the second power supply 32, and the current source 33 are, for example, power supply circuits that switch whether or not an output is present, polarity is inverted, and the like. The first power supply 31 and the second power supply 32 are power supply circuits for direct current, respectively. The current source 33 is a power supply circuit that outputs a constant current.

When the semiconductor device 10 is turned on (i.e., turned on in the positive direction), the positive electrode of the first power supply 31 is connected to the drain electrode 11. The negative electrode of the first power source 31 is connected to the negative electrodes of the source electrode 12, the second power source 32, and the current source 33. The positive electrode of the second power supply 32 is connected to the gate electrode 14. The positive electrode of the current source 33 is connected to the base electrode 13.

When the semiconductor device 10 is turned on, a predetermined positive voltage is applied to the gate electrode 14 with respect to the source electrode 12 by the second power supply 32, and thereby the n-inversion layer 21 is formed in the channel portion 19c of the p-base layer 19 adjacent to the gate oxide film 15. The n inversion layer 21 is a region of an n-type (n-type) semiconductor formed by drawing minority carriers of the channel portion 19c toward the interface of the gate oxide film 15. By forming n inversion layer 21 in channel portion 19c, electron current EC1 flows from drain electrode 11 through n ⁺ Drain layer 16, n ^- Drift layer 17, n inversion layer 21, and n ⁺ The source layer 20 flows toward the source electrode 12.

When the semiconductor device 10 is turned on, a predetermined current is supplied to the base electrode 13 by the current source 33, and the electron current EC2 flows from the drain electrode 11 through n ⁺ Drain layer 16, n ^- Drift layer 17, channel portion 19c of p base layer 19, and n ⁺ The source layer 20 flows toward the source electrode 12. Further, a hole current HC1 relatively smaller than the electron currents EC1 and EC2 is directed from the first contact portion 19a of the p base layer 19 toward n ^- The drift layer 17 flows. In addition, an electron current EC3, which is relatively smaller than the electron currents EC1 and EC2, is represented by the hole current HC1, from n ^- The drain electrode 11 side of the drift layer 17 faces n via the p-pillar layer 18 ^- The source electrode 12 side of the drift layer 17 flows.

When the semiconductor device 10 is turned on, the second contact portion 19b covering the interface of the base electrode 13 promotes the re-coupling of electrons flowing into the base electrode 13, thereby suppressing the inflow of electrons into the base electrode 13. For example, the direction from the base electrode 13 to n via the second contact portion 19b is suppressed ⁺ The electron current of the source layer 20 flows from the base electrode 13 to n via the second contact portion 19b, the first contact portion 19a, and the p-pillar layer 18 ^- The electron current of the drift layer 17 flows.

The comparative example shown in fig. 4 and 5 corresponds to, for example, the case where the second contact portion 19b is omitted in the semiconductor device 10 of the embodiment, and the p base layer 19 of the semiconductor device of the comparative example does not include the second contact portion 19b. In the semiconductor device of the comparative example, the first contact portion 19a of the p base layer 19 is bonded to the base electrode 13.

As shown in fig. 4, it was confirmed that the drain current Id at the time of conduction in the semiconductor device 10 of the embodiment was larger than the drain current Idc at the time of conduction in the semiconductor device of the comparative example due to the second contact portion 19b.

As shown in fig. 5, it was confirmed that the electron component eb of the base current at the time of conduction in the semiconductor device 10 of the embodiment was smaller than the electron component ebc of the base current at the time of conduction in the semiconductor device of the comparative example. That is, the ratio of the hole component of the base current in the semiconductor device 10 of the embodiment is larger than that in the semiconductor device of the comparative example.

Fig. 6 is a cross-sectional view of a half cell H showing a state in reverse conduction of the semiconductor device 10 in the embodiment. Fig. 7 is a graph showing an example (simulated example) of the relationship between the drain voltage and the drain current at the time of reverse conduction in each of the semiconductor device 10 of the embodiment and the semiconductor device of the comparative example.

As shown in fig. 6, the negative electrode of the first power supply 31 is connected to the drain electrode 11 when the semiconductor device 10 is turned on in the reverse direction (i.e., turned on in the reverse direction). The positive electrode of the first power source 31 is connected to the source electrode 12 and the negative electrodes of the second power source 32 and the current source 33. The positive electrode of the second power supply 32 is connected to the gate electrode 14. The positive electrode of the current source 33 is connected to the base electrode 13.

In the reverse conduction of the semiconductor device 10, as in the conduction, a predetermined positive voltage is applied to the gate electrode 14 with respect to the source electrode 12 by the second power supply 32, whereby the n-inversion layer 21 is formed in the channel portion 19c of the p-base layer 19 adjacent to the gate oxide film 15. By forming n inversion layer 21 in channel portion 19c, electron current EC4 flows from source electrode 12 through n ⁺ Source layer 20, n inversion layer 21, n ^- Drift layer 17 and n ⁺ The drain layer 16 flows toward the drain electrode 11.

In the reverse conduction of the semiconductor device 10, a predetermined current is supplied to the base electrode 13 by the current source 33, and the electron current EC5 passes from the source electrode 12 through n ⁺ Source layer 20, channel portions 19c, n of p base layer 19 ^- Drift layer 17 and n ⁺ The drain layer 16 flows toward the drain electrode 11. Further, a hole current HC2 relatively smaller than the electron currents EC4 and EC5 is directed from the first contact portion 19a of the p base layer 19 toward n ^- The drift layer 17 flows. In addition, electron current EC6, which is relatively smaller than electron currents EC4 and EC5, is represented by hole current HC2, from n ^- The source electrode 12 side of the drift layer 17 faces n via the p-pillar layer 18 ^- The drain electrode 11 side of the drift layer 17 flows.

In the reverse conduction of the semiconductor device 10, the second contact portion 19b covering the interface of the base electrode 13 promotes the recombination of electrons flowing into the base electrode 13, and suppresses the inflow of electrons into the base electrode 13, as in the conduction. For example, the direction from the base electrode 13 toward n via the second contact portion 19b, the first contact portion 19a, and the p-pillar layer 18 is suppressed ^- The electron current of the drift layer 17 flows.

The comparative example shown in fig. 7 corresponds to, for example, the case where the second contact portion 19b is omitted in the semiconductor device 10 of the embodiment, and the p base layer 19 of the semiconductor device of the comparative example does not include the second contact portion 19b. In the semiconductor device of the comparative example, the first contact portion 19a of the p base layer 19 is bonded to the base electrode 13.

As shown in fig. 7, it was confirmed that the drain current Id at the time of reverse conduction in the semiconductor device 10 of the embodiment was larger than the drain current Idc at the time of reverse conduction in the semiconductor device of the comparative example due to the second contact portion 19b.

As described above, according to the semiconductor device 10 of the embodiment, the second contact portion 19b is provided so as to cover the entire area of the interface of the base electrode 13, and the impurity concentration is relatively higher than the impurity concentration of the other portion of the p base layer 19, whereby the recombination of minority carriers (electrons) at the second contact portion 19b can be promoted, and the minority carriers (electrons) can be suppressed from flowing into the base electrode 13. By increasing the ratio of the carrier component (hole component) in the base current flowing to the base electrode 13, it is possible to improve the current density and current amplification factor while ensuring a desired withstand voltage.

Through n ^- A so-called superjunction structure in which the drift layer 17 and the p-pillar layer 18 are arranged adjacently is ensured byDesired withstand voltage, and at the same time by making n ^- The impurity concentration of the drift layer 17 increases, and the current density can be increased.

By providing the second contact portion 19b, minority carriers (electrons) can be prevented from flowing into the base electrode 13 through the p-pillar layer 18 in the superjunction structure, and the current density and current amplification factor can be improved.

For example, compared to the p-base layer 19 and the p-pillar layers 18 and n ⁺ In the case where a resistive layer that suppresses the flow of minority carriers (electrons) is provided at each interface of the source layers 20, the manufacturing process can be suppressed from being complicated.

The thickness of the second contact portion 19b along the Y-axis direction is a thickness that is sufficiently long with respect to the diffusion length of minority carriers (electrons) corresponding to the impurity concentration of the second contact portion 19b, and can promote the recombination of minority carriers (electrons) at the second contact portion 19b.

(modification)

A modification of the embodiment will be described below. The same reference numerals are given to the same parts as those of the above-described embodiments, and the description thereof is omitted or simplified.

In the above embodiment, the semiconductor device 10 is of an n-channel type, but the present invention is not limited thereto, and may be of a p-channel type.

Fig. 8 is a cross-sectional view of a half cell H showing a state of the semiconductor device 10A in the first modification of the embodiment at the time of conduction.

As shown in fig. 8, a semiconductor device 10A according to a first modification includes a drain electrode 11, a source electrode 12, a base electrode 13, a gate electrode 14, and gate oxide films 15 and p ⁺ Drain layer 41 (second semiconductor region), p ^- A drift layer 42 (second semiconductor region), at least one n-pillar layer 43 (fourth semiconductor region), an n-base layer 44 (third semiconductor region), and p ⁺ Source layer 45 (first semiconductor region).

The drain electrode 11 is disposed at a first end portion of the semiconductor device 10A, out of the two end portions along the Y-axis direction. Drain electrode 11 is aligned with p along the Y-axis direction ⁺ The drain layer 41 is bonded.

The source electrode 12 is disposed at a second end portion of the semiconductor device 10A, out of the two end portions along the Y-axis direction. The source electrode 12 is aligned with p along the Y-axis direction ⁺ The source layer 45 is bonded.

The base electrode 13 is disposed at a second end portion of the two end portions of the semiconductor device 10A along the Y-axis direction. The base electrode 13 is arranged apart from the source electrode 12 along the X-axis direction. The base electrode 13 is bonded to the n base layer 44 along the Y-axis direction.

The gate electrode 14 and the gate oxide film 15 are formed in a so-called trench-type gate structure having a shape buried in the substrate along the Y-axis direction, for example. The gate electrode 14 is covered with a gate oxide film 15. Gate oxide film 15 and source electrode 12, p ^- Drift layer 42, n base layer 44 and p ⁺ The source layers 45 are adjacent to each other. The gate electrode 14 is connected to the source electrodes 12, p via a gate oxide film 15 ^- Drift layer 42, n base layer 44 and p ⁺ The source layers 45 are adjacent to each other.

p ⁺ The drain layer 41 is formed of a p-type (p-type) semiconductor having a relatively large carrier concentration. P is p ⁺ The drain layer 41 is bonded to the drain electrode 11 along the Y-axis direction.

p ^- The drift layer 42 is formed of a p-type semiconductor having a relatively small carrier concentration. P is p ^- Drift layer 42 to align with p along the Y-axis direction ⁺ The drain layer 41 is laminated with p ⁺ The drain layer 41 is adjacent.

Each n-pillar layer 43 is formed of an n-type (n-type) semiconductor. Each n pillar layer 43 is provided at p, for example ^- A portion of the drift layer 42. For example, the plurality of n-pillar layers 43 are arranged in order with appropriate intervals therebetween along the X-axis direction, so as to be aligned with p along the X-axis direction ^- The drift layers 42 are alternately arranged. Each n-pillar layer 43 is formed along the Y-axis direction and p ⁺ The drain layer 41 is laminated with p ⁺ The drain layer 41 is adjacent.

The n base layer 44 is formed of an n-type (n-type) semiconductor. n base layer 44 to align with p along the Y-axis direction ^- Drift layer 42 and n-pillar layer 43 are stacked together with p ^- The drift layer 42 and the n pillar layer 43 are adjacent. The n-base layer 44 includes, for example, a first contact portion 44a and a second contact portion 44b (contact portion), and a channel portion 44c.

The first contact portion 44a is sandwiched by the n-pillar layer 43 and the second contact portion 44b from both sides along the Y-axis direction. The first contact portion 44a is adjacent to the n-pillar layer 43 and the second contact portion 44b along the Y-axis direction, and separates the n-pillar layer 43 from the second contact portion 44 b.

The second contact portion 44b is joined to the base electrode 13 along the Y-axis direction. The second contact portion 44b is adjacent to the first contact portion 44a so as to be laminated with the first contact portion 44a along the Y-axis direction. The second contact portion 44b is provided so as to cover the entire area of the interface between the base electrodes 13 adjacent to the n base layer 44.

Channel portion 44c extends from p along the Y-axis direction ^- Drift layer 42 and p ⁺ The source layer 45 is sandwiched from both sides. Channel portions 44c and p ^- Drift layer 42 and p ⁺ Source layer 45 is adjacent to p ^- Drift layer 42 and p ⁺ The source layers 45 are separated. The channel portion 44c is adjacent to the gate electrode 14 along the X-axis direction with the gate oxide film 15 interposed therebetween.

The impurity concentration of the second contact portion 44b is set to be relatively higher than the impurity concentration of other portions of the n-base layer 44, for example, the impurity concentrations of the first contact portion 44a and the channel portion 44c.

For example, the impurity concentration of the second contact portion 44b is 1×10 ²⁰ (cm ^-3 ) And the like, the impurity concentration of the first contact portion 44a and the channel portion 44c is 1×10 ¹⁸ (cm ^-3 ) Etc. The thickness of the second contact portion 44b along the Y-axis direction is, for example, a thickness sufficiently long with respect to the diffusion length of minority carriers (holes) corresponding to the impurity concentration of the second contact portion 44b, and the impurity concentration is 1×10 ²⁰ (cm ^-3 ) The thickness of (C) is 0.5 μm or the like.

p ⁺ The source layer 45 is formed of a p-type semiconductor having a relatively large carrier concentration. P is p ⁺ The source layer 45 is adjacent to the channel portion 44c of the n base layer 44 so as to be stacked with the channel portion 44c along the Y axis direction. P is p ⁺ The source layer 45 is bonded to the source electrode 12 along the Y-axis direction.

In the above embodiment and the first modification, the gate oxide film 15 is adjacent to the source electrode 12, but is not limited thereto. The gate oxide film 15 and the source electrode 12 may not be adjacent to each other.

In the above embodiment and the first modification, the gate electrode 14 is adjacent to the source electrode 12 through the gate oxide film 15, but is not limited thereto. The gate electrode 14 and the source electrode 12 may not be adjacent to each other through the gate oxide film 15.

In the above embodiment, the p base layer 19 includes the first contact portion 19a, but the present invention is not limited thereto, and the first contact portion 19a may be omitted. In this case, the second contact portion 19b is adjacent to the base electrode 13 and the p-pillar layer 18 along the Y-axis direction.

In the first modification described above, the n-base layer 44 includes the first contact portion 44a, but the present invention is not limited thereto, and the first contact portion 44a may be omitted. In this case, the second contact portion 44b is adjacent to the base electrode 13 and the n-pillar layer 43 along the Y-axis direction.

In the above-described embodiment, the semiconductor device 10 is a combined Bipolar-and-MOS (so-called BiMOS) formed by combining a BJT and a MOS, but is not limited thereto. The semiconductor device 10 may have at least a structure corresponding to a BJT.

For example, the semiconductor device 10 may be a BJT or a BJT having a superjunction structure, or the like.

The embodiments of the present invention are presented as examples, and are not intended to limit the scope of the invention. These embodiments can be implemented in various other modes, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications are included in the invention described in the claims and the equivalent scope thereof, as are included in the scope and gist of the invention.

Claims (3)

1. A semiconductor device, wherein,

the semiconductor device includes:

a first semiconductor region of a first conductivity type;

a first electrode bonded to the first semiconductor region;

a second semiconductor region of the first conductivity type;

a second electrode bonded to the second semiconductor region;

a third semiconductor region of a second conductivity type having a channel portion separating the first semiconductor region from the second semiconductor region; and

a third electrode bonded to the third semiconductor region,

the third semiconductor region includes a contact portion adjacent to the third electrode, and an impurity concentration of the contact portion is relatively higher than an impurity concentration of other portions of the third semiconductor region.

2. The semiconductor device according to claim 1, wherein,

the semiconductor device includes a fourth semiconductor region of the second conductivity type, the fourth semiconductor region being adjacent to the third semiconductor region along a direction in which the first semiconductor region, the channel portion, and the second semiconductor region are sequentially arranged, and being adjacent to the second semiconductor region along a direction orthogonal to the direction in which the first semiconductor region, the channel portion, and the second semiconductor region are arranged.

3. The semiconductor device according to claim 1 or 2, wherein,

the size of the contact portion is larger than the diffusion length of minority carriers corresponding to the impurity concentration of the contact portion.