CN116802810A

CN116802810A - Photoelectric conversion device, photoelectric conversion system, and moving object

Info

Publication number: CN116802810A
Application number: CN202280011178.9A
Authority: CN
Inventors: 岩田旬史; 森本和浩; 前桥雄; 林良之
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2021-01-22
Filing date: 2022-01-14
Publication date: 2023-09-22

Abstract

The photoelectric conversion device includes: a first substrate provided with a plurality of avalanche diodes; a second substrate provided with a plurality of pixel circuits; and a third substrate provided with a signal processing circuit. The second substrate and the third substrate are stacked such that a third wiring structure is provided between two semiconductor layers of the second substrate and the third substrate. A first through wiring penetrating the semiconductor layer of the third substrate is provided.

Description

Photoelectric conversion device, photoelectric conversion system, and moving object

Technical Field

The invention relates to a photoelectric conversion device, a photoelectric conversion system, and a moving object.

Background

A photoelectric conversion apparatus known in the art includes a pixel array configured such that pixels including a plurality of avalanche diodes (hereinafter abbreviated as APDs) are arranged in a two-dimensional array layout in a plan view. In each pixel, the photo-charge generated by a single photon causes avalanche multiplication due to the application of a reverse bias voltage to the PN junction diode. APDs operate in at least two modes. One is a geiger mode, i.e., an operation mode in which the potential difference between the anode and cathode is greater than the breakdown voltage when a reverse bias voltage is supplied. The other is a linear mode, i.e. an operation mode in which the potential difference between the anode and the cathode is close to or below the breakdown voltage. APDs configured to operate in geiger mode are known as SPADs (single photon avalanche diodes).

Fig. 3B of patent document 1 discloses a photoelectric conversion apparatus in which a first substrate, a second substrate, and a third substrate are stacked, the first substrate includes a SPAD array, the second substrate includes a counter, and the third substrate includes a memory device.

CITATION LIST

Patent literature

Patent document 1: specification of U.S. patent publication No. 2015/015131

Disclosure of Invention

Technical problem

Although patent document 1 discloses a photoelectric conversion device in which a first substrate, a second substrate, and a third substrate are stacked, a wiring structure for electrical connection between the second substrate and the third substrate is not considered therein. In view of this, the present invention aims to propose a specific configuration of a photoelectric conversion device including three or more substrates including avalanche diodes.

Solution to the problem

The photoelectric conversion device according to the present invention includes: a first substrate including a first semiconductor layer including a plurality of photoelectric conversion units and a first wiring structure; a second substrate including a second semiconductor layer including a plurality of pixel circuits provided in a manner corresponding to the plurality of photoelectric conversion units and a second wiring structure; a third substrate including a third semiconductor layer including a signal processing circuit configured to process signals output from the plurality of pixel circuits and a third wiring structure; a first through wiring penetrating the third semiconductor layer; and a semiconductor element overlapping the first through wiring in a plan view, wherein each of the plurality of photoelectric conversion units includes an avalanche diode; the first substrate and the second substrate are stacked such that the first wiring structure and the second wiring structure are disposed between the first semiconductor layer and the second semiconductor layer, and the second substrate and the third substrate are stacked such that the third wiring structure is disposed between the second semiconductor layer and the third semiconductor layer.

Advantageous effects of the invention

The present invention makes it possible to propose a specific configuration of a photoelectric conversion device including three or more substrates including avalanche diodes.

Drawings

Fig. 1 is a block diagram of a photoelectric conversion apparatus;

FIG. 2 is a block diagram of the functionality of a first substrate;

FIG. 3 is a block diagram of the functionality of a second substrate;

FIG. 4 is a block diagram of the functionality of a third substrate;

FIG. 5 is a circuit diagram and functional block diagram of a pixel;

FIG. 6 is a diagram for explaining a relationship between an operation of an APD and an output signal;

fig. 7 is a schematic diagram of an electrical connection relationship between a first substrate and a second substrate according to a first embodiment;

fig. 8 is a schematic diagram of an electrical connection relationship between a second substrate and a third substrate according to the first embodiment;

fig. 9 is a schematic diagram of an electrical connection relationship between a third substrate and another substrate or the like according to the first embodiment;

fig. 10 is a sectional view of the photoelectric conversion apparatus according to the first embodiment;

fig. 11 is a step of manufacturing a photoelectric conversion device according to the first embodiment;

fig. 12 is a step of manufacturing a photoelectric conversion device according to the first embodiment;

fig. 13A is a step of manufacturing a photoelectric conversion device according to the first embodiment;

fig. 13B is a step of manufacturing a photoelectric conversion device according to the first embodiment;

Fig. 14 is a sectional view of a photoelectric conversion apparatus according to a second embodiment;

fig. 15 is a sectional view of a photoelectric conversion apparatus according to a third embodiment;

fig. 16 is a sectional view of a photoelectric conversion apparatus according to a fourth embodiment;

fig. 17 is a sectional view of a photoelectric conversion apparatus according to a fifth embodiment;

fig. 18 is a sectional view of a photoelectric conversion apparatus according to a sixth embodiment;

fig. 19 is a sectional view of a photoelectric conversion apparatus according to a seventh embodiment;

fig. 20 is a sectional view of a photoelectric conversion apparatus according to an eighth embodiment;

fig. 21 is a sectional view of a photoelectric conversion apparatus according to a ninth embodiment;

fig. 22 is a sectional view of a photoelectric conversion apparatus according to a tenth embodiment;

fig. 23 is a schematic view of an electrical connection relationship between a first substrate and a second substrate according to an eleventh embodiment;

fig. 24 is a schematic view of an electrical connection relationship between a second substrate and a third substrate according to an eleventh embodiment;

fig. 25 is a schematic view of an electrical connection relationship between a third substrate and another substrate or the like according to an eleventh embodiment;

fig. 26 is a schematic diagram of an electrical connection relationship between a first substrate and a second substrate according to a twelfth embodiment;

fig. 27 is a schematic view of an electrical connection relationship between a second substrate and a third substrate according to a twelfth embodiment;

Fig. 28 is a schematic view of an electrical connection relationship between a third substrate and another substrate or the like according to a twelfth embodiment;

fig. 29 is a sectional view of a photoelectric conversion apparatus according to a twelfth embodiment;

fig. 30 is a schematic view of an electrical connection relationship between a second substrate and a third substrate according to a thirteenth embodiment;

fig. 31 is a schematic view of an electrical connection relationship between a third substrate and another substrate or the like according to a thirteenth embodiment;

fig. 32 is a sectional view of a photoelectric conversion apparatus according to a thirteenth embodiment;

fig. 33 is a sectional view of a photoelectric conversion apparatus according to a fourteenth embodiment;

fig. 34 is a sectional view of a photoelectric conversion apparatus according to a fourteenth embodiment;

fig. 35 is a sectional view of a photoelectric conversion apparatus according to a fourteenth embodiment;

fig. 36 is a sectional view of a photoelectric conversion apparatus according to a fourteenth embodiment;

fig. 37 is a sectional view of a photoelectric conversion apparatus according to a fourteenth embodiment;

fig. 38 is a sectional view of a photoelectric conversion apparatus according to a fourteenth embodiment;

fig. 39 is a sectional view of a photoelectric conversion apparatus according to a fifteenth embodiment;

fig. 40 is a sectional view of a photoelectric conversion apparatus according to a sixteenth embodiment;

fig. 41 is a sectional view of a photoelectric conversion apparatus according to a seventeenth embodiment;

Fig. 42 is a functional block diagram of a photoelectric conversion system according to an eighteenth embodiment;

fig. 43 is a functional block diagram of a distance sensor according to a nineteenth embodiment;

FIG. 44 is a functional block diagram of an endoscopic procedure according to a twentieth embodiment;

fig. 45A is a diagram of a photoelectric conversion system and a moving body according to a twenty-first embodiment;

fig. 45B is a diagram of a photoelectric conversion system and a moving body according to a twenty-first embodiment;

FIG. 46A is a functional block diagram of an endoscopic procedure according to a twenty-second embodiment;

fig. 46B is a functional block diagram of an endoscopic procedure according to a twenty-second embodiment.

Detailed Description

The embodiments described below are intended to specifically explain the technical concept of the present invention and should not be construed as limiting the scope of the present invention. The dimensions of the components shown in the drawings and the positional relationship therebetween are sometimes exaggerated for clarity of description. In the following description, the same reference numerals will be assigned to the same components, and explanation thereof may be omitted.

The embodiments described below relate to a photoelectric conversion device including SPADs (single photon avalanche diodes) configured to count the number of photons incident on the avalanche diodes thereof. The photoelectric conversion device includes at least an avalanche diode.

In the following description, the anode of the avalanche diode has a fixed potential, and a signal is taken out from the cathode side thereof. Therefore, the semiconductor region of the first conductivity type whose majority carrier is a charge of the same conductivity type as the signal charge is an N-type semiconductor region, and the semiconductor region of the second conductivity type is a P-type semiconductor region. The invention is also true in the case where the cathode of the avalanche diode has a fixed potential and the signal is taken out from its anode side. In this case, the semiconductor region of the first conductivity type whose majority carrier is a charge of the same conductivity type as the signal charge is a P-type semiconductor region, and the semiconductor region of the second conductivity type is an N-type semiconductor region. Although a case where a fixed potential is set at one node of the avalanche diode will be described below, the potentials at the two nodes may fluctuate.

In this specification, a plan view refers to a view seen in a direction perpendicular to a light incident surface of the semiconductor layer. The cross-sectional view refers to a view taken at a plane perpendicular to the light incident surface of the semiconductor layer. In the case where the light incident surface of the semiconductor layer is a rough surface at the time of microscopic observation, the term "plan view" is defined based on the light incident surface of the semiconductor layer at the time of macroscopic observation.

(first embodiment)

Fig. 1 is an overall view of a photoelectric conversion device 100. The first substrate 1100, also referred to as a sensor chip, has a pixel region 12, and pixels having photoelectric conversion units are arranged in a two-dimensional layout in the pixel region 12. The peripheral region 13 is disposed between the pixel region 12 and the chip end of the photoelectric conversion device 100. The second substrate 2100, also referred to as a pixel circuit chip, has a pixel circuit region 22, and a pixel circuit configured to process a signal from the photoelectric conversion unit is provided in the pixel circuit region 22. The third substrate 3100, also referred to as a signal processing chip, has a signal processing circuit region 32, and a signal processing circuit configured to process a signal from a pixel circuit is provided in the signal processing circuit region 32. The photoelectric conversion device 100 includes a first substrate 1100, a second substrate 2100, and a third substrate 3100 stacked.

(first substrate)

Fig. 2 is a configuration diagram of a first substrate 1100. On the first substrate, a pixel region 12 is provided, and at the pixel region 12, pixels 101 having photoelectric conversion units 102 including avalanche photodiodes (hereinafter simply referred to as "APDs") are arranged in a two-dimensional layout. The array of pixels 101 in the pixel region 12 may be one-dimensional. A detailed explanation of the photoelectric conversion unit 102 will be given later.

The pixels 101 are typically pixels for forming an image, but it is not necessarily necessary to form an image when used for TOF (time of flight). That is, the pixel 101 may be an element for measuring the time of arrival of light and measuring the amount of light.

(second substrate)

Fig. 3 is a configuration diagram of the second substrate 2100. The second substrate 2100 includes a pixel circuit unit 201 configured to process charges obtained by photoelectric conversion of the photoelectric conversion unit 102, a control pulse generation unit 206, a horizontal scanning circuit unit 203, a signal line 205, and a vertical scanning circuit unit 202. The pixel circuit region 22 shown in fig. 2 is a region in which at least the pixel circuit unit 201 is provided.

The photoelectric conversion unit 102 shown in fig. 2 is electrically connected to the pixel circuit unit 201 shown in fig. 3 via connection wirings provided separately for pixels.

The vertical scanning circuit unit 202 receives the control pulse supplied from the control pulse generating unit 206, and supplies the control pulse to each pixel. Logic circuits such as a shift register or an address decoder are used for the vertical scanning circuit unit 202.

The signal output from the photoelectric conversion unit 102 of each pixel is processed by the pixel circuit unit 201.

The pixel circuit unit 201 is provided with a counter, a memory, and the like. The digital values are stored in a memory.

The horizontal scanning circuit unit 203 inputs control pulses for sequential selection into the pixel circuit unit 201 for the purpose of performing signal readout from a memory storing each pixel of the digital signal.

A signal is output from the pixel circuit unit 201 of the pixel selected by the vertical scanning circuit unit 202 to the signal line 205 of the selected column.

In fig. 2 and 3, for each pixel 101, one pixel circuit unit 201 is provided correspondingly. However, the pixel circuit unit 201 may be configured such that, for example, one pixel circuit unit 201 is shared by a plurality of pixels 101, and signal processing is sequentially performed. This makes it possible to make the pixel circuit region 22 more space-saving.

(third substrate)

Fig. 4 is a configuration diagram of the third substrate 3100. The third substrate 3100 includes a memory 301, a first signal processing unit 304, a second signal processing unit 305, and control circuit units 302 and 303.

The memory 301 stores, for example, image data and the like output from the horizontal scanning circuit unit 203. The memory 301 is, for example, SRAM (static random access memory) or DRAM.

The control circuit units 302 and 303 control writing information to the memory 301 and reading information from the memory 301.

The first signal processing unit 304 performs various signal processings on the image data (image data as a processing target) read out from the memory 301. For example, if the image data as the processing target is a color image, the first signal processing unit 304 converts the format of the image data into YUV format, RGB format, or the like.

The first signal processing unit 304 performs processing such as denoising or white balance adjustment on the image data as a processing target as needed. In addition to this processing, the first signal processing unit 304 performs various signal processing (also referred to as "preprocessing") required for the second signal processing unit 305 to process the image data as a processing target.

In the case where the photoelectric conversion apparatus 100 also functions as a distance measuring apparatus, the first signal processing unit 304 also functions as, for example, a distance measuring processing unit. For example, based on information obtained from a TDC circuit (time-to-digital converter) which will be described later, the first signal processing unit 304 generates a histogram, performs distance calculation, and outputs the result to the second signal processing unit 305. The horizontal axis of the histogram represents bins (bins) with respect to time, and the vertical axis thereof represents frequencies in each bin. The frequency is the number of times light is received during a predetermined light receiving time. In the histogram, a count based on reflected light and a count based on ambient light are included in a mixed manner. Thus, the count of reflected light components and the count of ambient light components are separated from each other by setting a predetermined threshold. The distance between the distance measuring device and the measurement target object is calculated from the light arrival time corresponding to the reflected light component.

The first signal processing unit 304 can generate three-dimensional distance image data based on the calculated distance. The three-dimensional distance image data may be generated from only the information obtained at the distance measurement processing unit; alternatively, the three-dimensional distance image data may be generated by adding the calculation data acquired by the distance measurement processing unit to the image data of the two-dimensional plane.

The second signal processing unit 305 is, for example, a DSP (digital signal processor). The second signal processing unit 305 functions as a processing unit configured to execute various processes using a trained model created by machine learning by running a program stored in the memory 301. For example, the trained model is created by machine learning using a Deep Neural Network (DNN). Such trained models are also referred to as neural network computational models.

The trained model may be designed based on parameters generated by inputting training data into a predetermined machine learning model, wherein the input signals corresponding to the outputs from the pixel regions 12 and the labels of the input signals are associated with each other. The predetermined machine learning model may be a learning model using a multi-layer neural network. Such a trained model is also referred to as a multi-layer neural network model.

For example, the second signal processing unit 305 performs calculation processing based on the trained model stored in the memory 301. The result (calculation result) obtained by performing this calculation process is output to the memory 301 or the like.

The calculation result includes image data obtained by performing calculation processing using a trained model and various information (metadata) obtained from the image data. A memory controller configured to control access to the memory 15 may be built into the DSP 14.

The image data as the processing target of the second signal processing unit 305 may be image data read out from the pixel region 12 as usual, or may be reduced-size image data obtained by pixel decimation of the image data. It may be image data read out in a smaller data size than usual by performing pixel decimation readout from the pixel region 12.

The image data as the processing target of the second signal processing unit 305 may be three-dimensional distance image data. With the three-dimensional distance information data, since there is a larger amount of information than the two-dimensional image data, it is possible to recognize an object with higher accuracy and acquire object position information with higher accuracy.

As described above, when necessary, the memory 301 stores the image data output from the horizontal scanning circuit unit 203, the image data that has undergone signal processing at the first signal processing unit 304, the calculation result obtained at the second signal processing unit 305, and the like. The memory 301 also stores algorithms for the trained model run by the second signal processing unit 305.

Depending on the content of the calculation process, the second signal processing unit 305 can learn the training model by changing the weights of various parameters in the training model using the training data, and can change the training model to be used among a plurality of training models that have been prepared in advance. In addition, the second signal processing unit 305 can acquire a trained model from an external device and then perform the above-described calculation processing.

In the example shown in fig. 4, the memory 301, the first signal processing unit 304, and the second signal processing unit 305 are arranged in this order. However, as described above, the memory 301 stores information output from the first signal processing unit 304 and the second signal processing unit 305 and information input to the first signal processing unit 304 and the second signal processing unit 305. Accordingly, the memory 301 may be disposed between the first signal processing unit 304 and the second signal processing unit 305. Alternatively, the second signal processing unit 305 may be disposed between the memory 301 and the first signal processing unit 304.

The output unit 306 outputs the image data output from the second signal processing unit 305, as well as the image data and the calculation result stored in the memory 301.

The image data and the calculation result output from the output unit 306 are input to an application processor (not shown) configured to execute processing for a display, a user interface, or the like. The application processor is configured using, for example, a CPU (central processing unit) or the like, and runs an operating system, various application software, and the like. The application processor may have the function of a GPU (graphics processing unit), a baseband processor, or the like. The application processor performs various processes on the input image data and the input calculation result as needed, displays to the user, and transmits to the external cloud server via a predetermined network.

Various networks, such as the Internet, a wired LAN (local area network) or a wireless LAN, a mobile communication network,Etc. may be used as a network. The transmission destination of the image data and the calculation result is not limited to the cloud server. It may be a separately operated server, a file server archiving various data, or various information processing apparatuses (systems) having a communication function, for example, a communication terminal such as a mobile phone.

(APD and Pixel Circuit)

Fig. 5 is a diagram for explaining in more detail the block diagram that has been described with reference to fig. 2 and 3.

In fig. 2, a photoelectric conversion unit 102 having an APD 103 is provided on a first substrate 1100, and other members are provided on a second substrate 2100.

APD 103 generates charge pairs by photoelectric conversion when light enters. A voltage VL (first voltage) is supplied to the anode of APD 103. A voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of APD 103.

Reverse bias voltages that cause APD 103 to perform an avalanche multiplication operation are supplied to its anode and cathode. Supplying such a voltage causes avalanche multiplication of charges generated by incident light, thereby generating an avalanche current.

The operation mode in which the potential difference between the anode and the cathode is greater than the breakdown voltage when the reverse bias voltage is supplied is called geiger mode. The mode of operation in which the potential difference between the anode and the cathode is close to or below the breakdown voltage is referred to as the linear mode. APDs configured to operate in geiger mode are referred to as SPADs. For example, the voltage VL (first voltage) is-30V, and the voltage VH (second voltage) is 1V. In this case, for example, a potential difference between 0V, which is the ground voltage, and the voltage VL (first voltage) is larger than a potential difference between the ground voltage and the voltage VH (second voltage). For this reason, the voltage VL (first voltage) is referred to as a "high" voltage in some cases.

Quenching element 211 is connected to a power source configured to supply voltage VH and to APD 103. Quenching element 211 has the function of replacing the change in avalanche current generated at APD 103 with a voltage signal. When signal multiplication is caused due to avalanche multiplication, the quenching element 211 functions as a load circuit (quenching circuit) and has an effect of suppressing the voltage supplied to the APD 103, thereby suppressing avalanche multiplication (referred to as quenching operation).

The signal processing unit 201 includes a waveform shaping unit 212, a circuit 213 (counter circuit), and a selection circuit 214. In this specification, it is sufficient that the signal processing unit 201 includes at least any one of the waveform shaping unit 212, the circuit 213 (counter circuit), and the selection circuit 214.

The waveform shaping unit 212 shapes a change in the potential of the cathode of the APD 103 obtained during photon detection, and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 212. Although fig. 5 illustrates an example in which a single inverter is used as the waveform shaping unit 212, a circuit in which a plurality of inverters are connected in series may be used, or any other circuit having a waveform shaping effect may be used.

The circuit 213 (counter circuit) counts the pulse signals output from the waveform shaping unit 212, and holds the count value. Further, when the control pulse prs is supplied via the drive line 215, a signal held in the circuit 213 (counter circuit) is reset. The circuit 213 (counter circuit) provided for the pixel alone will tend to make the circuit scale large; accordingly, some of them may be disposed on the third substrate 3100, instead of only disposing all of them on the second substrate 2100.

The selection circuit 214 receives the control pulse pSEL supplied from the vertical scanning circuit unit 202 shown in fig. 3 via the drive line 216 shown in fig. 5, and performs switching between electrical connection and disconnection of the circuit 213 (counter circuit) and the signal line 217. The selection circuit 214 includes, for example, a buffer circuit for outputting a signal.

In the case of configuring the quenching element 211 using, for example, a MOS transistor, a pulse having a clock period may be applied to the gate of the MOS transistor. In this case, a pulse having a predetermined clock period is input from a PLL (phase locked loop) circuit not shown to the gate of the transistor constituting the quenching element 211. Assuming that the quenching element 211 has a PMOS configuration, the quenching element 211 is in an off state when a pulse supplied from the PLL circuit is at a high level. In this case, APD 103 is in a non-detection mode because no reverse bias is applied to APD 103. On the other hand, when the pulse supplied from the PLL circuit is at a low level, the quenching element 211 is in an on state, and a reverse bias is applied to the APD 103, resulting in the APD 103 being in a detection mode (standby mode). Since the clock pulse from the PLL circuit has a predetermined period, forced reset of the output signal is performed every time a clock period in the period elapses. For this reason, the photon count of one pulse is one, and even under a high-luminance condition, a signal corresponding in number to the number of photons incident thereon can be generated. The PLL circuit is disposed on any one or more of the first substrate 1100, the second substrate 2100, and the third substrate 3100.

A switch such as a transistor may be provided between the quenching element 211 and the APD 103 or between the photoelectric conversion unit 102 and the signal processing unit 201 to switch the electrical connection. Similarly, the supply of the voltage VH or the voltage VL to the photoelectric conversion unit 102 may be electrically switched using a switch such as a transistor.

In the above description, a configuration using the circuit 213 as a counter circuit is disclosed. However, the circuit 213 may be a time-to-digital conversion circuit (time-to-digital converter, hereinafter abbreviated as "TDC" circuit) that operates as a time measurement circuit, instead of the counter circuit. This makes it possible to configure the photoelectric conversion apparatus 100 that acquires the pulse detection timing.

When so configured, the timing of generation of the pulse signal output from the waveform shaping unit 212 is converted into a digital signal by the TDC circuit 213. In order to measure the timing of the pulse signal, a control pulse prsf (reference signal) is supplied from the vertical scanning circuit unit 202 shown in fig. 3 to the TDC circuit 213 via a drive line. When the input timing is regarded as a relative time with respect to the control pulse pREF, the TDC circuit 213 acquires a signal in the form of a digital signal based on the input timing of the signal output from each pixel via the waveform shaping unit 212.

The TDC circuit 213 includes, for example, an RS flip-flop, a coarse counter, and a fine counter. The driving pulse pREF drives the light emitting cell and sets the RS flip-flop. The RS flip-flop is reset by a signal pulse input from each pixel. In this way, a signal having a pulse width corresponding to the time of flight of light is generated. The generated signals are counted by a coarse counter and a fine counter each having a predetermined time resolution. As a result, a digital code is output.

A phase-locked loop circuit that generates the driving pulse prsf of the TDC circuit 213 is provided on any one or more of the first substrate 1100, the second substrate 2100, and the third substrate 3100. However, if there is a delay in the driving pulse pREF input to the TDC circuit, it will have an effect on the accuracy of the information output from the TDC circuit 213. For this reason, the PLL circuit is preferably provided on the same substrate as the substrate on which the TDC circuit 213 is provided. For example, in the present embodiment, the TDC circuit 213 and the PLL circuit configured to generate pulses to be supplied to the TDC circuit 213 are provided on the second substrate 2100.

In some cases, the PLL circuit also performs input to a circuit provided on the third substrate 3100. In this case, the following configuration may be adopted: a PLL circuit for the TDC circuit 213 is provided on the second substrate 2100, and a PLL circuit for a circuit provided on the third substrate 3100 is provided on the third substrate 3100. For example, it is conceivable to provide a single PLL circuit on the second substrate 2100, and supply a pulse signal from the PLL circuit provided on the second substrate 2100 to the circuit of the third substrate 3100. However, in this case, the following is true: the pulse signal is supplied from the PLL circuit provided on the second substrate 2100 to the circuit of the third substrate 3100 via the TSV wiring connecting the second substrate 2100 and the third substrate 3100. For this reason, there is a possibility that a process performed by the circuit of the third substrate 3100, for example, a high-speed process performed by the signal processing circuit will be affected due to a wiring capacitance of the TSV wiring or the like. To avoid this, a PLL circuit for the second substrate 2100 and a PLL circuit for the third substrate 3100 may be provided on each substrate.

In the example shown in fig. 5, a TDC circuit 213 is provided for each pixel. However, as will be described later, the TDC circuit 213 may be shared by a plurality of pixels.

(operation of APD and output Signal)

Fig. 6 is a diagram schematically illustrating the relationship between the operation of an APD and an output signal. Fig. 6 (a) is an illustration of only the APD 103, the quenching element 211, and the waveform shaping unit 212 shown in fig. 5. Let node a be the input side of the waveform shaping unit 212 and let node B be the output side of the waveform shaping unit 212. Fig. 6 (b) illustrates a change in waveform at the node a shown in fig. 6 (a). Fig. 6 (c) illustrates a change in waveform at the node B shown in fig. 6 (a).

During the period between time t0 and time t1, the potential difference between VH and VL is applied to APD 103 shown in fig. 6 (a). When a photon enters at time t1, an avalanche multiplication current flows through the quenching element 211, and the voltage of the node a drops. When the voltage drop amount further increases and the potential difference applied to APD 103 decreases, avalanche multiplication in APD 103 stops, and the voltage level of node a does not drop beyond a specific value. Thereafter, a current compensating for the voltage drop flows from the voltage VL to the node a, and at time t3, the potential level at the node a stabilizes back to its original level.

At this time, a portion of the output waveform at the node a exceeding a certain threshold is waveform shaped by the waveform shaping unit 212 and output as a signal at the node B.

In the present embodiment, a memory 301, control circuit units 302 and 303, a first signal processing unit 304, and a second signal processing unit 305 are provided on a third substrate 3100. In order to reduce the chip size of the photoelectric conversion apparatus 100, it is necessary to reduce the area other than the size of the pixel region. Further, since the avalanche photodiode includes pixel circuits configured to process signals corresponding to the photoelectric conversion units, a plurality of photoelectric conversion units are arranged on the first substrate 1100, and a plurality of pixel circuits are arranged on the second substrate 2100. For this reason, there is not enough space in the area of the second substrate 2100 overlapping the pixel area in a plan view, and therefore, it is difficult to arrange a memory and a signal processing unit on the second substrate 2100. To solve this problem, in the present embodiment, a memory and a signal processing unit are arranged on the third substrate 3100. In a plan view, the higher the ratio of the area of the pixel region to the area of the chip region of the photoelectric conversion device, the greater the need to arrange a memory and a signal processing unit on the third substrate 3100. This requirement is remarkable, for example, when the ratio of the area of the pixel region to the area of the chip region of the photoelectric conversion device is 0.8 or more.

The transistors constituting the memory and the signal processing unit provided on the third substrate 3100 are formed using finer processes than the transistors constituting the pixel circuits provided on the second substrate 2100. This is because the memory and the signal processing unit require a larger area of space than the pixel circuit. For example, the thickness of the gate oxide film of the transistor disposed on the third substrate 3100 is smaller than the thickness of the gate oxide film of the transistor disposed on the second substrate 2100. Alternatively, the gate length of the transistor disposed on the third substrate 3100 is smaller than the gate length of the transistor disposed on the second substrate 2100. Alternatively, the diameter of the via wiring provided between the interlayer films of the wiring structure (third wiring structure) of the third substrate 3100 is smaller than the diameter of the via wiring provided between the interlayer films of the wiring structure (second wiring structure) of the second substrate 2100. Alternatively, the wiring width and the inter-wiring distance of the wiring structure (third wiring structure) of the third substrate 3100 are smaller than those of the wiring structure (second wiring structure) of the second substrate 2100. The relationship with respect to the wiring width and the inter-wiring distance is a relationship defined by comparing the narrowest wiring widths of the respective two substrates with each other or comparing the shortest inter-wiring distances of the respective two substrates with each other.

Since the avalanche multiplication current flows through the quenching element 211 provided on the second substrate 2100, in the case where the quenching element 211 is configured using a MOS transistor, the gate oxide film of the MOS transistor is configured thick to enhance the withstand performance of the element. Accordingly, the process of the pixel circuit other than the quenching element 211 may be made finer than the process of the quenching element 211 on the second substrate 2100. The matters described above also apply to the quenching element 211 provided on the second substrate 2100 and transistors of other pixel circuits for the device structure in the case of making the process finer. For example, the thickness of the gate oxide film of the quenching element 211 (MOS transistor) of the second substrate 2100 is larger than the thickness of the gate oxide film of the transistor constituting the circuit other than the quenching element 211 of the second substrate 2100. Further, the thickness of the gate oxide film of the transistor constituting the circuit other than the quenching element 211 of the second substrate 2100 is larger than that of the transistor of the circuit provided on the third substrate 3100.

Further, the signal processing unit provided on the third substrate 3100 may be a processing unit using a so-called "non-von neumann" semiconductor technology, instead of a so-called "von neumann" processing unit.

(connection relation between substrates)

Referring to fig. 7 to 10, the electrical connection relationship from the first substrate to the third substrate will now be explained in detail. Fig. 7 to 9 are plan views illustrating the first to third substrates, respectively. Fig. 10 is a cross-sectional view of a photoelectric conversion device 100 including stacked first to third substrates.

(cross-sectional view of photoelectric conversion device)

Fig. 10 is a sectional view of the photoelectric conversion device 100. Light enters from the top side of fig. 10.

The first substrate 1100, the second substrate 2100, and the third substrate 3100 are sequentially formed as viewed from the light incident surface side.

The first substrate 1100 includes a semiconductor layer 1110 (first semiconductor layer) of the first substrate and a wiring structure 1120 (first wiring structure) of the first substrate.

The second substrate 2100 includes a semiconductor layer 2110 (second semiconductor layer) of the second substrate, a wiring structure 2120 (second wiring structure) of the second substrate, and a connection layer 2130 for connecting between the second wiring structure 2120 and a wiring structure 3120 (third wiring structure) of the third substrate.

The third substrate 3100 includes a semiconductor layer 3110 (third semiconductor layer) of the third substrate and a third wiring structure 3120.

The first substrate 1100 and the second substrate 2100 are attached to each other such that the first wiring structure 1120 and the second wiring structure 2120 face each other. The second substrate 2100 and the third substrate 3100 are attached to each other such that the second semiconductor layer 2110 and the third wiring structure 3120 face each other, and the connection layer 2130 is interposed between the second semiconductor layer 2110 and the third wiring structure 3120.

The package substrate 5120 is disposed on a side of the third substrate 3100 opposite to the light incident surface side, and the insulating bonding region 5110 is interposed between the package substrate 5120 and the third substrate 3100.

A first semiconductor region 1011 of a first conductivity type and a second semiconductor region 1012 of a second conductivity type are provided in the first semiconductor layer 1110 to form a PN junction and configure the APD 103 shown in fig. 5.

The third semiconductor region 1013 of the second conductivity type is arranged at a light incident surface side position with respect to the second semiconductor region 1012. The impurity concentration of the third semiconductor region 1013 is lower than that of the second semiconductor region 1012.

The "impurity concentration" referred to herein refers to the net impurity concentration compensated by the impurity of the opposite conductivity type impurity. That is, "impurity concentration" refers to the net concentration. For example, the region having a higher P-type additive impurity concentration than the N-type additive impurity concentration is a P-type semiconductor region. In contrast, the region having a higher concentration of the N-type additive impurity than the P-type additive impurity is an N-type semiconductor region.

Each pixel is separated by a fourth semiconductor region 1014 of the second conductivity type. The fifth semiconductor region 1015 of the second conductivity type is disposed at a light incident surface side position with respect to the fourth semiconductor region 1014. The fifth semiconductor region 1015 is provided as a common semiconductor region shared by pixels.

The voltage VL (first voltage) shown in fig. 5 is supplied to the fourth semiconductor region 1014. The voltage VH (second voltage) shown in fig. 5 is supplied to the first semiconductor region 1011. Due to the voltage supplied to the fourth semiconductor region 1014 and the voltage supplied to the first semiconductor region 1011, a reverse bias voltage is supplied to the second semiconductor region 1012 and the first semiconductor region 1011. Thus, a reverse bias voltage is supplied thereto that causes APD 103 to perform an avalanche multiplication operation.

The pinning layer 1031 is disposed at a light incident surface side position with respect to the fifth semiconductor region 1015. The pinning layer 1031 is a layer provided for the purpose of suppressing dark current. For example, hafnium oxide (HfO) ₂ ) The pinning layer 1031 is formed. Zirconium dioxide (ZrO) ₂ ) Tantalum oxide (Ta) ₂ O ₅ ) Etc. may be used to form the pinning layer 1031. A microlens 1032 is disposed on the pinning layer 1031 at each pixel. Although not shown, a color filter, a light shielding film such as a grid for optical separation of pixels, or the like may be provided between the microlens 1032 and the pinning layer 1031. As a material of the light shielding film, any material capable of blocking light may be used. For example, tungsten (W), aluminum (Al), copper (Cu), or the like can be used.

As described above, for the purpose of causing avalanche multiplication, a voltage serving as a reverse bias is supplied to the fourth semiconductor region 1014 and the first semiconductor region 1011. In fig. 10, a first through hole wiring (contact wiring) 1021a of the first substrate is electrically connected to the fourth semiconductor region 1014, and a wiring 1022a of the first wiring layer of the first substrate is electrically connected to the contact wiring 1021a. The wiring 1022a of the first wiring layer is electrically connected to the wiring 1022b.

The suffix "a" after the reference numeral indicates a wiring located in the pixel region 12 where the photoelectric conversion unit 102 is arranged. On the other hand, the suffix "b" is assigned to a wiring located in an area other than the pixel area 12 or in an area other than an area overlapping with the pixel area 12 in a plan view.

The wiring 1022a of the first wiring layer may be electrically connected to the wiring 1022b via another wiring layer. In the first wiring layer, the wiring 1022a and the wiring 1022b can be electrically connected to each other by being continuously/integrally formed.

The wiring 1022b is electrically connected to the second via wiring 1023b of the first substrate. The via wiring 1023b is electrically connected to the joint 1040b of the first substrate. The joint 1040b of the first substrate is in contact with and electrically connected to the joint 2040b of the second substrate. The joint described herein, which is obtained by the joint 1040b exposed in the joint face of the first substrate and the joint 2040b exposed in the joint face of the second substrate, is sometimes referred to as a metal joint (MB) structure, or a metal joint. Since copper and copper (Cu) are used in many cases, this bonding is sometimes called Cu-Cu bonding (Cu-Cu bonding).

The joint portion 2040b of the second substrate is electrically connected to the second through hole wiring 2023b of the second substrate. The second via wiring 2023b is electrically connected to the wiring 2022b of the first wiring layer of the second substrate. The wiring 2022b of the first wiring layer is electrically connected to a through wiring (hereinafter referred to as "TSV (through silicon via) wiring") 5010. The TSV wiring 5010 is a wiring formed through the semiconductor layer 2010 of the second substrate and the semiconductor layer 3010 of the third substrate. The TSV wiring 5010 is electrically connected to a wiring 3031 of a TSV opening side (side opposite to the light incident surface side) wiring layer of the third substrate. The wiring 3031 is electrically connected to the electrode 5140 via the bump 5130.

Since the voltage VL (first voltage) is supplied to the electrode 5140 electrically connected to the TSV wiring 5010, the voltage VL (first voltage) is also supplied to the fourth semiconductor region 1014 via the above-described connection wiring structure.

On the other hand, a first through-hole wiring (contact wiring) 1021a of the first substrate is electrically connected to the first semiconductor region 1011, and a wiring 1022a of the first wiring layer of the first substrate is electrically connected to the contact wiring 1021a. In addition, the wiring 1022a of the first wiring layer is electrically connected to the second via wiring 1023a of the first substrate. The via wiring 1023a is electrically connected to the joint 1040a of the first substrate. The joint 1040a of the first substrate is in contact with and electrically connected to the joint 2040a of the second substrate. The joint portion 2040a of the second substrate is electrically connected to the second through hole wiring 2023a of the second substrate. The second via wiring 2023a is electrically connected to the wiring 2022a of the first wiring layer of the second substrate. The wiring 2022a is electrically connected to a first via wiring (contact wiring) 2021 of the second substrate. The contact wiring 2021 is electrically connected to the sixth semiconductor region 2011. The sixth semiconductor region 2011 is disposed in the semiconductor layer 2010 of the second substrate. Each region of the sixth semiconductor region 2011 is separated from other regions by an element isolation region 2012. For example, the sixth semiconductor region 2011 is part of the quenching element 211. More specifically, in the case where the quenching element 211 is a MOS transistor, the sixth semiconductor region 2011 is a source region or a drain region of the MOS transistor. Although not shown in fig. 10, a waveform shaping unit 212, a counter circuit 213, and a selection circuit 214 are provided in the second substrate 2100.

The sixth semiconductor region 2011 is electrically connected to the wiring 2022b via a plurality of wirings and the semiconductor region. The wiring 2022b of the first wiring layer is electrically connected to the TSV wiring 5020. The TSV wiring 5020 is a wiring formed through the semiconductor layer 2010 of the second substrate and the semiconductor layer 3010 of the third substrate. The TSV wiring 5020 is electrically connected to the electrode 5140 via the wiring 3031 and the bump 5130.

Since the voltage VH (second voltage) is supplied to the electrode 5140 electrically connected to the TSV wire 5020, the voltage VH (second voltage) is also supplied to the first semiconductor region 1011 via the above-described connection wire structure.

The voltage supplied from the TSV wiring 5020 may be configured to be supplied to pixel circuits such as the waveform shaping unit 212, the counter circuit 213, and the selection circuit 214. That is, the voltage VH (second voltage) serves as a driving voltage for the circuits provided in the second substrate 2100. The driving voltage and the ground voltage are reference voltages, and the circuit is operated by the driving voltage and the ground voltage.

In addition, a ground voltage may be supplied to the first substrate 1100 and the second substrate 2100 through the TSV wirings 5020. However, the TSV wirings 5020 for the ground signal are another TSV wirings which are different from and electrically isolated from the TSV wirings 5020 for the driving signal, although they are described using the same drawing for convenience.

In the above description, an example in which the driving voltage for the avalanche diode provided in the first substrate 1100 and the driving voltage for the pixel circuit provided in the second substrate 2100 are supplied via the same TSV wiring 5020 has been described. However, another TSV wiring different from the TSV wiring 5020 for the avalanche diode may be provided, and a driving voltage may be supplied to the pixel circuit provided in the second substrate 2100 through the other TSV wiring.

The signal line 217 shown in fig. 5 corresponds to at least a part of the contact wiring 2021, the wiring 2022a, and the wiring 2022b in fig. 10, and these types of wirings are electrically connected to the TSV wiring 5040. The TSV wiring 5040 is electrically connected to the TSV wiring 5050 via a wiring 3031. That is, the TSV wirings 5040, 5050 are wirings for inputting a signal output from the second substrate 2100 into the third substrate 3100.

A seventh semiconductor region 3011 is formed in the semiconductor layer 3010 of the third substrate illustrated in fig. 10. Each region of the seventh semiconductor region 3011 is separated from other regions by an element isolation region 3012. The seventh semiconductor region 3011 forms transistors and the like constituting the memory 301, the first signal processing unit 304, the second signal processing unit 305, and the like. A wiring 3021 of the first through hole wiring (contact) of the third substrate is connected to the seventh semiconductor region 3011. Although not shown, the wiring 3021 of the first through hole wiring (contact) of the third substrate is also connected to the gate of the transistor provided in the third substrate. The wiring 3021 is connected to a wiring 3022 of the first wiring layer of the third substrate. Although fig. 10 illustrates only an example of a single wiring layer, the number of wiring layers may be two or more.

The wiring 3022 of the first wiring layer is electrically connected to the TSV wiring 5030. The TSV wiring 5030 is a wiring formed through the semiconductor layer 3010 of the third substrate. The TSV wiring 5030 is electrically connected to the electrode 5140 via the wiring 3031 and the bump 5130. A driving voltage for a circuit provided in the third substrate is supplied to the electrode 5140 connected to the TSV wiring 5030. The TSV wiring 5030 may be a wiring through which a ground voltage is supplied to a circuit provided in the third substrate. However, the TSV wiring 5030 for the ground signal is another TSV wiring, which is different from and electrically isolated from the TSV wiring 5030 for the driving signal, although they are described using the same drawing for convenience.

The TSV wiring 5020 is, for example, a wiring through which a driving voltage for the pixel circuit provided in the second substrate 2100 is supplied. Therefore, there is a possibility that the potential of the TSV wiring 5020 may change due to a large current and a voltage drop caused by avalanche multiplication. For this reason, if the shared TSV wirings are provided for the purpose of supplying the driving voltages for the second substrate 2100 and the third substrate 3100, there is a possibility that the voltage supplied to the circuits of the third substrate 3100 may fluctuate, and this may have an effect on high-speed operation or the like. In view of this, in the present embodiment, the TSV wiring 5020 for supplying the driving voltage for the second substrate 2100 and the TSV wiring 5030 for supplying the driving voltage for the third substrate 3100 are arranged separately from each other, thereby suppressing the influence on the third substrate 3100.

Although the TSV wirings 5010, 5020, 5030 are wirings to which a voltage having a predetermined voltage value is supplied from the outside, a power supply circuit configured to generate a voltage whose value is different from the predetermined voltage value may be provided inside the photoelectric conversion apparatus 100. The power supply circuit may be disposed on any one or more of the first substrate 1100, the second substrate 2100, and the third substrate 3100.

The number of the plurality of wirings for connecting the wirings of the first wiring structure 1120 and the wirings of the second wiring structure 2120 through the joint surface of the first substrate 1100 and the second substrate 2100 is defined herein as "first connection number". The number of the plurality of wirings for connecting the wirings of the second wiring structure 2120 and the wirings of the third wiring structure 3120 through the bonding surface of the second substrate 2100 and the third substrate 3100 is defined herein as "second connection number". When this definition is given, the first number of connections is larger than the second number of connections. Further, even if the pixel region 12 is of interest, the first connection number is larger than the second connection number.

(connection relationship between first substrate and second substrate)

Fig. 7 schematically illustrates an electrical connection relationship between the first substrate 1100 and the second substrate 2100 in a plan view. The pixels 101 having the photoelectric conversion units 102 including APDs are arranged in a two-dimensional layout.

The connection region 121 shown in fig. 7 corresponds to a joint 1040a, and the first semiconductor region 1011 of each pixel 101 is electrically connected to the second substrate via the joint 1040 a. That is, in the pixel region 12, the first substrate and the second substrate are electrically connected to each other pixel by pixel at each pixel.

The wiring 161 shown in fig. 7 corresponds to the wiring 1022b shown in fig. 10. The connection region 151 is a wiring corresponding to the joint 1040b electrically connected to the wiring 1022b shown in fig. 10.

Reference numeral 131 shown in fig. 7 denotes a unit (block) in which a predetermined circuit provided on the second substrate is shared by a plurality of pixels 101. For example, the predetermined circuit is a TDC circuit provided on the first substrate. That is, as shown in fig. 8 described later, in the example shown in fig. 7, pixels of a 4×4 matrix share one TDC circuit for a total of 16 pixels. According to this structure, the area occupied by the TDC circuit in the second substrate can be reduced. Furthermore, variations in signal timing in the block can be reduced. For example, the TDC circuit is arranged at the center of the block in the second substrate, and wiring from each pixel circuit is equally designed. This makes it possible to reduce variation in signal timing due to a wiring layout difference.

There are at least two schemes for sharing one TDC circuit for a total of 16 pixels of a 4×4 matrix.

The first approach is to use pixels of a 4 x 4 matrix as one ranging pixel for imaging. Since the circuit scale of the TDC circuit is large, for example, when a plurality of small pixels are arranged, it is difficult to individually arrange the TDC circuit for each pixel. Thus, a scheme in which a plurality of pixels share one TDC circuit may be adopted. Specifically, when used for ranging, it is not necessary to use each pixel unlike a photoelectric conversion device used for imaging purposes, and in some cases, it is not problematic to adopt a scheme of putting signals of a plurality of pixels together into one and outputting it. In this case, a scheme in which one TDC circuit is shared by a plurality of pixels is effective. Also, for avalanche diodes, there is dead time after one photon enters until it is recharged. Even if the next photon enters the same pixel during dead time, it is not possible to detect it in the form of a signal. For this reason, by configuring the pixels of the 4×4 matrix as one ranging pixel, the count loss caused by the dead time can be reduced as compared with the case where one ranging pixel is constituted by only one pixel. However, if this scheme is adopted, it is not possible to identify from which pixel the signal is output.

The second scheme is to input address information of each pixel from each pixel of the 4×4 matrix into the TDC circuit together with an output signal from the photoelectric conversion unit, and process it. With this method, unless light enters a plurality of pixels at the same time, it can be recognized from which pixel the acquired light arrival time corresponds to the output.

(connection relationship between the second substrate and the third substrate)

Fig. 8 schematically illustrates an electrical connection relationship between the second substrate 2100 and the third substrate 3100 in a plan view. In fig. 8, the vertical scanning circuit unit 202, the horizontal scanning circuit unit 203, and the control pulse generating unit 206, which have been described with reference to fig. 3, are omitted.

The connection region 221 shown in fig. 8 corresponds to the engagement portion 2040a engaged with the engagement portion 1040a shown in fig. 10. The circuit 241 is, for example, a TDC circuit, and one circuit is provided for each block 231. In the example shown in fig. 8, since signals output from sixteen pixels are processed by one circuit 241, one circuit 241 is provided for each block 231. The plurality of circuits 241 provided on each column block are connected via wirings 261. Each circuit 241 is provided for a corresponding block 231. The first circuit 241 corresponding to the first block 231 is disposed in such a manner as to overlap the first block 231 in a plan view. This layout makes it possible to reduce the signal propagation delay because the physical distance from the plurality of photoelectric conversion units belonging to the first block 231 to the first circuit 241 configured to process the output signals from these photoelectric conversion units is short. Therefore, variations in timing of processing signals between a plurality of pixels belonging to each block can be reduced.

In addition, in fig. 8, DFE 242 is correspondingly provided for each column of blocks, and each DFE 242 is connected to wiring 261. The output from the DFE 242 is input to the third substrate 3100 via the TSV wiring 252 (TSV wiring 5040 shown in fig. 10). As described herein, in the second substrate 2100, the DFE 242 is a final signal processing circuit and outputs a signal to the third substrate 3100. Accordingly, disposing the DFE 242 on the side where the TSV wire 252 (5040) is disposed facilitates efficient routing wiring, and the second substrate 2100 is connected to the third substrate 3100 via the TSV wire 252. That is, in the case where the TSV wirings through which the second substrate 2100 is connected to the third substrate 3100 are disposed in a predetermined direction with respect to the pixel region in a plan view, the DFE 242 is also disposed in a predetermined direction with respect to the pixel region. Specifically, in fig. 8, the predetermined direction is toward the bottom of the paper surface of fig. 8 with respect to the pixel region.

Further, in the present embodiment, DFE 242 is disposed in second substrate 2100, and DFE 242 is not disposed in third substrate 3100. Thus, the following is possible: DFE 242 is disposed between circuit 241 (TDC circuit) and TSV wiring 252 (5040) which are part of the pixel circuit. If the pixel circuit is connected to the TSV wiring 252 (5040) and if the TDC circuit is disposed downstream thereof, the capacitance added to the pixel circuit increases. Thus, signal propagation delays may occur, which may lead to variations in signal processing. In view of this, DFE 242 is disposed between the TDC circuitry and TSV wiring 252 (5040), thereby suppressing the above-described problems.

In fig. 8, the TSV wiring 251 of the second substrate 2100 (TSV wiring 5010 shown in fig. 10) is a wiring via which the voltage VL is supplied to the APD 103. The TSV wiring 253 of the second substrate 2100 (TSV wiring 5020 shown in fig. 10) is a wiring through which a driving voltage is supplied to the second substrate 2100.

(connection relation between the third substrate and other Member)

Fig. 9 schematically illustrates in a plan view an electrical connection relationship between the third substrate 3100 and the outside of the semiconductor device, the second substrate 2100, and the first substrate 1100.

In fig. 9, a memory 301, control circuit units 302 and 303, a first signal processing unit 304, and a second signal processing unit 305 shown in fig. 4 are illustrated.

At the top of fig. 9, a TSV wiring 354 (TSV wiring 5030 shown in fig. 10) and a TSV wiring 355 (TSV wiring 5020 shown in fig. 10) are illustrated. At the bottom of fig. 9, a TSV wiring 352 (TSV wiring 5030 shown in fig. 10), a TSV wiring 355 (TSV wiring 5020 shown in fig. 10), and a TSV wiring 354 (TSV wiring 5030 shown in fig. 10) are illustrated.

Referring back to fig. 10, the bonding portions 1040a and 1040b of the first substrate include a plurality of bonding portions that are not electrically connected to the first semiconductor region 1011 of the first substrate 1100 or the semiconductor region constituting the circuit of the second substrate 2100. The purpose of these joints is to strengthen the joint of the first substrate 1100 and the second substrate 2100 with each other. These junctions may be electrically floating or electrically connected to a drive voltage or a ground voltage.

(manufacturing method)

Fig. 11 to 13B are diagrams for explaining a method of manufacturing the photoelectric conversion apparatus 1000 according to the first embodiment.

Fig. 11 is a diagram illustrating a step of bonding the first substrate 1100 and the second substrate 2100 to each other. Specifically, the first substrate 1100 and the second substrate 2100 are stacked such that a wiring structure 1120 (first wiring structure) of the first substrate and a wiring structure 2120 (second wiring structure) of the second substrate are provided between the first semiconductor layer 1010 and the second semiconductor layer 2010. In this step, the joint 1040 of the first substrate and the joint 2040 of the second substrate are joined to each other to become metal joints.

Fig. 12 is a diagram illustrating a step of stacking the third substrate 3100 on the first substrate 1100 and the second substrate 2100 after stacking these substrates. Specifically, the third substrate is stacked such that a wiring structure 3020 thereof (a third wiring structure) is provided between the second semiconductor layer 2010 and the third semiconductor layer 3010.

Before stacking the third substrate 3100, the second semiconductor layer 2010 of the second substrate 2100 is thinned through a thinning step. In addition, after the step of thinning the second semiconductor layer 2010, an insulating layer 2030 is provided. The insulating layer 2030 is a layer made of, for example, silicon oxide. Thereafter, as shown in fig. 12, the third substrate 3100 is stacked on the stack including the first substrate 1100 and the second substrate 2100.

Fig. 13A is a diagram illustrating a wiring step of disposing TSVs and a thinning step of thinning the first substrate. Specifically, TSV wirings 5010 to 5050 and the like are formed, and a support substrate 3050 for the third substrate is provided on the surface (back surface) of the third substrate 3100 on the third semiconductor layer 3010 side. Next, a thinning step of thinning the first semiconductor layer 1010 of the first substrate 1100 from the light incident surface side (back surface side) is performed. The support substrate 3050 is a step required in the step of thinning the first semiconductor layer 1010.

Fig. 13B is a diagram illustrating the wafer step and the mounting step in the latter half of the process. Specifically, first, the pinning layer 1031 and the microlenses 1032 are provided. Next, the support substrate 3050 for the third substrate is removed. This completes the wafer step. Finally, as a mounting step, the package substrate 5120 is mounted with the bump 5130 and the insulating bonding region 5110 sandwiched therebetween.

The thickness of the first substrate 1100 provided with the pixels is about one fifth to one tenth of the thickness of the second substrate 2100 and the thickness of the third substrate 3100. This is because the thickness of the first semiconductor layer 1110 is reduced to about 2 to 10 μm by the above-mentioned thinning step depending on the wavelength of the photoelectrically converted light. The thickness of the second substrate 2100 and the thickness of the third substrate 3100 are determined depending on the elements provided in the respective substrates; for example, in the case where a DRAM is provided as a memory in the third substrate 3100, the third substrate 3100 is configured to have a thickness of about 50 to 100 μm. The same is true in the case where processing circuits other than the memory are provided in the third substrate. The number of wiring layers provided in the wiring structure 1120 of the first substrate 1100 is smaller than the number of wiring layers provided in the wiring structure of the substrate in which the memory or the processing circuit is provided. The number of wiring layers provided in the wiring structure 1120 of the first substrate 1100 and the number of wiring layers provided in the wiring structure of the substrate in which the memory or the processing circuit is provided are each about 5 to 10. In each wiring structure, wirings different in main component from one wiring layer to another wiring layer may be provided. The main component is, for example, aluminum, copper, tungsten, etc. For example, one of the six wiring layers may be aluminum as a main component, and the other five layers may be copper as a main component. Further, the main component contained in the largest number of wiring layers in one wiring structure may be different from the main component contained in the largest number of wiring layers in another wiring structure. For example, the main component contained in the largest number of wiring layers in the wiring structure 1120 of the first substrate 1100 may be copper, and the main component contained in the largest number of wiring layers in the wiring structure 2120 of the second substrate 2100 may be aluminum.

(second embodiment)

A second embodiment is illustrated in fig. 14. The second embodiment is different from the first embodiment in contact with the wiring structure 1120 of the first substrate.

That is, as shown in fig. 10, in the first embodiment, the TSV wiring 5010 is in contact with the wiring structure 2120 of the second substrate, whereas in the second embodiment, the TSV wiring 5010 extends through the wiring structure 2120 of the second substrate and is in contact with the wiring structure 1120 of the first substrate. Further, the TSV wiring 5010 does not transmit the supplied voltage via metal bonding provided in the wiring structure 1120 of the first substrate and the wiring structure 2120 of the second substrate.

The voltage VL supplied to the TSV wiring 5010 is a voltage supplied to the fourth semiconductor region 1014 and is high. In addition, a circuit to which a fine process is applied may be provided in the signal processing unit 201 provided in the second substrate 2100. Accordingly, a voltage can be directly supplied to the fourth semiconductor region 1014 via the TSV wiring 5010 without passing through a wiring provided in a wiring layer of the wiring structure 2120 of the second substrate. In this way, the possibility of damaging the circuit provided in the second substrate 2100 to which the fine process is applied can be reduced.

(third embodiment)

A third embodiment is illustrated in fig. 15. The third embodiment is different from the first and second embodiments in that an electrode electrically connected to the outside is provided on the light incident side.

That is, in the first embodiment and the second embodiment, the electrode 5140 provided in the side surface (second surface) opposite to the light incident surface (first surface) is an electrode electrically connected to the outside. In contrast, in the third embodiment, the electrodes 4210, 4220, and 4230 provided on the light incident side are electrodes electrically connected to the outside. The electrodes 4210 to 4230 are also referred to as "pad electrodes".

As described above, the voltage VL supplied to the fourth semiconductor region 1014 is a high voltage, and a circuit to which a fine process is applied is provided in the second substrate 2100. Accordingly, as shown in fig. 15, by adopting a configuration in which the voltage supplied from the electrode 4210 is supplied only to the first substrate 1100, it is possible to avoid a high voltage from being applied to a circuit to which a fine process is applied and which is provided in the second substrate 2100.

Further, in fig. 15, an electrode 4220 through which a driving voltage for the second substrate 2100 is supplied from the outside is provided in the wiring layer of the wiring structure 2120. In some cases, circuits required for high-speed operation are provided in the second substrate 2100. A case where a driving voltage is supplied to the wiring layer of the wiring structure 2120 of the second substrate via the wiring structure 1120 of the first substrate is defined as a first case. The case where voltage is directly supplied to the wiring structure 2120 of the second substrate is defined as a second case. In the second case, the length of wiring from the electrode connected to the outside to the circuit provided in the second substrate 2100 is smaller than that in the first case. As the wiring length increases, there is a possibility that the operation of circuits required for high-speed operation may become slow due to signal propagation delay. In view of this, in the present embodiment, the electrode 4220 through which the driving voltage for the second substrate 2100 is externally supplied is provided in the wiring layer of the wiring structure 2120.

Further, in fig. 15, an electrode 4230 through which a driving voltage for the third substrate 3100 is externally supplied is provided in a wiring layer of the wiring structure 2120 of the second substrate. The electrode 4230 is electrically connected to the TSV wiring 5070 via a wiring layer of a wiring structure 2120 of the second substrate. The TSV wiring 5070 shown in fig. 15 is a wiring corresponding to the TSV wiring 5030 shown in fig. 10. However, the TSV wiring 5070 shown in fig. 15 extends through the semiconductor layer 2010 of the second substrate, the wiring structure 3120 of the third substrate, and the semiconductor layer 3010 of the third substrate and is electrically connected to the TSV wiring 5030.

(fourth embodiment)

A fourth embodiment is illustrated in fig. 16. The fourth embodiment is different from the third embodiment in that an electrode which is electrically connected to the outside and via which a driving voltage is supplied to a circuit of the third substrate 3100 is provided in the wiring structure 3120 of the third substrate.

In some cases, circuits required for high-speed operation are also provided in the third substrate 3100. In view of this, as shown in fig. 16, an electrode 4240 may be provided in the wiring structure 3120 of the third substrate, and a driving voltage for the third substrate 3100 may be supplied from the outside via the electrode 4240. With this structure, wiring from the electrode 4240 to which the driving voltage is supplied from the outside to the circuit provided in the third substrate 3100 can be made shorter, and the possibility of an operation delay of the circuit required for high-speed operation can be reduced.

When the electrodes 4210, 4220, and 4240 shown in fig. 16 are formed, it is necessary to provide a pad opening by etching an interlayer insulating film or the like which is a part of a wiring structure or a silicon substrate. Since the wiring layers in contact with the three electrodes are wiring layers having different levels from each other, the number of opening steps corresponding to the number of pad openings is required.

(fifth embodiment)

Fig. 17 illustrates a fifth embodiment. The fifth embodiment is different from the first and second embodiments in that an electrode which is electrically connected to the outside and via which a voltage is supplied to the fourth semiconductor region 1014 of the first substrate 1100 is led out from the light irradiation face side.

That is, in the first embodiment described with reference to fig. 10 and the second embodiment described with reference to fig. 14, all the electrodes electrically connected to the outside are led out from the side face (second face) opposite to the light incident face (first face). However, for the purpose of suppressing the decrease in reliability, it is desirable not to supply a voltage to the high-voltage wiring for supplying power to the first substrate 1100 via the second substrate 2100 and the third substrate 3100. For this reason, in fig. 17, the electrode 4210 is disposed on the wiring layer of the wiring structure 1120 of the first substrate, and does not supply a high voltage to the second substrate 2100 or the third substrate 3100.

(sixth embodiment)

Fig. 18 illustrates a sixth embodiment. The sixth embodiment is different from the first embodiment in that the wiring structure of the second substrate and the wiring structure of the third substrate have metal bonding structures.

That is, in fig. 10, the electrode 5140 is connected to a wiring layer of the wiring structure 2120 of the second substrate by using a single TSV wiring 5010. In contrast, in fig. 18, the electrode 5140 is connected to the wiring layer of the wiring structure 2120 of the second substrate by using a TSV wiring having a two-level structure including two TSV wirings 5310 and 5320. In addition, a metal bonding structure including a bonding portion 2050b of a second substrate and a bonding portion 3040b of a third substrate bonded to each other is provided between the TSV wiring 5310 and the TSV wiring 5320.

Further, in fig. 18, the TSV wiring 5040 shown in fig. 10 is also replaced with a TSV wiring having a two-stage structure including a TSV wiring 5330 and a TSV wiring 5340. In addition, a metal bonding structure is provided between the TSV wiring 5330 and the TSV wiring 5340.

Further, in fig. 18, the TSV wiring 5020 shown in fig. 10 is also replaced with a TSV wiring having a two-stage structure including a TSV wiring 5350 and a TSV wiring 5360. In addition, a metal bonding structure is provided between the TSV wiring 5350 and the TSV wiring 5360.

The above-described structure shown in fig. 18 makes it unnecessary to provide TSV wirings extending through both the semiconductor layer 2010 of the second substrate and the semiconductor layer 3010 of the third substrate.

In addition, a metal bonding structure including a bonding portion 2050a of the second substrate and a bonding portion 3040a of the third substrate bonded to each other is provided at the pixel region. The metal bond structure need not form part of the circuitry provided in the substrate. In this way, the bonding strength of the second substrate 2100 and the third substrate 3100 may be increased.

(seventh embodiment)

A seventh embodiment is illustrated in fig. 19. The seventh embodiment is different from the third embodiment shown in fig. 15 in that the second substrate and the third substrate are electrically connected to each other via a metal bonding structure. Further, the seventh embodiment is different from the sixth embodiment shown in fig. 18 in that an electrode connected to the outside is provided on the light incident surface (first surface) side.

As shown in fig. 19, a joint 2050b of the second substrate and a joint 3040b of the third substrate are provided; thus, in fig. 19, the TSV wirings 5050 and 5040 shown in fig. 15 are functionally integrated into a monolithic TSV wiring 5370. Although the TSV wiring 5040 extends through both the semiconductor layer 2010 of the second substrate and the semiconductor layer 3010 of the third substrate in fig. 15, the structure according to the seventh embodiment makes such double-pass TSV wiring unnecessary.

In addition, in fig. 19, the TSV wiring 5030 and the TSV wiring 5070 shown in fig. 15 are functionally integrated as a monolithic TSV wiring 5380. Although the TSV wiring 5070 extends through both the semiconductor layer 2010 of the second substrate and the semiconductor layer 3010 of the third substrate in fig. 15, the structure according to the seventh embodiment makes such double-pass TSV wiring unnecessary.

Further, a wiring via which a driving voltage is supplied to a circuit provided in the second substrate is electrically connected to a wiring layer of the wiring structure 1120 of the first substrate via the joint 1040b of the first substrate and the joint 2040b of the second substrate. An electrode 4250 is provided on the wiring layer. The electrode 4250 functions as a pad portion for electrical connection to the outside.

In addition, a wiring via which a driving voltage is supplied to a circuit provided in the third substrate is electrically connected to the wiring layer of the wiring structure 1120 of the first substrate via the bonding portion 2050b of the second substrate and the bonding portion 3040b of the third substrate. An electrode 4260 is provided on the wiring layer. The electrode 4260 serves as a pad portion for electrical connection to the outside.

As described above, the electrode 4210, the electrode 4250, and the electrode 4260 are provided so as to be in contact with the same wiring layer of the wiring structure 1120 of the first substrate. For this reason, the pad openings formed when forming these electrodes have substantially the same depth. Therefore, the process of the wiring step is easier to perform than the example shown in fig. 15.

(eighth embodiment)

An eighth embodiment is illustrated in fig. 20. In a sixth embodiment, a metal bond is used to bond the second and third substrates together. The eighth embodiment is different from the eighth embodiment in that the second substrate and the third substrate are bonded together using micro bumps.

As shown in fig. 20, a wiring 3021 of a first via wiring and a wiring 3022 of a first wiring layer connected thereto are provided in a wiring structure 3120 of the third substrate. In addition, a wiring 3023 connected to a second via wiring of the wiring 3022 and a wiring 3024 connected to a second wiring layer of the wiring 3023 are provided. On the other hand, in the wiring structure 2120 of the second substrate, a wiring 2060 connected to the TSV wiring 5340 is provided, and the wiring 2060 of the second substrate is electrically connected to the wiring 3024 of the third substrate via the microbump 2070. The micro bumps are formed using Cu bump bonding based on solid phase diffusion or using micro bump bonding based on solder melting. An organic filler material is placed in the gaps between the microbumps 2070.

(ninth embodiment)

A ninth embodiment is illustrated in fig. 21. In the first embodiment, the TSV wirings are used to input signals output from the second substrate into the third substrate. The ninth embodiment differs therefrom in that a metal bond is used for this purpose.

As shown in fig. 21, an output from a circuit provided in the second substrate 2100 is input to a circuit provided in the third substrate 3100 via a wiring 2080. A trench structure 2081, i.e., a DTI (deep trench isolation) structure, penetrating the semiconductor layer 2010 of the second substrate is formed in the second substrate 2100. The trench structure 2081 is filled with an insulating material 2082 to avoid electrical connection between the wiring 2080 and the semiconductor layer 2010 of the second substrate.

In fig. 21, it is assumed that a circuit corresponding to each pixel is provided in the second substrate 2100, and it is shown that an output from the circuit corresponding to each pixel is input into a circuit of the third substrate. In this case, a wiring 2080 is provided for each pixel, and the wiring 2080 is connected via a joint 2050a of the second substrate, a joint 3040a of the third substrate, or the like, for input to a circuit of the third substrate 3100. The circuit of the third substrate 3100 is also provided correspondingly for each pixel. That is, in the example shown in fig. 18, the photoelectric conversion unit is electrically connected to the circuit of the second substrate 2100 pixel by pixel via metal bonding, and a signal is input from the photoelectric conversion unit to the circuit of the second substrate 2100. In addition, the circuit of the second substrate 2100 configured to output a signal to the circuit of the third substrate 3100 is electrically connected to the circuit of the third substrate 3100 pixel by pixel via metal bonding.

In fig. 21, a distance between a plurality of wirings 2080 positioned adjacent to each other is denoted as L1. In the case where there are a plurality of distances between the plurality of wirings 2080 positioned adjacent to each other, L1 represents the shortest distance. When P represents the pitch between pixels, the relationship of 0.8P < L1 < 1.2P is satisfied. Preferably, the relationship 0.9P < L1 < 1.1P is satisfied.

A distance between the plurality of contact wirings 1021 connected to the first semiconductor region 1011 may be defined as a pitch P. That is, a distance between the first contact wiring 1021 connected to the first semiconductor region 1011 of the first pixel and the second contact wiring 1021 connected to the first semiconductor region 1011 of the second pixel positioned adjacent to the first pixel may be defined as a pitch P.

In fig. 21, TSV wirings 5040 and 5050 for electrical connection between the second substrate 2100 and the third substrate 3100 are provided. In fig. 10 according to the first embodiment, TSV wirings 5040, 5050 are wirings for inputting a signal output from the second substrate 2100 into the third substrate 3100. In the present embodiment, a plurality of wirings 2080 are used to input signals output from the second substrate 2100 into the third substrate 3100; thus, the TSV wirings 5040 and 5050 can be omitted.

On the other hand, the circuit provided in the second substrate 2100 and the circuit provided in the third substrate 3100 may share a power wiring or a ground wiring for applying a driving voltage. In this case, a common potential can be supplied to the circuit provided in the second substrate 2100 and the circuit provided in the third substrate 3100 by using the TSV wirings 5040 and 5050 shown in fig. 21. Alternatively, a common potential may be supplied to the circuit provided in the second substrate 2100 and the circuit provided in the third substrate 3100 by using metal bonding wires including the bonding portion 2050b of the second substrate and the bonding portion 3040b of the third substrate.

The circuits of the second substrate 2100 provided correspondingly for the respective pixels may be of a translationally symmetrical layout as viewed in a plan view. Alternatively, the circuits of the second substrate 2100 correspondingly provided for the respective pixels may be in a line symmetrical (mirror symmetrical) layout when viewed in a plane. In the case of employing a mirror-symmetrical layout, the first circuit of the second substrate 2100 corresponding to the first pixel and the second circuit of the second substrate 2100 corresponding to the second pixel easily share part of functions or members, thereby realizing a smaller space. For example, a common well of MOS transistors constituting the first circuit and the second circuit may be employed. In this way, the area of the circuit provided in the second substrate 2100 can be reduced. In particular, in the case where the photoelectric conversion units are arranged at a narrow pitch, it is possible to avoid a case where the photoelectric conversion units cannot be arranged at a narrow pitch due to the limitation of the area occupied by the circuits of the second substrate 2100.

In addition, the circuits of the third substrate 3100 provided correspondingly for the respective pixels may be in a translationally symmetrical layout or in a line symmetrical (specular) layout when viewed in a plane. In the latter case, the above benefits may be enjoyed.

As described above, fig. 21 discloses an example in which the circuit of the second substrate 2100 configured to output signals to the circuit of the third substrate 3100 and the circuit of the third substrate 3100 are separately provided for pixels. However, even in the case of providing the circuit of the second substrate 2100 to which a signal is input from the photoelectric conversion unit on a pixel-by-pixel basis, a circuit configured to perform subsequent signal processing may be provided on a pixel-by-pixel basis. That is, one signal processing circuit of the second substrate 2100 is provided for each pixel block. In this case, the following is the case: the circuit of the second substrate 2100 configured to output a signal to the circuit of the third substrate 3100 is not electrically connected to the circuit of the third substrate 3100 via metal bonding for each pixel but for each pixel block. Specifically, the following are: the wiring 2080 is not provided for each pixel but for each pixel block. In this case, the number of the plurality of metal bonds via which the first substrate 1100 and the second substrate 2100 are bonded to each other is greater than the number of the plurality of metal bonds via which the second substrate 2100 and the third substrate 3100 are bonded to each other.

(tenth embodiment)

A tenth embodiment is illustrated in fig. 22. The pixel structure of the photoelectric conversion unit according to the tenth embodiment is different from that of the first embodiment in that it has a smaller avalanche multiplication region.

In fig. 22, the width (length in the horizontal direction of the drawing) of the first semiconductor region 1011 of the first conductivity type is smaller than the width of the first semiconductor region 1011 shown in fig. 10. Although not shown, the area of the first semiconductor region 1011 shown in fig. 19 is smaller than the area of the first semiconductor region 1011 shown in fig. 10 in a plan view.

Further, in a plan view, the sixth semiconductor region 1016 is provided at a position where it overlaps the first semiconductor region 1011 of the first conductivity type. The sixth semiconductor region 1016 may be of the first conductivity type or the second conductivity type. The sixth semiconductor region 1016 is configured such that a potential related to the signal charge is lower than a potential at the second semiconductor region 1012. For example, if the sixth semiconductor region 1016 is of the first conductivity type, the impurity concentration of the sixth semiconductor region 1016 is lower than the impurity concentration of the first semiconductor region 1011.

Due to the above potential structure, the electric charges generated at the third semiconductor region 1013 are more easily collected to the sixth semiconductor region 1016 than the second semiconductor region 1012. The collected signal charges are multiplied at an avalanche multiplication region formed between the sixth semiconductor region 1016 and the first semiconductor region 1011.

Further, seventh semiconductor regions 1017 are provided on both sides adjacent to the first semiconductor regions 1011 of the first conductivity type. The conductivity type of the seventh semiconductor region 1017 may be the first conductivity type or the second conductivity type. For example, if the seventh semiconductor region 1017 is of the first conductivity type, the impurity concentration of the seventh semiconductor region 1017 of the first conductivity type is lower than the impurity concentration of the first semiconductor region 1011. If the seventh semiconductor region 1017 is of the second conductivity type, the impurity concentration of the seventh semiconductor region 1017 is lower than the impurity concentration of the fourth semiconductor region 1014 of the second conductivity type.

By using the relationship of the impurity concentrations described above, the possibility of formation of an avalanche multiplication region between the first semiconductor region 1011 and the seventh semiconductor region 1017 can be reduced.

Since the present embodiment includes the above-described structure, the charges generated at the third semiconductor region 1013 can be effectively collected and avalanche multiplication is caused; therefore, the sensitivity of the photoelectric conversion unit is more easily improved. Further, since the width or area of the first semiconductor region 1011 is smaller than that in the first embodiment, the avalanche multiplication region can be made smaller; therefore, the value of DCR (dark count rate) can be reduced.

(eleventh embodiment)

An eleventh embodiment is illustrated in fig. 23 to 25. Fig. 1 to 6 and 10 described previously in the first embodiment are also applicable to the structure of the eleventh embodiment. The eleventh embodiment is different from the first embodiment in which a processing circuit is provided for each pixel block in that a processing circuit is provided for each pixel column.

Fig. 23 schematically illustrates an electrical connection relationship between the first substrate 1100 and the second substrate 2100 in a plan view. The difference from fig. 7 is that the concept of pixel blocks is not illustrated in the figure.

Fig. 24 schematically illustrates an electrical connection relationship between the second substrate 2100 and the third substrate 3100 in a plan view. In fig. 8, a circuit 241 is provided for each block, and in fig. 21, a circuit 241 is provided for each pixel column. Further, in fig. 8, the circuit 21 is provided at a region overlapping with the pixel region, whereas in fig. 24, the circuit 21 is provided at a region not overlapping with the pixel region. That is, in fig. 24, the circuit 241 is provided at a peripheral region located outside the pixel region. The circuit 241 is, for example, a TDC circuit. With this structure, since the heat propagation from the plurality of photoelectric conversion units and the heat propagation from the TDC circuit do not interfere with each other, the heat propagation between the first substrate 1100 and the second substrate 2100 can be suppressed. This makes it possible to stably operate the photoelectric conversion apparatus 100.

A pixel circuit region in which pixel circuits configured to process signals from the photoelectric conversion units are two-dimensionally disposed is provided in the second substrate 2100. If the TDC circuit is disposed in the pixel region, the area occupied by the pixel circuit will be limited. In order to realize a complex function of the pixel circuit, the area occupied by the pixel circuit needs to be large. Therefore, in order to realize a complex function of the pixel circuit, the TDC circuit is provided at a peripheral region located outside the pixel region. For example, if it is assumed to be used as a ToF system, it is conceivable to separately set an external light removal circuit for each pixel. Providing the TDC circuit at the peripheral region makes it possible to arrange the external light removing circuit as a pixel circuit at the pixel region of the second substrate 2100. This makes it possible to realize a complex function of the pixel circuit.

Further, it is preferable that the circuit 241 (for example, a TDC circuit) should be disposed at a distance of 2 μm or more between the circuit 241 and a pixel circuit located closest to the circuit 241 in a plan view among the pixel circuits. Since the distance between the circuit 241 and the pixel region where the photoelectric conversion unit is arranged increases in a plan view, the distance between the circuit 241 of the second substrate 2100 and the pixel region of the first substrate 1100 also increases. Therefore, even if heat is generated in the pixel region of the first substrate 1100, the influence of the heat on the TDC circuit can be reduced. In contrast, even if the TDC circuit of the second substrate 2100 generates heat, the influence of the heat on the photoelectric conversion unit included in the pixel region of the first substrate 1100 can be reduced.

Fig. 25 schematically illustrates in a plan view an electrical connection relationship between the third substrate 3100 and the outside of the semiconductor device, the second substrate 2100, and the first substrate 1100. The difference from fig. 9 is that the memory 301 is not provided in the third substrate 3100. In fig. 25, a third signal processing unit 309 is provided. That is, the signal output from the second substrate 2100 is processed by the third substrate 3100 without passing through the memory. With this structure, it is possible to make the area where the signal processing unit is provided larger and to perform processing with a heavier load than in the first embodiment. For example, a trained model may be installed to perform the more heavily loaded calculations.

(twelfth embodiment)

A twelfth embodiment is illustrated in fig. 26 to 29. The twelfth embodiment is different from the first embodiment in that a processing result of a signal processing unit provided in a third substrate is fed back to a control circuit unit of a second substrate to realize a photoelectric conversion device of high accuracy or complex function.

Fig. 26 schematically illustrates an electrical connection relationship between the first substrate 1100 and the second substrate 2100 in a plan view. Reference numeral 131 denotes a unit (block) in which a predetermined circuit provided on the second substrate is shared by the plurality of pixels 101.

Fig. 27 schematically illustrates an electrical connection relationship between the second substrate 2100 and the third substrate 3100 in a plan view. In fig. 27, the vertical scanning circuit unit 202 and the horizontal scanning circuit unit 203 (which may be collectively referred to as "scanning circuit unit") omitted in fig. 8 described previously in the first embodiment are illustrated. Further, a control unit 243 for controlling the scanning circuit units 202, 203 or other circuits is provided. Fig. 27 illustrates an example in which the control unit 243 controls the scan circuit units 202, 203. In the example shown in fig. 27, control lines are supplied from the scanning circuit units 202, 203 to the pixel circuit units block by block; however, the control lines may be provided pixel by pixel.

The TSV wiring 254 (TSV wiring 5080 shown in fig. 29) is a wiring for transmitting a processing result of the signal processing unit provided in the third substrate 3100 to the control unit 243 provided in the second substrate 2100. Specifically, as shown in fig. 29, the processing result of the signal processing unit of the third substrate 3100 is input into the control unit 243 via the TSV wiring 5090, the wiring 3031, and the TSV wiring 5080 (TSV wiring 254 shown in fig. 27).

The control unit 243 can perform various controls.

For example, exposure control may be performed so that the exposure time of one pixel block is different from the exposure time of another pixel block. Specifically, in the pixel region, when comparison is performed in a unit time, there may be a pixel block (first pixel block) in which a larger number of photons are detected and a pixel block (second pixel block) in which a smaller number of photons are detected. In this case, the control unit 243 can perform control so that the exposure time of the second pixel block is longer than the exposure time of the first pixel block. In this way, the dynamic range can be enlarged. For example, the control unit 243 can control the exposure time of each pixel block acquired in the previous frame based on the count value of the pixel block, that is, the processing result of the signal processing unit of the third substrate 3100. The exposure time may be controlled based on whether reverse bias is applied to the photoelectric conversion unit for the purpose of performing avalanche multiplication, or based on whether pulses corresponding to photons are counted by a counter.

As another example, when the photoelectric conversion apparatus disclosed herein is applied to a system (e.g., a monitoring camera) that ensures safety or assurance, there is a need to perform image capturing at low resolution before an event occurs and at high resolution after the event occurs. This is because the power consumption of the avalanche diode is large due to the application of a high voltage, and thus image capturing at a low resolution before an event occurs makes it possible to reduce such power consumption of the avalanche diode. In view of this, the signal processing unit of the third substrate 3100 may determine whether an event occurs, and based on the result of the determination, the control unit 243 may perform control of switching from the low resolution mode to the high resolution mode. Specifically, for example, a low resolution mode can be realized by acquiring photons by applying a reverse bias to only one pixel out of a total of four pixels of a 2×2 matrix of pixels. Then, when an event occurrence is detected, the control unit 243 performs control to use all pixels of the 2×2 matrix for photon acquisition. A second signal processing unit 305 with a trained model created by machine learning may be used to determine if an event has occurred. The event is detection of a suspicious person or a suspicious object, detection of a person or object whose number is greater than a predetermined number, collision prediction of a moving body, or the like. Although the power consumption reduction is achieved by switching the photoelectric conversion unit in the above description, the power consumption reduction may be achieved by switching whether or not the counting of the counter is performed.

As another example, only information about a region of interest (ROI) may be acquired. For example, when there is a detection target object of interest only in a partial region thereof, photoelectric conversion of other regions thereof is wasteful of power consumption. To avoid such wasteful consumption, the control unit 243 performs control to acquire information about the region of interest. Specifically, the signal processing unit of the third substrate 3100 determines a region of interest of the detection target object, and the control unit 243 controls to photoelectrically convert the region of interest, but not the region other than the region of interest. In this way, power consumption can be reduced. Alternatively, the control unit 243 may perform control so as not to count photons of the region of interest by the counter, and to count photons of the region of interest by the counter. Also in this case, power consumption can be reduced by stopping unnecessary counting.

Fig. 28 schematically illustrates in a plan view an electrical connection relationship between the third substrate 3100 and the outside of the semiconductor device, the second substrate 2100, and the first substrate 1100. The difference from fig. 9 described previously in the first embodiment is that TSV wiring 356 (TSV wiring 5090 shown in fig. 26) and TSV wiring 357 (TSV wiring 5080 shown in fig. 26) are illustrated in this figure. These TSV wirings are used to transmit the processing results of the signal processing unit provided in the third substrate 3100 to the control unit 243 provided in the second substrate 2100.

(thirteenth embodiment)

A thirteenth embodiment is illustrated in fig. 30 to 42. The thirteenth embodiment is different from the first embodiment in that a circuit (e.g., a TDC circuit) is provided in a third substrate. In the thirteenth embodiment, the electrical connection relationship of the first substrate 1100 is the same as that of fig. 26; thus, reference is made thereto.

Fig. 30 schematically illustrates an electrical connection relationship between the second substrate 2100 and the third substrate 3100, and the like in a plan view. The control circuit units 302 and 303 are omitted. The TSV wirings 254 are disposed at the center of each block 231. The TSV wiring 254 (TSV wiring 5040 shown in fig. 32) is a wiring for inputting the output of the second substrate 2100 into the third substrate 3100.

Fig. 31 schematically illustrates an electrical connection relationship between the second substrate 2100 and the third substrate 3100 in a plan view. In the third substrate 3100, a plurality of signal processing blocks 331 are provided for the plurality of blocks 231 of the first substrate 1100 and the second substrate 2100, respectively.

Specifically, in the thirteenth embodiment, a circuit 307 corresponding to the circuit 241 of the first embodiment is provided for each signal processing block. The circuit 307 is, for example, a TDC circuit. For example, in a case where it is difficult to arrange the TDC circuit 307 in the second substrate 2100 due to an increase in the circuit scale of other circuits arranged in the second substrate 2100, the TDC circuit 307 may be provided in the third substrate 3100 as in the present embodiment.

Further, in the case where the photoelectric conversion apparatus 100 is used as an imaging photoelectric conversion apparatus, the counter circuit 213 may be provided in both the second substrate 2100 and the third substrate 3100. This is because, in the APD, a counter is provided for each pixel, and thus the circuit scale constituting the counter is large, and the area occupied in the second substrate 2100 is also large. Further, in the thirteenth embodiment, DFE 308 corresponding to DFE 242 of the first embodiment is provided in each signal processing block 331.

Further, in the thirteenth embodiment, a memory 301 is provided in each signal processing block 331.

In fig. 31, an output from the memory 301 provided in each signal processing block is input into the first signal processing unit 304, and an output from the first signal processing unit 304 is input into the second signal processing unit 305.

As described above, in the thirteenth embodiment, each signal processing block is provided for a corresponding one of the pixel blocks, and signal processing may be performed simultaneously at the circuit 307 (e.g., TDC circuit); therefore, high-speed signal processing can be performed.

The first signal processing unit 304 and the second signal processing unit 305 may be provided inside each signal processing block. The first signal processing unit 304 may be disposed inside each signal processing block, and as shown in fig. 31, the second signal processing unit 305 may be disposed outside the area where the signal processing blocks are disposed.

(fourteenth embodiment)

A fourteenth embodiment is illustrated in fig. 33 to 39. The same members as those in the first embodiment are assigned the same reference numerals, and explanation thereof will be omitted. The fourteenth embodiment is different from the first embodiment in that a fourth substrate 4100 is stacked in addition to the first substrate 1100, the second substrate 2100, and the third substrate 3100.

In the structure shown in fig. 33, an electrode which is electrically connected to the outside and via which a driving voltage is supplied to a circuit of the fourth substrate 4100 is provided in the wiring structure 4120 of the fourth substrate. Each electrode through which a driving voltage is supplied to a circuit of a corresponding substrate of the first to third substrates is provided in a wiring structure of the corresponding substrate of the first to third substrates. Specifically, the electrode 4210 for the first substrate is provided in the wiring structure of the first substrate, the electrode 4220 for the second substrate is provided in the wiring structure of the second substrate, the electrode 4240 for the third substrate is provided in the wiring structure of the third substrate, and the electrode 4270 for the fourth substrate is provided in the wiring structure of the fourth substrate.

Further, each of the electrical connection between the second substrate 2100 and the third substrate 3100 and the electrical connection between the third substrate 3100 and the fourth substrate 4100 is provided by TSV wirings. Specifically, the second substrate is connected to the wiring 3031 of the wiring layer of the third substrate via the bump 5040, and the wiring 3031 is connected to the third substrate via the bump 5050. The first substrate is connected to the wiring 4031 of the wiring layer of the fourth substrate via the bump 5060, and the wiring 4031 is connected to the fourth substrate via the bump 5100.

With this structure, wiring from the electrode via which the driving voltage is supplied from the outside to the circuits provided in the respective substrates can be shortened, and the possibility of delay in circuit operation due to signal propagation delay can be reduced. Further, a driving voltage suitable for the element arranged in the corresponding substrate may be supplied from each electrode.

In the structure shown in fig. 34, although electrodes through which driving voltages are supplied to circuits of the respective substrates are provided in the wiring structure of the respective substrates similarly to fig. 33, there is a difference from fig. 33 in that: each of the connection between the second substrate 2100 and the third substrate 3100 and the connection between the third substrate 3100 and the fourth substrate 4100 is provided by TSV wirings. Specifically, the third substrate is connected to the wiring 4031 of the wiring layer of the fourth substrate via the bump 5150, and the wiring 4031 is connected to the fourth substrate via the bump 5100.

In the structure shown in fig. 35, in each of the first substrate 1100, the third substrate 3100, and the fourth substrate 4100, electrodes of a circuit through which a driving voltage is supplied to the substrates are provided. This structure is the same as the structure shown in fig. 34 in that each of the connection between the second substrate 2100 and the third substrate 3100 and the connection between the third substrate 3100 and the fourth substrate 4100 is provided by TSV wiring. The electrode 4250 is disposed in the first substrate 1100. The electrical connection between the first substrate 1100 and the second substrate 2100 is provided by bonding the bonding portion 1040 of the first substrate and the bonding portion 2040 of the second substrate to each other.

In the structure shown in fig. 36, in each of the first substrate 1100 and the third substrate 3100, electrodes of a circuit through which a driving voltage is supplied to the substrates are provided. The first substrate 1100 and the second substrate 2100 are electrically connected to each other by the bonding portions 1040 and 2040 of the first and second substrates being bonded to each other. The third substrate 3100 and the fourth substrate 4100 are electrically connected to each other via TSV wirings. The electrode 4210 and the electrode 4250 are provided so as to be in contact with the same wiring layer of the wiring structure 1120 of the first substrate. The electrode 4240 and the electrode 4280 are provided so as to be in contact with the same wiring layer of the wiring structure 3120 of the third substrate. Accordingly, the depth of the pad opening formed when the electrode 4210 is formed is substantially the same as the depth for the electrode 4250, or the depth of the pad opening formed when the electrode 4240 is formed is substantially the same as the depth for the electrode 4270. Thus, this structure makes it easier to perform the process of the wiring step.

In the structure shown in fig. 37, electrodes of a circuit through which a driving voltage is supplied to the first substrate 1100 are provided in the first substrate 1100. The first substrate 1100 and the second substrate 2100 are electrically connected to each other by the bonding portions 1040 and 2040 of the first and second substrates being bonded to each other. The second substrate 2100 and the third substrate 3100 are electrically connected to each other via TSV wirings, and the second substrate 2100 and the fourth substrate 4100 are electrically connected to each other via TSV wirings.

That is, the electrode 4210, the electrode 4250, the electrode 4260, and the electrode 4290 are provided so as to be in contact with the same wiring layer of the wiring structure 1120 of the first substrate. Accordingly, the pad openings formed when the respective electrodes are formed have substantially the same depth. Further, this structure makes it unnecessary to provide deep pad openings for wiring from the first substrate 1100 to the fourth substrate 4100, thus making it easier to perform the process of the wiring step.

In the structure shown in fig. 38, TSV wirings are connected to each of the first to fourth substrates. The wiring of the first substrate 1100 is connected to the wiring 5031 of the wiring layer of the fourth substrate via the bump 5250, and the wiring of the second substrate 2100 is connected to the wiring 5032 via the bump 5240. The wiring of the third substrate 3100 is connected to the wiring 5033 via the bump 5230, and the fourth substrate 4100 is connected to the wiring 5034 via the bump 5220. Since this structure allows all the connection terminals for connection to the outside to be provided on the surface side of the photoelectric conversion device, the area for disposing the terminals in the vicinity of the pixel area becomes smaller; therefore, a space-saving area design of the photoelectric conversion device can be expected.

(fifteenth embodiment)

Fig. 39 is a sectional view of a photoelectric conversion apparatus according to a fifteenth embodiment. The same members as those in the first embodiment are assigned the same reference numerals, and explanation thereof will be omitted. The gist of the modification of the structure of the first embodiment to the fifteenth embodiment resides in the structure of the pad electrode 4290.

The wiring structure 1120 includes a first wiring layer M1, a second wiring layer M2, a third wiring layer M3, a fourth wiring layer M4, and a joint 1040 of the first substrate. The wiring structure 2120 includes a first wiring layer M1, a second wiring layer M2, and a joint 2040 of the second substrate. Each wiring layer is a so-called copper wiring. Each wiring layer may have, for example, a mesh structure in plan view. That is, wirings arranged in a certain direction in a plan view and wirings intersecting them constitute a mesh-like wiring layer.

In the wiring structure 1120 and the wiring structure 2120, the first wiring layer includes a conductor pattern including copper as its main component. The conductor pattern of the first wiring layer has a single damascene structure. Contacts are provided for electrical connection between the first wiring layer and the semiconductor layer 1110. The contact is a conductor pattern containing tungsten as its main component. The second and third wiring layers include conductor patterns containing copper as their main components. The conductor patterns of the second and third wiring layers have a dual damascene structure and include a portion serving as a wiring and a portion serving as a via. The structure of the fourth wiring layer is the same as that of the second and third wiring layers.

The pad electrode 4290 is a conductor pattern containing aluminum as its main component. The pad electrode 4290 is not provided in the wiring structure, but is provided in an opening of the semiconductor layer 1110. In the illustrated structure, the pad electrode 4290 has an exposed surface between the second surface P2 and the first surface P1. However, the exposed surface of the pad electrode may be located on the second plane P2.

How the structure of the present embodiment is formed will now be briefly described. A pad opening is formed through the semiconductor layer 1110 in such a manner that a portion of the wiring layer Ml of the wiring structure 1120 is exposed. Then, insulators 40 to 101 are formed in such a manner as to cover the second face P2 of the semiconductor layer 1110 and the pad opening. Openings serving as through holes of the pad electrodes 4290 are formed in the insulators 40 to 101. After the conductive film serving as the pad electrode 4290 is formed, an unnecessary portion of the conductive film is removed, thereby obtaining a desired pattern. Then, after the insulators 40 to 102 are formed, openings for exposing the pad electrodes 4290 are formed. In this way, the structure of the present embodiment can be formed.

The through-electrodes 40 to 104 may be provided from the second surface P2 side. The through electrodes 40 to 104 may be made of a conductor whose main component is copper, and may have a barrier metal between the semiconductor layer 1110 and the conductor.

Conductors 40 to 103 are provided on the through electrodes 40 to 104. The conductors 40 to 103 may be provided as a common conductor shared with another through electrode, and may have a function of reducing conductor diffusion of the through electrodes 40 to 104.

The materials and structures of the respective wiring layers of the wiring structures 1120, 2120 are not limited to the disclosed examples; for example, a conductor layer between the wiring layer and the semiconductor layer may be further included. The contact may have a two-stage stacked contact structure.

(sixteenth embodiment)

Fig. 40 is a sectional view of a photoelectric conversion apparatus according to a sixteenth embodiment. The same members as those in the first embodiment are assigned the same reference numerals, and explanation thereof will be omitted. The gist of the modification of the structure of the first embodiment to the fifteenth embodiment resides in the structure of the pad electrode 4290.

The wiring structure 1120 includes a first wiring layer M1, a second wiring layer M2, a third wiring layer M3, a fourth wiring layer M4, and a joint 1040 of the first substrate. The wiring structure 2120 includes a first wiring layer M1, a second wiring layer M2, and a joint 2040 of the second substrate. Each wiring layer is a so-called copper wiring.

In the wiring structure 1120 and the wiring structure 2120, the first wiring layer includes a conductor pattern including copper as its main component. The conductor pattern of the first wiring layer has a single damascene structure. Contacts are provided for electrical connection between the first wiring layer and the semiconductor layer 1120. The contact is a conductor pattern containing tungsten as its main component. The second and third wiring layers include conductor patterns containing copper as their main components. The conductor patterns of the second and third wiring layers have a dual damascene structure and include a portion serving as a wiring and a portion serving as a via. The structure of the fourth wiring layer is the same as that of the second and third wiring layers.

The pad electrode 4300 is a conductor pattern containing aluminum as its main component. The pad electrode 4300 is disposed across the second wiring layer to the third wiring layer of the wiring structure 1120. For example, a portion serving as a via for connection between the first wiring layer and the second wiring layer and a portion serving as a wiring of the third wiring layer are included therein. The pad electrode 4300 is located between, for example, the second plane P1 and the fifth plane P5. The pad electrode 4300 may be disposed between the second face P2 and the fourth face P4, or between the second face P2 and the fifth face P5.

The pad electrode 4300 has a first face and a second face opposite to the first face. A portion of the first face is exposed through the opening of the semiconductor layer. The exposed portion of the pad electrode 4300 may serve as a portion for connection to an external terminal, so-called a pad portion. The pad electrode 4300 is connected at its second face to a plurality of conductors whose main component is copper.

As another embodiment modified from the present embodiment, the pad electrode 4300 may have an electrical connection portion at a non-exposed portion of the first face side thereof. For example, the pad electrode 4300 may have a through hole made of a conductor containing aluminum as its main component, and may be electrically connected to a conductor located on the first face side and containing copper as its main component through the through hole. The pad electrode 4300 may be connected to the first wiring layer of the wiring structure 1120 at the first face thereof through a conductor containing tungsten as its main component.

The pad electrode 4300 may be formed by, for example, after forming an insulator covering the third wiring layer, removing a portion of the insulator, forming a film containing aluminum as its main component to serve as the pad electrode 4300, and then patterning. After forming the copper wiring, a pad electrode 4300 is formed; in this way, the pad electrode 4300 having a large film thickness can be formed while maintaining good copper wiring flatness.

Although the case where the pad electrode 4300 is included in the wiring structure 1120 has been disclosed in the present embodiment, it may be included in the wiring structure 2120. The position where the pad electrode is provided may be in the wiring structure 1120 or the wiring structure 2120, and is not limited. The materials and structures of the respective wiring layers of the wiring structures 1120, 2120 are not limited to the disclosed examples; for example, a conductor layer between the first wiring layer and the semiconductor layer may be further included. The contact may have a two-stage stacked contact structure.

The pad electrode which has been described in the foregoing embodiments and the present embodiment is connected to the outside of the semiconductor device, and is used to output a signal generated inside the semiconductor device to the outside to receive an input of a voltage supplied from the outside for driving a circuit of the semiconductor device. Since external noise such as static electricity and surge voltage also enters through the pad electrode, a protection circuit for protecting an internal circuit can be provided in the vicinity of the pad electrode. The protection circuit is for example a diode, a gate-grounded MOS, an RC trigger MOS or a combination of these elements. The protection circuit may be provided at a region overlapping the pad electrode in a plan view, or may be provided in each substrate depending on a voltage for driving elements provided in each stacked substrate or depending on a pad layout.

(seventeenth embodiment)

Fig. 41 is a sectional view of a photoelectric conversion apparatus according to a seventeenth embodiment. The same members as those in the first embodiment are assigned the same reference numerals, and explanation thereof will be omitted. The gist of a modification of the structure of the first embodiment to the seventeenth embodiment is to arrange the positions of the pixels.

In the above-described embodiment, the TSV wirings are disposed in a range where they overlap with the peripheral region 13 located outside the pixel region 12 in plan view. However, for example, the TSV wirings may be disposed in a range where they overlap with the pixel region 12 in a plan view. In the photoelectric conversion apparatus according to the present embodiment, since at least three semiconductor substrates are stacked, even at a region overlapping with the TSV wiring in a plan view, the influence of the voltage input/output through the TSV wiring on the pixel is suppressed, thereby achieving effective area utilization.

The pixels disposed at the region overlapping the TSV wirings in the plan view are not limited to effective pixels configured to output signals based on photoelectric conversion. For example, the pixel may be an OB pixel (optical black pixel) whose incident surface side is covered with a light shielding film so as not to allow light to enter, a virtual pixel which is not connected to an output line and thus does not output a signal, or the like. The dummy pixels are, for example, pixels disposed between the effective pixels and the dummy pixels to prevent oblique light from entering the OB pixels. Even if such pixels are affected by the voltage input/output through the TSV wiring, the effect on image quality is small; therefore, in order to effectively use the area, the dummy pixels may be arranged at the region overlapping the TSV wirings in the plan view.

The element disposed at the region overlapping the TSV wiring in the plan view is not limited to the photoelectric conversion element such as the pixel described above. For example, a semiconductor element such as a transistor may be provided. Forming elements such as transistors in the semiconductor region 1110 makes it possible to enhance substrate flatness. The element provided at the region overlapping the TSV wiring in the plan view may be, for example, a protection element having the function of the aforementioned protection circuit.

(eighteenth embodiment)

Fig. 42 is a block diagram illustrating the configuration of the photoelectric conversion system 11200 according to the present embodiment. The photoelectric conversion system 11200 according to the present embodiment includes a photoelectric conversion apparatus 11204. The photoelectric conversion apparatus according to any of the foregoing embodiments may be applied to the photoelectric conversion apparatus 11204. The photoelectric conversion system 11200 can be used as an image capturing system, for example. Specific examples of the image capturing system include a digital still camera, a digital video camera, and a monitoring camera. In the example shown in fig. 42, the photoelectric conversion system 11200 is a digital still camera.

The photoelectric conversion system 11200 shown in fig. 42 includes a photoelectric conversion device 11204 and a lens 11202 for forming an optical image of an object on the photoelectric conversion device 11204. The photoelectric conversion system 11200 includes an aperture 11203 for making the amount of light passing through the lens 11202 variable and a barrier 11201 for protecting the lens 11202. The lens 11202 and the diaphragm 11203 constitute an optical system for converging light onto the photoelectric conversion device 11204.

The photoelectric conversion system 11200 includes a signal processing unit 11205 that processes an output signal output from the photoelectric conversion apparatus 11204. The signal processing unit 11205 performs operations for processing an input signal by various corrections and compression as needed and outputting the processed signal. The photoelectric conversion system 11200 further includes a buffer memory unit 11206 for temporarily storing image data and an external interface unit (external I/F unit) 11209 for communicating with an external computer or the like. The photoelectric conversion system 11200 further includes a storage medium 11211 such as a semiconductor memory for writing or reading captured image data, and a storage medium control interface unit (storage medium control I/F unit) 11210 for writing or reading the storage medium 11211. The storage medium 11211 may be built in the photoelectric conversion system 11200 or may be configured to be attachable and detachable. Communication from the storage medium control I/F unit 11210 to the storage medium 11211 and communication from the external I/F unit 11209 may be performed wirelessly.

The photoelectric conversion system 11200 further includes an overall control and calculation unit 11208 that performs various calculations and controls the entire digital still camera, and a timing generation unit 11207 that outputs various timing signals to the photoelectric conversion device 11204 and the signal processing unit 11205. The timing signal or the like may be input from the outside. It is sufficient that the photoelectric conversion system includes at least the photoelectric conversion apparatus 11204 and the signal processing unit 11205 that processes the output signal output from the photoelectric conversion apparatus 11204. The overall control and calculation unit 11208 and the timing generation unit 11207 may be configured to perform some or all of the control functions of the photoelectric conversion apparatus 11204.

The photoelectric conversion device 11204 outputs an image signal to the signal processing unit 11205. The signal processing unit 11205 performs predetermined signal processing on the image signal output from the photoelectric conversion device 11204, and outputs image data. In addition, the signal processing unit 11205 generates an image using the image signal. The signal processing unit 11205 can perform ranging calculation on the signal output from the photoelectric conversion device 11204. The signal processing unit 11205 and the timing generating unit 11207 may be installed in the photoelectric conversion device 11204. That is, the signal processing unit 11205 and the timing generating unit 11207 may be provided on a substrate on which pixels are arranged or may be provided on another substrate. Configuring the image capturing system using the photoelectric conversion device according to each of the foregoing embodiments makes it possible to realize an image capturing system capable of obtaining an image with enhanced quality.

(nineteenth embodiment)

Fig. 43 is a block diagram illustrating an example of the configuration of a distance image sensor which is an electronic apparatus using the photoelectric conversion apparatus described in the foregoing embodiment.

As shown in fig. 43, the distance image sensor 12401 includes an optical system 12407, a photoelectric conversion device 12408, an image processing circuit 12404, a monitor 12405, and a memory 12406. The distance image sensor 12401 can obtain a distance image corresponding to a distance to an object by receiving light (modulated light or pulsed light) emitted from the light source device 12409 toward the object and then reflected by the surface of the object.

The optical system 12407 includes a single lens or a plurality of lenses, guides image light (incident light) from an object to the photoelectric conversion device 12408, and forms an image on a light receiving surface (sensor portion) of the photoelectric conversion device 12408.

The photoelectric conversion apparatus according to each of the foregoing embodiments may be applied to the photoelectric conversion apparatus 12408. A distance signal indicating a distance calculated from the received light signal output from the photoelectric conversion device 12408 is supplied to the image processing circuit 12404.

The image processing circuit 12404 performs image processing for constructing a distance image based on the distance signal supplied from the photoelectric conversion device 12408. Then, the distance image (image data) obtained from the image processing is supplied to and displayed on the monitor 12405, or is supplied to and stored (recorded) in the memory 12406.

In the range image sensor 12401 having such a configuration, for example, with the above-described photoelectric conversion device, a more accurate range image can be obtained due to improvement of pixel characteristics.

(twentieth embodiment)

The technique according to the present disclosure (the present technique) can be applied to various products. For example, techniques according to the present disclosure may be applied to endoscopic surgical systems.

Fig. 44 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

Fig. 44 illustrates a state in which an operator (surgeon) 13131 performs an operation on a patient 13132 lying on a hospital bed 13133 using an endoscopic surgical system 13003. As shown therein, the endoscopic surgical system 13003 includes an endoscope 13100, a surgical tool 13110, and a cart 13134 on which various devices for endoscopic surgery are mounted.

The endoscope 13100 includes: a lens barrel 13101 having a portion of a predetermined length from a head end configured to be inserted into a body cavity of a patient 13132; and a camera head 13102 connected to a base end of the lens barrel 13101. In the illustrated example, the endoscope 13100 is configured as a so-called hard endoscope including a lens barrel 13101 having a hard structure. However, the endoscope 13100 may be configured as a so-called soft endoscope including a soft lens barrel.

The head end of the lens barrel 13101 is provided with an opening into which an objective lens is fitted. The light source device 13203 is connected to the endoscope 13100. Light generated by the light source device 13203 is guided to the head end of the lens barrel 13101 through a light guide extending inside the lens barrel 13101. The light is emitted toward an observation target in a body cavity of the patient 13132 through an objective lens. The endoscope 13100 may be a direct view endoscope, a squint endoscope, or a side view endoscope.

An optical system and a photoelectric conversion device are provided inside the camera head 13102. Reflected light (observation light) from the observation target is condensed onto the photoelectric conversion device by the optical system. The observation light is photoelectrically converted by the photoelectric conversion device, and an electric signal corresponding to the observation light, that is, an image signal corresponding to an observation image is generated. As the photoelectric conversion device, the photoelectric conversion device described in each of the foregoing embodiments can be used. The image signal is transmitted to a Camera Control Unit (CCU) 13135 in the form of RAW data.

The CCU 13135 is constituted by a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and the like, and centrally controls the operations of the endoscope 13100 and the display device 13136. Further, the CCU 13135 receives an image signal from the camera head 13102, and performs various image processing, for example, development processing (demosaicing processing), on the image signal for displaying an image based on the image signal.

The display device 13136 performs image display based on the image signal having undergone the image processing of the CCU 13135 under the control of the CCU 13135.

The light source device 13203 is formed of, for example, a light source such as a Light Emitting Diode (LED), and supplies illumination light for capturing an image of a surgical site or the like to the endoscope 13100.

The input device 13137 is an input interface to the endoscopic surgical system 13003. The user can input various information and instructions to the endoscopic surgery system 13003 via the input device 13137.

The treatment tool control device 13138 controls actuation of the energy treatment tool 13112 for tissue cauterization, dissection or vascular occlusion.

The light source device 13203 configured to supply illumination light to the endoscope 13100 for capturing an image of a surgical site may be formed of a white light source formed of, for example, an LED, a laser light source, or a combination thereof. In the case where the white light source is formed by a combination of R, G, B laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high accuracy, and thus the captured image can be white-balance-adjusted by the light source device 13203. In this case, the laser beams from the respective R, G and B laser light sources can be emitted to the observation target in a time-division manner, and the driving of the imaging element of the camera head 13102 is controlled in synchronization with the emission timing; in this way, an image corresponding to R, G, B can be captured in a time-division manner. According to this method, a color image can be obtained without providing a color filter on the imaging element.

The driving of the light source device 13203 may be controlled such that the intensity of the output light changes at predetermined time intervals. The driving of the imaging element of the camera head 13102 is controlled in synchronization with the timing of the light intensity change, so that images are obtained in a time-division manner, and by combining these images, a high dynamic range image can be generated without shading or excessively bright high light.

The light source device 13203 may be configured to be capable of supplying light having a predetermined wavelength range corresponding to special light observation. For example, in special light observation, the wavelength dependence of light absorption in body tissue is used. Specifically, light in a narrower frequency band than illumination light for general observation (i.e., white light) is emitted, and a high-contrast image of a predetermined tissue such as blood vessels on a mucosal surface is captured. Alternatively, in special light observation, fluorescent observation in which an image is obtained by using fluorescent light generated in response to emission of excitation light may be performed. In the fluorescence observation, excitation light may be applied to a body tissue and fluorescence from the body tissue is observed, or an agent such as indocyanine green (ICG) is locally injected into the body tissue and excitation light corresponding to the fluorescence wavelength of the agent is applied to the body tissue to obtain a fluorescence image or the like. The light source device 13203 may be configured to be able to supply narrowband light and/or excitation light suitable for such special light viewing.

(twenty-first embodiment)

The photoelectric conversion system and the moving body according to the present embodiment will now be described with reference to fig. 45A and 45B and fig. 46A and 46B. Fig. 45A and 45B are schematic diagrams illustrating an example of the configuration of the photoelectric conversion system and the moving body according to the present embodiment. In the present embodiment, an in-vehicle camera is disclosed as an example of the photoelectric conversion system.

Fig. 45A and 45B illustrate an example of a vehicle system and a photoelectric conversion system mounted in the vehicle system and configured to perform image capturing. The photoelectric conversion system 14301 includes a photoelectric conversion device 14302, an image preprocessing unit 14315, an integrated circuit 14303, and an optical system 14314. The optical system 14314 forms an optical image of the object on the photoelectric conversion device 14302. The photoelectric conversion device 14302 converts an optical image of an object formed by the optical system 14314 into an electric signal. The photoelectric conversion device 14302 is a photoelectric conversion device according to any of the foregoing embodiments. The image preprocessing unit 14315 performs predetermined signal processing on the signal output from the photoelectric conversion device 14302. The functions of the image preprocessing unit 14315 may be integrated into the photoelectric conversion device 14302. The photoelectric conversion system 14301 includes at least two groups of optical systems 14314, photoelectric conversion devices 14302, and an image preprocessing unit 14315, and an output from the image preprocessing unit 14315 in each group is input to the integrated circuit 14303.

The integrated circuit 14303 is an integrated circuit for an image capturing system, and includes an image processing unit 14304, an optical ranging unit 14306, a ranging calculation unit 14307, an object recognition unit 14308, and an abnormality detection unit 14309, the image processing unit 14304 including a memory 14305. The image processing unit 14304 performs image processing such as development processing and defect correction on the output signal from the image preprocessing unit 14315. The memory 14305 temporarily stores captured images and stores the locations of defective imaging pixels. The optical ranging unit 14306 focuses on the object and performs ranging. The ranging calculation unit 14307 calculates ranging information from a plurality of pieces of image data obtained by a plurality of photoelectric conversion devices 14302. The object recognition unit 14308 recognizes objects such as automobiles, roads, signs, and people. When an abnormality in the photoelectric conversion device 14302 is detected, the abnormality detection unit 14309 issues an abnormality alarm to the main control unit 14313.

The integrated circuit 14303 may be implemented as specially designed hardware, software modules, or a combination thereof. The integrated circuit may be formed, for example, by an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or a combination thereof.

The main control unit 14313 centrally controls the operation of the photoelectric conversion system 14301, the vehicle sensor 14310, the control unit 14320, and the like. A method (for example, in compliance with a Control Area Network (CAN) standard) in which the main control unit 14313 is not included and the photoelectric conversion system 14301, the vehicle sensor 14310, and the control unit 14320 individually have communication interfaces and the control signals are individually transmitted and received via a communication network may also be employed.

The integrated circuit 14303 has a function of transmitting a control signal and a set value to the photoelectric conversion device 14302 in response to a control signal received from the main control unit 14313 or when instructed by a control unit included therein.

The photoelectric conversion system 14301 is connected to the vehicle sensor 14310, and can detect the running state of the host vehicle including the vehicle speed, the yaw rate, the steering angle, and the like, the environmental state outside the host vehicle, and the states of other vehicles and obstacles. The vehicle sensor 14310 is a distance information acquirer that acquires information on a distance to a target object. The photoelectric conversion system 14301 is connected to the driving assistance control unit 1311, and the driving assistance control unit 1311 provides various driving assistance including an automatic steering function, an automatic traveling function, an anti-collision function, and the like. Specifically, regarding the collision determination function, a collision with another vehicle or obstacle is predicted, and occurrence of the collision is determined based on detection results of the photoelectric conversion system 14301 and the vehicle sensor 14310. In this way, avoidance control is performed in the event of a predicted collision, and the safety device is activated at the time of the collision.

The photoelectric conversion system 14301 is also connected to an alarm device 14312, the alarm device 14312 being configured to issue an alarm to the driver based on the determination result of the collision determination unit. For example, in the case where the determination result of the collision determination unit considers that the possibility of collision is high, the main control unit 14313 performs vehicle control to avoid collision or reduce damage by, for example, applying a brake, releasing a throttle, or suppressing the output of the engine. The alert device 14312 alerts the user, for example, by sounding an alert, displaying an alert message on a display screen, such as a car navigation system or dashboard, or vibrating a seat belt or steering wheel.

In the present embodiment, the photoelectric conversion system 14301 captures a surrounding image of the vehicle, such as a front image or a rear image. Fig. 45B illustrates an example of the arrangement of the photoelectric conversion system 14301 when the photoelectric conversion system 14301 captures an image in front of the vehicle.

Two photoelectric conversion devices 14302 are disposed in the front of the vehicle 14300. Specifically, the two photoelectric conversion devices 14302 are disposed axisymmetrically with respect to a center line extending in the front-rear direction of the vehicle 14300 or a center line of an outer shape (e.g., vehicle width) thereof. This configuration is preferable for acquiring information on a distance between the vehicle 14300 and an object as a capturing target and determining a possibility of collision. The photoelectric conversion device 14302 should preferably be disposed so as not to obstruct the driver's field of view when the driver looks outside the vehicle 14300 from the driver's seat. The alerting device 14312 should preferably be deployed such that it is easily located within the field of view of the driver.

Although the control for preventing a collision with another vehicle has been described in the present embodiment, other applications are also possible, such as automatic driving control for following another vehicle or control for automatic driving so as not to deviate from a lane. Further, the photoelectric conversion system 14301 is applicable not only to a vehicle such as an automobile but also to other moving bodies (moving devices) such as a ship, an airplane, or an industrial robot. In addition, the photoelectric conversion system 14301 is applicable not only to a moving body but also to various apparatuses that perform object recognition, such as an Intelligent Transportation System (ITS).

The photoelectric conversion apparatus according to the present invention may be configured to be able to obtain various types of information such as distance information.

(twenty-second embodiment)

Fig. 46A and 46B illustrate glasses 16600 (smart glasses) according to an application example. The eyeglasses 16600 include a photoelectric conversion device 16602. The photoelectric conversion device 16602 is a photoelectric conversion device according to each of the foregoing embodiments. A display device including a light emitting device such as an OLED or an LED may be provided on the back surface of the lens 16601. A single photoelectric conversion device 16602 or a plurality of photoelectric conversion devices 16602 may be provided. A combination of a plurality of photoelectric conversion devices may be used. The position where the photoelectric conversion device 16602 is provided is not limited to the position shown in fig. 43 (a).

The spectacles 16600 further comprise a control device 16603. The control device 16603 functions as a power source for supplying electric power to the photoelectric conversion device 16602 and the display device described above. The control device 16603 controls operations of the photoelectric conversion device 16602 and the display device. An optical system for condensing light onto the photoelectric conversion device 16602 is formed in the lens 16601.

Fig. 46B illustrates glasses 16610 (smart glasses) according to an application example. The spectacles 16610 include a control device 16612. The control device 16612 includes a photoelectric conversion device and a display device, which correspond to the photoelectric conversion device 16602. A photoelectric conversion device in the control device 16612 and an optical system for projecting light emitted from the display device are formed in the lens 16611. The image is projected onto a lens 16611. The control device 16612 functions as a power source that supplies electric power to the photoelectric conversion device and the display device and controls operations of the photoelectric conversion device and the display device. The control device 16612 may comprise a line of sight detection unit that detects the line of sight of the wearer. For detecting the line of sight, infrared rays may be used. The infrared emission unit emits infrared rays to eyeballs of a user who looks at the display image. The captured image of the eyeball may be obtained by detecting reflected light from the eyeball irradiated with the emitted infrared ray by an image capturing unit including a light receiving element. A unit for reducing light from the infrared emission unit toward the display unit in a plan view is provided to suppress degradation of image quality.

From a captured image of an eyeball obtained by performing capturing using infrared rays, a line of sight of a user toward a display image is detected. Any known method may be used to detect a line of sight using a captured image of an eyeball. For example, a line-of-sight detection method based on purkinje images using reflection of illumination light at the cornea may be used.

More specifically, a line-of-sight detection process based on the pupillary cornea reflection method is performed. By using the pupil cornea reflection method, a line of sight vector indicating the azimuth (rotation angle) of the eyeball is calculated based on a pupil image included in a captured image of the eyeball and based on the purkinje image, thereby detecting the line of sight of the user.

The display device according to the present embodiment may include a photoelectric conversion device that includes a light receiving element, and may control a display image of the display device based on line-of-sight information of a user from the photoelectric conversion device.

Specifically, on the display device, a first field of view region and a second field of view region other than the first field of view region at which the user gazes are determined based on the line of sight information. The first field of view region and the second field of view region may be determined by a control device of the display device or may receive a region determined by an external control device. In the display region of the display device, the display resolution of the first field of view region may be controlled to be higher than the display resolution of the second field of view region. That is, the resolution of the second field of view region may be lower than the resolution of the first field of view region.

The display region may include a first display region and a second display region different from the first display region, and a region having a higher priority may be determined from among the first display region and the second display region based on the line-of-sight information. The first field of view region and the second field of view region may be determined by a control device of the display device or may receive a region determined by an external control device. The resolution of the region having the higher priority may be controlled to be higher than that of the region other than the region having the higher priority. That is, the region having a relatively low priority may have a lower resolution.

The AI may be used to determine a first field of view region and a region with a higher priority. The AI may be a model configured to estimate a line of sight angle and a distance from an eyeball image to a fixation target when using the eyeball image and an actual observation direction of an eyeball in the image as teacher data. The program of AI may be installed in the display device, the photoelectric conversion device, or the external device. In the case of being mounted in an external device, it is transmitted to the display device via communication.

In the case where display control is performed based on visual detection, this embodiment can be preferably applied to smart glasses further including a photoelectric conversion device that captures an image of an external scene. The smart glasses are capable of displaying the captured external information in real time.

< other examples >

Although the embodiments have been described, the present invention should not be construed as being limited to these embodiments, and various changes and modifications may be made. These embodiments may be applied to each other. That is, a portion of one embodiment may be replaced with a portion of another embodiment. A portion of one embodiment and a portion of another embodiment may be added together. A portion of a particular embodiment may be omitted.

The invention should not be construed as being limited to the foregoing embodiments. Various changes and modifications may be made without departing from the spirit and scope of the invention. In order to open the scope of the invention to the public, the appended claims are attached.

This patent application claims the benefit of priority based on Japanese patent application Nos. 2021-008439 filed on 22 days of 2021 and Japanese patent application No.2022-000316 filed on 5 days of 2022. The contents of the description and illustrations thereof are incorporated herein by reference in their entirety.

Claims

1. A photoelectric conversion device, characterized by comprising:

a first substrate including a first semiconductor layer including a plurality of photoelectric conversion units and a first wiring structure;

a second substrate including a second semiconductor layer including a plurality of pixel circuits provided in a manner corresponding to the plurality of photoelectric conversion units and a second wiring structure;

A third substrate including a third semiconductor layer and a third wiring structure, the third semiconductor layer including a signal processing circuit configured to process signals output from the plurality of pixel circuits; and

a first through wiring passing through the third semiconductor layer, wherein

Each of the plurality of photoelectric conversion units includes an avalanche diode;

the first substrate and the second substrate are stacked such that the first wiring structure and the second wiring structure are disposed between the first semiconductor layer and the second semiconductor layer, and

the second substrate and the third substrate are stacked such that the third wiring structure is disposed between the second semiconductor layer and the third semiconductor layer.

2. The photoelectric conversion device according to claim 1, further comprising:

a second through wiring passing through the second semiconductor layer, wherein

The second through wiring is a wiring for electrical connection between a wiring of the second wiring structure and a wiring of the third wiring structure.

3. The photoelectric conversion device according to claim 2, wherein

The second through wiring is a wiring penetrating the third semiconductor layer.

4. The photoelectric conversion device according to claim 2 or 3, wherein

The second through wiring is formed from a surface of the third semiconductor layer opposite to a surface on which the third wiring structure is provided toward the third wiring structure.

5. The photoelectric conversion device according to any one of claims 2 to 4, wherein

The second through wiring is a wiring for inputting signals output from the plurality of pixel circuits of the second substrate into the signal processing circuit of the third substrate.

6. The photoelectric conversion device according to any one of claims 2 to 5, wherein

The second through wiring is a wiring for supplying a driving voltage for the plurality of pixel circuits of the second substrate and a driving voltage for the signal processing circuit of the third substrate.

7. The photoelectric conversion device according to any one of claims 1 to 6, further comprising:

a third through wiring passing through the third semiconductor layer and the second semiconductor layer, wherein

The third through wiring is a wiring for supplying a voltage to the wiring of the second wiring structure.

8. The photoelectric conversion device according to claim 7, further comprising:

A fourth through wiring passing through the second semiconductor layer, wherein

The fourth through wiring is a wiring for supplying a voltage to the wiring of the third wiring structure, and

the third through wiring and the fourth through wiring are not electrically connected to each other.

9. The photoelectric conversion device according to any one of claims 1 to 8, having:

a pixel region provided with a plurality of pixels including the plurality of photoelectric conversion units, wherein

The first wiring structure includes a plurality of first bonding portions,

the second wiring structure includes a plurality of second bonding portions,

the plurality of first bonding portions are bonded to the plurality of second bonding portions, respectively, thereby forming a plurality of metal bonding portions, and

each of the plurality of metal junctions arranged in the pixel region is provided for a corresponding one of the plurality of photoelectric conversion units in a plan view.

10. The photoelectric conversion device according to any one of claims 1 to 8, having:

a pixel region provided with a plurality of pixels including the plurality of photoelectric conversion units; and

a peripheral region disposed between the pixel region and a chip end of the photoelectric conversion device, wherein

The first wiring structure includes a plurality of first bonding portions,

the second wiring structure includes a plurality of second bonding portions,

the plurality of metal joints are disposed in the peripheral region.

11. The photoelectric conversion device according to any one of claims 1 to 8, having:

The second wiring structure includes a plurality of third bonding portions, the third wiring structure includes a plurality of fourth bonding portions, and

the plurality of third joint portions are joined to the plurality of fourth joint portions, respectively, thereby forming a plurality of metal joint portions.

12. The photoelectric conversion device according to claim 11, wherein

At least one of the plurality of third bonding portions is electrically connected to a wiring of the first wiring structure via a third through-wiring penetrating the second semiconductor layer, and

an insulator is provided between the third through wiring and the second semiconductor layer.

13. The photoelectric conversion device according to any one of claims 1 to 8, wherein

The first connection number, which is the number of wirings for connecting the wirings of the first wiring structure and the wirings of the second wiring structure through the bonding surfaces of the first substrate and the second substrate, is larger than the second connection number, which is the number of wirings for connecting the wirings of the second wiring structure and the wirings of the third wiring structure through the bonding surfaces of the second substrate and the third substrate.

14. The photoelectric conversion device according to claim 13, comprising:

a pixel region provided with the plurality of photoelectric conversion units, wherein

In the pixel region, the first connection number is greater than the second connection number.

15. The photoelectric conversion device according to any one of claims 1 to 14, further comprising:

time measurement circuit, wherein

The time measurement circuit is arranged in the second substrate, and

the time measurement circuit is shared by the plurality of photoelectric conversion units.

16. The photoelectric conversion device according to claim 15, wherein

In a plan view, the time measurement circuit shared by the plurality of photoelectric conversion units overlaps at least a part of the plurality of photoelectric conversion units sharing the time measurement circuit.

17. A photoelectric conversion system comprising:

the photoelectric conversion device according to any one of claims 1 to 16; and

and a signal processing unit configured to process a signal output from the photoelectric conversion device.

18. A mobile body, comprising:

the photoelectric conversion device according to any one of claims 1 to 16;

a distance information acquirer configured to acquire information on a distance to a target object from distance measurement information based on a signal output from the photoelectric conversion device; and

and a controller configured to control the moving body based on the distance information.