CN1167998C - Signal converter - Google Patents
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- CN1167998C CN1167998C CNB001353640A CN00135364A CN1167998C CN 1167998 C CN1167998 C CN 1167998C CN B001353640 A CNB001353640 A CN B001353640A CN 00135364 A CN00135364 A CN 00135364A CN 1167998 C CN1167998 C CN 1167998C
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- signal
- logical circuit
- horizontal vertical
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- vertical mixed
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Abstract
The present invention relates to a signal converter which outputs a processing signal according to the horizontal and vertical mixing signal of a display and an integrated signal and comprises a first logic circuit, a second logic circuit, a third logic circuit and a fourth logic circuit, wherein the first logic circuit is used for receiving the horizontal and vertical mixing signal and the integrated signal, and when the horizontal and vertical mixing signal is changed into a low level from a high level and the integrated signal is in a low level, a high-level signal is outputted; the second logic circuit is used for receiving the horizontal and vertical mixing signal and the output of the first logic circuit, and when the horizontal and vertical mixing signal is changed into the high level from the low level and the output of the first logic circuit is in a high level, a low-level signal is outputted; the third logic circuit is used for receiving the horizontal and vertical mixing signal and the output of the first logic circuit, and when the horizontal and vertical mixing signal and the output of the first logic circuit are in low accurate positions, a low-accurate position signal is outputted; the fourth logic circuit receives the outputs of the third logic circuit and the second logic circuit, and when the outputs of the third logic circuit and the second logic circuit are in high accurate positions, a high-accurate signal is outputted.
Description
Technical field
The present invention relates to a kind of chromacoder, particularly a kind of chromacoder of the horizontal vertical mixed signal in order to processing display.
Background technology
Generally employed color monitor (color monitor) on personal computer mostly is to design according to the RGB system.That is behind display reception R (representative red video signal), G (representative video green signal) and the B (representative blue video signal), produce colored image.In addition, display also must receive synchronizing signal, goes up the mode of display image to determine each frame (frame).The mode of display display image, be to combine with continuous frame (being single picture), and each frame is to utilize the sweep trace of specific quantity further to constitute, the mode of scanning then is that the sweep trace by the top begins, sweep trace to the bottom finishes, and finishes single frame.Therefore, vertical synchronizing signal in the synchronizing signal (be called for short V) and horizontal-drive signal (being called for short H) promptly are used for synchronously the sequential of vertical scanning (promptly scanning every sweep trace in regular turn) and the horizontal scanning at every turn scanning of picture element on the sweep trace (promptly for).In sum, display must receive R, G, B, V, five signals of H at least, and the beginning can be carried out correct video picture function.
Generally speaking, produce described vision signal R, G, B and synchronizing signal V, H and deliver to the mode that display shows, controlled by the video card in the computer system (video card or display card).With reference to Fig. 1, Fig. 1 represents the structural representation of display part in the general computer system.As shown in the figure, video card 10 generally is to be inserted on the expansion slot of computer system, and by peripheral data bus, and for example AGP or PCI obtain data to be shown by the other parts of computer system.Video card just can produce described R, G, B, V, H signal according to these data, is sent to display 20.
Generally speaking, vision signal R, G, B remain separately and send, but transmitting on the synchronizing signal, the difference of different modes are just arranged.A kind of mode is referred to as to separate synchronizing signal (separate sync) mode, and its vertical synchronizing signal V is to send into respectively in the terminals different in the display with horizontal-drive signal H.Another kind of mode is referred to as composite synchronizing signal (composite sync) mode, and wherein vertical synchronizing signal V and horizontal-drive signal H produce composite synchronizing signal in the mode that superposes, and send in specific input end of display again, are generally the V terminal.At this moment, the A/D conversion circuit of display interior will pass through PLL (PLL) generation clock according to composite synchronizing signal.
Display must be separated into the composite synchronizing signal that receives independently horizontal-drive signal and vertical synchronizing signal, and the beginning can be carried out video picture.When separating composite synchronizing signal, be composite synchronizing signal to be given integration and look polarity whether anti-phasely determining to do by a particular electrical circuit, and produce a mask signal, and the PLL (PLL) of closing A/D conversion circuit inside with described mask signal, to stop the output of clock.
Yet when handling composite synchronizing signal, the many mistakes that can not expect take place in regular meeting.This mistake can cause the mistake of the shown picture of display usually.
With reference to Fig. 2, Fig. 2 shows the composite synchronizing signal (HS) of conventional art and the clock figure of mask signal (COAST-A).If want correct separation composite synchronizing signal, the scope of mask signal (COAST-A) must be covered in the composite synchronizing signal (HS) fully by the part between the B to K.Thus, crooked result takes place in the image of avoiding showing but the clock of ability termination phase phase-locked loop is exported.But because the problem that the characteristic of circuit unit and signal can't real time reactions, mask signal (COAST-A) can't cover in the composite synchronizing signal (HS) fully by the part between the B to K usually.And then influenced picture displayed.
When mask signal (COAST-A) does not cover in the composite synchronizing signal (HS) by the part between the B to C, the A/D conversion circuit of display will continue to provide the former clock signal that should be provided in A to B time span in B to C time span.So will influence the shown picture of display.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of chromacoder, composite synchronizing signal can be done to handle in advance, with the abnormal signal of active correction, then inputs to display again.And according to handling the mask signal that composite synchronizing signal later produces correspondence.Described mask signal will be able to satisfy fully cover the characteristic of handling composite synchronizing signal later, solve the present problem of conventional art.
For obtaining described purpose, the present invention proposes a kind of chromacoder, be applicable to according to a horizontal vertical mixed signal of scanner and an integrated signal of described horizontal vertical mixed signal and export a processing signals, comprise: one first logical circuit, in order to receive described horizontal vertical mixed signal and described integrated signal, only change low level into by high level and described integrated signal when being low level, export a high level signal in described horizontal vertical mixed signal; One second logical circuit, couple described first logical circuit, in order to receive the output of described horizontal vertical mixed signal and described first logical circuit, only change high level into by low level and described first logical circuit when being output as high level, export a low level signal in described horizontal vertical mixed signal; One the 3rd logical circuit in order to receiving the output of described horizontal vertical mixed signal and described first logical circuit, and only when described horizontal vertical mixed signal and described first logical circuit are output as low level, is exported a low level signal; And one the 4th logical circuit, in order to receiving the output of described the 3rd logical circuit and described second logical circuit, and only when described the 3rd logical circuit and described second logical circuit are output as high level, export a high level signal, i.e. this processing signals.
In addition, the present invention proposes a kind of signal conversion method, be applicable to the horizontal vertical mixed signal of processing display, this horizontal vertical mixed signal may further comprise the steps: the positive signal with first width is provided by being formed according to a horizontal-drive signal and a vertical synchronizing signal; Detect the undesired pulse of described horizontal vertical mixed signal, and described pulse is extended to the falling edge of described positive signal according to described positive signal, and obtain one first processing signals; Provide one with the negative polarity signal of this vertical synchronizing signal; And will described first processing signals and the negative polarity signal input to one with, and produce one second processing signals.
For described purpose of the present invention, feature and advantage can be become apparent, will lift a preferred embodiment below, and in conjunction with the accompanying drawings, elaborate.
Description of drawings
Fig. 1 represents the structural representation of display part in the general computer system.
Fig. 2 shows the composite synchronizing signal (HS) of conventional art and the clock figure of mask signal (COAST-A).
Fig. 3 is the circuit block diagram that shows according to the embodiment of the invention.
Fig. 4 shows structural drawing in a circuit according to the invention, in order to the electric connection of describing each chip and external resistance and the state of electric capacity.
Fig. 5 is the sequential chart that shows according to the embodiment of the invention.
Fig. 6 is the signal processing flow that shows according to the embodiment of the invention.
Embodiment
With reference to Fig. 3, Fig. 3 is the circuit block diagram that shows according to the embodiment of the invention.
The invention provides a kind of chromacoder, be arranged between video card and the display, be applicable to according to a horizontal vertical mixed signal (HS) of display and an integrated signal of described horizontal vertical mixed signal and export a processing signals (HS-RC), the display of present embodiment is to be example with LCD (LCD) at this, and is to comprise following structure according to the circuit of the embodiment of the invention.
Integrator 30 is in order to being described integrated signal (HS-RC) with described horizontal vertical mixed signal (HS) integration.
First logical circuit 31, in order to receive described horizontal vertical mixed signal (HS) and described integrated signal (HS-RC), only in described horizontal vertical mixed signal (HS) change low level into by high level and described integrated signal (HS-RC) when the low level, export a high level signal.
Second logical circuit 32, couple described first logical circuit 31, in order to receive the output (2Q) of described horizontal vertical mixed signal (HS) and described first logical circuit 31, only change high level into by low level and described first logical circuit 31 when being output as high level, export a low level signal in described horizontal vertical mixed signal (HS).
The 3rd logical circuit 33, in order to receive the output (2Q) of described horizontal vertical mixed signal (HS) and described first logical circuit 31, and only when described horizontal vertical mixed signal (HS) and described first logical circuit 31 are output as low level, export a low level signal.
The 4th logical circuit 34 in order to receiving the output of described the 3rd logical circuit 33 and described second logical circuit 32, and only when described the 3rd logical circuit 33 and described second logical circuit 32 are output as high level, is exported a high level signal.Wherein the 3rd logical circuit 33 be one or the door, and the 4th logical circuit 34 be one with the door.
According to the chromacoder of the embodiment of the invention, wherein said first logical circuit 31 also comprises following structure:
The first logic device 311, in order to receive described horizontal vertical mixed signal (HS) and described integrated signal (HS-RC), only in described horizontal vertical mixed signal (HS) change low level into by high level and described integrated signal (HS-RC) when the low level, export a low level signal.
The second logic device 312, in order to receive the output (CLR) of described horizontal vertical mixed signal (HS) and the described first logic device 311, only change high level into by low level and the described first logic device 311 when being output as high level in described horizontal vertical mixed signal (HS), export one first signal specific, wherein said first signal specific is the square wave with one first width.
The 3rd logic device 313, in order to receive the output (1Q) of described horizontal vertical mixed signal (HS) and the described second logic device 312, only change low level into by high level and described second logical circuit 312 when being output as high level in described horizontal vertical mixed signal (HS), export one second signal specific to described second logical circuit 32, wherein said second signal specific is the square wave with one second width.
And first width and second width are to adjust by the RC circuit of correspondence.
With reference to Fig. 4, Fig. 4 shows structural drawing in a circuit according to the invention, in order to the electric connection of describing each chip and external resistance and the state of electric capacity, and the chip number that is adopted in the present embodiment.
It below is the operating process of introducing according to the embodiment of the invention.With reference to Fig. 4, Fig. 5 is the sequential chart that shows according to the embodiment of the invention.
At first, use an integrator 30, and produce the HS-RC signal horizontal vertical mixed signal (HS) integration.Then, HS and HS-RC are inputed to the first logic device 311, and produce the CLR signal according to following truth table.
| Input | Output | ||
| CLK | D | Q | Q |
| ↑ | H | H | L |
| ↑ | L | L | H |
B point HS ↑, HS-RC is H, so output Q is H.
D point HS ↑, HS-RC is L, so output Q is L.
G point HS ↑, HS-RC is L, so output Q is L.
H point HS ↑, HS-RC is H, so output Q is H.
Then, HS and CLR are imported the second logic device 312 (Monostable), can obtain the output of 1Q according to following truth table.
| Input | Output | |||
| CLEAR | A | B | Q | Q |
| H | L | ↑ | ||
| H | ↑ | H | ||
| L | X | X | L | H |
A point HS ↑, CLR is H, thus output Q be.
D point HS ↑, CLR is L, thus output Q be.
H point HS ↑, CLR is H, thus output Q be.
Wherein, the pulse width (pulse width of 1Q) of output Q must produce 2Q greater than the pulse width between the BC so that enough trigger modes (trigger state) to be provided.In addition, the pulse width of 1Q can be adjusted by R801 and C813.
Then, HS and 1Q are imported the 3rd logic device 313 (Monostable), can obtain the output of 2Q according to described truth table.
C point HS ↑, 1Q is H, thus output Q be.
Wherein, the pulse width (pulse width of 2Q) of output Q must produce 3Q greater than the pulse width between the CD so that enough trigger modes (trigger state) to be provided.In addition, the pulse width of 2Q can be adjusted by R800 and C810.
Then, HS and 2Q are inputed to second logical circuit 32, and produce the 3Q signal according to following truth table.
| Input | Output | ||
| CLK | D | Q | Q |
| ↑ | H | H | L |
| ↑ | L | L | H |
B point HS ↑, 2Q is H, so output Q is H.
D point HS ↑, 2Q is L, so output Q is L.
E point HS ↑, 2Q is H, so output Q is H.
In addition, it is or door therefore to export the waveform of HS-OR that HS and 2Q are inputed to the 3rd logical circuit 33, the three logical circuits 33.
At last, 3Q and HS-OR being inputed to the 4th logical circuit 34, the four logical circuits 34 is and door therefore to export the waveform of HSOOT.HSOOT is the signal of normal process.
With reference to Fig. 6, Fig. 6 is the signal processing flow of demonstration according to the embodiment of the invention.In embodiments of the present invention, propose a kind of signal conversion method, be applicable to the horizontal vertical mixed signal of processing display, may further comprise the steps, and the signal that reaches described in each step is with reference to Fig. 5.
Step S1: provide to have first width one positive signal (2Q) of (the C point is between the J point) is to adjust (as C810 and the R800 of Fig. 4) by a RC circuit at this first width.
Step S2: detect the undesired pulse (the BC section of HS among Fig. 5) of described horizontal vertical mixed signal, and described pulse extended to the falling edge (J point) of described positive signal according to described positive signal 2Q, and obtain one first processing signals (HS-OR).
Step S3: provide one with the synchronous negative polarity signal (3Q) of vertical synchronizing signal,
Step S4: with described first processing signals (HS-OR) and negative polarity signal (3Q) input to one with door 34 (with reference to Fig. 3), and produce one second processing signals (HSOOT).
When second processing signals (HSOOT) of last result is inputed to the analog/digital converter of display, will make display be able to normal demonstration, its principle is as follows:
As shown in Figure 2, the BC pulse in the HS signal is abnormal pulse.When described signal inputs to the analog/digital converter of display, because therefore COAST-A just activation after the BC pulse can cause analog/digital converter that the sequential mistake takes place when the computing pixel, and then cause the crooked of display frame.By circuit according to the embodiment of the invention, but active detecting goes out abnormal horizontal vertical mixed signal, and it recovery is normal, make the soak time of COAST-B contained treated horizontal vertical mixed signal HSOOT between EK scope and obtain normal display result.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention should be with being as the criterion that the claim scope is defined.
Claims (9)
1. a chromacoder is applicable to according to a horizontal vertical mixed signal of display and an integrated signal of described horizontal vertical mixed signal and exports a processing signals, comprising:
One first logical circuit in order to receive described horizontal vertical mixed signal and described integrated signal, only changes low level into by high level and described integrated signal when being low level in described horizontal vertical mixed signal, exports a high level signal;
One second logical circuit, couple described first logical circuit, in order to receive the output of described horizontal vertical mixed signal and described first logical circuit, only change high level into by low level and described first logical circuit when being output as high level, export a low level signal in described horizontal vertical mixed signal;
One the 3rd logical circuit in order to receiving the output of described horizontal vertical mixed signal and described first logical circuit, and only when described horizontal vertical mixed signal and described first logical circuit are output as low level, is exported a low level signal; And
One the 4th logical circuit in order to receiving the output of described the 3rd logical circuit and described second logical circuit, and only when described the 3rd logical circuit and described second logical circuit are output as high level, is exported a high level signal, i.e. this processing signals.
2. chromacoder as claimed in claim 1 also comprises an integrator, in order to being described integrated signal with described horizontal vertical mixed signal integration.
3. chromacoder as claimed in claim 2, wherein said first logical circuit also comprises:
One first logic device in order to receive described horizontal vertical mixed signal and described integrated signal, only changes low level into by high level and described integration letter when being low level in described horizontal vertical mixed signal, exports a low level signal;
One second logic device, in order to receive the output of described horizontal vertical mixed signal and the described first logic device, only change high level into by low level and the described first logic device when being output as high level in described horizontal vertical mixed signal, output one is first signal specific of square wave with one first width; And
One the 3rd logic device, in order to receive the output of described horizontal vertical mixed signal and the described second logic device, only change low level into by high level and the described second logic device when being output as high level in described horizontal vertical mixed signal, output one for second signal specific of square wave with one second width to described second logical circuit.
4. chromacoder as claimed in claim 5, wherein said first width and second width are the RC circuit adjustment by correspondence.
5. chromacoder as claimed in claim 6, wherein said the 3rd logical circuit be one or the door.
6. chromacoder as claimed in claim 7, wherein said the 4th logical circuit be one with the door.
7. chromacoder as claimed in claim 2, wherein said integrator are a RC integrator.
8. signal conversion method is applicable to the horizontal vertical mixed signal of processing display, and this horizontal vertical mixed signal be may further comprise the steps by forming according to a horizontal-drive signal and a vertical synchronizing signal:
Positive signal with first width is provided;
Detect the undesired pulse of described horizontal vertical mixed signal, and described pulse is extended to the falling edge of described positive signal according to described positive signal, and obtain one first processing signals;
Provide one with the synchronous negative polarity signal of this vertical synchronizing signal; And
With described first processing signals and negative polarity signal input to one with door, and produce one second processing signals.
9. signal conversion method as claimed in claim 8, wherein said first width are by a RC circuit adjustment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001353640A CN1167998C (en) | 2000-12-12 | 2000-12-12 | Signal converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001353640A CN1167998C (en) | 2000-12-12 | 2000-12-12 | Signal converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1357819A CN1357819A (en) | 2002-07-10 |
| CN1167998C true CN1167998C (en) | 2004-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001353640A Expired - Fee Related CN1167998C (en) | 2000-12-12 | 2000-12-12 | Signal converter |
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|---|---|
| CN (1) | CN1167998C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270108A (en) * | 2010-06-07 | 2011-12-07 | 宏碁股份有限公司 | Display system and function awaking method of display device |
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- 2000-12-12 CN CNB001353640A patent/CN1167998C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CN1357819A (en) | 2002-07-10 |
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Granted publication date: 20040922 Termination date: 20100112 |