CN116796669A - Reliability verification method and system for electric power edge computing chip - Google Patents
Reliability verification method and system for electric power edge computing chip Download PDFInfo
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Abstract
The application discloses a reliability verification method and a system for an electric power edge computing chip, which relate to the technical field of chip testing and comprise the steps of obtaining a preset reliability verification strategy; performing reliability verification on pins in the power edge computing chip, and determining output signal variation of the pins before and after verification is performed; aiming at a target pin of which the output signal variation exceeds a preset threshold, determining that the target pin is mapped to a target interface correspondingly; determining configuration parameters, and adjusting configuration information of a target interface according to the configuration parameters; triggering the target interface to execute a preset function to carry out function loading processing, and checking the reliability of the power edge computing chip based on the fed-back loading processing result. The application comprehensively considers a plurality of check indexes, can provide more comprehensive and accurate reliability evaluation, and is very valuable for applications requiring higher reliability evaluation and comprehensive evaluation.
Description
Technical Field
The application relates to the technical field of chip testing, in particular to a reliability verification method and system for an electric power edge computing chip.
Background
Currently, prior to mass production of chips, reliability tests are often performed on the chips to ensure the usability and stability of the chips. However, existing reliability testing methods often ignore comprehensive testing of chip functionality and interface stability. This results in the possibility that the function and stability of the chip may not be sufficiently verified before the chip is interconnected and put into practical use. Although in reliability testing, pin reliability, interface communication defects, communication capability and the like are checked, the prior art ignores interface stability detection, which results in an insufficient detection result.
The prior art generally only focuses on pin reliability and communication capability in reliability test, but lacks comprehensive detection of chip interface stability. This may lead to interface stability problems encountered in practical applications, such as data transmission interruption, timing inconsistencies, etc. The prior art functional tests generally only verify the basic correctness of the chip function, but lack comprehensive functional tests under different operating modes and load conditions. This may lead to functional problems found in practical applications, such as non-response of the functional module, inaccurate output results, etc. The prior art lacks comprehensive test on the chip and other hardware or systems, and cannot comprehensively verify the compatibility and stability of the chip. This may cause problems in interconnection with other devices in practical applications, such as unstable communication, data loss, etc.
Disclosure of Invention
This section is intended to outline some aspects of embodiments of the application and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section as well as in the description of the application and in the title of the application, which may not be used to limit the scope of the application.
The application is provided in view of the reliability verification of the existing power edge computing chip and the problems existing in the system.
Therefore, the problem to be solved by the present application is how to provide a reliability check and system for a power edge computing chip. The application checks the reliability priori of the chip pins, and correspondingly updates the target interfaces mapped to the detected defective pins in a targeted manner, if the target interfaces still cannot normally carry out function loading after configuration updating, the interface operation can be further considered to be unstable, and the current chip cannot normally work, so that whether the chip can work normally or not can be accurately judged before the chip is used for interconnection and intercommunication, and the loss caused by the fact that the chip cannot work normally after interconnection and intercommunication is avoided.
In order to solve the technical problems, the application provides the following technical scheme:
in a first aspect, an embodiment of the present application provides a reliability verification method for a power edge computing chip, which includes obtaining a preset reliability verification policy based on a power edge computing chip identifier; based on a reliability verification strategy, performing reliability verification on pins in the power edge computing chip, and determining output signal variation of the pins before and after verification is performed; aiming at a target pin of which the output signal variation exceeds a preset threshold, determining that the target pin is mapped to a target interface correspondingly; determining configuration parameters according to the variation of the output signals, and adjusting configuration information of the target interface according to the configuration parameters; triggering the target interface to execute a preset function to carry out function loading processing, and checking the reliability of the power edge computing chip based on the fed-back loading processing result.
As a preferable scheme of the reliability verification method of the power edge computing chip, the application comprises the following steps: the reliability verification strategy specifically comprises the steps that corresponding reliability verification strategies are pre-configured and stored for each power edge computing chip to be detected; comparing the pin output signals with other redundant pins, detecting whether the difference exists, verifying whether the output signals of the pins meet the preset time sequence requirement, measuring the voltage and the current of the pins, and ensuring that the voltage and the current are within the allowable range; performing association binding on the configured reliability verification strategy and the corresponding chip identifier, and acquiring a target chip identifier of the current power edge computing chip to be verified when receiving a reliability verification trigger signal; and acquiring a corresponding reliability verification policy based on the target chip identifier when the association binding relation between the configured reliability verification policy and the corresponding chip identifier is known.
As a preferable scheme of the reliability verification method of the power edge computing chip, the application comprises the following steps: the reliability verification specifically comprises the steps of calling a corresponding verification code based on a reliability verification strategy; and executing the check code to trigger the reliability check of the pins in the power edge computing chip.
As a preferable scheme of the reliability verification method of the power edge computing chip, the application comprises the following steps: the output signal variation amount specifically comprises the steps of placing a power edge computing chip in a testing environment with normal power supply and signal connection, fixing pins by using a fixing clamp, correctly connecting a logic analyzer to the pins to be measured, opening the logic analyzer, ensuring connection to a correct input channel, continuously capturing signals according to an automatic triggering mode by using a pulse trigger to determine the output signal variation amount before and after the pins, and performing relevant calculation, wherein the calculation formula is as follows:
RMSE＝√(1/n*∑(S1-S2) 2 )
I(X,Y)＝∑∑p(x,y)*log(p(x,y)/(p(x)*p(y)))
wherein, RMSE is root mean square error, I (X, Y) is the association degree between the output signals before and after the pins; r is the linear correlation degree between the output signals before and after the pins, S1 is the data volume after the pins output signals, and S2 is the data volume before the pins output.
As a preferable scheme of the reliability verification method of the power edge computing chip, the application comprises the following steps: the mapping includes mapping pins to a T0 class interface when RMSE >0.2 and I (X, Y) < 0.5; when RMSE is below 0.2, if I (X, Y) is above 0.5 and r is above 0.7, then mapping pins to be T1 class interfaces; when the RMSE is below 0.2, if I (X, Y) <0.5, at this time, if r is above 0.9, then mapping the pins to the T3 class interface; if 0.7< r <0.9, mapping the pins to a T1 type interface; if r is less than 0.7, mapping the pins to a T0 type interface; when RMSE is below 0.1, if I (X, Y) is above 0.7 and r is above 0.9, mapping pins to the T4 class interface; if I (X, Y) is above 0.5 and r <0.7, mapping the pins to a T2 type interface; when RMSE is below 0.05, if I (X, Y) is above 0.8 and r is above 0.9, then pins are mapped to the T5 class interface.
As a preferable scheme of the reliability verification method of the power edge computing chip, the application comprises the following steps: the configuration information of the target interface specifically comprises the steps of carrying out linear modeling through a system identification method, referring to an adaptive control algorithm to update a parameter adjustment strategy, setting initial configuration parameter values for the adaptive algorithm, using a sensor to collect feedback signals of the system in real time to adjust the configuration parameters, controlling the adjustment speed of the parameters based on the difference between error signals and parameter estimation, and using a learning rate; the communication protocol, the speed and the data format of the interface are defined to determine the configuration parameters to be adjusted, the relation between the configuration parameters and the interface performance is analyzed based on the collected system information and the known configuration parameters, and the optimization target is set according to the specification requirements of the interface.
As a preferable scheme of the reliability verification method of the power edge computing chip, the application comprises the following steps: the checking specifically comprises the steps of obtaining loading result data of a target interface in a preset execution period, and analyzing the loading result data to obtain an execution data set corresponding to a plurality of function loading stages; performing time sequence discretization processing on the loading time data corresponding to the function loading period to obtain discrete time data, and performing recognition of the function loading stage on the discrete time data to obtain a plurality of function loading stages; performing data mapping and data fusion processing on the execution data set according to the multiple function loading stages to obtain execution fusion data; inputting the execution fusion data into a trained chip reliability analysis model to perform reliability analysis, and checking the reliability of the power edge calculation chip based on the reliability analysis result.
In a second aspect, an embodiment of the present application provides a reliability verification system for a power edge computing chip, including: the information processing module is used for calculating a chip identifier according to the power edge and acquiring a preset reliability verification strategy; the pin verification module is used for carrying out reliability verification on the pins in the power edge calculation chip and determining the output signal variation of the pins before and after verification is carried out; the interface configuration adjustment module is used for determining configuration parameters according to the variation of the output signals and adjusting the configuration information of the target interface according to the configuration parameters; and the interface verification module is used for executing a preset function according to the target interface to carry out loading processing and verifying the reliability of the power edge computing chip based on the fed-back loading processing result.
In a third aspect, embodiments of the present application provide a computer apparatus comprising a memory and a processor, the memory storing a computer program, wherein: and the processor executes any step of the reliability verification method of the power edge computing chip.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium having a computer program stored thereon, wherein: the computer program when executed by the processor implements any step of the reliability checking method of the power edge computing chip.
The application has the beneficial effects that a plurality of check indexes such as repeatability test, comparison with actual data, reference standard, sensitivity analysis, uncertainty analysis and the like are comprehensively considered. By comprehensively evaluating a plurality of indexes, a more comprehensive and accurate reliability evaluation can be provided. By evaluating multiple aspects of the calculation results, a more comprehensive, accurate assessment of accuracy may be provided. Not only the consistency of the result is considered, but also the comparison with the actual data is considered, the uncertainty of the input parameters and the statistical analysis of the calculation result are considered, the reliability of the calculation result can be better estimated through the uncertainty analysis, and the quantitative estimation of the uncertainty is provided. The method is suitable for complex reliability check and is very valuable for applications requiring higher reliability evaluation and comprehensive evaluation. Through comprehensive evaluation and accurate reliability evaluation, important basis and support can be provided for decision making. In a decision making environment where high reliability is desired, more accurate, reliable results can be provided to assist in making informed decisions.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
fig. 1 is a flowchart of a reliability verification method of a power edge computing chip.
Fig. 2 is a block diagram of a reliability verification system of a power edge computing chip.
Detailed Description
So that the manner in which the above recited objects, features and advantages of the present application can be understood in detail, a more particular description of the application, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Example 1
Referring to fig. 1 and 2, a first embodiment of the present application provides a reliability verification method for a power edge computing chip, including:
s1: and calculating a chip identifier based on the power edge, and acquiring a preset reliability verification strategy.
Specifically, for each chip to be detected, the chip identifier provided by the chip to be detected can be associated and bound with a preset reliability verification policy in advance so as to facilitate subsequent data call.
It should be noted that whether the chip pins are qualified or not is a key of detection of the molding separation process, in the current embodiment, the formulated reliability verification policy includes a first verification policy corresponding to the communication capability of the verification pins, a second verification policy corresponding to whether the verification pins are oxidized (including power-on inspection, that is, the voltage can be slightly increased by 0.5V-1V, whether the chip heats or not is detected, so that the oxidation condition is perceived), a third verification policy for judging the reliability of the pins by comparing with the general voltage data, and the like, and the specific policy content is not limited at present, and the adopted verification policies can be slightly different for chips of different models. And (3) pre-configuring and storing corresponding reliability verification strategies for each power edge computing chip to be detected.
The reliability verification policy is written into a preset storage node in advance, and it should be noted that the storage node exists in the storage process and can be identified as an object server for storing data. Specifically, in implementation, operations of adding, updating and deleting can be performed for each storage node.
When a plurality of storage nodes are adopted for data storage, the storage nodes can be uniformly stored in a preset storage set. Alternatively, the storage set may comprise one or more primary and secondary storage nodes.
Pre-configuring and storing corresponding reliability verification strategies for each power edge computing chip to be detected; and comparing the pin output signals with other redundant pins, detecting whether the difference exists, verifying whether the output signals of the pins meet the preset time sequence requirement, measuring the voltage and the current of the pins, and ensuring that the voltage and the current are within the allowable range.
And carrying out association binding on the configured reliability verification strategy and the corresponding chip identifier, and acquiring the target chip identifier of the current power edge computing chip to be verified when receiving the reliability verification trigger signal.
And acquiring a corresponding reliability verification policy based on the target chip identifier when the association binding relation between the configured reliability verification policy and the corresponding chip identifier is known.
And the configured reliability verification strategy is associated with the corresponding chip identifier at present to form corresponding associated data. And when receiving the corresponding trigger signal, forming corresponding retrieval conditions based on the target chip identifier, and extracting a reliability verification strategy corresponding to the target chip identifier from the associated data based on the retrieval conditions. Through the pre-configured association binding relation, when the chip identifier is calculated by the power edge, the reliability verification strategy corresponding to the chip identifier can be determined efficiently, the data query efficiency is improved, and the high-efficiency storage and intelligent management of big data are realized.
S2: based on a reliability verification strategy, reliability verification is carried out on pins in the power edge computing chip, and output signal variation of the pins before and after verification is carried out is determined.
Specifically, signals which are correspondingly output before and after the pin is subjected to verification are collected and recorded in advance, so that corresponding output signal variation can be obtained through subsequent calculation.
In the signal acquisition process, determining a threshold value of a signal to be recorded, and recording the signal which is currently acquired when the current acquisition is determined and the amplitude value of the signal to be recorded is larger than the threshold value, otherwise, not recording. The output signal variation of each pin before and after verification is performed is determined through the variation of the signal amplitude or phase. In addition, the basic characteristics related to information change in the signals can be abstracted, and the output signal change quantity of each pin before and after verification is executed can be determined through measurement of the information quantity. After the reliability verification policy is obtained, a verification execution flow is further determined, and a corresponding verification code is called according to the verification execution flow. Based on a preset code generation template, when a reliability verification strategy is known, corresponding verification codes are generated by taking the reliability verification strategy as a code generation condition. And triggering the reliability verification of each pin in the power edge computing chip in the process of executing the verification code.
Based on a preset code generation template or when checking an execution flow, the corresponding check code is called according to the check execution flow, so that the code generation efficiency can be improved, various errors caused by manually writing the code can be avoided, and the writing style specification of the code is unified.
S3: and aiming at the target pins of which the output signal variation exceeds a preset threshold, determining that the target pins are mapped to the target interfaces correspondingly.
Placing the power edge computing chip in a testing environment with normal power supply and signal connection, fixing pins by using a fixing clamp, correctly connecting a logic analyzer to the pins to be measured, opening the logic analyzer and ensuring connection to a correct input channel, continuously capturing signals according to an automatic triggering mode by using a pulse trigger to determine the variation of output signals before and after the pins, and performing related computation, wherein the calculation formula is as follows:
RMSE＝√(1/n*∑(S1-S2) 2 )
I(X,Y)＝∑∑p(x,y)*log(p(x,y)/(p(x)*p(y)))
wherein, RMSE is root mean square error, I (X, Y) is the association degree between the output signals before and after the pins; r is the linear correlation degree between the output signals before and after the pins, S1 is the data volume after the pins output signals, and S2 is the data volume before the pins output.
The mapping rules include mapping pins to a T0 class interface when RMSE >0.2 and I (X, Y) < 0.5.
When RMSE is below 0.2, if I (X, Y) is above 0.5 and r is above 0.7, then pins are mapped to be a T1 class interface.
When the RMSE is below 0.2, if I (X, Y) <0.5, at this time, if r is above 0.9, then mapping the pins to the T3 class interface; if 0.7< r <0.9, mapping the pins to a T1 type interface; if r <0.7, the pins are mapped to a T0 class interface.
When RMSE is below 0.1, if I (X, Y) is above 0.7 and r is above 0.9, mapping pins to the T4 class interface; if I (X, Y) is above 0.5 and r <0.7, then the pins are mapped to a T2 class interface.
When RMSE is below 0.05, if I (X, Y) is above 0.8 and r is above 0.9, then pins are mapped to the T5 class interface.
RMSE is an index for measuring an error between a predicted value and an actual value, and represents a root mean square error, a smaller threshold value is selected to ensure that an error between a value after output and a value before output is small, I (X, Y) is an index for indicating a degree of correlation between a value after output and a value before output, a larger value is selected as a threshold value to ensure that a higher degree of correlation between a value after output and a value before output is provided, r is a degree of linear correlation between a value after output and a value before output is provided, and a larger threshold value is selected to ensure that a higher degree of linear correlation between a value after output and a value before output is provided.
S4: and determining configuration parameters according to the variation of the output signals, and adjusting the configuration information of the target interface according to the configuration parameters.
Specifically, after the configuration parameter a to be adjusted is determined according to the output signal variation, an original configuration file of the target interface is obtained, wherein original configuration information of the interface is recorded in the original configuration file. And then, carrying out reorganization and updating on the original configuration information recorded in the original configuration file based on the configuration parameter A, so that the subsequent target interface can execute corresponding functions according to the updated configuration parameter table.
The method comprises the steps of performing linear modeling through a system identification method, updating a parameter adjustment strategy by referring to an adaptive control algorithm, setting initial configuration parameter values for the adaptive algorithm, using a sensor to collect feedback signals of a system in real time to adjust the configuration parameters, based on differences between error signals and parameter estimation, and using a learning rate to control the adjustment speed of the parameters.
The communication protocol, the speed and the data format of the interface are defined to determine the configuration parameters to be adjusted, the relation between the configuration parameters and the interface performance is analyzed based on the collected system information and the known configuration parameters, and the optimization target is set according to the specification requirements of the interface.
S5: triggering the target interface to execute a preset function to carry out function loading processing, and checking the reliability of the power edge computing chip based on the fed-back loading processing result.
Specifically, loading result data of the target interface in a preset execution period is obtained. And analyzing the loading result data to obtain an execution data set corresponding to a plurality of function loading stages. Performing time sequence discretization processing on the loading time data corresponding to the function loading period to obtain discrete time data, and performing recognition of the function loading stage on the discrete time data to obtain a plurality of function loading stages. And performing data mapping and data fusion processing on the execution data set according to a plurality of function loading stages to obtain execution fusion data. Inputting the fusion data into a trained chip reliability analysis model for reliability analysis, and checking the reliability of the power edge calculation chip based on the obtained result. The correlation calculation formula is:
K＝W1*1/(1+RMSE)+W2*I(X,Y)+W3*r
k is a reliability index; w1, W2 and W3 are weight coefficients, wherein W1 is 0.5; w2 is 0.3; w3 is 0.2.
When the reliability index reaches a set threshold, judging the reliability as preliminary reliability, and simultaneously judging the root mean square error, the correlation degree between the output signals before and after the pins and the linear correlation degree between the output signals before and after the pins in sequence, and checking the reliability as extremely reliable when the reliability index meets the set conditions; if the set condition factors are not met, judging whether a certain change range is met, if so, checking to be reliable, and if not, checking to be generally reliable.
When the reliability index does not reach the set threshold, judging the reliability as preliminary unreliability, simultaneously judging the root mean square error in sequence, and checking the reliability as extremely unreliability when the correlation degree between the output signals before and after the pins and the linear correlation degree between the output signals before and after the pins are not in accordance with the set conditions; when the factors meeting the set conditions exist, judging whether a certain change range is met, if so, checking is unreliable, and if not, checking is very unreliable.
Further, the present embodiment also provides a reliability verification system of a power edge computing chip, including: the information processing module is used for calculating a chip identifier based on the power edge and acquiring a preset reliability verification strategy; the power edge detection system is also used for calculating chips aiming at each power edge to be detected, and pre-configuring and storing corresponding reliability verification strategies; performing association binding on the configured reliability verification strategy and the corresponding chip identifier, and acquiring a target chip identifier of the current power edge computing chip to be verified when receiving a reliability verification trigger signal; and acquiring a corresponding reliability verification policy based on the target chip identifier when the association binding relation between the configured reliability verification policy and the corresponding chip identifier is known.
The pin verification module is used for carrying out reliability verification on each pin in the power edge calculation chip based on a reliability verification strategy, and determining the output signal variation of each pin before and after verification is carried out; the method is also used for calling corresponding check codes based on the reliability check strategy; and executing a check code, and triggering the reliability check of each pin in the power edge computing chip in the execution process.
The information processing module is also used for determining a target interface to which the target pin is mapped correspondingly aiming at the target pin of which the output signal variation exceeds the preset threshold value.
The interface configuration adjustment module is used for determining configuration parameters according to the output signal variation and adjusting the configuration information of the target interface according to the configuration parameters.
The interface verification module is used for triggering the target interface to execute a preset function to carry out function loading processing and verifying the reliability of the power edge computing chip based on the fed-back loading processing result. The method is also used for acquiring loading result data of the target interface in a preset execution period; analyzing the loading result data to obtain an execution data set corresponding to a plurality of function loading stages; performing time sequence discretization processing on the loading time data corresponding to the function loading period to obtain discrete time data, and performing recognition of the function loading stage on the discrete time data to obtain a plurality of function loading stages; performing data mapping and data fusion processing on the execution data set according to the multiple function loading stages to obtain execution fusion data; inputting the fusion data into a trained chip reliability analysis model for reliability analysis, and checking the reliability of the power edge calculation chip based on the obtained result.
The embodiment also provides a computer device, which is suitable for the situation of the reliability verification method of the power edge computing chip, and comprises a memory and a processor; the memory is used for storing computer executable instructions, and the processor is used for executing the computer executable instructions to implement the reliability checking method of the power edge computing chip according to the embodiment.
The computer device may be a terminal comprising a processor, a memory, a communication interface, a display screen and input means connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
The present embodiment also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements a method for implementing reliability verification of a power edge computing chip as proposed in the above embodiments.
The storage medium according to the present embodiment belongs to the same inventive concept as the data storage method according to the above embodiment, and technical details not described in detail in the present embodiment can be seen in the above embodiment, and the present embodiment has the same advantageous effects as the above embodiment.
As can be seen from the above, the present application provides a priori verification of the reliability of the chip pins, and then performs a rearrangement update of the configuration information on the target interfaces mapped to the detected defective pins correspondingly, if the target interfaces still cannot perform function loading normally after the configuration update, the operation of the interfaces can be further considered to be unstable, and the chip cannot normally operate, so that before the chip is used for interconnection, whether the chip can normally operate can be accurately judged, and the loss caused by the chip cannot normally operate after the interconnection is avoided.
Example 2
Referring to tables 1 and 2, for the second embodiment of the present application, a reliability verification method of a power edge calculation chip is provided, and in order to verify the beneficial effects of the present application, scientific demonstration is performed through economic benefit calculation and simulation experiments.
Table 1 comparison table of test indexes
| Inspection index | The method | Conventional method |
| Pin reliability | 95％ | 90％ |
| Interface communication defect | 92％ | 85％ |
| Communication capability | 96％ | 88％ |
| Interface stability | 94％ | 82％ |
| Comprehensive function | 93％ | 87％ |
| Overall accuracy rate | 94.8％ | 86.4％ |
As shown in the table, the pin reliability detection accuracy of the method reaches 95%, and compared with the conventional method, the method is only 90%. The accuracy of the interface communication defect detection is 92%, and the accuracy of the traditional method is 85%. The method has excellent performance in the aspect of communication capability detection, and the accuracy reaches 96%, while the traditional method is only 88%. The detection accuracy for the stability of the interface is 94%, and the accuracy of the traditional method is only 82%. The comprehensive function detection accuracy is 93%, and the accuracy of the traditional method is 87%.
By comprehensively considering all indexes, the overall accuracy of the method reaches 94.8 percent, which is obviously higher than 86.4 percent of that of the traditional method. This means that the method can provide more accurate and comprehensive results in terms of reliability test, which helps to ensure the reliability and proper operation of the chip.
Table 2 comparison table of technical characteristics of the present method and conventional method
From the above, the method comprehensively considers a plurality of check indexes, such as repeatability test, comparison with actual data, reference standard or literature, sensitivity analysis, uncertainty analysis and the like. By comprehensively evaluating a plurality of indexes, a more comprehensive and accurate reliability evaluation can be provided. By evaluating multiple aspects of the calculation results, a more comprehensive, accurate assessment of accuracy may be provided. Not only the consistency of the results, but also the comparison with the actual data, the degree of conformity with the reference standard or literature, etc. can be considered. The uncertainty of the input parameters and the statistical analysis of the calculation results are taken into account. By uncertainty analysis, the reliability of the calculation result can be better evaluated, and quantitative evaluation of uncertainty can be provided. The method is suitable for complex reliability check and is very valuable for applications requiring higher reliability evaluation and comprehensive evaluation. Through comprehensive evaluation and accurate reliability evaluation, important basis and support can be provided for decision making. In a decision making environment where high reliability is desired, more accurate, reliable results can be provided to assist in making informed decisions.
It should be noted that the above embodiments are only for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present application may be modified or substituted without departing from the spirit and scope of the technical solution of the present application, which is intended to be covered in the scope of the claims of the present application.
Claims (10)
1. A reliability verification method of a power edge computing chip is characterized by comprising the following steps of: comprising the steps of (a) a step of,
calculating a chip identifier based on the power edge, and acquiring a preset reliability verification strategy;
based on a reliability verification strategy, performing reliability verification on pins in the power edge computing chip, and determining output signal variation of the pins before and after verification is performed;
aiming at a target pin of which the output signal variation exceeds a preset threshold, determining that the target pin is mapped to a target interface correspondingly;
determining configuration parameters according to the variation of the output signals, and adjusting configuration information of the target interface according to the configuration parameters;
triggering the target interface to execute a preset function to carry out function loading processing, and checking the reliability of the power edge computing chip based on the fed-back loading processing result.
2. The reliability verification method of a power edge computing chip of claim 1, wherein: the reliability verification policy specifically includes,
pre-configuring and storing corresponding reliability verification strategies for each power edge computing chip to be detected;
comparing the pin output signals with other redundant pins, detecting whether the difference exists, verifying whether the output signals of the pins meet the preset time sequence requirement, measuring the voltage and the current of the pins, and ensuring that the voltage and the current are within the allowable range;
performing association binding on the configured reliability verification strategy and the corresponding chip identifier, and acquiring a target chip identifier of the current power edge computing chip to be verified when receiving a reliability verification trigger signal;
and acquiring a corresponding reliability verification policy based on the target chip identifier when the association binding relation between the configured reliability verification policy and the corresponding chip identifier is known.
3. The reliability verification method of the power edge computing chip as claimed in claim 2, wherein: the performing of the reliability check specifically includes,
invoking a corresponding check code based on a reliability check policy;
and executing the check code to trigger the reliability check of the pins in the power edge computing chip.
4. The reliability verification method of a power edge computing chip of claim 3, wherein: the output signal variation amount specifically includes,
placing the power edge computing chip in a testing environment with normal power supply and signal connection, fixing pins by using a fixing clamp, correctly connecting a logic analyzer to the pins to be measured, opening the logic analyzer and ensuring connection to a correct input channel, continuously capturing signals according to an automatic triggering mode by using a pulse trigger to determine the variation of output signals before and after the pins, and performing related computation, wherein the calculation formula is as follows:
RMSE＝√(1/n*∑(S1-S2) 2 )
I(X,Y)＝∑∑p(x,y)*log(p(x,y)/(p(x)*p(y)))
wherein, RMSE is root mean square error, I (X, Y) is the association degree between the output signals before and after the pins; r is the linear correlation degree between the output signals before and after the pins, S1 is the data volume after the pins output signals, and S2 is the data volume before the pins output.
5. The method for verifying the reliability of the power edge computing chip as defined in claim 4, wherein: the mapping may comprise a mapping of the plurality of images,
when RMSE >0.2 and I (X, Y) <0.5, then map pins to the T0 class interface;
when RMSE is below 0.2, if I (X, Y) is above 0.5 and r is above 0.7, then mapping pins to be T1 class interfaces;
when the RMSE is below 0.2, if I (X, Y) <0.5, at this time, if r is above 0.9, then mapping the pins to the T3 class interface; if 0.7< r <0.9, mapping the pins to a T1 type interface; if r is less than 0.7, mapping the pins to a T0 type interface;
when RMSE is below 0.1, if I (X, Y) is above 0.7 and r is above 0.9, mapping pins to the T4 class interface; if I (X, Y) is above 0.5 and r <0.7, mapping the pins to a T2 type interface;
when RMSE is below 0.05, if I (X, Y) is above 0.8 and r is above 0.9, then pins are mapped to the T5 class interface.
6. The reliability verification method of the power edge computing chip of claim 5, wherein: the configuration information of the target interface specifically includes,
linear modeling is carried out through a system identification method, a parameter adjustment strategy is updated by referring to an adaptive control algorithm, an initial configuration parameter value is set for the adaptive algorithm, a sensor is used for collecting feedback signals of a system in real time to adjust configuration parameters, the difference between error signals and parameter estimation is based, and the learning rate is used for controlling the adjustment speed of the parameters;
the communication protocol, the speed and the data format of the interface are defined to determine the configuration parameters to be adjusted, the relation between the configuration parameters and the interface performance is analyzed based on the collected system information and the known configuration parameters, and the optimization target is set according to the specification requirements of the interface.
7. The reliability verification method of the power edge computing chip of claim 6, wherein: the checking comprises in particular the steps of,
obtaining loading result data of a target interface in a preset execution period, and analyzing the loading result data to obtain an execution data set corresponding to a plurality of function loading stages;
performing time sequence discretization processing on the loading time data corresponding to the function loading period to obtain discrete time data, and performing recognition of the function loading stage on the discrete time data to obtain a plurality of function loading stages;
performing data mapping and data fusion processing on the execution data set according to the multiple function loading stages to obtain execution fusion data;
inputting the execution fusion data into a trained chip reliability analysis model to perform reliability analysis, and checking the reliability of the power edge calculation chip based on the reliability analysis result.
8. A reliability verification system of a power edge computing chip, based on the reliability verification method of the power edge computing chip according to any one of claims 1 to 7, characterized in that: comprising the steps of (a) a step of,
the information processing module is used for calculating a chip identifier according to the power edge and acquiring a preset reliability verification strategy;
the pin verification module is used for carrying out reliability verification on the pins in the power edge calculation chip and determining the output signal variation of the pins before and after verification is carried out;
the interface configuration adjustment module is used for determining configuration parameters according to the variation of the output signals and adjusting the configuration information of the target interface according to the configuration parameters;
and the interface verification module is used for executing a preset function according to the target interface to carry out loading processing and verifying the reliability of the power edge computing chip based on the fed-back loading processing result.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that: the processor, when executing the computer program, implements the steps of the reliability verification method of the power edge computing chip of any one of claims 1 to 7.
10. A computer-readable storage medium having stored thereon a computer program, characterized by: the computer program when executed by a processor implements the steps of the reliability verification method of a power edge computing chip according to any one of claims 1 to 7.
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