CN116794866B - Display panel, display device and mother board - Google Patents
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- CN116794866B CN116794866B CN202310792775.6A CN202310792775A CN116794866B CN 116794866 B CN116794866 B CN 116794866B CN 202310792775 A CN202310792775 A CN 202310792775A CN 116794866 B CN116794866 B CN 116794866B
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- 238000012360 testing method Methods 0.000 claims abstract description 150
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- 230000002093 peripheral effect Effects 0.000 claims description 12
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- 238000000034 method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 7
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- 238000000059 patterning Methods 0.000 description 6
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- 239000010409 thin film Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 230000002159 abnormal effect Effects 0.000 description 1
- 238000009638 autodisplay Methods 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
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Abstract
The disclosure provides a display panel, a display device and a motherboard, and relates to the technical field of display. The display panel comprises a substrate, and a redundant pixel and a subpixel which are arranged on the substrate, wherein the redundant pixel comprises a test transistor and a capacitor, the test transistor comprises a first pole, a second pole and a control pole, the capacitor comprises a first polar plate and a second polar plate, and the second pole of the test transistor is electrically connected with the first polar plate; the display panel further comprises a first contact electrically connected with the first pole of the test transistor and a second contact electrically connected with the control pole of the test transistor, the first contact, the second contact and the second pole plate being adapted to be electrically connected with a test device for testing characteristics of the test transistor. The characteristics of the transistors within the liquid crystal display panel can be inferred more accurately.
Description
Technical Field
The disclosure relates to the field of display technologies, and in particular, to a display panel, a display device and a motherboard.
Background
Liquid CRYSTAL DISPLAY (LCD) panels are widely used because of their long life, low cost, and vivid color. In the process of manufacturing a liquid crystal display panel, a TEG is generally disposed at the periphery of the liquid crystal display panel, and the TEG has a similar structure to a transistor in the liquid crystal display panel, so that characteristics of the transistor in the liquid crystal display panel can be deduced through characteristics of the TEG.
However, the inference by TEG is also inaccurate for the characteristics of the transistors within the liquid crystal display panel.
Disclosure of Invention
Embodiments of the present disclosure provide a display panel, a display device, and a motherboard, which can more accurately infer characteristics of transistors in a liquid crystal display panel.
In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:
in one aspect, a display panel is provided, including a substrate, and a redundant pixel and a subpixel disposed on the substrate, the redundant pixel including a test transistor and a capacitor, the test transistor including a first pole, a second pole, and a control pole, the capacitor including a first plate and a second plate, the second pole of the test transistor being electrically connected to the first plate; the display panel further comprises a first contact and a second contact, wherein the first contact is electrically connected with a first pole of the test transistor, the second contact is electrically connected with a control pole of the test transistor, and the first contact, the second contact and the second pole plate are electrically connected with test equipment to test the characteristics of the test transistor.
In some embodiments, the substrate includes a display region and a non-display region, the sub-pixels and the redundant pixels being located in the display region.
In some embodiments, the display area includes a plurality of sub-pixel areas, the plurality of sub-pixel areas are arranged in an array, and one sub-pixel or one redundant pixel is disposed in one sub-pixel area.
In some embodiments, the redundant pixels are disposed at the edge of the display area.
In some embodiments, the sub-pixel includes a pixel electrode and a common electrode for forming an electric field for driving deflection of liquid crystal molecules; the plurality of the public electrodes of the sub-pixels are electrically connected, the second polar plate and the public electrode are arranged on the same layer and are electrically connected, and the public electrode is used for being electrically connected with the testing equipment.
In some embodiments, the display panel further includes a data line, a gate line, a first test line extending in a direction of the data line, and a second test line extending in a direction of the gate line, the first test line electrically connecting the first contact and the first pole of the test transistor, the second test line electrically connecting the second contact and the control pole of the test transistor.
In some embodiments, the first contact and the second contact are located in the non-display area.
In some embodiments, the display panel further comprises a first conductive ring partially surrounding and spaced apart from the first contact; and/or the display panel further comprises a second conductive ring, wherein the second conductive ring partially surrounds the second contact and is arranged at intervals with the second contact.
In another aspect, a motherboard is provided, including a plurality of panel regions and a peripheral region located between two adjacent panel regions, the panel regions being configured to form an array substrate after being cut and separated from the peripheral region, the peripheral region including a substrate and a redundant pixel disposed on the substrate, the redundant pixel including a test transistor and a capacitor, the test transistor including a first pole, a second pole, and a control pole, the capacitor including a first pole plate and a second pole plate, the second pole of the test transistor being electrically connected to the first pole plate; the display panel further comprises a first contact and a second contact, wherein the first contact is electrically connected with a first pole of the test transistor, the second contact is electrically connected with a control pole of the test transistor, and the first contact, the second contact and the second pole plate are electrically connected with test equipment to test the characteristics of the test transistor.
In yet another aspect, a display device is provided, including the display panel.
According to the display panel, the display device and the motherboard provided by the embodiment of the disclosure, since the redundant pixels are arranged in the display panel, the distance between the test transistor and the driving transistor is closer, the thickness of the active layer of the test transistor is more consistent with that of the active layer of the driving transistor, namely, the characteristics of the test transistor are closer to those of the driving transistor, and the characteristics of the driving transistor are more accurate through the characteristics of the test transistor.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 schematically shows a front view structure of a display device;
FIG. 2 schematically illustrates a simplified diagram of a display panel;
FIG. 3 shows a simplified diagram of a motherboard of the related art;
FIG. 4 shows a simplified diagram of a TEG;
fig. 5 and 6 are structures of related art for performing a characteristic test on a display panel;
FIG. 7 schematically illustrates a simplified diagram of another display panel;
FIG. 8 schematically illustrates a simplified diagram of another display panel;
FIG. 9 schematically illustrates a simplified diagram of another display panel;
fig. 10 schematically shows a schematic of a motherboard.
Detailed Description
The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
In the embodiments of the present disclosure, the words "first," "second," "third," "fourth," etc. are used to distinguish between the same item or similar items that have substantially the same function and function, but merely for clarity of description of the technical solutions of the embodiments of the present disclosure, and are not to be construed as indicating or implying a relative importance or implying an indication of the number of technical features indicated.
In the embodiments of the present disclosure, the meaning of "a plurality" means two or more, and the meaning of "at least one" means one or more, unless specifically defined otherwise.
In the embodiments of the present disclosure, the azimuth or positional relationship indicated by the terms "upper", "lower", etc., are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present disclosure.
Fig. 1 schematically shows a front view structure of a display device. As shown in fig. 1, some embodiments of the present disclosure provide a display device 100, which display device 100 may be any device that displays both motion (e.g., video) and stationary (e.g., still image) and whether textual or pictorial. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal Data Assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cabin controllers and/or displays, displays of camera views (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like. In fig. 1, the display device 100 is illustrated as a mobile phone.
The display device 100 includes a display panel 110, and the display panel 110 may be a Liquid Crystal Display (LCD) panel CRYSTAL DISPLAY. Illustratively, the display device 100 further includes a control board and a flexible circuit board electrically connecting the control board and the display panel 110 such that the control board provides driving signals to the display panel 110 through the flexible circuit board. In practical applications, the display device 100 may further include a housing, and the display panel 110, the flexible circuit board, and the control board may be disposed in the housing.
Fig. 2 schematically shows a schematic of a display panel. As shown in fig. 2, the display panel 110 includes a substrate 101, and the substrate 101 may have a display area AA and a non-display area NA electrically connected to the display area AA. The non-display area NA may be located at one side, two sides, or three sides of the display area AA, or the non-display area NA may be disposed around the display area AA. The case where the non-display area AA is disposed around the display area AA is shown in fig. 2.
The display area AA is provided with a plurality of sub-pixels P1. Illustratively, the plurality of sub-pixels P1 may be arranged in an array. For example, after the plurality of sub-pixels P1 are arranged in an array, a plurality of sub-pixel P1 rows and a plurality of sub-pixel P1 columns are formed, the plurality of sub-pixels P1 in one sub-pixel row are arranged along the first direction X, and the plurality of sub-pixels P1 in one sub-pixel column are arranged along the second direction Y. Wherein the first direction X and the second direction Y cross each other. The included angle between the first direction X and the second direction Y can be selected and set according to actual needs. Illustratively, the angle between the first direction X and the second direction Y may be 85 °, 88 °, 90 °, 92 °, 95 °, or the like.
The subpixel P1 includes a pixel electrode and a common electrode between which an electric field driving the liquid crystal molecules to deflect may be formed. Illustratively, the pixel electrode and the common electrode are opposite to each other and are arranged at intervals, liquid crystal molecules are arranged between the pixel electrode and the common electrode, and when the pixel electrode and the common electrode are connected with a driving voltage, an electric field perpendicular to the light emitting surface is formed between the pixel electrode and the common electrode. Illustratively, the pixel electrode and the common electrode are provided with liquid crystal molecules on a side facing the light-emitting surface, and an electric field parallel to the light-emitting surface is formed between the pixel electrode and the common electrode when the pixel electrode and the common electrode are connected to a driving voltage.
The common electrode in the plurality of sub-pixels P1 may be electrically connected to form a whole.
The sub-pixel P1 further includes a driving transistor including a first electrode, a second electrode, and a control electrode, the first electrode of the driving transistor being electrically connected to the data signal line, the second electrode of the driving transistor being electrically connected to the pixel electrode, the control electrode of the driving transistor being electrically connected to the scan signal line. When the pixel electrode is in operation, the control electrode of the driving transistor receives a scanning signal from the scanning signal line to enable the driving transistor to be turned on, so that a data signal in the data signal line is written into the pixel electrode through the driving transistor, and the common electrode keeps a constant potential, so that an electric field corresponding to the data signal is formed between the pixel electrode and the common electrode.
The transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors (e.g., oxide thin film transistors), or other switching devices having the same characteristics, and the embodiments of the present disclosure are described by taking the thin film transistors as examples. The control of each transistor is the gate of the transistor, one of the source and drain of the first transistor, and the second transistor is the other of the source and drain of the transistor. Since the source and drain of a transistor may be symmetrical in structure, the source and drain thereof may be indistinguishable in structure, that is, the first and second poles of the transistor in embodiments of the present disclosure may be indistinguishable in structure.
Since the data signal is written into the pixel electrode through the driving transistor, the characteristics of the driving transistor (such as the threshold voltage of the driving transistor) directly affect the display effect of the display panel 110, so that the characteristics of the driving transistor need to be monitored when the display panel 110 is manufactured, and when the characteristics of the driving transistor are abnormal, the process parameters need to be adjusted so that the characteristics of the driving transistor are within the acceptable range.
Fig. 3 shows a schematic diagram of a motherboard in the related art. As shown in fig. 3, in the related art, a plurality of TEGs are typically disposed outside the display Panel, and characteristics of transistors in the display Panel are determined by testing characteristics of the TEGs. The TEG includes a semiconductor channel, and the semiconductor channel and the active layer of the transistor in the display Panel are formed in the same patterning process, so that the thickness of the film layer of the semiconductor channel in the TEG is considered to be the same as the thickness of the active layer in the display Panel, and further, the characteristics of the TEG are considered to be approximately the same as the characteristics of the transistor in the display Panel.
Fig. 4 shows a schematic of a TEG. As shown in fig. 4, the TEG further includes three connection points, including a first connection point G serving as a TEG gate, a second connection point S serving as a TEG source, and a third connection point D serving as a TEG drain. The test equipment EPM comprises three probes, and the three probes are respectively contacted with the three connection points to realize electric connection during test, so that the characteristics of the TEG are obtained.
However, since the TEG is disposed outside the display Panel, the distance between the TEG and the transistor in the display Panel is long, and the film thickness of the semiconductor channel in the TEG is greatly different from the active layer thickness of the transistor in the display Panel, the characteristics of the TEG are greatly different from those of the transistor in the display Panel, so that the characteristics of the transistor in the display Panel are not accurately determined by the characteristics of the TEG.
In addition, when the test characteristics of the TEG are not within the acceptable range, it is necessary to destroy one display Panel, thereby performing the characteristic test on the transistors within the display Panel. Fig. 5 and 6 are structures of the related art when a characteristic test is performed on a display panel. Specifically, the wires in the white circles in fig. 5 and 6 need to be disconnected to complete the characteristic test, and after the wires are disconnected, the display Panel cannot be used normally, so that the display Panel is wasted.
In view of this, with continued reference to fig. 2, the display panel 110 of the embodiment of the disclosure includes a redundant pixel P2 disposed on the substrate 101, the redundant pixel P2 includes a test transistor and a capacitor, the test transistor includes a first pole, a second pole, and a control pole, the capacitor includes a first plate and a second plate, and the second pole of the test transistor is electrically connected to the first plate. The display panel 110 further includes a first contact T1 and a second contact T2, the first contact T1 being electrically connected to the first electrode of the test transistor, and the second contact T2 being electrically connected to the control electrode of the test transistor. During testing, the testing device can be electrically connected with the first contact T1, the second contact T2 and the second polar plate of the capacitor, so that the characteristics of the testing transistor are obtained.
The structure of the redundant pixel P2 may be the same as or similar to the structure of the sub-pixel P1 in the display panel 110.
Illustratively, the active layer of the test transistor and the active layer of the drive transistor are fabricated in the same patterning process; the control electrode of the test transistor and the control electrode of the driving transistor are manufactured in the same patterning process; the first pole and the second pole of the test transistor and the first pole and the second pole of the driving transistor are manufactured in the same patterning process. Thus, the structure of the test transistor is consistent with that of the driving transistor, and the characteristics of the test transistor are closer to those of the driving transistor.
Illustratively, the first plate of the capacitor and the pixel electrode are made in the same patterning process, and the structures of the first plate and the pixel electrode are the same; the second polar plate of the capacitor and the common electrode are manufactured in the same patterning process. Therefore, the structure of the redundant pixel P2 is more consistent with that of the sub-pixel P1, and the characteristic of the driving transistor is judged more accurately by testing the redundant pixel P2.
The size of the redundant pixel P2 may be the same as the size of the sub-pixel P1, and the size of the redundant pixel P2 may be different from the size of the sub-pixel P1. For example, the size of the redundant pixel P2 is smaller than that of the sub-pixel P1, so that the space occupation of the redundant pixel P2 can be reduced.
The first contact T1 and the second contact T2 may be a snap-on disc made of an electrically conductive material. The shape and size of the first contact T1 and the second contact T2 are not limited in the embodiments of the present disclosure, as long as the electrical connection of the test transistor and the test device can be achieved. Illustratively, during testing, the first and second contacts T1, T2 are exposed, thereby facilitating electrical connection of the first and second contacts T1, T2 to the test equipment.
Since the redundant pixel P2 is disposed in the display panel 110, the distance between the test transistor and the driving transistor is shorter, the thickness of the active layer of the test transistor is more consistent with that of the active layer of the driving transistor, that is, the characteristics of the test transistor are closer to those of the driving transistor, and the characteristics of the driving transistor are more accurate through the characteristics of the test transistor.
The second electrode plate may be arranged in the same layer as the common electrode and electrically connected such that the test device may be electrically connected to the second electrode plate by being electrically connected to the common electrode. Because the area of the common electrode is larger, when the testing equipment is electrically connected with the common electrode, the selectable connection areas are more, the electrical connection between the testing equipment and the second electrode plate is more convenient, and the testing equipment is easy to realize the automation of the testing process.
The sub-pixel P1 and the redundant pixel P2 may be both located in the display area AA, so that the distance between the test transistor and the driving transistor is closer, the thickness of the active layer of the test transistor is more consistent with that of the active layer of the driving transistor, that is, the characteristics of the test transistor are closer to those of the driving transistor, and the characteristics of the driving transistor are more accurate through the characteristics of the test transistor.
Because the sub-pixel P1 and the redundant pixel P2 are both positioned in the display area AA, the characteristics of the test transistor are closer to those of the driving transistor, and the display panel 110 is not required to be destroyed to directly test the characteristics of the driving transistor in the test process, so that the waste of the display panel 110 in the preparation process is reduced.
In addition, a film formation ensuring region exists when an active layer is deposited on the substrate 101, and the thickness of the active layer in the film formation ensuring region is uniform. In the process of manufacturing the display panel 110, the display area AA is generally located in the film forming guarantee area, so that the redundant pixel P2 and the sub-pixel P1 are both disposed in the display area AA, so that the thicknesses of the active layers in the test transistor and the driving transistor located in the film forming guarantee area are closer together, that is, the characteristics of the test transistor are closer to those of the driving transistor, and the characteristics of the driving transistor are more accurate through the characteristics of the test transistor.
When the redundant pixel P2 is disposed in the display area AA, the redundant pixel P2 may be disposed at a position where the sub-pixel P1 is originally required to be disposed to replace the sub-pixel P1. For example, the display area AA may include a plurality of sub-pixel areas, where the plurality of sub-pixel areas are arranged in an array, and one sub-pixel P1 or one redundant pixel P2 is disposed in one sub-pixel area.
The plurality of sub-pixel regions are arranged in an array to form a plurality of sub-pixel region rows and a plurality of sub-pixel region columns, wherein the plurality of sub-pixel regions in the sub-pixel region rows are arranged along the first direction X, and the plurality of sub-pixel regions in the sub-pixel region columns are arranged along the second direction Y. The redundant pixel P2 is disposed in any one of the sub-pixel regions.
When the display area AA is not provided with the redundant pixel P2, each sub-pixel area is provided with one sub-pixel P1; when the redundant pixel P2 is disposed in the display area AA, the redundant pixel P2 is disposed in the sub-pixel area. That is, the sub-pixel P1 is replaced with the redundant pixel P2, which is disposed in the sub-pixel region. This minimizes modifications to the Mask required to fabricate the display panel 110.
The redundancy pixel P2 is used to test the characteristics of the test transistor, and does not emit light when the display panel 110 is operated. In order to reduce the influence of the redundant pixel P2 on the display of the display panel 110, the redundant pixel P2 may be disposed at the edge of the display area AA. The edge of the display area AA is connected with a non-display area NA that does not emit light, and the redundant pixel P2 is disposed at the edge of the display area AA, so that the non-display area AA that does not emit light and the redundant pixel P2 are visually connected together, and the redundant pixel P2 is not easily perceived by a user when viewing the display panel 110.
The arrangement of the redundant pixel P2 at the edge of the display area AA means that the redundant pixel P2 is arranged near the edge of the display area AA. Of course, the sub-pixel P1 may also be disposed between the redundant pixel P2 and the edge of the display area AA, which is not limited in the embodiment of the disclosure.
When the display panel 110 is provided with a plurality of redundancy pixels P2, a portion of the plurality of redundancy pixels P2 may be disposed at an edge of the display area AA, and another portion of the plurality of redundancy pixels P2 may be disposed at a middle area of the display area AA. Of course, a plurality of redundant pixels P2 may be disposed at the edge of the display area AA.
Illustratively, the display area AA has a quadrilateral shape, and the redundant pixels P2 are disposed at corner regions of the quadrilateral shape.
Fig. 7 schematically shows a schematic view of another display panel. Illustratively, as shown in fig. 7, the display area AA has a quadrilateral shape, a partial redundant pixel P2 is disposed in a middle area of one side of the quadrilateral shape, and a partial redundant pixel P2 is disposed in a corner area of the quadrilateral shape.
In addition, dummy pixels are usually disposed at the edge of the display area AA, and are electrically connected to the scan driving circuit, and the Dummy pixels do not emit light when the display panel 110 is in operation. The redundant pixel P2 in the embodiment of the present disclosure may be a design change of the Dummy pixel. For example, a structure originally used as a Dummy pixel is disconnected from an external circuit such as a scan driving circuit, a data driving chip, or the like, and a first contact T1 and a second contact T2 electrically connected to the Dummy pixel structure are provided.
The display panel 110 further includes a data line electrically connected to the first electrode of the driving transistor and a gate line electrically connected to the control electrode of the driving transistor. Illustratively, the data lines extend in the second direction Y, the data lines are electrically connected to the first poles of the driving transistors in one sub-pixel column at the same time, the gate lines extend in the first direction X, and the gate lines are electrically connected to the control poles of the driving transistors in one sub-pixel row at the same time.
With continued reference to fig. 2, the display panel 110 further includes a first test line L1 and a second test line L2, the first test line L1 extends along the direction of the data line, the second test line L2 extends along the direction of the gate line, the first test line L1 is electrically connected to the first contact T1 and the first electrode of the test transistor, and the second test line L2 is electrically connected to the second contact T2 and the control electrode of the test transistor.
The embodiment of the disclosure does not limit the lengths of the first test line L1 and the second test line L2, and the shorter the lengths of the first test line L1 and the second test line L2, the smaller the resistance and the weaker the interference signal in the test process.
Fig. 8 schematically shows a schematic view of another display panel. As shown in fig. 8, the first test line L1 and the second test line L2 may be located in the display area AA. With continued reference to fig. 2, the first and second test lines L1 and L2 may also extend to the non-display area NA. The positions of the first and second test lines L1 and L2 may be determined according to the positions of the first and second contacts T1 and T2 and the redundant pixel P2.
The first test line L1 and the second test line L2 are both located in the display area AA, the redundant pixel P2 is disposed in a corner area of the display area AA, one ends of the first test line L1 and the second test line L2 extend to the corner area to be electrically connected with the redundant pixel P2, and the other ends of the first test line L1 and the second test line L2 are electrically connected with the first contact T1 or the second contact T2.
Illustratively, the first contact T1 and the second contact T2 are located outside the display panel 110, and the partial areas of the first test line L1 and the second test line L2 are located outside the display panel 110.
To facilitate electrical connection of the first and second contacts T1, T2 to the test device, the first and second contacts T1, T2 are typically provided larger. At this time, the first contact T1 and the second contact T2 may be located in the non-display area NA, thereby reducing the influence of the first contact T1 and the second contact T2 on the display effect.
Fig. 9 schematically shows a schematic view of another display panel. As shown in fig. 9, the display panel 110 may be provided with two first test lines L1 and two second test lines L2. Illustratively, two first test lines L1 are disposed at two opposite edges of the display area AA, and two second test lines L2 are disposed at two other opposite edges of the display area AA. The redundant pixels P2 are disposed at the intersections of the first and second test lines L1 and L2, so that the number of the redundant pixels P2 can be increased to test the characteristics of the test transistors from a plurality of positions.
In the process of manufacturing the display panel 110, since the first contact T1 and the second contact T2 are in a Floating state (Floating), charges cannot be released, and electrostatic generation is easily generated between the first contact T1 and/or the second contact T2 and surrounding conductive structures in the process of performing dry etching, so that the structures of the first contact T1 and the second contact T2 are damaged. In order to prevent the first contact T1 and the second contact T2 from being electrostatically amplified with the surrounding conductive structures, the display panel 110 may further include a first conductive ring partially surrounding the first contact T1 and spaced apart from the first contact T1. Similarly, the display panel 110 may further include a second conductive ring partially surrounding the second contact T2 and spaced apart from the second contact T2.
Illustratively, the first conductive ring and/or the second conductive ring are annular, and the annular ring is provided with an opening to allow the first test line L1 to protrude from the first conductive ring or the second test line L2 to protrude from the second conductive ring.
Fig. 10 schematically shows a schematic of a motherboard. As shown in fig. 10, the embodiment of the present disclosure also provides a motherboard including a plurality of panel areas a and a peripheral area B located between two adjacent panel areas a. The panel area a is configured to form an array substrate after being cut and separated from the peripheral area B, and the array substrate and the color film substrate are arranged in a box-to-box manner to form the liquid crystal display panel 110. The peripheral area B includes a substrate 101 and a redundant pixel P2 disposed on the substrate 101, the redundant pixel P2 includes a test transistor and a capacitor, the test transistor includes a first pole, a second pole and a control pole, the capacitor includes a first pole plate and a second pole plate, and the second pole of the test transistor is electrically connected to the first pole plate. The display panel 110 further includes a first contact T1 and a second contact T2, the first contact T1 being electrically connected to a first pole of the test transistor, the second contact T2 being electrically connected to a control pole of the test transistor, the first contact T1, the second contact T2 and the second pole plate being for electrically connecting to a test device for testing characteristics of the test transistor.
The motherboard provided by the embodiment of the disclosure is provided with the redundant pixels P2 in the peripheral area B, and the characteristics of the test transistor can be obtained by testing the redundant pixels P2, so that the characteristics of the driving transistor can be inferred. Since the redundant pixel P2 includes the test transistor and the capacitor, and the sub-pixel P1 includes the driving transistor, the pixel electrode and the common electrode, the structure of the redundant pixel P2 is similar to that of the sub-pixel P1, and the characteristic of the driving transistor is determined more accurately by the characteristic of the test transistor.
In addition, the redundant pixel P2 is disposed in the peripheral area B, so that the structure of the display panel 110 does not need to be changed, the space of the display panel 110 is not occupied, and the redundant pixel P2 can be cut off when the mother board is cut.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. The display panel is characterized by comprising a substrate, and a redundant pixel and a subpixel which are arranged on the substrate, wherein the redundant pixel comprises a test transistor and a capacitor, the test transistor comprises a first pole, a second pole and a control pole, the capacitor comprises a first polar plate and a second polar plate, and the second pole of the test transistor is electrically connected with the first polar plate;
The display panel further includes a first contact electrically connected with the first pole of the test transistor and a second contact electrically connected with the control pole, the first contact, the second contact and the second pole plate being for electrically connecting with a test device for testing characteristics of the test transistor.
2. The display panel of claim 1, wherein the substrate comprises a display region and a non-display region, the sub-pixels and the redundant pixels being located in the display region.
3. The display panel according to claim 2, wherein the display area includes a plurality of sub-pixel areas, the plurality of sub-pixel areas are arranged in an array, and one of the sub-pixel areas is provided with one of the sub-pixels or one of the redundant pixels.
4. The display panel of claim 2, wherein the redundant pixels are disposed at the display area edge.
5. The display panel according to any one of claims 1 to 4, wherein the sub-pixel includes a pixel electrode and a common electrode for forming an electric field for driving deflection of liquid crystal molecules; the plurality of the public electrodes of the sub-pixels are electrically connected, the second polar plate and the public electrode are arranged on the same layer and are electrically connected, and the public electrode is used for being electrically connected with the testing equipment.
6. The display panel of any one of claims 1 to 4, further comprising a data line, a gate line, a first test line extending in a direction of the data line, and a second test line extending in a direction of the gate line, the first test line electrically connecting the first contact and a first pole of the test transistor, the second test line electrically connecting the second contact and a control pole of the test transistor.
7. The display panel of any one of claims 1 to 4, wherein the first contact and the second contact are located in a non-display area.
8. The display panel of any one of claims 2 to 4, further comprising a first conductive ring partially surrounding and spaced apart from the first contact; and/or the display panel further comprises a second conductive ring, wherein the second conductive ring partially surrounds the second contact and is arranged at intervals with the second contact.
9. A motherboard, comprising a plurality of panel areas and a peripheral area between two adjacent panel areas, wherein the panel areas are configured to form an array substrate after being cut and separated from the peripheral area, the peripheral area comprises a substrate and a redundant pixel arranged on the substrate, the redundant pixel comprises a test transistor and a capacitor, the test transistor comprises a first pole, a second pole and a control pole, the capacitor comprises a first pole plate and a second pole plate, and the second pole of the test transistor is electrically connected with the first pole plate;
the peripheral region further includes a first contact electrically connected to a first pole of the test transistor and a second contact electrically connected to the control pole, the first contact, the second contact, and the second pole plate being configured to electrically connect to a test device to test a characteristic of the test transistor.
10. A display device comprising the display panel according to any one of claims 1 to 8, or the motherboard according to claim 9.
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