CN116782641A - Method for preparing semiconductor structure and semiconductor structure - Google Patents

Method for preparing semiconductor structure and semiconductor structure Download PDF

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Publication number
CN116782641A
CN116782641A CN202310815307.6A CN202310815307A CN116782641A CN 116782641 A CN116782641 A CN 116782641A CN 202310815307 A CN202310815307 A CN 202310815307A CN 116782641 A CN116782641 A CN 116782641A
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layer
contact hole
nitride layer
source
doped region
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曾以志
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The disclosure provides a method for preparing a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing a substrate, wherein a grid structure is arranged on the substrate, and the substrate comprises a source-drain doping region; forming a dielectric stack layer covering the source-drain doped region on the substrate, wherein the dielectric stack layer comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially stacked, and at least the oxide layer covers the side wall of the gate structure; etching the dielectric stack to form an initial contact hole, exposing at least the oxide layer to form at least a portion of a sidewall of the initial contact hole; forming a third nitride layer covering the initial contact hole and the top surface of the second nitride layer in a conformal manner; implanting a doping element into the third nitride layer to form a doped nitride layer; etching back the doped nitride layer to form a contact hole exposing the source-drain doped region, wherein the reserved doped nitride layer at least covers the side wall of the oxide layer; and forming a contact plug electrically connected with the source-drain doped region in the contact hole. The method can avoid the short circuit between the contact plug and the grid electrode.

Description

Method for preparing semiconductor structure and semiconductor structure
Technical Field
The disclosure relates to the technical field of semiconductor manufacturing, and in particular relates to a manufacturing method of a semiconductor structure and the semiconductor structure.
Background
As semiconductor technology is maturing, the integration density of memories is increasing, for example, in DRAM (dynamic random access memory ), the line width is gradually decreasing, the size of the space between the contact plug and the gate is gradually decreasing, so that the risk of short circuit between the contact plug and the gate is increased, the yield and reliability of products are reduced, and the line width of next-generation products is reduced.
The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and thus it may include information that does not form a related art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which can prevent a contact plug from being in short circuit with a grid, improve the yield and reliability of products, and can not influence the reduction of the line width of next-generation products.
The embodiment of the disclosure provides a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate, wherein a grid structure is arranged on the substrate, and the substrate comprises source-drain doped regions positioned on two opposite sides of the grid structure; forming a dielectric stack layer covering the source-drain doped region on the substrate, wherein the dielectric stack layer comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially stacked on the source-drain doped region, and at least the oxide layer covers the side wall of the grid structure; etching the dielectric stack to form an initial contact hole exposing at least the oxide layer to form at least a portion of a sidewall of the initial contact hole; forming a third nitride layer covering the initial contact hole and the top surface of the second nitride layer in a conformal manner; implanting doping elements into the third nitride layer by adopting an ion implantation process to form a doped nitride layer; etching back the doped nitride layer to form a contact hole exposing the source-drain doped region, wherein the remained doped nitride layer at least covers the side wall of the oxide layer; and forming a contact plug in the contact hole, wherein the contact plug is electrically connected with the source-drain doped region.
In some embodiments of the present disclosure, the initial contact hole passes through the first nitride layer and exposes the source-drain doped region.
In some embodiments of the present disclosure, the initial contact hole exposes the first nitride layer without exposing the source drain doped region; etching back the doped nitride layer to form the contact hole exposing the source-drain doped region, comprising: the doped nitride layer located on the bottom of the initial contact hole and the first nitride layer located under the bottom of the initial contact hole are etched to form the contact hole exposing the source-drain doped region.
In some embodiments of the present disclosure, a doped nitride layer located on a sidewall of the initial contact hole has a first portion proximate to an opening of the initial contact hole and a second portion distal to the opening of the initial contact hole, the first portion having a doping concentration greater than a doping concentration of the second portion; during the etching back of the doped nitride layer, the etching rate of the first portion is greater than the etching rate of the second portion.
In some embodiments of the present disclosure, the doping element includes at least one of B and As.
In some embodiments of the present disclosure, before forming the third nitride layer, further comprising: nitriding the side wall of the oxide layer exposed by the initial contact hole by using a far-field plasma nitriding process to form a nitrogen oxide layer; wherein after forming the doped nitride layer and etching back the doped nitride layer, the remaining doped nitride layer covers at least the oxynitride layer.
In some embodiments of the present disclosure, forming the contact plug in the contact hole includes: forming a diffusion barrier layer covering the contact hole in a conformal manner; and forming a metal layer which covers the diffusion barrier layer and fills the contact hole.
In some embodiments of the present disclosure, during the forming of the contact hole, a recess is formed in the source-drain doped region; the method further comprises the steps of: forming a metal silicide layer in the recess; the contact plug is electrically connected with the source-drain doped region through the metal silicide layer.
In some embodiments of the present disclosure, the gate structure includes a gate stack and a nitride spacer and an oxide spacer sequentially stacked on sidewalls of the gate stack, the first nitride layer covering the gate stack and the oxide spacer.
The embodiment of the disclosure also provides a semiconductor structure, which comprises a substrate, a gate structure, a dielectric stack, a doped nitride layer and a contact plug.
A gate structure is located on the substrate, the substrate including source-drain doped regions located on opposite sides of the gate structure.
And the dielectric stack layer is positioned on the substrate and covers the source-drain doped region, the dielectric stack layer comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially stacked, an initial contact hole penetrating through the dielectric stack layer is arranged in the dielectric stack layer, and at least the oxide layer covers the side wall of the grid structure.
And the doped nitride layer is positioned on the inner wall of the initial contact hole and at least covers the oxide layer of the dielectric stack, and is provided with a contact hole exposing the source-drain doped region.
The contact plug is positioned in the contact hole and is electrically connected with the source-drain doped region.
In some embodiments of the present disclosure, the semiconductor structure further comprises: and the oxynitride layer is positioned between the doped nitride layer and the oxide layer and covers the side wall of the oxide layer exposed by the initial contact hole.
In some embodiments of the present disclosure, the semiconductor structure further comprises: and the contact plug is electrically connected with the source-drain doped region through the metal silicide layer. The contact plug includes: a diffusion barrier layer covering the contact holes in a conformal manner; and the metal layer covers the diffusion barrier layer and fills the contact hole.
As can be seen from the above technical solutions, the method for manufacturing a semiconductor structure according to the embodiments of the present disclosure has at least one of the following advantages and positive effects:
in the embodiment of the disclosure, the third nitride layer is formed to cover the initial contact hole and the top surface of the second nitride layer along with the shape, so that a nitride interlayer is arranged between the initial contact hole and the gate structure, doping elements are injected into the third nitride layer by adopting an ion injection process to form the doped nitride layer, the doped nitride layer is easier to etch back the doped nitride layer in the subsequent process, the contact hole exposing the source drain doping region is formed, the reserved doped nitride layer at least covers the side wall of the oxide layer, and a contact plug is formed in the contact hole, therefore, the doped nitride layer is finally formed between the contact plug and the gate structure to serve as a blocking layer, the electric connection between the contact plug and the gate structure can be prevented, the yield and the reliability of products are improved, and the reduction of the linewidth of next-generation products can not be influenced.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure shown in some embodiments of the present disclosure;
FIG. 2 is a schematic illustration of forming a dielectric stack shown in some embodiments of the present disclosure;
FIG. 3 is a schematic illustration of forming an initial contact hole in a dielectric stack, as shown in some embodiments of the present disclosure;
FIG. 4 is a schematic diagram illustrating nitridation of sidewalls of an oxide layer exposed by an initial contact hole using a far-field plasma nitridation process to form an oxynitride layer, as shown in some embodiments of the present disclosure;
FIG. 5 is a schematic illustration of forming a third nitride layer shown in some embodiments of the present disclosure;
FIG. 6 is a schematic diagram of a doped nitride layer formed by implanting a doping element into a third nitride layer using an ion implantation process according to some embodiments of the present disclosure;
FIG. 7 is a schematic diagram of etching back a doped nitride layer to form a contact hole exposing a source-drain doped region, as shown in some embodiments of the present disclosure;
FIG. 8 is a schematic illustration of forming recesses in source drain doped regions as shown in some embodiments of the present disclosure;
fig. 9 is a schematic diagram illustrating the formation of a metal silicide layer in a recess according to some embodiments of the present disclosure;
fig. 10 is a schematic diagram illustrating formation of contact plugs according to some embodiments of the present disclosure.
Reference numerals illustrate:
1. a substrate; 101. a source-drain doped region; 102. shallow trench isolation; 103. an active region; 2. a gate structure; 201. a gate dielectric layer; 202. a gate layer; 203. an insulating cap layer; 204. a nitride spacer layer; 205. an oxide spacer layer; 3. a dielectric stack; 301. a first nitride layer; 302. an oxide layer; 303. a second nitride layer; 304. a nitrogen oxide layer; 4. a third nitride layer; 5. doping the nitride layer; 501. a first portion; 502. a second portion; 6. a metal silicide layer; 7. a contact plug; 701. a diffusion barrier layer; 702. a metal layer; h1, initial contact holes; h2, contact holes; r, concave; x, horizontal direction; y, vertical direction.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration various exemplary structures in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various exemplary features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the directions of examples in the drawings. Nothing in this specification should be construed as requiring a particular three-dimensional orientation of structures to fall within the scope of this disclosure. Furthermore, the terms "first," "second," and the like in the claims are used merely as labels, and are not intended to limit the numerals of their objects.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
In addition, in the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless specifically defined otherwise.
As shown in fig. 1, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps S110 to S170.
S110: a substrate 1 is provided, on which substrate 1 a gate structure 2 is provided, the substrate 1 comprising source and drain doped regions 101 on opposite sides of the gate structure 2.
S120: a dielectric stack 3 is formed on the substrate 1 covering the source-drain doped regions 101, the dielectric stack 3 comprising a first nitride layer 301, an oxide layer 302 and a second nitride layer 303 stacked in sequence on the source-drain doped regions 101, and at least the oxide layer 302 covering the sidewalls of the gate structure 2.
S130: dielectric stack 3 is etched to form initial contact holes H1, initial contact holes H1 exposing at least the sidewalls of oxide layer 302.
S140: a third nitride layer 4 is formed to cover the initial contact hole H1 and the top surface of the second nitride layer 303 in a conformal manner.
S150: a doping element is implanted into the third nitride layer 4 using an ion implantation process to form a doped nitride layer 5.
S160: the doped nitride layer 5 is etched back to form a contact hole H2 exposing the source drain doped region 101, wherein the remaining doped nitride layer 5 covers at least the sidewalls of the oxide layer 302.
S170: a contact plug 7 is formed in the contact hole H2, and the contact plug 7 is electrically connected to the source-drain doped region 101.
According to the preparation method in the embodiment of the disclosure, the doped nitride layer 5 can be finally formed between the contact plug 7 and the gate structure 2 to serve as a barrier layer, so that electrical connection between the contact plug 7 and the gate structure due to line width reduction is prevented, the yield and reliability of products are improved, and the line width reduction of next-generation products is not affected.
The following describes in detail the method for manufacturing the semiconductor structure according to the embodiments of the present disclosure.
S110: a substrate 1 is provided, on which substrate 1 a gate structure 2 is provided, the substrate 1 comprising source and drain doped regions 101 on opposite sides of the gate structure 2.
As shown in fig. 2, in some embodiments, the material of the substrate 1 may be silicon, silicon carbide, silicon-on-insulator-germanium, or germanium-on-insulator, etc. The substrate 1 may also be implanted with certain dopant particles to change electrical parameters according to design requirements.
In some embodiments, as shown in fig. 2, shallow trench isolations 102 are formed on the substrate 1 with active regions 103 between the shallow trench isolations, and the gate structures 2 are located in the active regions 103. The active region 103 further has a bit line structure and a word line structure (not shown) therein, and the word line structure and the bit line structure are located at different heights, and the word line structure and the bit line structure are electrically connected to the active region 103.
As shown in fig. 2, in the active region 103 of the substrate 1, source-drain doped regions 101 are further provided, which are located at both sides of the gate structure 2. One of the source-drain doped regions 101 may function as a source and the other may function as a drain.
In some embodiments, as shown in fig. 2, the gate structure 2 includes a gate stack and a nitride spacer layer and an oxide spacer layer sequentially stacked on sidewalls of the gate stack.
As shown in fig. 2, the gate structure 2 includes a gate stack including a gate dielectric layer 201, a gate layer 202, and an insulating cap layer 203 stacked in order from the surface of the substrate 1. The gate layer 202 may be a stack, including a polysilicon layer and a metal material layer sequentially stacked from the gate dielectric layer 201, or the gate layer 202 is a polysilicon layer or a metal material layer, which is not particularly limited herein. In some embodiments, the metal material layer may include at least one of tungsten, copper, aluminum. In some embodiments, the material of gate dielectric layer 201 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the insulating cap layer 203 may be silicon nitride.
As shown in fig. 2, nitride spacer layer 204 covers the sidewalls of the gate stack, insulating the gate stack from other functional layers or structures, and in some embodiments, the material of nitride spacer layer 204 may include at least one of silicon nitride and silicon oxynitride, and oxide spacer layer 205 covers the sidewalls of nitride spacer layer 204, further insulating the gate stack from other functional layers or structures, and protecting the gate stack. In some embodiments, the material of the oxide spacer layer 205 may include silicon oxide.
The gate structure 2 may be formed by a deposition process and an etching process, which are not described herein. Before forming the gate structure 2, a metal element may be doped in the substrate 1 located at both sides of the gate structure 2 using an ion implantation process to form the source drain doped region 101.
S120: a dielectric stack 3 is formed on the substrate 1 covering the source-drain doped regions 101, the dielectric stack 3 comprising a first nitride layer 301, an oxide layer 302 and a second nitride layer 303 stacked in sequence on the source-drain doped regions 101, and at least the oxide layer 302 covering the sidewalls of the gate structure 2.
As shown in fig. 2, a first nitride layer 301 may be formed on the semiconductor substrate 1, on the oxide spacer 205 and on the gate stack using a deposition process, i.e. the first nitride layer 301 covers the gate stack and the oxide spacer 205. The material of the first nitride layer 301 may include silicon nitride. The deposition process is continued to form an oxide layer 302 on the first nitride layer 301, and the material of the oxide layer 302 may be silicon oxide or silicon oxynitride. The top surfaces of the oxide layer 302 and the first nitride layer 301 are polished using a chemical mechanical polishing process such that the top surfaces of the oxide layer 302 and the first nitride layer 301 are flush, or the oxide layer 302 is flush with the top surface of the insulating cap layer 203, providing a planar surface for the subsequent formation of the second nitride layer 303. A second nitride layer 303 is formed on the oxide layer 302 and on the surface of the first nitride layer 301 using a deposition process to form the dielectric stack 3. The material of the second nitride layer 303 may include silicon nitride.
In the presently disclosed embodiment, at least oxide layer 302 covers the sidewalls of gate structure 2. It should be noted that, the oxide layer 302 covers the sidewall of the gate structure 2, and the oxide layer 302 is not necessarily in direct contact with the sidewall of the gate structure 2, but in the horizontal direction X, the projection of the oxide layer 302 on the gate structure 2 can cover the sidewall of the gate structure 2, so that when the oxide layer 302 is processed by adopting the far-field plasma nitridation process in the subsequent step, the formed oxynitride layer 304 can cover the sidewall of the gate structure 2, so that the subsequently formed third nitride layer 4 can cover at least the sidewall of the gate structure 2, and finally, after the contact plug 7 is formed in the subsequent step, the third oxynitride layer 4 is located between the contact plug 7 and the gate structure 2 in the horizontal direction X to form a barrier layer, thereby avoiding the electrical connection between the gate layer 202 of the gate structure 2 and the contact plug 7 due to the line width reduction, improving the yield and reliability of the product, and not affecting the line width reduction of the next-generation product.
It should be noted that, the "vertical direction Y" in the embodiment of the present disclosure may be understood as a direction perpendicular to the surface of the substrate 1, for example, when the gate layer 202 is a stack of a polysilicon layer and a metal material layer, the polysilicon layer and the metal material layer are stacked in the vertical direction Y; the "horizontal direction X" may be understood as a direction parallel to the surface of the substrate 1, for example, the initial contact holes H1 are distributed on both sides of the gate structure 2 in the horizontal direction X. The horizontal direction X and the vertical direction Y are perpendicular to each other, and the technical term is merely for convenience of description and is not meant to be limiting.
The deposition process in embodiments of the present disclosure may employ at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.
S130: the dielectric stack 3 is etched to form an initial contact hole H1, the initial contact hole H1 exposing at least the oxide layer 302 to form at least part of the sidewalls of the initial contact hole H1.
As shown in fig. 3, the dielectric stack 3 may be etched using a dry etching process to form an initial contact hole H1. The initial contact holes H1 are located at two sides of the gate structure 2, and the initial contact holes H1 correspond to the source-drain doped regions 101 on the substrate 1 in the vertical direction Y.
In some embodiments, the initial contact hole H1 passes through the first nitride layer 301 and exposes the source-drain doped region 101. I.e. the initial contact hole H1 extends through the entire dielectric stack 3.
In other embodiments, the initial contact hole H1 exposes the first nitride layer 301, and does not expose the source-drain doped region 101, i.e., the initial contact hole H1 does not penetrate the first nitride layer 301, and the first nitride layer 301 with the bottom portion not penetrated may be removed by an etching back process together with other functional layers in a subsequent process.
The initial contact hole H1 is formed to expose at least the oxide layer 302 in the dielectric stack 3, so that nitridation treatment is performed on the sidewall of the oxide layer 302 in a subsequent process. In some embodiments, portions of the first nitride layer 301 on the sidewalls of the oxide spacer 205 are removed, exposing portions of the oxide spacer 205, and initial contact holes H1 are formed exposing the oxide spacer 205 and the oxide layer 302. In other embodiments, the first nitride layer 301 on the sidewall of the oxide spacer 205 is not removed, the oxide spacer 8 is not exposed, and the initial contact hole H1 is formed exposing the first nitride layer 301 and the oxide layer 302. In other embodiments, the first nitride layer 301 is not removed, and the sidewalls of the initial contact hole H1 are exposed from the oxide layer 302.
S140: a third nitride layer 4 is formed to cover the initial contact hole H1 and the top surface of the second nitride layer 303 in a conformal manner.
As shown in fig. 4, in some embodiments, the method may further comprise, prior to forming the third nitride layer 4: the sidewalls of the oxide layer 302 exposed by the initial contact hole H1 are nitrided using a far-field plasma nitridation process to form an oxynitride layer 304.
Referring to fig. 4, after the sidewall of the oxide layer 302 is treated by the far-field plasma nitridation process, the characteristics of the oxide layer 302 can be changed to form the oxynitride layer 304, and the properties of the oxynitride layer 304 are closer to those of the third nitride layer 4 formed by the subsequent process, so that the third nitride layer 4 can be formed on the oxynitride layer 304 more stably. At the same time, diffusion of the metal of the contact plug 7 formed later can be further prevented.
In some embodiments, as shown in fig. 4, the initial contact hole H1 may expose a portion of the first nitride layer 301 located on the sidewall of the oxide spacer layer 205, and since the first nitride layer 301 has properties closer to those of the third nitride layer 4 than the oxide layer 302, a stable third nitride layer 4 can be more easily formed on the first nitride layer 301 when the first nitride layer 301 is exposed.
In other embodiments, the first nitride layer 301 on the sidewall of the oxide spacer 205 may not be exposed by the initial contact hole H1, the inner wall of the initial contact hole H1 may be the oxide layer 302, and the sidewall of the oxide layer 302 exposed by the initial contact hole H1 may be nitrided by using the far-field plasma nitridation process to form the oxynitride layer 304.
In other embodiments, the sidewalls of the initial contact hole H1 may also be exposed by the oxide spacer 205 on one side and exposed by the oxide layer 302 on the other side, and then the sidewalls of the oxide spacer 205 and the oxide layer 302 exposed by the initial contact hole H1 are nitrided by a far-field plasma nitridation process, so that the oxynitride layers 304 may be formed on the surfaces of the oxide spacer 205 and the oxide layer 302, respectively.
As shown in fig. 5, after the oxynitride layer 304 is formed, a third nitride layer 4 may be formed to conformally cover the initial contact hole H1 and the top surface of the second nitride layer 303 using a deposition process. The material of the third nitride layer 4 may comprise silicon nitride. The third nitride layer 4 can be more stably formed on the surface of the oxynitride layer 304.
In some embodiments, the oxynitride layer 304 may be formed directly in the initial contact hole H1 instead of the far-field plasma nitridation process, and those skilled in the art may select the embodiment according to practical situations, for example, when the inner wall of one side of the initial contact hole H1 is the first nitride layer 301, the oxynitride layer 304 may not be formed, which is not limited herein.
S150: a doping element is implanted into the third nitride layer 4 using an ion implantation process to form a doped nitride layer 5.
As shown in fig. 6, a doping element is implanted into the third nitride layer 4 using an ion implantation process, and in some embodiments, the doping element includes at least one of boron (B) and arsenic (As). By doping the third nitride layer 4 with the above elements to form the doped nitride layer 5, the rate of etching back the doped nitride layer 5 in the subsequent process can be increased.
S160: the doped nitride layer 5 is etched back to form a contact hole H2 exposing the source drain doped region 101, wherein the remaining doped nitride layer 5 covers at least the sidewalls of the oxide layer 302.
The third nitride layer 4 is doped to form a doped nitride layer 5, and in some embodiments, as shown in fig. 6, the doped nitride layer 5 on the sidewall of the initial contact hole H1 has a first portion 501 (a portion above the dotted line in the figure) close to the opening of the initial contact hole H1 and a second portion 502 (a portion below the dotted line in the figure) far from the opening of the initial contact hole H1, where the doping concentration of the first portion 501 is greater than the doping concentration of the second portion 502, and in the process of etching back the doped nitride layer 5, the etching rate of the first portion 501 is greater than the etching rate of the second portion 502, as shown in fig. 7. After the doped nitride layer 5 is etched back, since the etching rate of the first portion 501 is greater than that of the second portion 502, the first portion 501 of the doped nitride layer 5 is etched away more than the second portion 502, so that the radial dimension of the contact hole H2 located in the first portion 501 becomes larger, which is beneficial to forming the contact plug 7 in the contact hole H2.
In some embodiments, after the initial contact hole H1 is formed, the source-drain doped region 101 is not exposed, i.e. the bottom of the initial contact hole H1 is the first nitride layer 301, then when the doped nitride layer 5 is not etched back, the bottom of the contact hole H2 has the doped nitride layer 5, and the first nitride layer 301 is located under the doped nitride layer 5, then the doped nitride layer 5 is etched back to form the contact hole H2 exposing the source-drain doped region 101, including: the doped nitride layer 5 located on the bottom of the initial contact hole H1 and the first nitride layer 301 located under the bottom of the initial contact hole H1 are etched to form a contact hole H2 exposing the source-drain doped region 101.
In some embodiments, after forming the doped nitride layer 5 and etching back the doped nitride layer 5, the remaining doped nitride layer 5 covers at least the oxynitride layer 304. That is, the doped nitride layer 5 correspondingly covers at least the gate structure 2 in the horizontal direction X, so that after the contact plug 7 is formed in the contact hole H2, the doped nitride layer 5 is provided between the contact plug 7 and the gate structure 2 as a barrier layer, thereby preventing the electrical connection between the contact plug 7 and the gate structure 2 due to the reduction of the line width, improving the yield and reliability of the product, and not affecting the reduction of the line width of the next-generation product.
S170: a contact plug 7 is formed in the contact hole H2, and the contact plug 7 is electrically connected to the source-drain doped region 101.
As shown in fig. 8, before forming the contact plug 7, in forming the contact hole H2, a recess R may be formed in the source-drain doped region 101. I.e. the source and drain doped regions 101 continue to be etched down after the contact holes H2 are formed, to form recesses R, while the doped nitride layer 5 is etched back. After forming the recess R, as shown in fig. 9, the manufacturing method further includes: a metal silicide layer 6 is formed in the recess R, and a contact plug 7 formed in a subsequent process is electrically connected to the source drain doped region 101 through the metal silicide layer 6.
In some embodiments, the metal elements of the metal silicide layer 6 include at least one of Co, ni, pt, ti, ta, mo and W, which are capable of forming a stable metal silicide in combination with silicon in the substrate 1, reducing the contact resistance with the contact plug 7.
As shown in fig. 10, the contact plug 7 may be formed in the contact hole H2 using a deposition process, including: forming a diffusion barrier 701 covering the contact hole H2 in a conformal manner; a metal layer 702 is formed to cover the diffusion barrier 701 and fill the contact hole H2.
As shown in fig. 10, a diffusion barrier layer 701 may be formed in the contact hole H2 using a deposition process, the diffusion barrier layer 701 serving to prevent diffusion of metal of the contact plug 7, ensuring stability of electrical properties of the semiconductor structure. The diffusion barrier 701 may be a layer or a stack of layers having different materials. In some embodiments, the material of the diffusion barrier 701 may be at least one of titanium nitride and tungsten nitride.
After the diffusion barrier 701 is formed, a deposition process is again used to form a metal layer 702 that covers the diffusion barrier 701 and fills the contact hole H2. The metal layer 702 may be at least one of W, cu and Al, so as to be electrically connected to the source/drain doped region 101.
In summary, in the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure, the third nitride layer 4 is formed to cover the initial contact hole H1 and the top surface of the second nitride layer 303 along with the shape, so that a layer of nitride interlayer is formed between the initial contact hole H1 and the gate structure 2, the doped element is implanted into the third nitride layer 4 by using the ion implantation process to form the doped nitride layer 5, so that the etching back of the doped nitride layer 5 in the subsequent process is easier, the doped nitride layer 5 is etched back, the contact hole H2 exposing the source-drain doped region 101 is formed, the remaining doped nitride layer 5 covers at least the sidewall of the oxide layer 302, and the contact plug 7 is formed in the contact hole H2, so that the doped nitride layer 5 is finally formed between the contact plug 7 and the gate structure 2 as a barrier layer, and thus, the electrical connection between the contact plug 7 and the gate structure 2 can be prevented, the yield and reliability of the product can be improved, and the line width reduction of the next generation product can not be affected.
The disclosed embodiments also provide a semiconductor structure, as shown in fig. 10, comprising a substrate 1, a gate structure 2, a dielectric stack 3, a doped nitride layer 5 and a contact plug 7.
The substrate 1 is a semiconductor substrate 1, shallow trench isolations 102 are formed on the substrate 1, active regions 103 are arranged between the shallow trench isolations 102, and the gate structures 2 are located in the active regions 103. The active region 103 further has a bit line structure and a word line structure (not shown) therein, and the word line structure and the bit line structure are located at different heights, and the word line structure and the bit line structure are electrically connected to the active region 103.
The gate structure 2 is located on a substrate 1, the substrate 1 comprising source and drain doped regions 101 located on opposite sides of the gate structure 2. As shown in fig. 10, the gate structure 2 may include a gate stack and a nitride spacer 204 and an oxide spacer 205 sequentially stacked on sidewalls of the gate stack.
As shown in fig. 10, the gate stack includes a gate dielectric layer 201, a gate layer 202, and an insulating cap layer 203 stacked in order from the surface of the substrate 1. A gate dielectric layer 201 is located on the substrate 1, i.e. on the channel, to insulate the gate layer 202 from the channel. The gate layer 202 may be a stack, including a polysilicon layer and a metal material layer sequentially stacked from the gate dielectric layer 201, or the gate layer 202 is a polysilicon layer or a metal material layer, which is not particularly limited herein. In some embodiments, the metal material layer may include at least one of tungsten, copper, aluminum. In some embodiments, the material of gate dielectric layer 201 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the insulating cap layer 203 may be silicon nitride such that the top of the gate layer 202 is insulated from other functional layers.
As shown in fig. 10, nitride spacer 204 covers the sidewalls of the gate stack, insulating the gate stack from other functional layers or structures, and in some embodiments, the material of nitride spacer 204 may include at least one of silicon nitride and silicon oxynitride, and oxide spacer 205 covers the sidewalls of nitride spacer 204, further insulating the gate stack structure from other functional layers or structures, and protecting the gate stack. In some embodiments, the material of the oxide spacer layer 205 may include silicon oxide.
With continued reference to fig. 10, a dielectric stack 3 is located on the substrate 1 and covers the source drain doped regions 101, the dielectric stack 3 comprising a first nitride layer 301, an oxide layer 302 and a second nitride layer 303 stacked in sequence, as shown in fig. 3, an initial contact hole H1 is provided in the dielectric stack 3 through the dielectric stack 3, wherein at least the oxide layer 302 covers the sidewalls of the gate structure 2.
In some embodiments, the first nitride layer 301 may cover the oxide spacer 205 and the gate stack of the gate structure 2, and the first nitride layer 301 may serve as an inner wall of one side of the initial contact hole H1.
As shown in fig. 7 and 10, the doped nitride layer 5 is located on the inner wall of the initial contact hole H1 and covers the oxide layer 302 of the dielectric stack 3 at least in the horizontal direction X, and the doped nitride layer 5 has a contact hole H2 exposing the source-drain doped region 101.
In some embodiments, the doping element in the doped nitride layer 5 includes at least one of boron (B) and arsenic (As), so that the etching rate of the doped nitride layer 5 can be increased during the manufacturing process. Since at least the oxide layer 302 covers the sidewall of the gate structure 2 and the doped nitride layer 5 is located on the inner wall of the initial contact hole H1 and covers at least the oxide layer 302 of the dielectric stack 3, the doped nitride layer 5 can cover the sidewall of the gate structure 2 in the horizontal direction X, so that the doped nitride layer 5 can be located between the gate structure 2 and the contact plug 7 to form a barrier layer therebetween, thereby preventing electrical connection between the two due to line width reduction, improving the yield and reliability of the product, and not affecting the line width reduction of the next-generation product.
The contact plug 7 is located in the contact hole H2 and is electrically connected to the source-drain doped region 101. In some embodiments, the material of the contact plug 7 may include at least one of tungsten, copper, and aluminum to electrically connect the source drain doped region 101 with other conductive structures.
In some embodiments, as shown in fig. 4 and 10, the semiconductor structure further includes an oxynitride layer 304 located between the doped nitride layer 5 and the oxide layer 302 and covering the sidewalls of the oxide layer 302 exposed by the initial contact hole H1. In some embodiments, oxynitride layer 304 is also located between doped nitride layer 5 and oxide spacer layer 205 and covers the sidewalls of oxide spacer layer 205 that are exposed by initial contact hole H1. The oxynitride layer 304 can be more stably combined with the doped nitride layer 5 to improve the stability of the electrical performance of the semiconductor structure.
In some embodiments, as shown in fig. 10, the semiconductor structure further includes a metal silicide layer 6 between the contact plug 7 and the source-drain doped region 101, and the contact plug 7 is electrically connected to the source-drain doped region 101 through the metal silicide layer 6. The metal silicide layer 6 can reduce the contact resistance with the contact plug 7 and improve the electrical performance of the semiconductor structure.
In some embodiments, as shown in fig. 10, the contact plug 7 includes a diffusion barrier 701 and a metal layer 702. The diffusion barrier 701 conformally covers the contact hole H2, and the metal layer 702 covers the diffusion barrier 701 and fills the contact hole H2. The diffusion barrier layer 701 can prevent the diffusion of the metal of the contact plug 7, and ensure the stability of the electrical performance of the semiconductor structure. The diffusion barrier 701 may be a layer or a stack of layers having different materials. The contact plug 7 is electrically connected to the metal silicide layer 6 through the diffusion barrier layer 701, and thus the material of the diffusion barrier layer 701 is a conductive material, for example, the diffusion barrier layer 701 may be at least one of titanium nitride and tungsten nitride.
In summary, in the semiconductor structure of the embodiment of the disclosure, the doped nitride layer 5 is located on the inner wall of the initial contact hole H1 and at least covers the oxide layer 302 of the dielectric stack 3, the contact plug 7 is located in the contact hole H2 and is electrically connected with the source-drain doped region 101, so that the doped nitride layer 5 is located between the contact plug 7 and the gate structure 2, and the doped nitride layer 5 becomes a barrier layer between the contact plug 7 and the gate structure 2, which can prevent the electrical connection between the contact plug 7 and the gate structure 2 due to the reduction of the line width, improve the yield and reliability of the product, and not affect the reduction of the line width of the next-generation product.
It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the disclosure. The disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined herein extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims (12)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein a grid structure is arranged on the substrate, and the substrate comprises source-drain doped regions positioned on two opposite sides of the grid structure;
forming a dielectric stack layer covering the source-drain doped region on the substrate, wherein the dielectric stack layer comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially stacked on the source-drain doped region, and at least the oxide layer covers the side wall of the grid structure;
etching the dielectric stack to form an initial contact hole exposing at least the oxide layer to form at least a portion of a sidewall of the initial contact hole;
forming a third nitride layer covering the initial contact hole and the top surface of the second nitride layer in a conformal manner;
implanting doping elements into the third nitride layer by adopting an ion implantation process to form a doped nitride layer;
etching back the doped nitride layer to form a contact hole exposing the source-drain doped region, wherein the remained doped nitride layer at least covers the side wall of the oxide layer;
and forming a contact plug in the contact hole, wherein the contact plug is electrically connected with the source-drain doped region.
2. The method of claim 1, wherein the initial contact hole passes through the first nitride layer and exposes the source drain doped region.
3. The method of claim 1, wherein the initial contact hole exposes the first nitride layer without exposing the source drain doped region;
etching back the doped nitride layer to form the contact hole exposing the source-drain doped region, comprising:
the doped nitride layer located on the bottom of the initial contact hole and the first nitride layer located under the bottom of the initial contact hole are etched to form the contact hole exposing the source-drain doped region.
4. A method according to any of claims 1 to 3, characterized in that the doped nitride layer located on the sidewalls of the initial contact hole has a first portion close to the opening of the initial contact hole and a second portion remote from the opening of the initial contact hole, the doping concentration of the first portion being greater than the doping concentration of the second portion;
during the etching back of the doped nitride layer, the etching rate of the first portion is greater than the etching rate of the second portion.
5. The method of claim 4, wherein the doping element comprises at least one of B and As.
6. A method according to any one of claims 1 to 3, further comprising, prior to forming the third nitride layer:
nitriding the side wall of the oxide layer exposed by the initial contact hole by using a far-field plasma nitriding process to form a nitrogen oxide layer;
wherein after forming the doped nitride layer and etching back the doped nitride layer, the remaining doped nitride layer covers at least the oxynitride layer.
7. A method according to any one of claims 1 to 3, wherein forming the contact plug in the contact hole comprises:
forming a diffusion barrier layer covering the contact hole in a conformal manner;
and forming a metal layer which covers the diffusion barrier layer and fills the contact hole.
8. The method of claim 7, wherein during forming the contact hole, a recess is formed in the source-drain doped region;
the method further comprises the steps of: forming a metal silicide layer in the recess;
the contact plug is electrically connected with the source-drain doped region through the metal silicide layer.
9. A method according to any of claims 1 to 3, wherein the gate structure comprises a gate stack and a nitride spacer and an oxide spacer laminated in sequence on sidewalls of the gate stack, the first nitride layer covering the gate stack and the oxide spacer.
10. A semiconductor structure, comprising:
a substrate;
the grid structure is positioned on the substrate, and the substrate comprises source-drain doped regions positioned on two opposite sides of the grid structure;
a dielectric stack layer, which is positioned on the substrate and covers the source-drain doped region, wherein the dielectric stack layer comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially stacked, an initial contact hole penetrating through the dielectric stack layer is arranged in the dielectric stack layer, and at least the oxide layer covers the side wall of the grid structure;
a doped nitride layer located on the inner wall of the initial contact hole and at least covering the oxide layer of the dielectric stack, wherein the doped nitride layer is provided with a contact hole exposing the source-drain doped region;
and the contact plug is positioned in the contact hole and is electrically connected with the source-drain doped region.
11. The semiconductor structure of claim 10, further comprising:
and the oxynitride layer is positioned between the doped nitride layer and the oxide layer and covers the side wall of the oxide layer exposed by the initial contact hole.
12. The semiconductor structure of claim 11, further comprising:
the contact plug is electrically connected with the source-drain doped region through the metal silicide layer;
the contact plug includes:
a diffusion barrier layer covering the contact holes in a conformal manner;
and the metal layer covers the diffusion barrier layer and fills the contact hole.
CN202310815307.6A 2023-07-03 2023-07-03 Method for preparing semiconductor structure and semiconductor structure Pending CN116782641A (en)

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