CN116782640A - Method for preparing semiconductor structure and semiconductor structure - Google Patents

Method for preparing semiconductor structure and semiconductor structure Download PDF

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Publication number
CN116782640A
CN116782640A CN202310814986.5A CN202310814986A CN116782640A CN 116782640 A CN116782640 A CN 116782640A CN 202310814986 A CN202310814986 A CN 202310814986A CN 116782640 A CN116782640 A CN 116782640A
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layer
contact hole
nitride
oxide
silicon substrate
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曾以志
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202310814986.5A priority Critical patent/CN116782640A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The disclosure provides a preparation method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a silicon substrate, wherein a grid structure is arranged on the silicon substrate and comprises a source-drain doping region; forming a dielectric stack layer covering the source-drain doped region on the silicon substrate, wherein the dielectric stack layer comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially stacked; etching the dielectric stack to form an initial contact hole exposing the source-drain doped region, wherein the lateral dimension of the initial contact hole in the first nitride layer and the oxide layer is smaller than that of the initial contact hole in the second nitride layer; etching the oxide layer and the first nitride layer to form a contact hole, wherein the lateral dimension of the contact hole in the first nitride layer and the oxide layer is larger than that in the second nitride layer; forming a metal silicide layer at the bottom of the contact hole; forming a nitride liner layer on the side wall of the contact hole; and forming a contact plug in the contact hole and connecting with the metal silicide layer. The present disclosure is easy to form a metal silicide layer and can prevent metal diffusion of a contact plug.

Description

Method for preparing semiconductor structure and semiconductor structure
Technical Field
The disclosure relates to the technical field of semiconductor manufacturing, and in particular relates to a manufacturing method of a semiconductor structure and the semiconductor structure.
Background
As semiconductor technology is mature, the integration density of the memory is higher and higher, for example, in DRAM (dynamic random access memory ), the line width is gradually reduced, and the Aspect ratio (Aspect ratio) of the contact plug becomes very large, so that the difficulty of forming the metal silicide in the substrate at the bottom of the contact plug is increased, and the contact resistance is increased. In addition, metal diffusion caused by forming the contact plug can affect the stability of the semiconductor structure, and reduce the yield.
The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and thus it may include information that does not form a related art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which can reduce the aspect ratio of a contact plug, facilitate forming a metal silicide layer, reduce contact resistance, prevent metal diffusion of the contact plug, improve the stability of the semiconductor structure and improve the yield.
The embodiment of the disclosure provides a preparation method of a semiconductor structure, which comprises the following steps: providing a silicon substrate, wherein a grid structure is arranged on the silicon substrate, and the silicon substrate comprises source and drain doped regions positioned on two opposite sides of the grid structure; forming a dielectric stack layer covering the source-drain doped region on the silicon substrate, wherein the dielectric stack layer comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially stacked on the source-drain doped region, and the thickness of the first nitride layer is smaller than that of the second nitride layer; etching the dielectric stack to form an initial contact hole exposing the source-drain doped region, wherein the lateral dimension of the initial contact hole in the first nitride layer and the oxide layer is smaller than the lateral dimension of the initial contact hole in the second nitride layer; etching sidewalls of the oxide layer and the first nitride layer exposed by the initial contact hole to form a contact hole, wherein a lateral dimension of the contact hole in the first nitride layer and the oxide layer is greater than a lateral dimension of the contact hole in the second nitride layer; forming a metal silicide layer at the bottom of the contact hole; forming a nitride liner layer on the side wall of the contact hole; and forming a contact plug in the contact hole, wherein the contact plug is electrically connected with the source-drain doped region through the metal silicide layer.
In some embodiments of the present disclosure, before forming the nitride liner layer on the sidewall of the contact hole, the method further includes: nitriding the side wall of the oxide layer exposed by the contact hole by using a far-field plasma nitriding process to form a nitrogen oxide layer; wherein the nitride liner layer covers the oxynitride layer.
In some embodiments of the present disclosure, the gate structure includes a gate stack structure, a nitride isolation layer covering sidewalls of the gate stack structure, and an oxide isolation layer covering sidewalls of the nitride isolation layer; the first nitride layer also covers the oxide isolation layer; the oxide isolation layer is partially etched in the process of forming the initial contact hole; the oxide isolation layer is partially etched during the formation of the contact hole.
In some embodiments of the present disclosure, before forming the nitride liner layer on the sidewall of the contact hole, the method further includes: nitriding the side wall of the oxide layer and the side wall of the oxide isolation layer exposed by the contact hole by using a far-field plasma nitriding process to form a nitrogen oxide layer; wherein the nitride liner layer covers the oxynitride layer.
In some embodiments of the present disclosure, the contact hole includes a recess in the silicon substrate, the metal silicide layer being located within the recess.
In some embodiments of the present disclosure, forming the contact plug in the contact hole includes: forming a diffusion barrier layer covering the nitride liner layer and the metal silicide layer in a conformal manner; and forming a metal layer which covers the diffusion barrier layer and fills the contact hole.
The embodiment of the disclosure also provides a semiconductor structure, which comprises: a silicon substrate; the grid structure is positioned on the silicon substrate, and the silicon substrate comprises source-drain doped regions positioned on two opposite sides of the grid structure; the dielectric stack comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially stacked on the source-drain doped region, wherein the thickness of the first nitride layer is smaller than that of the second nitride layer, and a contact hole exposing the source-drain doped region is formed in the dielectric stack; the metal silicide layer is arranged at the bottom of the contact hole; a nitride liner layer arranged on the side wall of the contact hole; the contact plug is arranged in the contact hole taking the nitride liner layer as the side wall and is electrically connected with the source-drain doped region through the metal silicide layer; wherein a lateral dimension of the contact plug in the first nitride layer and the oxide layer is greater than a lateral dimension of the contact plug in the second nitride layer.
In some embodiments of the present disclosure, the semiconductor structure further comprises: and the oxynitride layer is positioned between the nitride liner layer and the oxide layer and covers the side wall of the oxide layer exposed by the contact hole.
In some embodiments of the present disclosure, the gate structure includes a gate stack structure, a nitride isolation layer covering sidewalls of the gate stack structure, and an oxide isolation layer covering sidewalls of the nitride isolation layer; the oxynitride layer is disposed between the oxide isolation layer and the nitride liner layer.
In some embodiments of the present disclosure, the contact plug includes: a diffusion barrier layer conformally covering the nitride liner layer and the metal silicide layer; and the metal layer covers the diffusion barrier layer and fills the contact hole.
As can be seen from the above technical solutions, the method for manufacturing a semiconductor structure according to the embodiments of the present disclosure has at least one of the following advantages and positive effects:
in the embodiment of the disclosure, the exposed oxide layer and the exposed side wall of the first nitride layer of the initial contact hole are etched to form the contact hole, and the lateral dimension of the contact hole in the first nitride layer and the oxide layer is larger than that of the contact hole in the second nitride layer, so that the aspect ratio of the contact hole is reduced, the metal silicide layer is easier to form at the bottom of the contact hole, and the contact resistance of the contact plug is reduced; since the nitride liner layer is formed on the side wall of the contact hole, the metal diffusion of the contact plug can be prevented, the stability of the semiconductor structure can be improved, and the yield can be improved.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure shown in some embodiments of the present disclosure;
FIG. 2 is a schematic illustration of forming a dielectric stack on a silicon substrate, as shown in some embodiments of the present disclosure;
FIG. 3 is a schematic illustration of forming an initial contact hole in a dielectric stack, as shown in some embodiments of the present disclosure;
FIG. 4 is a schematic illustration of forming contact holes by etching sidewalls of an exposed oxide layer and a first nitride layer of an initial contact hole, as shown in some embodiments of the present disclosure;
FIG. 5 is a schematic illustration of a contact hole including a recess in a silicon substrate, as shown in some embodiments of the present disclosure;
fig. 6 is a schematic diagram illustrating the formation of a metal silicide layer in a recess according to some embodiments of the present disclosure;
FIG. 7 is a schematic diagram of a nitridation process to form an oxynitride layer on sidewalls of an oxide layer and sidewalls of an oxide isolation layer exposed by a contact hole using a far-field plasma nitridation process as illustrated in some embodiments of the present disclosure;
fig. 8 is a schematic illustration of forming a nitride liner layer within a contact hole and over a dielectric stack, as shown in some embodiments of the present disclosure;
fig. 9 is a schematic diagram illustrating formation of a nitride liner layer on sidewalls of a contact hole according to some embodiments of the present disclosure;
fig. 10 is a schematic diagram illustrating formation of a contact plug in a contact hole according to some embodiments of the present disclosure.
Reference numerals illustrate:
1. a silicon substrate; 101. a source-drain doped region; 102. shallow trench isolation; 103. an active region; 2. a gate structure; 201. a gate dielectric layer; 202. a gate layer; 203. an insulating cap layer; 204. a nitride isolation layer; 205. an oxide isolation layer; 3. a dielectric stack; 301. a first nitride layer; 302. an oxide layer; 303. a second nitride layer; 304. a nitrogen oxide layer; 4. a nitride liner layer; 5. a metal silicide layer; 6. a contact plug; 601. a diffusion barrier layer; 602. a metal layer; h1, initial contact holes; h2, contact holes; r, concave; x, horizontal direction; y, vertical direction.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration various exemplary structures in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various exemplary features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the directions of examples in the drawings. Nothing in this specification should be construed as requiring a particular three-dimensional orientation of structures to fall within the scope of this disclosure. Furthermore, the terms "first," "second," and the like in the claims are used merely as labels, and are not intended to limit the numerals of their objects.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
In addition, in the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless specifically defined otherwise.
As shown in fig. 1, an embodiment of the present disclosure provides a method for manufacturing a memory, including the following steps S110 to S170.
S110: a silicon substrate 1 is provided, on which silicon substrate 1 a gate structure 2 is provided, the silicon substrate 1 comprising source and drain doped regions 101 located on opposite sides of the gate structure 2.
S120: a dielectric stack 3 covering the source-drain doped regions 101 is formed on the silicon substrate 1, the dielectric stack 3 comprising a first nitride layer 301, an oxide layer 302 and a second nitride layer 303 sequentially stacked on the source-drain doped regions 101. Wherein the thickness of the first nitride layer 301 is smaller than the thickness of the second nitride layer 303.
S130: the dielectric stack 3 is etched to form an initial contact hole H1 exposing the source drain doped region 101, the lateral dimensions of the initial contact hole H1 in the first nitride layer 301 and the oxide layer 302 being smaller than the lateral dimensions of the initial contact hole H1 in the second nitride layer 303.
S140: sidewalls of the oxide layer 302 and the first nitride layer 301 exposed by the initial contact hole H1 are etched to form a contact hole H2, and a lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 is greater than a lateral dimension of the contact hole H2 in the second nitride layer 303.
S150: a metal silicide layer 5 is formed at the bottom of the contact hole H2.
S160: a nitride liner layer 4 is formed on the side wall of the contact hole H2.
S170: a contact plug 6 is formed in the contact hole H2, and the contact plug 6 is electrically connected to the source-drain doped region 101 through the metal silicide layer 5.
According to the preparation method in the embodiment of the disclosure, the side walls of the oxide layer 302 and the first nitride layer 301 exposed by the initial contact hole H1 are etched to form the contact hole H2, the lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 is larger than that of the contact hole H2 in the second nitride layer 303, the depth-to-width ratio of the contact hole H2 is reduced, so that the metal silicide layer 5 is easier to form at the bottom of the contact hole H2, the area of the metal silicide layer 5 is larger, and the contact resistance of the contact plug 6 is reduced; since the nitride liner layer 4 is formed on the sidewall of the contact hole H2, the metal diffusion of the contact plug 6 can be prevented, the stability of the semiconductor structure can be improved, and the yield can be improved.
The following describes in detail the method for manufacturing the semiconductor structure according to the embodiments of the present disclosure.
S110: a silicon substrate 1 is provided, on which silicon substrate 1 a gate structure 2 is provided, the silicon substrate 1 comprising source and drain doped regions 101 located on opposite sides of the gate structure 2.
As shown in fig. 2, the material of the silicon substrate 1 in the embodiment of the present disclosure is single crystal silicon to facilitate formation of the metal silicide layer 5.
In some embodiments, as shown in fig. 2, shallow trench isolations 102 are formed on the silicon substrate 1, active regions 103 are provided between the shallow trench isolations 102, and the gate structure 2 is located in the active regions 103. The active region 103 further has a bit line structure and a word line structure (not shown) therein, and the word line structure and the bit line structure are located at different heights, and the word line structure and the bit line structure are electrically connected to the active region 103.
As shown in fig. 2, in the active region 103 of the substrate 1, source-drain doped regions 101 are further provided, which are located at both sides of the gate structure 2. One of the source-drain doped regions 101 may function as a source and the other may function as a drain.
In some embodiments, as shown in fig. 2, the gate structure 2 includes a gate stack structure, a nitride isolation layer 204 covering sidewalls of the gate stack structure, and an oxide isolation layer 205 covering sidewalls of the nitride isolation layer 204.
As shown in fig. 2, the gate structure 2 includes a gate stack structure. The gate stack structure includes a gate dielectric layer 201, a gate layer 202, and an insulating cap layer 203 stacked in order from the surface of the silicon substrate 1. The gate layer 202 may be a stack, including a polysilicon layer and a metal material layer sequentially stacked from the gate dielectric layer 201, or the gate layer 202 is a polysilicon layer or a metal material layer, which is not particularly limited herein. In some embodiments, the metal material layer may include at least one of tungsten, copper, aluminum. In some embodiments, the material of gate dielectric layer 201 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the insulating cap layer 203 may be silicon nitride.
As shown in fig. 2, the nitride spacer 204 covers sidewalls of the gate stack structure such that the gate stack structure is insulated from other functional layers or structures, and in some embodiments, the material of the nitride spacer 204 may include at least one of silicon nitride and silicon oxynitride. The oxide isolation layer 205 covers the sidewalls of the nitride isolation layer 204, further isolating the gate stack from other functional layers or structures and protecting the gate stack. In some embodiments, the material of oxide isolation layer 205 may include silicon oxide.
The gate structure 2 may be formed by a deposition process and an etching process, which are not described herein. Before forming the gate structure 2, a metal element may be doped in the silicon substrate 1 located at both sides of the gate structure 2 using an ion implantation process to form the source-drain doped region 101.
The deposition process in embodiments of the present disclosure may be at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.
S120: a dielectric stack 3 covering the source-drain doped regions 101 is formed on the silicon substrate 1, the dielectric stack 3 comprising a first nitride layer 301, an oxide layer 302 and a second nitride layer 303 sequentially stacked on the source-drain doped regions 101. Wherein the thickness of the first nitride layer 301 is smaller than the thickness of the second nitride layer 303.
With continued reference to fig. 2, a first nitride layer 301 may be formed on the silicon substrate 1 using a deposition process, the first nitride layer 301 covering the source drain doped region 101 of the silicon substrate 1 and the gate structure 2, the first nitride layer 301 also covering the oxide isolation layer 205 of the gate structure 2. In some embodiments, the material of the first nitride layer 301 may include at least one of silicon nitride and silicon oxynitride.
After the first nitride layer 301 is formed, the oxide layer 302 is formed on the first nitride layer 301 by using the deposition process, and the material of the oxide layer 302 may include silicon oxide, and the thickness of the oxide layer 302 is greater than that of the first nitride layer 301 in the vertical direction Y, so that the oxide layer 302 not only can further perform an insulating function, but also can perform a supporting function, and can serve as a main carrier for forming the initial contact hole H1 in a subsequent process.
After forming the oxide layer 302, the second nitride layer 303 is formed on the oxide layer 302 using the deposition process continuously. In some embodiments, the material of the second nitride layer 303 may include at least one of silicon nitride and silicon oxynitride. The thickness of the second nitride layer 303 is greater than the thickness of the first nitride layer 301, and the thickness of the second nitride layer 303 is less than the thickness of the oxide layer 302, so that when the contact hole H2 is subsequently formed using an etching process, the lateral dimensions of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 can be greater than the lateral dimensions of the contact hole H2 in the second nitride layer 303. The second nitride layer 303 serves as the top layer of the dielectric stack 3, so that reaction with other elements outside can be avoided, and stability of the dielectric stack 3 is improved. Wherein the thickness of the first nitride layer 301, the thickness of the oxide layer 302, and the thickness of the second nitride layer 303 refer to the dimensions of the first nitride layer 301, the oxide layer 302, and the second nitride layer 303 in the vertical direction Y directly above the source-drain doped region 101, respectively.
S130: the dielectric stack 3 is etched to form an initial contact hole H1 exposing the source drain doped region 101, the lateral dimensions of the initial contact hole H1 in the first nitride layer 301 and the oxide layer 302 being smaller than the lateral dimensions of the initial contact hole H1 in the second nitride layer 303.
As shown in fig. 3, the dielectric stack 3 may be etched using an etching process to form an initial contact hole H1 exposing the source-drain doped region 101, and in some embodiments, the bottom of the initial contact hole H1 may stop at the source-drain doped region 101 of the silicon substrate 1 as shown in fig. 3. In other embodiments, the bottom of the initial contact hole H1 may also extend into the source-drain doped region 101.
In some embodiments, the etching process may be a dry etching process. The dry etching process may be a plasma etching process, the etching gas used in the plasma etching process may be chlorine, and the etching degree may be controlled by controlling the amount of the etching gas.
As shown in fig. 3, the lateral dimensions of the initial contact hole H1 in the first nitride layer 301 and the oxide layer 302 are smaller than the lateral dimensions of the initial contact hole H1 in the second nitride layer 303, that is, the lateral dimensions of the initial contact hole H1 are gradually reduced from top to bottom, which makes the processing more convenient. The lateral dimension of the initial contact hole H1 may be understood as the dimension of the initial contact hole H1 in the horizontal direction X.
It should be noted that, the "vertical direction Y" in the embodiment of the disclosure may be understood as a direction perpendicular to the surface of the silicon substrate 1, for example, the gate dielectric layer 201, the gate layer 202, and the insulating cap layer 203 in the gate stack structure are stacked in the vertical direction Y, and the gate dielectric layer 201 is located on the silicon substrate 1, and the gate dielectric layer 201 is located under the gate layer 202; the "horizontal direction X" may be understood as a direction parallel to the surface of the silicon substrate 1, for example, the initial contact holes H1 are distributed on both sides of the gate structure 2 in the horizontal direction X. The horizontal direction X and the vertical direction Y are perpendicular to each other, and the technical terms are merely for convenience of description and are not meant to be limiting.
In some embodiments, the oxide isolation layer 205 of the gate structure 2 is partially etched during the formation of the initial contact hole H1, i.e., after etching away a portion of the first nitride layer 301 during the formation of the initial contact hole H1, a portion of the oxide isolation layer 205 is also etched away such that a portion of the oxide isolation layer 205 serves as an inner wall of the initial contact hole H1. Of course, in other embodiments, during the process of forming the initial contact hole H1, as shown in fig. 3, the oxide isolation layer 205 of the gate structure 2 may not be etched, but a portion of the first nitride layer 301 may be etched, and a person skilled in the art may adjust the etching range according to the actual situation, for example, according to the size of the lateral dimension of the initial contact hole H1, which is not limited herein.
S140: sidewalls of the oxide layer 302 and the first nitride layer 301 exposed by the initial contact hole H1 are etched to form a contact hole H2, and a lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 is greater than a lateral dimension of the contact hole H2 in the second nitride layer 303.
As shown in fig. 4, the exposed oxide layer 302 of the initial contact hole H1 and the sidewall of the first nitride layer 301 are etched by using an etching process to enlarge the lateral dimension of the initial contact hole H1, so that the height-to-depth ratio of the contact hole H2 is reduced, and the lateral dimension of the contact hole H2 is larger than that of the contact hole H2 in the second nitride layer 303, that is, the inner wall of the contact hole H2 located in the second nitride layer 303 is not etched, so that the contact plug 6 formed later is prevented from being electrically connected with other structures due to the excessive lateral dimension of the contact hole H2 located in the second nitride layer 303, thereby affecting the electrical performance of the semiconductor structure. Meanwhile, since the lateral dimension of the contact hole H2 located in the second nitride layer 303 is inherently large, the contact plug 6 is also easily formed in the contact hole H2.
In some embodiments, as shown in fig. 5, the contact hole H2 includes a recess R in the silicon substrate 1, and the metal silicide layer 5 is located within the recess R.
After etching the oxide layer 302 exposed by the initial contact hole H1 and the sidewall of the first nitride layer 301 to form the contact hole H2, as shown in fig. 4, the source-drain doped region 101 located in the silicon substrate 1 may be continuously etched to form a recess R, as shown in fig. 6, so that the metal silicide layer 5 formed in the subsequent process may be located in the recess R, and the metal silicide layer 5 may be electrically connected to the source-drain doped region 101, so that the contact plug 6 formed in the subsequent process may be electrically connected to the source-drain doped region 101 through the metal silicide layer 5, thereby reducing the contact resistance of the contact plug 6.
S150: a metal silicide layer 5 is formed at the bottom of the contact hole H2.
As described in the above steps, the bottom of the contact hole H2 includes a recess R in the silicon substrate 1, and as shown in fig. 6, a metal silicide layer 5 may be formed in the recess R using a metal silicide process. In some embodiments, the metal elements of the metal silicide layer 5 may include at least one of Co, ni, pt, ti, ta, mo and W, which are capable of forming a stable metal silicide in combination with silicon in the silicon substrate 1, reducing contact resistance with the contact plug 6.
S160: a nitride liner layer 4 is formed on the side wall of the contact hole H2.
As shown in fig. 8, after the metal silicide layer 5 is formed, a nitride liner layer 4 may be formed on the inner wall of the contact hole H2 and the surface of the second nitride layer 303 using a deposition process. The material of the nitride liner layer 4 may be silicon nitride. As shown in fig. 9, the nitride liner layer 4 is etched back to remove the nitride liner layer 4 on the bottom wall of the contact hole H2 and the second nitride layer 303, leaving the nitride liner layer 4 on the side wall of the contact hole H2. As shown in fig. 9, the contact holes H2 are located at two sides of the gate structure 2, and after the contact plugs 6 are formed in the contact holes H2 in the subsequent process, the nitride liner layer 4 can be used as a barrier layer, so that the influence of metal diffusion in the contact plugs 6 on the electrical performance of the gate structure 2 is avoided, and the stability of the semiconductor structure is improved.
In some embodiments, before the nitride liner layer 4 is formed on the sidewall of the contact hole H2, the method further includes: the sidewalls of the oxide layer 302 exposed by the contact hole H2 are nitrided by a far-field plasma nitridation process to form an oxynitride layer 304.
As shown in fig. 7, after the metal silicide layer 5 is formed, the sidewall of the oxide layer 302 exposed by the contact hole H2 may be nitrided by using a far-field plasma nitridation process, so that the characteristics of the oxide layer 302 may be changed, the sidewall may be formed into an oxynitride layer 304, and the properties of the oxynitride layer 304 may be closer to those of the nitride liner layer 4 formed by a subsequent process, so that the nitride liner layer 4 may be formed on the oxynitride layer 304 more stably. At the same time, diffusion of the metal of the contact plug 6 formed later can be further prevented.
In some embodiments, as shown in fig. 4, the oxide isolation layer 205 of the gate structure 2 is partially etched during the formation of the contact hole H2. I.e., the sidewalls of the contact hole H2 include a bare oxide isolation layer 205. The method further comprises, before the formation of the nitride liner layer 4 at the side wall of the contact hole H2: the sidewalls of the oxide layer 302 and the sidewalls of the oxide isolation layer 205 exposed by the contact hole H2 are nitrided by a far-field plasma nitridation process to form an oxynitride layer 304. That is, the oxynitride layer 304 is formed on the entire inner wall of the contact hole H2, and the nitride liner layer 4 formed in the subsequent process can cover the oxynitride layer 304, so that the nitride liner layer 4 formed in the subsequent process can be more stably formed in the contact hole H2.
In some embodiments, during the formation of the contact hole H2, the sidewalls of the contact hole H2 expose the first nitride layer 301 and the oxide layer 302, and before the sidewalls of the contact hole H2 form the nitride liner layer 4, the method further includes: the sidewalls of the oxide layer 302 exposed by the contact hole H2 are nitrided by a far-field plasma nitridation process to form an oxynitride layer 304. That is, the sidewall of one side of the contact hole H2 is covered with the oxynitride layer 304, and the sidewall of the other side is the first nitride layer 301, and the properties of the first nitride layer 301 are similar to those of the nitride liner layer 4, so that the first nitride layer can be stably bonded to the nitride liner layer 4.
S170: a contact plug 6 is formed in the contact hole H2, and the contact plug 6 is electrically connected to the source-drain doped region 101 through the metal silicide layer 5.
As shown in fig. 10, before forming the contact plug 6 in the contact hole H2, the method further includes: forming a diffusion barrier layer 601 covering the nitride liner layer 4 and the metal silicide layer 5 in a conformal manner; a metal layer 602 is formed to cover the diffusion barrier 601 and fill the contact hole H2.
As shown in fig. 10, a diffusion barrier layer 601 may be formed in the contact hole H2 using a deposition process, the diffusion barrier layer 601 serving to prevent diffusion of metal of the contact plug 6, ensuring stability of electrical properties of the semiconductor structure. The diffusion barrier 601 may be a layer or a stack of layers having different materials. In some embodiments, the material of the diffusion barrier layer 601 may be at least one of titanium nitride and tungsten nitride.
After the diffusion barrier layer 601 is formed, a metal layer 602 covering the diffusion barrier layer 601 and filling the contact hole H2 is formed again using a deposition process. The material of the metal layer 602 may include at least one of W, cu and Al to be electrically connected to the source and drain doped region 101.
In summary, in the method for manufacturing a semiconductor structure according to the embodiment of the disclosure, the sidewalls of the oxide layer 302 and the first nitride layer 301 exposed by the initial contact hole H1 are etched to form the contact hole H2, and the lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 is greater than the lateral dimension of the contact hole H2 in the second nitride layer 303, so that the aspect ratio of the contact hole H2 is reduced, the metal silicide layer 5 is easier to form at the bottom of the contact hole H2, the area of the metal silicide layer 5 is larger, and the contact resistance of the contact plug 6 is reduced; since the nitride liner layer 4 is formed on the sidewall of the contact hole H2, the metal diffusion of the contact plug 6 can be prevented, the stability of the semiconductor structure can be improved, and the yield can be improved.
The disclosed embodiments also provide a semiconductor structure, as shown in fig. 10, comprising a silicon substrate 1, a gate structure 2, a dielectric stack 3, a metal silicide layer 5, a nitride liner layer 4, and a contact plug 6.
As shown in fig. 2, the material of the silicon substrate 1 may be monocrystalline silicon, shallow trench isolations 102 are formed on the silicon substrate 1, active regions 103 are disposed between the shallow trench isolations 102, and the gate structure 2 is located in the active regions 103. The active region 103 further has a bit line structure and a word line structure (not shown) therein, and the word line structure and the bit line structure are located at different heights, and the word line structure and the bit line structure are electrically connected to the active region 103.
The gate structure 2 is located on a silicon substrate 1, the silicon substrate 1 comprising source and drain doped regions 101 located on opposite sides of the gate structure 2. As shown in fig. 10, the gate structure 2 includes a gate stack structure, a nitride isolation layer 204 covering sidewalls of the gate stack structure, and an oxide isolation layer 205 covering sidewalls of the nitride isolation layer 204.
With continued reference to fig. 10, the gate stack structure includes a gate dielectric layer 201, a gate layer 202, and an insulating cap layer 203 stacked in order from the surface of the silicon substrate 1. The gate layer 202 may be a stack, including a polysilicon layer and a metal material layer sequentially stacked from the gate dielectric layer 201, or the gate layer 202 is a polysilicon layer or a metal material layer, which is not particularly limited herein. In some embodiments, the metal material layer may include at least one of tungsten, copper, aluminum. In some embodiments, the material of gate dielectric layer 201 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the insulating cap layer 203 may be silicon nitride.
As shown in fig. 10, the nitride spacer 204 covers the sidewalls of the gate stack structure such that the gate stack structure is insulated from other functional layers or structures, and in some embodiments, the material of the nitride spacer 204 may include at least one of silicon nitride and silicon oxynitride. The oxide isolation layer 205 covers the sidewalls of the nitride isolation layer 204, further insulates the gate stack from other functional layers or structures, and protects the gate stack. In some embodiments, the material of oxide isolation layer 205 may include silicon oxide.
As shown in fig. 10, the dielectric stack 3 is located on the silicon substrate 1 and covers the source-drain doped region 101, the dielectric stack 3 includes a first nitride layer 301, an oxide layer 302 and a second nitride layer 303 which are sequentially stacked, as shown in fig. 4, the thickness of the first nitride layer 301 is smaller than that of the second nitride layer 303, and a contact hole H2 penetrating the dielectric stack 3 and exposing the source-drain doped region 101 is provided in the dielectric stack 3, the lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 is larger than the lateral dimension of the contact hole H2 in the second nitride layer 303, so that the height-depth ratio of the contact hole H2 is reduced, and as shown in fig. 5, the bottom of the contact hole H2 further includes a recess R for forming the metal silicide layer 5, the metal silicide layer 5 is more easily formed in the recess R due to the reduced height-depth ratio of the contact hole H2, and the contact resistance of the contact plug 6 is reduced.
As shown in fig. 5 and 10, the metal silicide layer 5 is disposed at the bottom of the contact hole H2, specifically, the metal silicide layer 5 is disposed at the bottom of the contact hole H2, and the bottom of the contact hole H2 is a recess R located in the source-drain doped region 101, that is, the metal silicide layer 5 is disposed in the source-drain doped region 101, so that the formed contact plug 6 can be electrically connected to the source-drain doped region 101.
As shown in fig. 10, a nitride liner layer 4 is disposed on a sidewall of the contact hole H2, and the material of the nitride liner layer 4 may be silicon nitride. The contact plug 6 is disposed in the contact hole H2 having the nitride liner layer 4 as a sidewall, and the contact plug 6 is electrically connected to the source/drain doped region 101 through the metal silicide layer 5.
Since the lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 is larger than the lateral dimension of the contact hole H2 in the second nitride layer 303, the lateral dimension of the contact plug 6 in the first nitride layer 301 and the oxide layer 302 is larger than the lateral dimension thereof in the second nitride layer 303, the contact area of the contact plug 6 and the metal silicide layer 5 is enlarged, and the contact resistance is further reduced.
In some embodiments, as shown in fig. 10, the contact plug 6 includes a diffusion barrier 601 and a metal layer 602. The diffusion barrier 601 conformally covers the nitride liner layer 4 in the contact hole H2, and the metal layer 602 covers the diffusion barrier 601 and fills the contact hole H2. The diffusion barrier layer 601 can prevent diffusion of metal of the contact plug 6, and ensure stability of electrical performance of the semiconductor structure. The diffusion barrier 601 may be a layer or a stack of layers having different materials. The contact plug 6 is electrically connected to the metal silicide layer 5 through the diffusion barrier layer 601, and thus the material of the diffusion barrier layer 601 is a conductive material, for example, the diffusion barrier layer 601 may be at least one of titanium nitride and tungsten nitride.
In some embodiments, the semiconductor structure further comprises an oxynitride layer 304 located between the nitride liner layer 4 and the oxide layer 302 and covering the sidewalls of the oxide layer 302 exposed by the contact holes H2.
In some embodiments, the oxynitride layer 304 is only located between the nitride liner layer 4 and the oxide layer 302, and the first nitride layer 301 is located between the nitride liner layer 4 and the oxide isolation layer 205, i.e. the oxide isolation layer 205 is not exposed during the formation of the initial contact hole H1 and the contact hole H2, but the first nitride layer 301 is exposed.
In other embodiments, as shown in fig. 10, the oxynitride layer 304 is not only located between the nitride liner layer 4 and the oxide layer 302, but also located between the nitride liner layer 4 and the oxide isolation layer 205, i.e. during the formation of the contact hole H2, at least part of the oxide isolation layer 205 is etched away, and the exposed oxide isolation layer 205 can be nitrided simultaneously to form the oxynitride layer 304 when the oxide layer 302 is nitrided by the far-field plasma nitridation process. Since the nitride liner layer 4 is located on the oxynitride layer 304, the bonding of the nitride liner layer 4 and the inner wall of the contact hole H2 is more stable, and at the same time, the oxynitride layer 304 can further prevent the diffusion of the metal of the contact plug 6.
In summary, in the semiconductor structure of the embodiment of the disclosure, since the lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 is greater than the lateral dimension of the contact hole H2 in the second nitride layer 303, the aspect ratio of the contact hole H2 is reduced, so that it is easier to form the metal silicide layer 5 at the bottom of the contact hole H2, and the area of the metal silicide layer 5 is larger, thereby reducing the contact resistance of the contact plug 6; since the nitride liner layer 4 is formed on the sidewall of the contact hole H2, the metal diffusion of the contact plug 6 can be prevented, the stability of the semiconductor structure can be improved, and the yield can be improved.
It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the disclosure. The disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined herein extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:
providing a silicon substrate, wherein a grid structure is arranged on the silicon substrate, and the silicon substrate comprises source and drain doped regions positioned on two opposite sides of the grid structure;
forming a dielectric stack layer covering the source-drain doped region on the silicon substrate, wherein the dielectric stack layer comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially stacked on the source-drain doped region, and the thickness of the first nitride layer is smaller than that of the second nitride layer;
etching the dielectric stack to form an initial contact hole exposing the source-drain doped region, wherein the lateral dimension of the initial contact hole in the first nitride layer and the oxide layer is smaller than the lateral dimension of the initial contact hole in the second nitride layer;
etching sidewalls of the oxide layer and the first nitride layer exposed by the initial contact hole to form a contact hole, wherein a lateral dimension of the contact hole in the first nitride layer and the oxide layer is greater than a lateral dimension of the contact hole in the second nitride layer;
forming a metal silicide layer at the bottom of the contact hole;
forming a nitride liner layer on the side wall of the contact hole;
and forming a contact plug in the contact hole, wherein the contact plug is electrically connected with the source-drain doped region through the metal silicide layer.
2. The method of claim 1, further comprising, prior to forming the nitride liner layer on sidewalls of the contact hole:
nitriding the side wall of the oxide layer exposed by the contact hole by using a far-field plasma nitriding process to form a nitrogen oxide layer;
wherein the nitride liner layer covers the oxynitride layer.
3. The method of claim 1, wherein the gate structure comprises a gate stack structure, a nitride spacer layer covering sidewalls of the gate stack structure, and an oxide spacer layer covering sidewalls of the nitride spacer layer;
the first nitride layer also covers the oxide isolation layer;
the oxide isolation layer is partially etched in the process of forming the initial contact hole;
the oxide isolation layer is partially etched during the formation of the contact hole.
4. The method of claim 3, further comprising, prior to forming the nitride liner layer on sidewalls of the contact hole:
nitriding the side wall of the oxide layer and the side wall of the oxide isolation layer exposed by the contact hole by using a far-field plasma nitriding process to form a nitrogen oxide layer;
wherein the nitride liner layer covers the oxynitride layer.
5. The method of any of claims 1-4, wherein the contact hole comprises a recess in the silicon substrate, the metal silicide layer being located within the recess.
6. The method according to any one of claims 1 to 4, wherein forming the contact plug in the contact hole includes:
forming a diffusion barrier layer covering the nitride liner layer and the metal silicide layer in a conformal manner;
and forming a metal layer which covers the diffusion barrier layer and fills the contact hole.
7. A semiconductor structure, comprising:
a silicon substrate;
the grid structure is positioned on the silicon substrate, and the silicon substrate comprises source-drain doped regions positioned on two opposite sides of the grid structure;
the dielectric stack comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially stacked on the source-drain doped region, wherein the thickness of the first nitride layer is smaller than that of the second nitride layer, and a contact hole exposing the source-drain doped region is formed in the dielectric stack;
the metal silicide layer is arranged at the bottom of the contact hole;
a nitride liner layer arranged on the side wall of the contact hole;
the contact plug is arranged in the contact hole taking the nitride liner layer as the side wall and is electrically connected with the source-drain doped region through the metal silicide layer;
wherein a lateral dimension of the contact plug in the first nitride layer and the oxide layer is greater than a lateral dimension of the contact plug in the second nitride layer.
8. The semiconductor structure of claim 7, further comprising:
and the oxynitride layer is positioned between the nitride liner layer and the oxide layer and covers the side wall of the oxide layer exposed by the contact hole.
9. The semiconductor structure of claim 8, wherein the gate structure comprises a gate stack structure, a nitride isolation layer covering sidewalls of the gate stack structure, and an oxide isolation layer covering sidewalls of the nitride isolation layer;
the oxynitride layer is disposed between the oxide isolation layer and the nitride liner layer.
10. The semiconductor structure of any one of claims 7 to 9, wherein the contact plug comprises:
a diffusion barrier layer conformally covering the nitride liner layer and the metal silicide layer;
and the metal layer covers the diffusion barrier layer and fills the contact hole.
CN202310814986.5A 2023-07-03 2023-07-03 Method for preparing semiconductor structure and semiconductor structure Pending CN116782640A (en)

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