CN116779593A - Alignment measurement mark structure, semiconductor structure and alignment measurement method - Google Patents

Alignment measurement mark structure, semiconductor structure and alignment measurement method Download PDF

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Publication number
CN116779593A
CN116779593A CN202310763471.7A CN202310763471A CN116779593A CN 116779593 A CN116779593 A CN 116779593A CN 202310763471 A CN202310763471 A CN 202310763471A CN 116779593 A CN116779593 A CN 116779593A
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China
Prior art keywords
layer
measurement
mark
measuring
alignment
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Pending
Application number
CN202310763471.7A
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Chinese (zh)
Inventor
杨尚勇
邱杰振
颜天才
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Wuyuan Semiconductor Technology Qingdao Co ltd
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Wuyuan Semiconductor Technology Qingdao Co ltd
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Priority to CN202310763471.7A priority Critical patent/CN116779593A/en
Publication of CN116779593A publication Critical patent/CN116779593A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
    • G03F7/7085—Detection arrangement, e.g. detectors of apparatus alignment possibly mounted on wafers, exposure dose, photo-cleaning flux, stray light, thermal load
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7046—Strategy, e.g. mark, sensor or wavelength selection
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Abstract

The application relates to an alignment measurement mark structure, a semiconductor structure and an alignment measurement method. The alignment measurement mark structure comprises a layer measurement mark and a front layer measurement mark; when the layer measurement mark comprises a first measurement group, the first measurement group comprises a plurality of first measurement units extending along a first direction, the plurality of first measurement units are arranged side by side, and a first interval is reserved between every two adjacent first measurement units; the front layer measurement mark comprises a second measurement set, wherein the second measurement set comprises a plurality of second measurement units extending along the first direction, the plurality of second measurement units are arranged side by side, and a second interval is arranged between every two adjacent second measurement units; when the layer is aligned with the front layer, the front projection of the first measuring unit is positioned in the front projection of the second interval, and the front projection of the second measuring unit is positioned in the front projection of the first interval; when at least one silicon layer exists between the layer measuring mark and the front layer measuring mark in the orthographic projection direction, the alignment measurement under the interval of the thick silicon layer is realized.

Description

Alignment measurement mark structure, semiconductor structure and alignment measurement method
Technical Field
The present application relates to a semiconductor manufacturing technology, and more particularly to an alignment measurement mark structure, a semiconductor structure and an alignment measurement method.
Background
Photolithography is one of the most important and critical process steps in chip fabrication. The photoetching process is to use exposure equipment to provide a light source to expose the circuit pattern on the mask plate to the silicon wafer. As the current chips become more complex, multiple exposure layers are often required on a chip, and certain connection and matching relation exists between circuits of each layer, which requires alignment and measurement of patterns between layers.
In the photolithography process, after the resist is fabricated, exposed and developed, the resist pattern must be aligned with the metal pattern of the previous layer. Currently, alignment measurement is performed by using an overlay mark (overlay mark), a front layer alignment measurement mark (shown in fig. 1 b) is aligned by using a current layer alignment mark (shown in fig. 1 a), measurement is performed by using a lithography alignment measurement machine, and finally, the actual offset of two layers after alignment (shown in fig. 1 c) is accurately measured.
At present, a silicon layer is manufactured by photolithography before a protective layer is formed due to the requirements of manufacturing process conditions. When the silicon layer exceeds a certain thickness, the light source of the photoetching alignment measurement machine cannot pass through the silicon layer, so that the light source can be completely shielded by the silicon layer, and the accurate position of the front layer alignment measurement mark cannot be obtained. In addition, the existing overlay mark is not suitable for the alignment measurement process of the above structure. Therefore, in this case, the existing measurement apparatus and overlay mark cannot accurately measure and calculate the current layer and the previous layer, and thus cannot accurately obtain the offset between the two layers.
Disclosure of Invention
Aiming at least one defect in the related art, the application provides an alignment measurement mark structure, a semiconductor structure and an alignment measurement method, so that alignment measurement under a thick silicon layer can be realized, and the offset between two layers can be accurately obtained.
To this end, a first aspect of the present application provides an alignment measurement mark structure, comprising:
when the layer is measured and marked, the layer comprises a first measuring group, wherein the first measuring group comprises a plurality of first measuring units extending along a first direction, the plurality of first measuring units are arranged side by side, and a first interval is reserved between every two adjacent first measuring units;
the front layer measuring mark comprises a second measuring group, wherein the second measuring group comprises a plurality of second measuring units extending along the first direction, the second measuring units are arranged side by side, and a second interval is reserved between every two adjacent second measuring units;
when the layer is aligned with the front layer, the front projection of the first measuring unit is positioned in the front projection of the second interval, and the front projection of the second measuring unit is positioned in the front projection of the first interval; at least one silicon layer exists between the current layer measuring mark and the front layer measuring mark in the orthographic projection direction.
In some embodiments of the first aspect, the layer-on-layer measurement mark further includes a first main unit extending along a second direction, the second direction being perpendicular to the first direction, the first main unit being connected to a plurality of the first measurement units on one side; the front layer measuring mark also comprises a second main unit extending along the second direction, and the second main unit is connected with a plurality of second measuring units at one side; when the layer is aligned with the front layer, the first main unit and the second main unit are respectively positioned at two sides of the first measuring set and the second measuring set, and the lengths of the first measuring unit and the second measuring unit in the first direction are equal.
In some embodiments of the first aspect, the silicon layer has a thickness of 300 μm or more, and the alignment measurement mark is suitable for use in an alignment measurement process under an infrared light source.
In some embodiments of the first aspect, the widths of the first measuring unit, the second measuring unit, the first interval, and the second interval in the second direction are all a.
In some embodiments of the first aspect, the first main unit and the second main unit each have a width b in the first direction.
In some embodiments of the first aspect, a=1 to 5 μm and b=5 to 10 μm.
In some embodiments of the first aspect, the layer-when measurement mark and the front layer measurement mark form a set of alignment measurement marks, the alignment measurement mark structure includes two sets of alignment measurement marks, and when the front projection surfaces of the layer and the front layer have an X direction and a Y direction perpendicular to each other, the first directions of the two sets of alignment measurement marks are respectively set along the Y direction and the X direction.
A second aspect of embodiments of the present application provides a semiconductor structure provided with an alignment measurement mark structure as described in any of the embodiments of the first aspect above.
In some embodiments of the second aspect, the semiconductor structure comprises:
a semiconductor substrate;
a metal layer formed over the semiconductor substrate, the front layer measurement mark being formed on the metal layer;
the silicon layer is formed on the metal layer, and the thickness of the silicon layer is more than or equal to 300 mu m;
and the protective layer is formed on the silicon layer, and the current layer measuring mark is formed on the protective layer.
A third aspect of the embodiments of the present application provides an alignment measurement method for measuring an alignment mark structure according to any one of the first aspect, the alignment measurement method comprising the steps of:
providing a semiconductor substrate;
forming a metal layer over the semiconductor substrate;
forming the front layer measuring mark on the surface of the metal layer;
forming the silicon layer over the metal layer, the silicon layer having a thickness of 300 μm or more;
forming a protective layer over the silicon layer;
forming the current layer measuring mark on the surface of the protective layer;
and irradiating the metal layer through the protective layer and the silicon layer by adopting an alignment measurement light source, and measuring the offset between the current layer measurement mark and the front layer measurement mark to obtain a measurement result.
In some embodiments of the third aspect, the alignment-measuring light source is an infrared light source.
In some embodiments of the third aspect, post-alignment metrology is performed using a bond alignment overlay tool.
Compared with the prior art, the application has the advantages and positive effects that:
(1) The alignment measurement mark structure provided by at least one embodiment of the application is suitable for alignment measurement of a semiconductor structure with a thick silicon layer at intervals and is suitable for alignment measurement by adopting an infrared light source, and the offset between the current layer pattern and the front layer pattern can be obtained according to the offset between the current layer measurement mark and the front layer measurement mark.
(2) According to the semiconductor structure provided by at least one embodiment of the application, the silicon layer is arranged between the metal layer to be aligned and the protective layer, and the alignment measurement of the two layers is carried out by respectively arranging the front layer measurement mark and the current layer measurement mark on the metal layer to be aligned and the protective layer, so that the alignment measurement can be carried out by adopting an infrared light source, the offset between the two layers can be accurately measured, and the alignment measurement under the condition of spacing a thick silicon layer is realized.
(3) According to the alignment measurement method provided by at least one embodiment of the application, the offset between the two layers can be accurately measured according to the offset between the first measurement unit and the second measurement unit serving as the scales or the offset between the first measurement unit and the second measurement unit, and the alignment measurement under the condition of the silicon layer being spaced is realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1a is a schematic diagram of a conventional overlay measurement mark;
FIG. 1b is a schematic diagram of a prior art overlay measurement mark;
FIG. 1c is a schematic diagram of a prior art alignment of a layer overlay measurement mark with a front layer overlay measurement mark;
FIG. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present application;
FIG. 3a is a schematic diagram illustrating a layer measurement mark in a first direction along a Y direction according to an embodiment of the present application;
FIG. 3b is a schematic view of the front layer measurement marks arranged along the Y direction in the first direction according to an embodiment of the present application;
FIG. 3c is a schematic view of FIG. 3a and FIG. 3b after the layer measurement marks and the front layer measurement marks are fully aligned;
FIG. 3d is a schematic diagram of the current layer measurement mark and the previous layer measurement mark in FIGS. 3a and 3 b;
FIG. 4a is a schematic diagram illustrating a layer measurement mark in a first direction along an X direction according to an embodiment of the present application;
FIG. 4b is a schematic view of the first direction of the front layer measurement marks along the X direction according to an embodiment of the present application;
FIG. 4c is a schematic view of FIG. 4a and FIG. 4b after the layer measurement marks and the front layer measurement marks are fully aligned;
FIG. 5 is a flowchart of an alignment measurement method according to an embodiment of the present application.
In the figure:
101. a semiconductor substrate; 102. a metal layer; 103. a silicon layer; 104. an interlayer dielectric layer; 105. a protective layer; 200. marking when the layer is measured; 210. a first measurement set; 211. a first measurement unit; 212. a first interval; 220. a first main unit; 300. a front layer measurement mark; 310. a second measurement set; 311. a second measurement unit; 312. a second interval; 320. and a second main unit.
Detailed Description
The technical solutions in the embodiments will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is possible for those of ordinary skill in the art to apply the present application to other similar situations according to these drawings without inventive effort. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure. The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the described embodiments of the application can be combined with other embodiments without conflict.
It is to be understood that, although the figures may show a particular order of method steps, the order of the steps may differ from what is depicted. Furthermore, two or more steps may be performed simultaneously or partially simultaneously. Such variations will depend on the software and hardware selected and the designer's choice. All such variations are within the scope of the present disclosure.
For some improved IGBT device structures, as shown in fig. 2, a metal layer 102 is formed on a semiconductor substrate 101 (IGBT wafer), a silicon layer 103 (carrier wafer) is further formed above the metal layer 102, an interlayer dielectric layer 104 is formed between the metal layer 102 and the silicon layer 103, and between the metal layer 102 and the semiconductor substrate 101, and a metal connection portion (not shown in the figure) is provided in the interlayer dielectric layer 104.
In the process of the IGBT device with the above structure, when patterning the silicon layer 103, the protection layer 105 is first formed on the surface of the silicon layer 103, and a desired circuit pattern is formed on the protection layer 105 by a photolithography process. At the same time of patterning, an alignment measurement mark is formed on the protection layer 105, and the surface of the metal layer 102 has been formed with an alignment measurement mark matching the alignment measurement mark on the protection layer 105 in the previous process. The patterns in the two layers are aligned by the alignment measurement marks on the protection layer 105 and the metal layer 102, and the aligned patterns are measured.
However, when the alignment and measurement are performed using the prior art overlay measurement marks and the front layer overlay measurement marks as shown in fig. 1a and 1b, if the thickness of the silicon layer 103 between the protective layer 105 and the front metal layer 102 is thicker, the silicon layer blocks the light source of the photo-alignment overlay measurement machine, and the size and structure of the overlay measurement marks as shown in fig. 1a and 1b are not suitable for the alignment measurement process after penetrating the silicon layer 103, so that accurate measurement and calculation of the offset between the layers of the IGBT device having the above structure cannot be achieved.
To this end, a first aspect of the embodiments of the present application provides an alignment measurement mark structure, which is suitable for alignment measurement of an IGBT device having the above structure.
The alignment measurement mark structure provided by the embodiment of the application comprises a layer measurement mark 200 and a front layer measurement mark 300, wherein when the layer measurement mark 200 is formed in a current layer to be aligned, the front layer measurement mark 300 is formed in a certain previous layer below the current layer. In the structure shown in fig. 2, the current layer is the passivation layer 105, the previous layer is the metal layer 102, and a silicon layer 103 is further disposed between the passivation layer 105 and the metal layer 102, that is, at least one silicon layer 103 is further disposed between the layer measurement mark 200 and the previous layer measurement mark 300 in the forward projection direction of the measurement light source.
As shown in fig. 3a, when the layer measurement mark 200 includes a first measurement set 210, the first measurement set 210 includes a plurality of first measurement units 211 extending along a first direction, the plurality of first measurement units 211 are disposed side by side with a first interval 212 between every two adjacent first measurement units 211.
As shown in fig. 3b, the front layer measurement mark 300 includes a second measurement set 310, where the second measurement set 310 includes a plurality of second measurement units 311 extending along the first direction, the plurality of second measurement units 311 are disposed side by side, and a second interval 312 is between every two adjacent second measurement units 311.
When the protective layer 105 is aligned with the front metal layer 102, the front projection of the first measurement unit 211 is located in the front projection of the second interval 312, and the front projection of the second measurement unit 311 is located in the front projection of the first interval 212. As shown in fig. 3c, after the passivation layer 105 is aligned with the pattern of the metal layer 102, the first measurement unit 211 is inserted into the second space 312 and the second measurement unit 311 is inserted into the first space 212 in the front projection view.
In some cases, if the layer is not completely aligned with the front layer, the layer measurement mark 200 and the front layer measurement mark 300 are misaligned (as shown in fig. 3 d), and the widths of the first measurement unit 211 and the second measurement unit 311 are known in advance, so that the offset of the pattern in the second direction (perpendicular to the first direction) is obtained.
In the alignment measurement mark structure provided in the embodiment of the present application, the first measurement unit 211 and the second measurement unit 311 have a scale function, and the actual offset of the pattern between the two layers can be obtained according to the offset of the first measurement unit 211 and the second measurement unit 311 in the first direction after alignment.
When the front projection surfaces of the layer and the front layer are two-dimensional planes, the two-dimensional planes have an X direction and a Y direction which are perpendicular to each other, and when the layer measuring mark 200 and the front layer measuring mark 300 form a set of alignment measuring marks, the alignment measuring mark structure comprises two sets of alignment measuring marks, and the first directions of the two sets of alignment measuring marks are respectively along the Y direction and the X direction. One set of alignment measurement marks in the two sets is arranged in the Y direction, the second set is arranged in the X direction (as shown in figures 3 a-3 d), and the other set of alignment measurement marks is arranged in the X direction, and the second set is arranged in the Y direction (as shown in figures 4 a-4 c). Therefore, the offset in the X direction and the Y direction can be measured by the alignment measuring marks.
In some embodiments, when the layer measurement mark 200 further includes a first main unit 220 extending along the second direction, the first main unit 220 is connected to a plurality of first measurement units 211 on one side; the front layer measurement mark 300 further includes a second main unit 320 extending along the second direction, where the second main unit 320 is connected to the plurality of second measurement units 311 at one side; when the layer is aligned with the front layer, the first main unit 220 and the second main unit 320 are respectively located at two sides of the first measurement set 210 and the second measurement set 310, and the lengths of the first measurement unit 211 and the second measurement unit 311 in the first direction are equal.
In the above embodiment, the first main unit 220 and the second main unit 320 extend along the second direction and have a certain width in the first direction, and the lengths of the first measurement unit 211 and the second measurement unit 311 are equal. In the case where the front layer is perfectly aligned with the front layer, the patterns of the front layer metrology mark 300 and the front layer metrology mark 200 after perfect alignment should be as shown in fig. 3c and 4c, where the end of the first main unit 220 coincides with the edge of the second main unit 320 at the end of the second gap, and the end of the second main unit 320 coincides with the edge of the first main unit 220 at the first gap. In case that the layer is not aligned with the previous layer, a pattern as shown in fig. 3d may occur, and according to the alignment result, the offset in the first direction may be obtained by measuring the distance of the first measuring unit 211 from the edge of the second main unit 320 or the distance of the second measuring unit 311 from the edge of the first main unit 220.
In some embodiments, in the case where the thickness of the silicon layer 103 between the layer measurement mark 200 and the front layer measurement mark 300 is 300 μm or more, such as in the case of using the conventional photolithography alignment overlay measurement machine, the light source cannot penetrate the silicon layer 103, and thus effective and precise measurement cannot be performed. In this case, an infrared light source may be used for measurement, and the alignment measurement mark structure provided by the embodiment of the application may be suitable for use in an alignment measurement process under the infrared light source.
In some embodiments, the widths of the first measurement unit 211, the second measurement unit 311, the first interval 212, and the second interval 312 in the second direction are all a, i.e., the scale of each set of alignment measurement marks in the second direction is in a unit. The specific value of a can be set according to the actual measurement requirement, for example, when the thickness of the silicon layer 103 is 300 μm or more, the value of a is 1 to 5 μm; alternatively, a=5 μm.
In some embodiments, the widths of the first main unit 220 and the second main unit 320 in the first direction are b, i.e., each set of alignment measurement marks has a scale in the first direction in b. The specific value of b can be set according to the actual measurement requirement, for example, when the thickness of the silicon layer 103 is 300 μm or more, the value of b is 5 to 10 μm; alternatively, b=10 μm.
A second aspect of embodiments of the present application provides a semiconductor structure provided with an alignment measurement mark structure as described in any of the embodiments above.
In some embodiments, the semiconductor structure includes:
a semiconductor substrate 101, i.e., the semiconductor substrate 101 in the drawing;
a metal layer 102 formed on the semiconductor substrate 101, the front layer measurement mark 300 being formed on the metal layer 102;
a silicon layer 103 formed on the metal layer 102, the thickness of the silicon layer 103 being 300 μm or more;
a protective layer 105 formed on the silicon layer 103, and a local layer measurement mark 200 formed on the protective layer 105.
The semiconductor structure in the above embodiment is an intermediate structure in the semiconductor device manufacturing process, which is capable of performing alignment measurement of two layers by disposing the front layer measurement mark 300 and the current layer measurement mark 200 on the metal layer 102 and the protection layer 105 to be aligned, respectively, and performing alignment measurement by using an infrared light source, and can accurately measure the offset between the two layers according to the offset between the first measurement unit 211 and the second measurement unit 311, which are scales, and the offset between the first main unit 220 and the second main unit 320, thereby realizing alignment measurement with the thick silicon layer 103 therebetween.
The silicon layer 103 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate.
The protection layer 105 is made of photoresist material, and after the exposure, the corresponding circuit pattern and the current layer measurement mark 200 will appear in the protection layer 105, and the silicon layer 103 under the protection layer 105 is etched by using the protection layer 105 as a mask to form the corresponding circuit pattern in the silicon layer 103.
In some embodiments, an interlayer dielectric layer 104 is further formed between the semiconductor substrate 101 and the metal layer 102 and between the metal layer 102 and the silicon layer 103, and the interlayer dielectric layer 104 may be made of silicon nitride (SiN), silicon dioxide (SiO 2 ) Silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), and the like. The interlayer dielectric layer 104 may be formed by chemical vapor deposition, such as plasma assisted chemical vapor deposition or low pressure chemical vapor deposition.
A metal connection (not shown) is also formed in the interlayer dielectric layer 104. The metal connection portion is used to connect the semiconductor substrate 101, the metal layer 102, and the silicon layer 103 over the metal layer 102, forming a current path.
A third aspect of the embodiments of the present application provides an alignment measurement method, which uses the alignment measurement mark structure as described in any one of the above. As shown in fig. 5, the alignment measurement method includes the following steps:
s401: providing a semiconductor substrate 101;
s402: forming a metal layer 102 over a semiconductor substrate 101;
s403: forming a front layer measurement mark 300 on the surface of the metal layer 102;
s404: forming a silicon layer 103 over the metal layer 102, the thickness of the silicon layer 103 being 300 μm or more;
s405: forming a protective layer 105 over the silicon layer 103;
s406: forming a layer-wise measuring mark 200 on the surface of the protective layer 105;
s407, the alignment measurement light source is used to irradiate and pass through the protection layer 105, the silicon layer 103 and the surface of the metal layer 102, and the offset between the current layer measurement mark 200 and the previous layer measurement mark 300 is measured to obtain a measurement result.
According to the alignment measurement method provided by the embodiment of the application, the previous layer measurement mark 300 and the current layer measurement mark 200 are respectively arranged on the metal layer 102 and the protection layer 105 to be aligned to perform alignment of two layers, and the offset between the two layers can be accurately measured according to the offset between the first measurement unit 211 and the second measurement unit 311 serving as the scales or the offset between the first measurement unit and the second main unit 220 and the second main unit 320, so that alignment measurement under the condition of spacing the silicon layer 103 is realized.
It will be appreciated that the alignment measurement method provided above only shows steps related to the improvement of the present application, not all the steps, so that the steps are not seamlessly joined, and other necessary steps may be inserted between the two steps as required.
Because the thickness of the silicon layer 103 is greater than or equal to 300 μm, the light source of the existing lithography alignment measurement machine cannot pass through the silicon layer 103 smoothly, and infrared light source is required to be used for measurement, and the offset between the two layers can be measured accurately by matching with the alignment measurement mark in the embodiment of the application.
In some embodiments, a bonding alignment overlay machine may be used instead of the existing photolithography alignment overlay measurement machine, where the light source of the bonding alignment overlay machine is an infrared light source, and may penetrate through the silicon layer 103 with a thickness of 300 μm or more, detect the current layer measurement mark 200 and the front layer measurement mark 300, and obtain the offset of the post-overlay pattern according to the offset of the scale after the alignment of the current layer measurement mark 200 and the front layer measurement mark 300.
In some embodiments, a step of forming the interlayer dielectric layer 104 is further included between step S402 and step S403 and between step S403 and step S404. The interlayer dielectric layer 104 may be made of silicon nitride (SiN), silicon dioxide (SiO 2 ) Silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), and the like. The interlayer dielectric layer 104 may be formed by chemical vapor deposition, such as plasma assisted chemical vapor deposition or low pressure chemical vapor deposition.
Finally, it should be noted that: in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The above embodiments are only for illustrating the technical solution of the present application and not for limiting the same; while the application has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that: modifications may be made to the specific embodiments of the present application or equivalents may be substituted for part of the technical features thereof; without departing from the spirit of the application, it is intended to cover the scope of the application as claimed.

Claims (12)

1. An alignment measurement mark structure, comprising:
when the layer is measured and marked, the layer comprises a first measuring group, wherein the first measuring group comprises a plurality of first measuring units extending along a first direction, the plurality of first measuring units are arranged side by side, and a first interval is reserved between every two adjacent first measuring units;
the front layer measuring mark comprises a second measuring group, wherein the second measuring group comprises a plurality of second measuring units extending along the first direction, the second measuring units are arranged side by side, and a second interval is reserved between every two adjacent second measuring units;
when the layer is aligned with the front layer, the front projection of the first measuring unit is positioned in the front projection of the second interval, and the front projection of the second measuring unit is positioned in the front projection of the first interval; at least one silicon layer exists between the current layer measuring mark and the front layer measuring mark in the orthographic projection direction.
2. The alignment measurement marking structure of claim 1, wherein,
the layer-when measuring mark further comprises a first main unit extending along a second direction, wherein the second direction is perpendicular to the first direction, and the first main unit is connected with a plurality of first measuring units at one side;
the front layer measuring mark also comprises a second main unit extending along the second direction, and the second main unit is connected with a plurality of second measuring units at one side;
when the layer is aligned with the front layer, the first main unit and the second main unit are respectively positioned at two sides of the first measuring set and the second measuring set, and the lengths of the first measuring unit and the second measuring unit in the first direction are equal.
3. The alignment mark structure of claim 1 or 2, wherein the thickness of the silicon layer is 300 μm or more, and the alignment mark is suitable for use in an alignment measurement process under an infrared light source.
4. The alignment measurement mark structure of claim 3, wherein the widths of the first measurement unit, the second measurement unit, the first space, and the second space in the second direction are a.
5. The alignment measurement mark structure of claim 4 wherein the widths of the first and second main units in the first direction are b.
6. The alignment mark structure of claim 5, wherein a=1 to 5 μm and b=5 to 10 μm.
7. The alignment measurement mark structure according to claim 1, wherein the current layer measurement mark and the front layer measurement mark form a set of alignment measurement marks, the alignment measurement mark structure comprises two sets of alignment measurement marks, and when the front projection surfaces of the current layer and the front layer have an X direction and a Y direction which are perpendicular to each other, the first directions of the two sets of alignment measurement marks are respectively along the Y direction and the X direction.
8. A semiconductor structure provided with an alignment measurement mark structure according to any of claims 1-7.
9. The semiconductor structure of claim 8, comprising:
a semiconductor substrate;
a metal layer formed over the semiconductor substrate, the front layer measurement mark being formed on the metal layer;
the silicon layer is formed on the metal layer, and the thickness of the silicon layer is more than or equal to 300 mu m;
and the protective layer is formed on the silicon layer, and the current layer measuring mark is formed on the protective layer.
10. An alignment measurement method, characterized in that the alignment measurement is performed using the alignment measurement mark structure according to any one of claims 1 to 7, the alignment measurement method comprising the steps of:
providing a semiconductor substrate;
forming a metal layer over the semiconductor substrate;
forming the front layer measuring mark on the surface of the metal layer;
forming the silicon layer over the metal layer, the silicon layer having a thickness of 300 μm or more;
forming a protective layer over the silicon layer;
forming the current layer measuring mark on the surface of the protective layer;
and irradiating the metal layer through the protective layer and the silicon layer by adopting an alignment measurement light source, and measuring the offset between the current layer measurement mark and the front layer measurement mark to obtain a measurement result.
11. The alignment measurement method of claim 10, wherein the alignment measurement light source is an infrared light source.
12. The alignment measurement method of claim 11, wherein the post-alignment measurement is performed using a bonding alignment overlay tool.
CN202310763471.7A 2023-06-26 2023-06-26 Alignment measurement mark structure, semiconductor structure and alignment measurement method Pending CN116779593A (en)

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