CN116779591A

CN116779591A - Electronic device

Info

Publication number: CN116779591A
Application number: CN202310256243.0A
Authority: CN
Inventors: F·阿布泽德; P·罗彻
Original assignee: STMicroelectronics Crolles 2 SAS
Current assignee: STMicroelectronics Crolles 2 SAS
Priority date: 2022-03-17
Filing date: 2023-03-16
Publication date: 2023-09-19
Also published as: CN219658705U

Abstract

Embodiments of the present disclosure relate to electronic devices. The electronic device includes a first electronic chip, a second electronic chip, and an interconnect circuit. The first region of the first surface of the first electronic chip is assembled to the third region of the third surface of the interconnect circuit by hybrid bonding. The second region of the second surface of the second electronic chip is intermixed to be assembled to the fourth region of the third surface of the interconnect circuit. In this configuration, the first electronic chip is electrically coupled to the second electronic chip through the interconnect circuit. The first surface of the first electronic chip further includes a fifth region that is not in contact with the interconnect circuitry. The fifth region includes a connection pad electrically connected to the connection substrate mounted with the interconnect circuit through the connection element.

Description

Electronic device

Cross Reference to Related Applications

The present application claims priority from french patent application number 2202331 filed 3/17 at 2022, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law.

Technical Field

The present disclosure relates generally to electronic devices and associated methods of manufacture.

Background

In order to comply with moore's law regarding the juxtaposition or stacking of a plurality of heterogeneous electronic chips per surface area unit, a solution is implemented, for example, using an interconnect substrate on which the chips are assembled, which substrate is provided with Through Silicon Vias (TSVs). However, the use of these through-silicon vias is a problem because it creates limitations, especially in radio frequency applications, and their implementation is expensive. Other limitations of through-silicon vias are related to the loss of available surface area due to the surface covered by the through-silicon vias and the need to adapt the connection pitch to the through-silicon via size.

It is desirable to integrate multiple chips with, for example, heterogeneous functions without using through silicon vias, and at the same time limit manufacturing costs.

There is a need in the art to overcome all or part of the disadvantages of known electronic devices.

Disclosure of Invention

One embodiment provides an electronic device comprising: a first electronic chip and a second electronic chip; and an interconnect circuit comprising a first planar surface; the first region of the first surface of the first electronic chip is assembled to the first region of the first surface of the interconnect circuit by hybrid bonding, the first region of the first surface of the second electronic chip is assembled to the second region of the first surface of the interconnect circuit by hybrid bonding, such that the first electronic chip is electrically coupled to the second electronic chip by the interconnect circuit; the first surface of the first electronic chip further comprises a second area which is not in contact with the interconnect circuitry and comprises at least one connection pad.

One embodiment provides a method of manufacturing an electronic device, the electronic device comprising: a first electronic chip and a second electronic chip; and an interconnect circuit including a first planar surface. The first region of the first surface of the first electronic chip is assembled to the first region of the first surface of the interconnect circuit by hybrid bonding. The first region of the first surface of the second electronic chip is assembled to the second region of the first surface of the interconnect circuit by hybrid bonding such that the first electronic chip is electrically coupled to the second electronic chip by the interconnect lines. In this configuration, the first surface of the first electronic chip further comprises a second region that is not in contact with the interconnect circuit and comprises at least one connection pad.

One embodiment provides a method of manufacturing an electronic device, comprising: providing a first electronic chip, a second electronic chip and a connecting circuit comprising a first planar surface; assembling a first region of the first surface of the first electronic chip to a first region of the first surface of the interconnect circuit by hybrid bonding; and assembling the first region of the first surface of the second electronic chip to the second region of the first surface of the interconnect circuit by hybrid bonding such that the first electronic chip is electrically connected to the second electronic chip through the interconnect circuit; wherein the first surface of the first electronic chip further comprises a second area which is not in contact with the interconnect circuitry and comprises at least one connection pad.

According to one embodiment, the first and second electronic chips and the connection circuit include a substrate and a conductive track. The conductive tracks of the first electronic chip are arranged over a plurality of levels and include at least one connection element arranged on a first surface of the first region of the first electronic chip. The conductive tracks of the second electronic chip are arranged over a plurality of levels and include at least one connection element arranged on a first area of the first surface of the second electronic chip. The conductive track of the interconnect circuit includes at least one connection element disposed on the first region and the second region of the first surface of the interconnect circuit. The connection element of at least one of the conductive tracks of the first area of the first electronic chip is in contact with the connection element of at least one of the conductive tracks of the first area of the interconnect circuit and the connection element of at least one of the conductive tracks of the first area of the second electronic chip is in contact with the connection element of at least one of the conductive tracks of the second area of the interconnect circuit.

According to one embodiment, the first electronic chip includes one or more active or passive components coupled to the conductive tracks of the first electronic chip. The connection elements of the conductive tracks of the second electronic chip are at least partially surrounded by an insulator. The second electronic chip includes one or more active or passive components coupled to the conductive tracks of the second electronic chip, wherein the connection elements of the conductive tracks of the second electronic chip are at least partially surrounded by an insulator. The interconnect circuit includes one or more active or passive components coupled to the conductive track of the interconnect circuit, and the connection element of the conductive track of the interconnect circuit is at least partially surrounded by an insulator.

According to one embodiment, assembling the first region of the first surface of the first electronic chip to the first region of the first surface of the interconnect circuit by hybrid bonding is performed between the connection element of the at least one conductive track of the first region of the first surface of the first electronic chip and the connection element of the at least one conductive track of the first region of the first surface of the interconnect circuit. Additionally or alternatively, the assembly by hybrid bonding is performed between an insulator of the connection element of the at least one conductive track surrounding the first area of the first surface of the first electronic chip and an insulator of the connection element of the at least one conductive track surrounding the first area of the first surface of the interconnect circuit. According to one embodiment, assembling the first region of the second electronic chip to the second region of the interconnect circuit by hybrid bonding is performed between the connection elements of the at least one conductive track of the first region of the first surface of the second electronic chip and the connection elements of the at least one conductive track of the second region of the first surface of the interconnect circuit. Additionally or alternatively, the assembly by hybrid bonding is performed between an insulator of the connection element of the at least one conductive track surrounding the first area of the first surface of the second electronic chip and an insulator of the connection element of the at least one conductive track surrounding the second area of the first surface of the interconnect circuit.

According to one embodiment, the interconnect circuitry has a thickness of less than or equal to 100 microns.

According to one embodiment, the first electronic chip and the second electronic chip are flip chips.

According to one embodiment, an electronic device includes: a connection substrate, one or more connection pads arranged at a level of a contact surface of the connection substrate; one or more electrical coupling elements connect the connection pad(s) of the second region of the first electronic chip to the connection pads of the connection substrate.

According to one embodiment, the first surface of the second electronic chip further comprises: the second region is not in contact with the interconnect circuit and includes at least one connection pad disposed at a level of the first surface of the second electronic chip.

According to one embodiment, the substrate of the interconnect circuit is in contact with a contact surface of the connection substrate.

According to one embodiment, the first electronic chip and the second electronic chip are kept fixed on the transfer substrate before the hybrid bonding assembly step, and the first electronic chip and the second electronic chip are separated from the transfer substrate after the hybrid bonding assembly step.

According to one embodiment, in the connecting step, the at least one connection pad of the second area of the first surface of the first electronic chip is placed in contact with an end of one of the electrical coupling elements by a thermal and/or mechanical treatment, and the electrical coupling element is placed in contact with one of the connection pads of the connection substrate with said treatment.

According to one embodiment, in the connecting step, the at least one connection pad of the second area of the first surface of the second electronic chip is placed in contact with an end of one of the electrical coupling elements by a thermal and/or mechanical treatment, and the other end of the electrical coupling element is placed in contact with another connection pad of the connection substrate with the treatment.

According to one embodiment, prior to the connecting step, the assembly formed by the first electronic chip, the second electronic chip and the interconnect circuit is flipped such that the interconnect circuit is located on the side of the connection substrate and such that the connection pads of the first and second electronic chips are oriented towards the connection substrate.

According to one embodiment, the device comprises a further interconnect circuit comprising a first planar surface and a third electronic chip; the first region of the third electronic chip is assembled to the first region of the first surface of the other interconnect circuit by hybrid bonding; the second region of the first electronic chip is assembled to the second region of the first surface of the further interconnect circuit by hybrid bonding such that the first electronic chip is electrically coupled to the third electronic chip by means of the further interconnect circuit.

Drawings

The above features and advantages and other features and advantages will be described in detail in the remaining disclosure of the particular embodiment by way of example and not limitation, with reference to the accompanying drawings wherein:

FIG. 1 illustrates an electronic device according to one embodiment of the present disclosure;

FIG. 2 illustrates an electronic device according to another embodiment of the present disclosure;

fig. 3 illustrates a method of manufacturing the electronic device of fig. 1 and 2; and

fig. 4 is a simplified enlarged cross-sectional view of a device according to another embodiment of the present disclosure.

Detailed Description

Like features are denoted by like reference numerals throughout the various figures. In particular, structural and/or functional features common to the various embodiments may have the same reference numerals and may have the same structural, dimensional, and material properties.

For clarity, only the steps and elements that are helpful in understanding the embodiments described herein have been illustrated and described in detail. For example, methods of molecular bonding or hybrid bonding or direct bonding between integrated circuits are known to those skilled in the art and will not be described in detail herein.

When referring to two elements connected together, this means that there is no direct connection of any intermediate element other than a conductor, unless otherwise indicated; when referring to two elements coupled together, it is meant that the two elements may be connected or coupled via one or more other elements.

In the following disclosure, unless otherwise specified, when absolute positional qualifiers such as the terms "front", "rear", "upper", "lower", "left", "right", etc., or relative positional qualifiers such as the terms "above", "below", "upper" and "lower", etc., or orientation qualifiers such as "horizontal", "vertical", etc., are referred to the orientations shown in the figures.

Unless otherwise specified, "about," "approximately," and "about" mean within 10%, preferably within 5%.

Fig. 1 illustrates an electronic device 100 according to one embodiment of the present disclosure. The electronic device 100 includes a first electronic integrated circuit chip 110 and a second electronic integrated circuit chip 130. The first chip 110 and the second chip 130 each include, for example, substrates 112, 132; electron tracks 117, 137; and active or passive components 118, 138. The substrates 112, 132 are, for example, semiconductor materials such as silicon. The electronic tracks 117, 137 are for example stacked over a plurality of interconnect layers, and they are coupled to the components 118, 138. In one example, the first chip 110 and the second chip 130 are flip-chip type chips.

The electronic device 100 further comprises, for example, an interconnect integrated circuit 150, which interconnect integrated circuit 150 comprises, for example, a first plane 151. The interconnect circuit 150 includes, for example, a substrate 152, the substrate 152 being, for example, a semiconductor, electronic tracks 156, and optional active or passive components 158. The electron rail 156 is stacked, for example, over a plurality of interconnect layers and is coupled, for example, to a component 158. The electronic track 156 of the interconnect circuit 150 comprises, for example, at least one connection element 153 arranged on the first surface 151 of the interconnect circuit 150. The connection elements 153 are for example flush and have a flat surface and are compatible with mixed bonding or placement in direct contact of one of the connection elements 113.

The first electronic chip 110 comprises a first region 115, e.g. a first surface 116, which first region 115 is in contact with a first region 157 of the surface 151 of the interconnect circuit 150. For example, the first region 115 of the first electronic chip 110 is assembled to the first region 157 of the interconnect circuit 150 by hybrid bonding. The hybrid bond between the two surfaces corresponds to the bond between the metal portions (such as the connection elements) of each surface and the bond between the insulator portions surrounding the metal portions.

The second electronic chip 130 comprises a first region 134, e.g. a first surface 133, which first region 134 is assembled to a second region 154 of the first surface 151 of the interconnect circuit 150, e.g. by hybrid bonding. Thus, the first electronic chip 110 is electrically coupled to the second electronic chip 130, for example, via the interconnect circuit 150. In one example, not shown, this enables a direct electrical connection to be made between interconnect network 117 of chip 110 and interconnect network 137 in chip 130 through conductive tracks 157 of interconnect circuit 150 without passing through active/passive devices 158 of interconnect circuit 150. The first surfaces 116, 133 of the first and second chips 110, 130 are, for example, located on the same horizontal plane. The first chip 110 and the second chip 130 have, for example, the same height, and each chip 110, 130 comprises, for example, a second surface opposite to their first surface, the second surfaces of the first chip 110 and the second chip 130 being, for example, located on the same horizontal plane. However, the first chip 110 and the second chip 130 may have different heights from each other. Due to the bonding, the first chip 110 and the second chip 130 are rigidly attached to the connection circuit 150. This allows manipulation of the assembly created by hybrid bonding.

The electronic track 117 of the first electronic chip 110 comprises, for example, at least one connection element 113, the at least one connection element 113 being arranged on the first surface 116 of the first region 115 of the first electronic chip. The connection elements 113 are for example flush with the surface and allow contact from outside the chip. The electronic track 137 of the second electronic chip 130 comprises, for example, at least one connection element 135 arranged on the first surface 133 of the first region 134 of the first electronic chip 130. The electronic chip 156 of the interconnect circuit 150 comprises, for example, at least one connection element 155 arranged on the first surface 151 of the interconnect circuit 150. The connection elements 155 are, for example, flush and have a flat surface and are compatible with hybrid bonding or direct placement contact of one of the connection elements 135 of the second chip 130. The connection elements 113, 135 of the conductive tracks of the first and second electronic chips 110, 130 and the connection elements 153, 155 of the interconnect circuit 150 are for example at least partially surrounded by an insulator. In one example, the insulator is the same for the first chip 110 and the second chip 130 and the interconnect circuit 150. This allows for optimal hybrid bonding. The insulator is, for example, silicon oxide or a low dielectric constant (low-k) insulator.

The connection elements 113, 135, 153 and 155 are, for example, connection pads and/or planar conductive surfaces and/or surfaces prepared by surface preparation, and are therefore suitable for hybrid bonding. The surface preparation step comprises, for example, chemical mechanical polishing and/or cleaning and/or chemical surface activation for improving its adhesion.

According to one embodiment, assembling the first region 115 of the first surface 116 of the first electronic chip 110 to the first region 157 of the first surface 151 of the interconnect circuit 150 by hybrid bonding is performed between the connection elements 113 of the at least one conductive track of the first region 115 of the first surface 116 of the first electronic chip 110 and the connection elements 153 of the at least one conductive track of the first region 157 of the first surface of the interconnect circuit 150. Hybrid bonding is performed, for example, between the insulator of the connection element 113 of the at least one conductive track 117 surrounding the first region 115 of the first surface 116 of the first electronic chip 110 and the insulator of the connection element 153 of the at least one conductive track surrounding the first region 157 of the first surface 151 of the interconnect circuit 150. For example, the insulator is prepared prior to hybrid bonding. The preparation may include chemical mechanical polishing and/or cleaning and/or chemical surface activation to improve its adhesion.

According to one example, assembling the first region 132 of the second electronic chip 130 to the second region 154 of the interconnect circuit 150 by hybrid bonding is performed between the connection element 135 of the at least one conductive track of the first region 134 of the first surface 133 of the second electronic chip 130 and the connection element 155 of the at least one conductive track of the second region 154 of the first surface of the interconnect circuit 150. Hybrid bonding is performed, for example, between the insulator surrounding the connection element 135 and the insulator of the connection element 155 surrounding the at least one conductive track of the second region 154 of the first surface 151 of the interconnect circuit 150.

The use of hybrid bonding enables reliable and high quality contacts to be created.

Such an electronic device 100 enables connection of two chips having, for example, heterogeneous functions without using through holes. The interconnect circuit 150 of fig. 1 does not require more chips than the two chips 110, 130, and this enables limiting the manufacturing costs.

The first surface 133 of the second electronic chip 130 comprises, for example, a second region 136, which second region 136 is not in contact with the interconnect circuit 150 and comprises, for example, a plurality of connection pads 131. In one example, a single connection pad 131 may be envisaged. The connection pad(s) 131 are coupled to the track 137, for example. The connection pads 131 include, for example, one or more barrier layers, such as, for example, titanium nitride and/or tantalum nitride. In one example, connection pad 131 is similar to connection pad 111.

According to the example of fig. 1, the electronic device 100 optionally comprises a connection substrate 180, the connection substrate 180 comprising on a contact surface 181, for example, connection pads (not shown), for example, connection pads 111, 131 similar to the first or second electronic chip 110, 130. The connection pads of the substrate 180 are coupled to, for example, conductive tracks (not shown) arranged, for example, in a wiring substrate 182 of the connection substrate 180. The electrical coupling element 119 connects, for example, the connection pads 111, 131 of the first and/or second electronic chip 110, 130 with the connection pads of the connection substrate 180. The electrical coupling element 119 is, for example, one or more conductive balls. In another example, the electrical coupling element 119 comprises copper pillars or micro bumps arranged on connection pads (under bump metallization layer UBM) at the chip surface, forming solder pads that can be soldered to connection pads provided at the surface of the substrate 180. In one example, the coupling element 119 is formed by welding (e.g., by hot pressing or by heat treatment) between one or more conductive balls and a copper pillar.

In one example, not shown, a protective material (underfill) is implemented between the first chip 110 and the same connection substrate 180. Underfill is present, for example, in the space 160 included between the electrical coupling elements 119 and/or in the space 162 between the surface 116 and the surface 181. The proportion of underfill used is application dependent and can be estimated by one skilled in the art in seeking a compromise between, for example, mechanical robustness and thermal performance. For example, after the application of the liquid, the underfill is hardened by ultraviolet treatment and/or heat treatment.

In the example of fig. 1, the semiconductor substrate 152 of the interconnect circuit 150 is in contact with the contact surface 181 of the connection substrate 180. This enables the stability of the device 100 to be ensured.

It should be noted that mounting the rear surface of the semiconductor substrate 152 of the interconnect circuit 150 to the front surface of the connection substrate 180 does not mean that a direct electrical connection is made between the interconnect circuit 150 and the connection substrate 180. The electrical connection (for signals and power) of the interconnect circuit 150 to the connection substrate 180 is made through one or more of the first and second electronic chips 110, 130.

Further, it should be noted that the interconnect circuit 150 is not in electrical contact with, for example, the connection substrate 180. In practice, only the semiconductor substrate 152 of the interconnect circuit 150 is in contact with, for example, the connection substrate 180.

Fig. 2 illustrates an electronic device 200 according to another embodiment of the present disclosure.

Electronic device 200 is similar to device 100 except that second chip 130 does not exceed the width of interconnect circuit 150. In the example of fig. 2, the second electronic chip 130 does not include the second region 136 and does not include the connection pad 131 either. Accordingly, the second electronic chip 130 is not soldered or coupled to the connection substrate 180.

The connection substrate 180 is not illustrated in fig. 2, but may be present as in the device 100 of fig. 1 and coupled to the first chip 110. The devices 100, 200 of fig. 1 and 2 may also not include the substrate 180, and the connection pads 111, 131 may be coupled to other circuits, for example, by connection lines.

Fig. 3 illustrates a method of manufacturing the electronic device of fig. 1 and 2.

At step 302 (providing interconnect circuitry), the connection circuitry 150 is provided.

At step 304 (first and second chips are provided on a transfer substrate), a first electronic chip 110 and a second electronic chip 130 are provided.

At optional step 306 (first and second chips are secured to a transfer substrate by molding), first electronic chip 110 and second electronic chip 130 are held, for example, secured side-by-side to the transfer substrate (not shown). This step may be performed, for example, by depositing the first chip 110 and the second chip 130 on a transfer substrate, and then by depositing a molding material to hold the two chips in place after hardening.

At step 308 (molecular bonding of the first and second chips on the interconnect circuit), the first chip 110 and the second chip 130 are assembled to the interconnect circuit 150 by hybrid bonding.

At optional step 310 (removal of the transfer substrate), the transfer substrate is separated from the first and second electronic chips 110, 130, for example by a laser or thermal or mechanical separation process, depending on the temporary bonding material under consideration.

At optional step 312 (flip-chip assembly of the first chip, the second chip and the interconnect circuit), the assembly formed by the first and second electronic chips 110, 130 molecularly bonded to the interconnect circuit 150 is flipped.

At optional step 314 (connecting the contact pads of the first chip with the contact elements of the connection substrate), the connection pads 111, 131 of the respective first and second electronic chips 110, 130 are contacted with the coupling element 119 by soldering or hot-pressing or heat treatment, wherein the coupling element itself is contacted with the corresponding connection pads of the connection circuit 180.

Such a method enables limiting manufacturing costs with parallel processing of the assembly, thereby further improving assembly accuracy.

Fig. 4 shows a simplified enlarged cross-sectional view of a device 100 according to another embodiment of the present disclosure. In the example of fig. 4, the first and second electronic chips 110, 130 and the interconnect circuit 150 are, for example, similar to those of fig. 1 or fig. 2. The view of fig. 4 focuses on the interface between the first chip 110 and the interconnect circuit 150.

In the example of fig. 4, the rails 117 of the first chip 110 are coupled or connected to the connection pads 111 of the area 114 of the first surface 116, for example, and to the connection elements 113 of the area 115 of the first surface 116.

The connection pads 111 comprise, for example, one or more barrier layers (not shown), such as, for example, titanium nitride and/or tantalum nitride. The insulator layer 402 partially covers, for example, the surface of the connection pads 111 arranged towards the electrical coupling element 119, while leaving, for example, an opening with the coupling element 119 arranged thereon.

At the level of the first region 115 of the first chip 110, at least one connection element 113 is for example flush with the surface and can be brought into contact with a corresponding connection element 153 of the interconnect circuit 150 arranged directly opposite.

Accordingly, the surface 116 of the chip 110 includes connection pads 111 capable of being connected with coupling elements (e.g., balls or pillars) and connection elements 113 capable of being in direct contact with corresponding connection elements 153 of the interconnect circuit 150 by hybrid bonding.

For example, a similar arrangement is achieved between the second chip 130 and the interconnect circuit 150.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined and that other variations may be implemented by those skilled in the art. In particular, one skilled in the art can implement more than 2 electronic chips so that they are assembled to the same interconnect circuit by hybrid bonding while being electrically connected together. In another case, the number of electronic chips is greater than 2, and they are assembled in pairs into a chain with different interconnect circuits between each assembled chip pair.

In one example, the device includes, for example, another interconnect circuit including the first planar surface and the third electronic chip. In this example, the first region of the third electronic chip is assembled to the first region of the first surface of the other interconnect circuit by hybrid bonding. In this example, the second region 114 of the first electronic chip is assembled to the second region of the first surface of the other interconnect circuit by hybrid bonding such that the first electronic chip is electrically connected to the third electronic chip by the other interconnect line. Such an example enables easy interconnection of multiple chips with several functions without the use of vias.

Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art.

Claims

1. An electronic device, comprising:

a first electronic chip having a first surface including a first region;

a second electronic chip having a second surface including a second region; and

an interconnect circuit including a third surface including a third region and a fourth region;

wherein the first region of the first surface of the first electronic chip is assembled to the third region of the third surface of the interconnect circuit by hybrid bonding,

wherein the second region of the second surface of the second electronic chip is assembled to the fourth region of the third surface of the interconnect circuit by hybrid bonding;

wherein the first electronic chip is electrically coupled to the second electronic chip through the interconnect circuitry; and

wherein the first surface of the first electronic chip further comprises a fifth region, which is not in contact with the interconnect circuit and comprises at least one connection pad.

2. The device of claim 1:

wherein the first and second electronic chips and the interconnect circuitry each comprise a substrate and a conductive track;

wherein the conductive tracks of the first electronic chip are arranged over a plurality of levels and comprise at least one connection element arranged on the first surface of the first area of the first electronic chip;

wherein the conductive tracks of the second electronic chip are arranged over a plurality of levels and comprise at least one connection element arranged on the second area of the second surface of the second electronic chip; and

wherein the conductive track of the interconnect circuit comprises at least one connection element arranged on the third and fourth areas of the third surface of the interconnect circuit;

wherein the connection element of at least one of the conductive tracks of the first region of the first electronic chip is in contact with the connection element of at least one of the conductive tracks of the third region of the interconnect circuit; and

wherein the connection element of at least one of the conductive tracks of the second region of the second electronic chip is in contact with the connection element of at least one of the conductive tracks of the fourth region of the interconnect circuit.

3. The device of claim 2, wherein:

the first electronic chip includes one or more active or passive components coupled to conductive tracks of the first electronic chip;

the connection elements of the conductive tracks of the first electronic chip are at least partially surrounded by an insulator;

the second electronic chip includes one or more active or passive components coupled to conductive tracks of the second electronic chip;

the connection elements of the conductive tracks of the second electronic chip are at least partially surrounded by an insulator;

the interconnect circuit includes one or more active or passive components coupled to a conductive track of the interconnect circuit; and

the connection element of the conductive track of the interconnect circuit is at least partially surrounded by an insulator.

4. The device of claim 3, wherein assembling the first region of the first surface of the first electronic chip to the third region of the third surface of the interconnect circuit by hybrid bonding is performed by:

a connection element of at least one of the conductive tracks of the first region of the first surface of the first electronic chip and a connection element of at least one of the conductive tracks of the third region of the third surface of the interconnect circuit; and

an insulator of a connection element of the at least one of the conductive tracks surrounding the first region of the first surface of the first electronic chip and an insulator of a connection element of the at least one of the conductive tracks surrounding the third region of the third surface of the interconnect circuit.

5. The device of claim 3, wherein the assembling of the second region of the second electronic chip to the fourth region of the interconnect circuit by hybrid bonding is performed by:

a connection element of at least one of the conductive tracks of the second area of the second surface of the second electronic chip and a connection element of at least one of the conductive tracks of the fourth area of the third surface of the interconnect circuit; and

an insulator of a connection element of the at least one of the conductive tracks of the second area surrounding the second surface of the second electronic chip and an insulator of a connection element of the at least one of the conductive tracks of the fourth area surrounding the third surface of the interconnect circuit.

6. The device of claim 1, wherein the interconnect circuitry has a thickness of less than or equal to 100 microns.

7. The device of claim 1, wherein the first electronic chip and the second electronic chip are flip chips.

8. The device of claim 1, wherein the electronic device further comprises:

a connection substrate comprising one or more connection pads arranged at a level of a contact surface of the connection substrate; and

and an electrical coupling element connecting the connection pads of the fifth region of the first electronic chip to the connection pads of the connection substrate.

9. The device of claim 8, wherein the second surface of the second electronic chip further comprises: a sixth region not in contact with the interconnect circuit and comprising at least one connection pad arranged at a level of the second surface of the second electronic chip.

10. The device of claim 8, wherein the substrate of the interconnect circuit is mounted to the contact surface of the connection substrate.

11. The device of claim 10, wherein the substrate of the interconnect circuit is a semiconductor material.

12. The device of claim 11, wherein the contact surface mounting the substrate of the interconnect circuit to the connection substrate does not form a direct electrical connection between the interconnect circuit and the connection substrate.

13. The device of claim 1, further comprising:

another interconnect circuit including another surface and a third electronic chip;

wherein a region of the third electronic chip is assembled to a first another region of the another surface of the another interconnect circuit by hybrid bonding;

wherein the fifth region of the first electronic chip is assembled to a second other region of the other surface of the other interconnect circuit by hybrid bonding,

wherein the first electronic chip is electrically coupled to the third electronic chip through the further interconnect circuit.

14. A method of manufacturing an electronic device, comprising:

providing a first electronic chip having a first surface, the first surface including a first region and a fifth region;

providing a second electronic chip having a second surface, the second surface including a second region;

providing a connection circuit having a third surface, the third surface comprising a third region and a fourth region;

assembling the first region of the first surface of the first electronic chip to the third region of the third surface of the interconnect circuit by hybrid bonding;

assembling the second region of the second surface of the second electronic chip to the fourth region of the third surface of the interconnect circuit by hybrid bonding;

wherein the fifth region of the first surface of the first electronic chip is not in contact with the interconnect circuit and includes at least one connection pad.

15. The method of claim 14, wherein hybrid bonding the first region of the first surface of the first electronic chip to the third region of the third surface of the interconnect circuit comprises:

bonding connection elements of the conductive tracks of the first electronic chip and connection elements of the conductive tracks of the interconnect circuit; and

an insulator surrounding a conductive track of the first electronic chip is engaged with an insulator surrounding a conductive track of the interconnect circuit.

16. The method of claim 14, wherein hybrid bonding the second region of the second surface of the second electronic chip to the fourth region of the third surface of the interconnect circuit comprises:

bonding the connection elements of the conductive tracks of the second electronic chip and the connection elements of the conductive tracks of the interconnect circuit; and

an insulator surrounding a conductive track of the second electronic chip is engaged with an insulator surrounding a conductive track of the interconnect circuit.

17. The method of claim 14, wherein the interconnect circuitry has a thickness of less than or equal to 100 microns.

18. The method of claim 14, wherein the first electronic chip and the second electronic chip are flip chips.

19. The method of claim 14, further comprising:

providing a connection substrate comprising connection pads arranged at a level of a contact surface of the connection substrate;

the connection pads of the fifth region of the first electronic chip are connected to the connection pads of the connection substrate using an electrical coupling element.

20. The method of claim 19, further comprising mounting a substrate of the interconnect circuit to the contact surface of the connection substrate.

21. The method of claim 20, wherein the substrate of the interconnect circuit is made of a semiconductor material.

22. The method of claim 21, wherein the mounting the substrate of the interconnect circuit to the contact surface of the connection substrate does not form a direct electrical connection between the interconnect circuit and the connection substrate.

23. The method of claim 14, further comprising: before the hybrid bonding, the first electronic chip and the second electronic chip are kept fixed on a transfer substrate, the hybrid bonding is performed with the first electronic chip and the second electronic chip fixed on the transfer substrate, and after the hybrid bonding, the first electronic chip and the second electronic chip are separated from the transfer substrate.

24. The method of claim 14, further comprising:

placing connection pads of the fifth region of the first surface of the first electronic chip in contact with ends of an electrical coupling element by thermal and/or mechanical treatment; and

the other end portion of the electric coupling element is placed in contact with a connection pad of a connection substrate on which the interconnect circuit is mounted by heat treatment and/or mechanical treatment.

25. The method of claim 24, further comprising:

placing a connection pad of a sixth area of the second surface of the second electronic chip in contact with an end of an electrical coupling element by heat treatment and/or mechanical treatment; and

the other end portion of the electric coupling element is placed in contact with another connection pad of the connection substrate on which the interconnect circuit is mounted by heat treatment and/or mechanical treatment.

26. The method of claim 24, further comprising: before the connecting step, an assembly formed by the first electronic chip, the second electronic chip and the interconnect circuit is flipped such that the interconnect circuit faces the connection substrate and the connection pads of the first electronic chip and the second electronic chip are oriented towards the connection substrate.