CN116779551A - Integrated packaging structure of power module and integrated packaging method thereof - Google Patents

Integrated packaging structure of power module and integrated packaging method thereof Download PDF

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Publication number
CN116779551A
CN116779551A CN202310420736.3A CN202310420736A CN116779551A CN 116779551 A CN116779551 A CN 116779551A CN 202310420736 A CN202310420736 A CN 202310420736A CN 116779551 A CN116779551 A CN 116779551A
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China
Prior art keywords
layer
substrate
power
electrode plate
metal
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CN202310420736.3A
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Chinese (zh)
Inventor
黄海波
崔守俊
陈立国
索旭
梅世亮
姜德胜
杨渊智
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Suzhou University
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Suzhou University
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Priority to CN202310420736.3A priority Critical patent/CN116779551A/en
Publication of CN116779551A publication Critical patent/CN116779551A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Abstract

The application provides an integrated packaging structure and an integrated packaging method of a power module, wherein the integrated packaging structure comprises a metal core substrate, a plastic sealing layer, a semiconductor IC and a circuit layer substrate, the metal core substrate comprises a metal base and a resin insulating layer, the semiconductor IC comprises a power IC and a non-power IC which are respectively positioned at the upper side and the lower side of the circuit layer substrate, the power IC and the non-power IC are electrically connected with the circuit layer substrate, a first conductive through hole is arranged in the resin insulating layer, a first electrode plate and a second electrode plate are respectively arranged at two ends of the first conductive through hole, the first electrode plate and the second electrode plate are respectively embedded into the resin insulating layer, one surface of the first electrode plate is exposed outside, one surface of the second electrode plate is exposed in the closed space, and the second electrode plate is electrically connected with the circuit layer substrate. The application enhances the mechanical reliability of power connection, eliminates the external pins of the electronic package, and is beneficial to the integrated development of the package.

Description

Integrated packaging structure of power module and integrated packaging method thereof
[ field of technology ]
The application relates to an integrated packaging structure of a power module and an integrated packaging method thereof.
[ background Art ]
The hybrid integrated circuit is widely applied to land, sea, air and heaven fields and covers communication, computer and other electronic systems of spaceflight, aviation, boats and the like by the obvious advantages of high density, high performance, high reliability, light weight, small volume and the like and the important functions exerted in the whole system. The current situation of the domestic power integrated circuit can not meet the time development demands of modern hybrid integrated circuits such as high power, high reliability, high density, miniaturization, low cost and systemization.
[ application ]
The application aims to provide an integrated packaging structure of a power module and a testing method thereof, which not only enhance the mechanical reliability of power connection, but also eliminate external pins of electronic packaging, greatly reduce the packaging height and facilitate the integrated development of packaging.
In order to achieve one of the above objects, the present application provides an integrated package structure of a power module, wherein the integrated package structure includes a metal core substrate, a plastic layer forming an enclosed space with the metal core substrate, a semiconductor IC and a circuit layer substrate both located in the enclosed space, the metal core substrate includes a metal base and a resin insulation layer surrounding a portion of the periphery of the metal base, the semiconductor IC includes a power IC and a non-power IC located on upper and lower sides of the circuit layer substrate, respectively, the power IC and the non-power IC are electrically connected with the circuit layer substrate, a first conductive through hole is provided in the resin insulation layer, one end of the first conductive through hole is provided with a first electrode pad, the other end of the first conductive through hole is provided with a second electrode pad, both the first electrode pad and the second electrode pad are embedded in the resin insulation layer, one surface of the first electrode pad is exposed to the outside, one surface of the second electrode pad is exposed to the outside, both the power IC and the non-power IC is electrically connected with the circuit layer substrate.
As a further improvement of an embodiment of the present application, the resin insulation layer includes a tile layer surrounding a part of an outer periphery of the metal base, a first stage layer provided above the tile layer, and a second stage layer provided above the first stage layer, an inner peripheral dimension of the first stage layer being smaller than an inner peripheral dimension of the second stage layer.
As a further improvement of an embodiment of the present application, the first conductive via includes a first portion disposed within the tile layer and a second portion disposed within the first step layer.
As a further improvement of an embodiment of the present application, the tile layer forms an enclosed space, the metal substrate includes a body located in the enclosed space and a plurality of bosses extending from the body into the enclosed space, and the power IC is located on the plurality of bosses.
As a further improvement of an embodiment of the present application, the integrated package structure further includes a plurality of flexible pads, two ends of which are respectively abutted against the resin insulation layer and the circuit layer substrate, and a certain distance is provided between the flexible pads and the power IC, and the circuit layer substrate is disposed on the resin insulation layer through the flexible pads to form upper and lower package layers
As a further improvement of an embodiment of the present application, the circuit layer substrate is provided with a second conductive via to construct an internal power loop of the upper and lower package layers.
As a further improvement of one embodiment of the present application, the metal substrate is a ceramic particle reinforced metal matrix composite.
As a further improvement of an embodiment of the present application, the resin insulation layer is made of ceramic powder reinforced epoxy resin material.
As a further improvement of an embodiment of the present application, the integrated package structure further includes a metal layer contacting the non-power IC, a heat spreader contacting the metal layer and exposed to the outside, and a heat dissipation pad contacting the metal substrate and exposed to the outside, wherein one side of the heat spreader is in contact with the resin insulation layer, and an outer periphery of the heat dissipation pad is in contact with the resin insulation layer.
In order to achieve the above another object, the present application further provides an integrated packaging method of a power module, where the integrated packaging method includes the following steps:
s101: the resin insulating layer wraps part of the metal substrate;
s102: preparing a first conductive through hole in the resin insulating layer;
s103: embedding a first electrode plate and a second electrode plate in the resin insulating layer, wherein the first electrode plate and the second electrode plate are positioned at two ends of the first conductive through hole;
s104: mounting a power IC on the metal substrate;
s105: mounting a circuit layer substrate on the resin insulation layer, electrically connecting the circuit layer substrate with the power IC, and electrically connecting the circuit layer substrate with the second electrode sheet;
s106: mounting a non-power IC above the circuit layer substrate, and electrically connecting the circuit layer substrate with the non-power IC;
s107: and preparing a plastic sealing layer, and forming a closed space by the plastic sealing layer, the metal substrate and the resin insulating layer.
As a further improvement of an embodiment of the present application, the first electrode tab and the second electrode tab are embedded in the resin insulation layer by an etching process, and the first conductive via is formed by a deposition, pitting process.
Compared with the prior art, the application has the following beneficial effects: through set up first conductive through-hole in the resin insulating layer is inside, and all imbeds first electrode slice and second electrode slice in the resin insulating layer, the one side of first electrode slice exposes in the outside, the one side of second electrode slice exposes in the enclosure space, so set up, both strengthened the mechanical reliability of power connection, eliminated the outside pin of electronic package simultaneously again, greatly reduced encapsulation height, be favorable to the integrated development of encapsulation.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
fig. 1 is a schematic diagram of an integrated package structure of a power module according to an embodiment of the application.
Fig. 2 is a schematic diagram of a metal substrate in the integrated package structure of the power module of fig. 1.
Fig. 3 is a schematic view of a metal substrate and a resin insulation layer in the integrated package structure of the power module of fig. 1.
Fig. 4 is a schematic diagram of a metal base, a resin insulation layer, a flexible pad and a circuit layer substrate in the integrated package structure of the power module of fig. 1.
Fig. 5 is a flowchart of an integrated packaging method of a power module according to an embodiment of the present application.
[ detailed description ] of the application
In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to the appended drawings. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "comprising" and "having" and any variations thereof herein are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1 to 5, the embodiment of the present application provides an integrated package structure of a power module, wherein the integrated package structure includes a metal core substrate, a plastic layer 20 forming an enclosed space with the metal core substrate, and a semiconductor IC and a circuit layer substrate 10 both located in the enclosed space, the metal core substrate includes a metal substrate 1 and a resin insulation layer surrounding a portion of the periphery of the metal substrate 1, the semiconductor IC includes a power IC13 and a non-power IC12 located on the upper and lower sides of the circuit layer substrate 10 respectively, the power IC13 and the non-power IC12 are electrically connected with the circuit layer substrate 10, a first conductive through hole 7 is disposed in the resin insulation layer, one end of the first conductive through hole 7 is provided with a first electrode pad 81, the other end of the first conductive through hole 7 is provided with a second electrode pad 82, both the first electrode pad 81 and the second electrode pad 82 are embedded in the resin insulation layer, one surface of the first electrode pad 81 is exposed to the outside, one surface of the second electrode pad 82 is exposed to the enclosed space, and the second electrode pad 82 is connected with the circuit layer 10.
In the preferred embodiment, through setting up first conductive through hole 7 in the resin insulating layer inside, and with first electrode piece 81 and second electrode piece 82 all imbeds in the resin insulating layer, the one side of first electrode piece 81 exposes in the outside, and the one side of second electrode piece 82 exposes in the enclosure space, so set up, both strengthened the mechanical reliability of power connection, eliminated the outside pin of electronic package simultaneously again, greatly reduced encapsulation height, be favorable to the integrated development of encapsulation.
Further, the resin insulation layer includes a tile layer 4 surrounding a part of the outer periphery of the metal base 1, a first step 5 provided above the tile layer 4, and a second step 6 provided above the first step 5, and an inner peripheral dimension of the first step 5 is smaller than an inner peripheral dimension of the second step 6.
The first conductive via 7 comprises a first portion disposed within the layup 4 and a second portion disposed within the first level 5.
The lay-flat layer 4 forms an enclosed space, the metal substrate 1 comprises a body located in the enclosed space and a plurality of bosses 2 extending from the body into the enclosed space, and the power IC13 is located on the plurality of bosses 2.
The integrated package structure further comprises a plurality of flexible cushion blocks 9 with two ends respectively abutted against the resin insulation layer and the circuit layer substrate 10, and the flexible cushion blocks 9 and the power ICs 13 are spaced at a certain distance, and the circuit layer substrate 10 is arranged on the resin insulation layer through the flexible cushion blocks 9 to form an upper package layer and a lower package layer
The circuit layer substrate 10 is provided with a second conductive via 11 to construct an internal power loop of the upper and lower package layers.
Preferably, the metal substrate 1 is a ceramic particle reinforced metal matrix composite. Specifically, in the present embodiment, the metal base 1 employs copper diamond. Of course, other materials may be used for the metal substrate 1.
The resin insulating layer is made of ceramic powder reinforced epoxy resin material. In particular, in this embodiment, the resin insulation layer is made of aluminum nitride, and the material has good thermal conductivity and good insulation performance. Of course, other materials such as ceramic powder reinforced epoxy resin may be used for the resin insulating layer.
The integrated package structure further comprises a metal layer 19 in contact with the non-power IC12, a radiator 21 in contact with the metal layer 19 and exposed outside, and a radiating pad 3 in contact with the metal substrate 1 and exposed outside, wherein one side of the radiator 21 is abutted against the resin insulation layer, and the periphery of the radiating pad 3 is abutted against the resin insulation layer.
Preferably, the heat dissipation pad 3 is made of copper or tin. The material of the first electrode tab 81 and the second electrode tab 82 is copper.
A heat dissipation pad 3 is fused on one side of the metal substrate 1 without the boss 2 in a hot pressing way; preparing a resin insulation layer according to the sequence of 'flat layer 4-first stage layer 5-second stage layer 6', wherein first conductive through holes 7 are arranged in the flat layer 4 and the first stage layer 5 of the resin insulation layer; the flat layer 4 of the resin insulating layer wraps the body of the metal substrate 1, the bottom surfaces of the boss 2 and the heat dissipation bonding pad 3 are exposed, the first electrode plate 81 is embedded in the lower bottom surface of the flat layer 4, the second electrode plate 82 is embedded around the upper surface of the first stage layer 5 and is matched with the first conductive through hole 7 in position, and in addition, the surfaces of the heat dissipation bonding pad 3 and the first electrode plate 81 exposed in the air are subjected to tinning treatment; the flexible cushion block 9 is arranged on the upper surface of the flat layer 4, a circuit layer substrate 10 is fixed on the flexible cushion block 9 by adopting a welding process, the space is divided into an upper packaging layer and a lower packaging layer, and a second conductive through hole 11 structure is arranged in the circuit layer substrate 10; the power IC13 is arranged on the boss 2 through a welding layer 14, a first group of conductive posts 15 and a first group of solder balls 16 are also prepared on the active surface of the boss, then the power IC is welded on the lower bottom surface of the circuit layer substrate 10, and finally the electric connection part is sealed by a first filling layer 17; the non-power IC12 is flip-chip mounted on the wiring layer substrate 10 by means of a second set of conductive pillars 22 and a second set of solder balls 23, followed by sealing the electrical connections with a second filler layer 24; the circuit layer substrate 10 is bonded with the second electrode sheet 82 through the aluminum wire 18; preparing a metal layer 19 on the passive side of the non-power IC 12; the plastic layer 20 is connected with the periphery of the top surface of the flat layer 4, the first stage layer 5 and the second stage layer 6 to construct a sealed package; and grinding the plastic layer 20 until the upper surface of the metal layer 19 is exposed, and connecting the radiator 21 and the metal layer 19 by adopting a hot-pressing fusion process to establish a radiating channel.
The application also provides an integrated packaging method of the power module, wherein the integrated packaging method comprises the following steps:
s101: the resin insulating layer wraps part of the metal substrate 1;
s102: preparing a first conductive via 7 in the resin insulation layer;
s103: embedding a first electrode tab 81 and a second electrode tab 82 in the resin insulation layer, wherein the first electrode tab 81 and the second electrode tab 82 are positioned at two ends of the first conductive through hole 7;
s104: mounting the power IC13 on the metal base 1;
s105: mounting the wiring layer substrate 10 on the resin insulation layer, and electrically connecting the wiring layer substrate 10 with the power IC13, and electrically connecting the wiring layer substrate 10 with the second electrode pad 82;
s106: mounting a non-power IC12 above the wiring layer substrate 10, and electrically connecting the wiring layer substrate 10 with the non-power IC 12;
s107: and preparing the plastic sealing layer 20, so that the plastic sealing layer 20, the metal substrate and the resin insulating layer form a closed space.
Specifically, in the present embodiment, the first electrode tab 81 and the second electrode tab 82 are embedded in the resin insulation layer by the etching process, and the first conductive via 7 is formed by the deposition and pitting processes.
After step S101, the heat dissipation pad 3 is heat-press-fused with the side of the metal base 1 without the boss 2. The metal base is wrapped by the flat layer 4 of the resin insulation layer. The circuit layer substrate 10 is arranged on the upper surface of the flat layer 4 through the flexible cushion 9.
In step S101, a boss 2 is prepared on a metal substrate 1, specifically: cutting and die casting are carried out on the metal substrate 1 to prepare a boss 2, wherein the boss 2 is arranged on the top surface of the metal substrate 1, and the boss 2 is of a cuboid structure and is arranged in plurality.
The resin insulation layer is provided with a paving layer 4, a first step layer 5 and a second step layer 6 from bottom to top in sequence, and the outer side surfaces of the paving layer 4, the first step layer 5 and the second step layer 6 are coplanar:
the first conductive via 77 is formed in the interior of the paving layer 4 and the first step layer 5, and the first conductive via 77 is disposed around the resin insulation layer.
When the heat dissipation pad 3 is thermally pressed and fused with the side of the substrate 1 without the boss 2, the heat dissipation pad is specifically:
grinding one surface of the heat dissipation bonding pad 3 to obtain a first surface metal mirror;
grinding one surface of the base of the metal substrate without the boss 2 to obtain a second-surface metal mirror;
and carrying out hot-pressing fusion on the first surface metal mirror and the second surface metal mirror, and combining the first surface metal mirror and the second surface metal mirror together.
In the resin insulation layer of the laying layer 4, the metal substrate 1 is wrapped, specifically: the tiled layer 4 of the resin insulation layer is prepared by injection molding, dispensing and other processes and wraps the substrate 1, and the whole is ground to expose the bottom surfaces of the boss 2 and the heat dissipation pad 3.
In step S103, the first electrode pad 81 and the second electrode pad 82 are respectively embedded on the surfaces of the tile layer 4 and the first step layer 5, specifically: the first electrode piece 81 and the second electrode piece 82 are embedded around the lower surface of the tiled layer 4 and the upper surface of the first level 5 through an etching process, and the surfaces of the first electrode piece 81 and the second electrode piece 82 are flush through the dimension design of the electrode piece 8 and the grinding means of the surface of the tiled layer 4 of the resin insulation layer.
The packaging method further comprises the step of carrying out surface treatment on the heat dissipation bonding pad 3 and the first electrode plate 81, and specifically comprises the following steps: and (3) exposing the heat dissipation pad 3 and the first electrode slice 818 on the air surface to perform surface tin plating treatment to prevent oxidation of the heat dissipation pad 3 and the first electrode slice 81.
In step s105, the circuit layer substrate 10 is disposed on the upper surface of the tile layer 4 through the flexible pad 9, specifically: the flexible cushion block 9 is fixed on the periphery of the upper surface of the tiling layer 4 through an insulating adhesive, and the circuit layer substrate 10 is fixed on the flexible cushion block 9 through a welding process, so that an upper packaging layer and a lower packaging layer are formed; the circuit layer substrate 10 is provided with a second conductive through hole 11 to construct an internal power loop of the upper and lower packaging layers, and the second conductive through hole 11 is also formed through a deposition and pitting process; the position and the height of the circuit layer substrate 10 and the position and the height of the flexible cushion block 9 are related to the sizes and the installation positions of the boss 2 of the metal substrate and the semiconductor non-power ICs 12 and 13.
In step S104, the power IC13 is mounted, specifically: a conductive interconnection structure is prepared on the active surface of the power IC13, wherein a first group of conductive pillars 15 is prepared on the active surface of the power IC13 through an electroplating process, and the first group of solder balls 16 are melted through a reflow soldering process or the like to connect the first group of conductive pillars 15 and the circuit layer substrate 10.
In step S104, the power IC13 is mounted, and the method further includes: the conductive interconnect structure is underfilled to form a first fill layer 17.
In step S106, the non-power IC12 is mounted, specifically: the active surface of the non-power IC12 is provided with a conductive interconnection structure, wherein a second group of conductive pillars 22 is prepared on the active surface of the non-power IC12 by an electroplating process, the second group of solder balls 23 are melted by a reflow soldering process or the like, and then the second group of conductive pillars 22 and the circuit layer substrate 10 are connected, and the conductive interconnection structure is underfilled to form a second filling layer 23.
The electrical connection between the semiconductor non-power IC12 and the power IC13, the wiring layer substrate 10, and the second electrode sheet 828 is specifically: the non-power IC12 and the power IC13 are electrically connected with the circuit layer substrate 10 through the second conductive through hole 11; the first electrode tab 81 establishes an electrical connection with the wiring layer substrate 10 through the aluminum wire 18 bonding process. Wherein: the semiconductor non-power ICs 12, 13 construct an internal electrical circuit through the second conductive via 11 and the wiring layer substrate 10, and an external electrical circuit through the aluminum wire 18, the first electrode pad 818 and the first conductive via 7. In the preferred embodiment, by providing the second conductive via 11, the non-power IC12 and the power IC13 are electrically connected to the circuit layer substrate 10 through the second conductive via 11, so that the electrical connection path is greatly shortened, the inductance is reduced, and the packaging density is increased.
In step S107, the plastic layer 20 is sealed specifically: the plastic layer 20 wraps the upper and lower package layers through injection molding, dispensing and other processes, and is connected with the resin insulation layer to construct a sealed package. The side surfaces of the plastic sealing layer 20 are flush with the side surfaces of the first stage layer 5 and the second stage layer 6, the bottom surface of the plastic sealing layer 20 is flush with the top surface of the flat layer 4, and the thickness of the plastic sealing layer 20 is slightly higher than that of the resin insulating layer, so that the insulating and airtight packaging effects are achieved.
Preferably, the molding layer 20 is made of ceramic powder reinforced epoxy resin material. Specifically, in this embodiment, aluminum nitride is used for the plastic sealing layer 20, so that the heat conductivity is improved while the insulation performance is improved, and the heat dissipation performance is improved.
Further, the integrated packaging method further includes S108, located in step S107, of mounting the heat spreader 21; the method comprises the following steps: carrying out chemical polishing treatment on the passive surface of the non-power IC12, preparing a metal layer 19 on the passive surface of the non-power IC12 after polishing, and adopting a metal material with high heat conductivity as the metal layer 19; further comprises:
grinding the bottom surface of the radiator 21 to obtain a third metal mirror surface;
grinding the surface of the metal layer 19 away from the non-power IC12 to obtain a fourth metal mirror surface;
and carrying out hot-pressing fusion on the third metal mirror surface and the fourth metal mirror surface to form a heat dissipation channel.
In the preferred embodiment, the power IC13 is directly connected to the boss 2 of the metal substrate 1, so as to reduce the propagation path of heat, and dissipate the heat through the heat dissipation pad 3, in addition, the non-power IC12 is in contact with the metal layer 19 and the metal layer 19 is in contact with the heat sink 21, so that the heat is dissipated through the heat sink 21, and therefore, the embodiment adopts a top-bottom double-sided heat dissipation structure, so that the heat transfer path is greatly increased, and the heat dissipation performance of the integrated package structure is better.
In addition, the metal substrate 1 adopts a ceramic particle reinforced metal matrix composite material with high thermal conductivity, such as copper diamond, and the like, and the plastic sealing layer 20 and the resin insulating layer adopt a ceramic powder reinforced epoxy resin composite material, so that the heat dissipation performance is further improved; the circuit layer substrate 10 and the flexible cushion block 9 enable components to be embedded into the metal core substrate, and the embedded packaging structure greatly optimizes a heat transfer path, improves packaging density, and is greatly beneficial to integrated development of packaging.
The foregoing is merely one specific embodiment of the application, and any modifications made in light of the above teachings are intended to fall within the scope of the application.

Claims (10)

1. The integrated packaging structure of the power module is characterized by comprising a metal core substrate, a plastic sealing layer, a semiconductor IC and a circuit layer substrate, wherein the plastic sealing layer and the metal core substrate form a closed space, the semiconductor IC and the circuit layer substrate are both positioned in the closed space, the metal core substrate comprises a metal substrate and a resin insulating layer which surrounds part of the periphery of the metal substrate, the semiconductor IC comprises a power IC and a non-power IC which are respectively positioned on the upper side and the lower side of the circuit layer substrate, the power IC and the non-power IC are electrically connected with the circuit layer substrate, a first conductive through hole is formed in the resin insulating layer, one end of the first conductive through hole is provided with a first electrode plate, the other end of the first conductive through hole is provided with a second electrode plate, the first electrode plate and the second electrode plate are both embedded into the resin insulating layer, one surface of the first electrode plate is exposed outside, one surface of the second electrode plate is exposed in the closed space, and the second electrode plate is connected with the circuit layer.
2. The integrated package structure of claim 1, wherein the resin insulation layer comprises a tile layer surrounding a portion of an outer periphery of the metal substrate, a first level disposed above the tile layer, and a second level disposed above the first level, an inner peripheral dimension of the first level being smaller than an inner peripheral dimension of the second level.
3. The integrated package of claim 2, wherein the first conductive via includes a first portion disposed within the tiling layer and a second portion disposed within the first step layer.
4. The integrated package of claim 3, wherein the tiled layer forms an enclosed space, the metal substrate includes a body in the enclosed space and a plurality of bosses extending from the body into the enclosed space, and the power IC is located on the plurality of bosses.
5. The integrated package structure of claim 1, further comprising a plurality of flexible pads having two ends respectively abutting against the resin insulation layer and the circuit layer substrate, wherein the flexible pads are spaced apart from the power IC by a certain distance, and the circuit layer substrate is disposed on the resin insulation layer through the flexible pads to form upper and lower package layers.
6. The integrated package of claim 5, wherein the circuit layer substrate has second conductive vias to form internal power loops of the upper and lower package layers.
7. The integrated package of claim 1, wherein the metal substrate is a ceramic particle reinforced metal matrix composite.
8. The integrated package of claim 1, further comprising a metal layer in contact with the non-power IC, a heat spreader in contact with the metal layer and exposed to the outside, a heat dissipation pad in contact with the metal substrate and exposed to the outside, and wherein one side of the heat spreader is in contact with the resin insulation layer, and an outer periphery of the heat dissipation pad is in contact with the resin insulation layer.
9. The integrated packaging method of the power module is characterized by comprising the following steps of:
s101: the resin insulating layer wraps part of the metal substrate;
s102: preparing a first conductive through hole in the resin insulating layer;
s103: embedding a first electrode plate and a second electrode plate in the resin insulating layer, wherein the first electrode plate and the second electrode plate are positioned at two ends of the first conductive through hole;
s104: mounting a power IC on the metal substrate;
s105: mounting a circuit layer substrate on the resin insulation layer, electrically connecting the circuit layer substrate with the power IC, and electrically connecting the circuit layer substrate with the second electrode sheet;
s106: mounting a non-power IC above the circuit layer substrate, and electrically connecting the circuit layer substrate with the non-power IC;
s107: and preparing a plastic sealing layer, and forming a closed space by the plastic sealing layer, the metal substrate and the resin insulating layer.
10. The integrated packaging method of a power module according to claim 9, wherein the first electrode pad and the second electrode pad are embedded in the resin insulation layer by an etching process, and the first conductive via is formed by a deposition, pitting process.
CN202310420736.3A 2023-04-19 2023-04-19 Integrated packaging structure of power module and integrated packaging method thereof Pending CN116779551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310420736.3A CN116779551A (en) 2023-04-19 2023-04-19 Integrated packaging structure of power module and integrated packaging method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310420736.3A CN116779551A (en) 2023-04-19 2023-04-19 Integrated packaging structure of power module and integrated packaging method thereof

Publications (1)

Publication Number Publication Date
CN116779551A true CN116779551A (en) 2023-09-19

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