CN116779428A - Wafer heterogeneous fusion method - Google Patents
Wafer heterogeneous fusion method Download PDFInfo
- Publication number
- CN116779428A CN116779428A CN202210228762.1A CN202210228762A CN116779428A CN 116779428 A CN116779428 A CN 116779428A CN 202210228762 A CN202210228762 A CN 202210228762A CN 116779428 A CN116779428 A CN 116779428A
- Authority
- CN
- China
- Prior art keywords
- wafer
- cavity
- ion beam
- bonding
- wafers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007500 overflow downdraw method Methods 0.000 title claims abstract description 16
- 235000012431 wafers Nutrition 0.000 claims abstract description 113
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 59
- 238000009499 grossing Methods 0.000 claims abstract description 33
- 150000002500 ions Chemical class 0.000 claims abstract description 33
- 230000004913 activation Effects 0.000 claims abstract description 21
- 238000004140 cleaning Methods 0.000 claims abstract description 21
- 230000005540 biological transmission Effects 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 17
- 230000007704 transition Effects 0.000 claims abstract description 14
- 239000002131 composite material Substances 0.000 claims abstract description 6
- 238000011068 loading method Methods 0.000 claims abstract description 3
- 238000012546 transfer Methods 0.000 claims description 13
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000007499 fusion processing Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 23
- 239000000463 material Substances 0.000 abstract description 13
- 230000004927 fusion Effects 0.000 abstract description 12
- 239000004065 semiconductor Substances 0.000 abstract description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052786 argon Inorganic materials 0.000 abstract description 3
- 238000002360 preparation method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000003746 surface roughness Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 239000003575 carbonaceous material Substances 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Abstract
The invention provides a wafer heterogeneous fusion method, and relates to the technical field of semiconductor material and device preparation. The method comprises the following steps: loading two wafers into a slide cavity, and vacuumizing the slide cavity; conveying the wafer to a surface smoothing cavity through a vacuum conveying cavity, and sequentially carrying out surface ion beam cleaning and surface smoothing treatment on the wafer; conveying the wafers to a bonding cavity through a vacuum conveying cavity, performing ion beam surface activation on the wafers, synchronously compensating surface bonding states by adopting composite elements, and forming transition layers at the opposite positions of the surfaces of two wafers respectively; aligning the transition layers of the two wafers, and bonding the two wafers under preset conditions; and conveying the bonded wafer to the slide cavity through the vacuum conveying cavity. The invention integrates the surface ion beam cleaning, the surface smoothing, the sample transmission in the anaerobic vacuum environment, the argon ion beam surface activation combined with the additional element ions and the wafer bonding technology, and realizes the high-quality heterogeneous fusion of the normal-temperature wafer.
Description
Technical Field
The invention relates to the technical field of semiconductor material and device preparation, in particular to a wafer heterogeneous fusion method.
Background
The development of the chip industry in the past decades depends on moore's law, and today the progress of chip process miniaturization has been retarded, and three-dimensional heterogeneous integration routes realize continuation of integration and further development. Heterogeneous integration scales enter from past microscale to nanoscale and even atomic scale, which requires new heterogeneous fusion technologies to support next-generation technological breakthroughs.
The normal temperature wafer heterogeneous fusion technology is different from the traditional technologies such as a high temperature bonding technology, a metal bonding technology and the like, can realize atomic-level direct bonding of wafer materials at normal temperature, has high bonding strength and good thermal compatibility, is particularly suitable for direct fusion of heterogeneous materials with larger thermal performance difference, and opens up a new space for integrated circuit development exceeding the molar direction. However, the technology has high requirements on the surface quality of the material, and needs to develop an integrated technology and equipment suitable for surface treatment and fusion so as to meet the requirements of high-quality surface treatment and bonding.
Disclosure of Invention
The invention provides a wafer heterogeneous fusion method, which aims at solving the technical problems of high requirement on the surface roughness of a wafer, unintentional contamination after grinding the wafer, thicker damaged layer and thicker transition layer after activation of a bonding surface and the like in the conventional normal-temperature wafer bonding process.
The invention provides a wafer heterogeneous fusion method, which comprises the following steps:
loading two wafers into a slide cavity, and vacuumizing the slide cavity;
conveying the wafer to a surface smoothing cavity through a vacuum conveying cavity, and sequentially carrying out surface ion beam cleaning and surface smoothing treatment on the wafer;
conveying the wafers to a bonding cavity through a vacuum conveying cavity, performing ion beam surface activation on the wafers, synchronously compensating surface bonding states by adopting composite elements, and forming transition layers at the opposite positions of the surfaces of two wafers respectively;
aligning the transition layers of the two wafers, and bonding the two wafers under preset conditions;
and conveying the bonded wafer to the slide cavity through the vacuum conveying cavity.
Further, the vacuum pressure for vacuumizing the slide cavity is not higher than 10 -3 Torr。
Further, the vacuum transmission cavity has a transmission vacuum pressure of not higher than 10 -4 Torr。
Further, the ion source for surface ion beam cleaning comprises an Ar ion beam or an O ion beam, the cleaning scanning included angle between the ion beam and the wafer is 60-90 degrees, and the vacuum pressure is not higher than 10 degrees -5 Torr。
Further, the ion source for surface smoothing treatment comprises an Ar ion beam or an O ion beam, a smoothing scanning included angle between the ion beam and the wafer is 1-20 degrees, and the vacuum pressure is not higher than 10 degrees -5 Torr。
Further, the included angle of the smoothing scan is specifically 1-10 degrees.
Further, the ion source for ion beam surface activation comprises an integrated ion beam with Ar ions carrying additional ions, an activation scanning included angle between the ion beam and a wafer is 1-20 degrees, and the vacuum pressure is not higher than 10 degrees -5 Torr。
Further, the additional ions comprise Si ions or Al ions, and the activation scanning included angle is specifically 1-10 degrees.
Further, both the smoothing scan angle and the activation scan angle may be adjusted by any of the following means:
changing the incidence angle of the ion beam through the rotating shaft; or alternatively
And rotating the wafer through the slide holder.
Further, both Ar ions and additional ions are ejected from the same device.
Further, the bonding temperature is-20 ℃ to 50 ℃.
Further, the slide cavity is adjacent to the upper part of the vacuum transmission cavity, and the surface smoothing cavity and the bonding cavity are respectively adjacent to the left side and the right side of the vacuum transmission cavity.
Compared with the prior art, the wafer heterogeneous fusion method provided by the invention has at least the following beneficial effects:
(1) The invention integrates the surface ion beam cleaning, the surface smoothing, the sample transmission in the anaerobic vacuum environment, the surface activation of the argon ion beam combined with the X element and the wafer bonding technology, realizes the heterogeneous fusion of normal-temperature wafer with high quality, and can realize the effects of in-situ treatment of the surface roughness of the wafer, ultra-clean transmission of the surface of the wafer, ultra-thin surface damage layer and transition layer, and the like;
(2) The invention adopts the ultra-high vacuum transmission technology, thereby effectively avoiding oxidation and secondary pollution after cleaning and smoothing the surface of the wafer;
(3) The invention adopts the surface ion beam cleaning and low-angle ion beam scanning smoothing technology, solves the problems that the existing wafer grinding technology needs wet cleaning of the surface, is not easy to integrate and has high surface roughness, and avoids the problem that the existing high-angle vertical etching technology synchronously reduces the peaks and the peaks of the surface, so that the cleaning, smoothing and surface activation room-temperature bonding are integrated, the surface roughness of the wafer is reduced to a level below 1nm, and the heterogeneous fusion of high-quality normal-temperature wafers is realized;
(4) The invention adopts a low-angle ion beam scanning technology and a composite element synchronous compensation technology, has small ion beam spots and small penetration depth, effectively reduces the surface damage of the wafer, thins the interface amorphous layer, reduces the thickness of the interface transition layer, reduces the interface thermal resistance, and improves the bonding energy, uniformity and bonding rate;
(5) The invention provides an innovative solution for heterogeneous fusion of high-quality wafers such as silicon-based materials, wide-bandgap semiconductor materials, carbon-based materials and the like.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 schematically illustrates a flow chart of a wafer heterojunction method in accordance with an embodiment of the present invention;
fig. 2 schematically illustrates a cavity arrangement and an operational flow diagram of a wafer hetero-fusion method according to an embodiment of the present invention.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed therewith; may be mechanically connected, may be electrically connected or may communicate with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.
Some of the block diagrams and/or flowchart illustrations are shown in the figures. It will be understood that some blocks of the block diagrams and/or flowchart illustrations, or combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the instructions, when executed by the processor, create means for implementing the functions/acts specified in the block diagrams and/or flowchart.
Fig. 1 schematically shows a flow chart of a wafer hetero-fusion method according to an embodiment of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a wafer heterogeneous fusion method, which includes the following operations S110 to S150.
In operation S110, two wafers are loaded into a slide chamber, and the slide chamber is evacuated.
Wherein the slide cavity is vacuumized so that the vacuum pressure of the slide cavity is not higher than 10 -3 Torr。
In operation S120, the wafer is transferred to the surface smoothing chamber through the vacuum transfer chamber, and surface ion beam cleaning and surface smoothing processes are sequentially performed on the wafer.
It is understood that surface ion beam cleaning is used to remove wafer surface contaminants and surface smoothing is used to reduce wafer surface roughness. Specifically, the ion source for surface ion beam cleaning comprises an Ar ion beam or an O ion beam, the cleaning scanning included angle between the ion beam and a wafer is 60-90 degrees, and the vacuum pressure is not higher than 10 degrees -5 Torr。
The surface ion beam cleaning may include, for example, RCA standard cleaning, or ultrasonic cleaning of acetone, isopropyl alcohol, ethanol, deionized water, etc., and the invention is not limited in particular.
The ion source for surface smoothing treatment comprises an Ar ion beam or an O ion beam, a smoothing scanning included angle between the ion beam and a wafer is 1-20 degrees, and the vacuum pressure is not higher than 10 degrees -5 Torr. Preferably, the smoothing scanning included angle is specifically 1-10 degrees.
In operation S130, the wafer is transferred to the bonding chamber through the vacuum transfer chamber, ion beam surface activation is performed on the wafer, the composite element is used to compensate the surface bonding state simultaneously, and the transition layers are formed at the opposite positions of the surfaces of the two wafers.
The ion source for activating the surface of the ion beam comprises an integrated ion beam with Ar ions carrying additional ions, an activation scanning included angle between the ion beam and a wafer is 1-20 degrees, and the vacuum pressure is not higher than 10 degrees -5 Torr。
Preferably, the additional ions comprise Si ions or Al ions, and the activation scanning included angle is specifically 1-10 degrees.
Further, for ion beam surface activated ion sources, both Ar ions and additional ions are ejected from the same device.
It can be seen that the surface smoothing treatment and the ion beam surface activation of this embodiment both use a small angle sweep scan, and strictly control the vacuum pressure during the treatment. In addition, the embodiment uses the low-angle ion beam scanning technology and the composite element synchronous compensation technology, has small ion beam spots and small penetration depth, effectively reduces the surface damage of the wafer, thins the interface amorphous layer, reduces the thickness of the interface transition layer, reduces the interface thermal resistance, and improves the bonding energy, uniformity and bonding rate.
In operation S140, the respective transition layers of the two wafers are aligned, and the two wafers are bonded under a predetermined condition.
In operation S150, the bonded wafer is transferred to the carrier chamber through the vacuum transfer chamber.
In the embodiment of the invention, the transmission vacuum pressure of the vacuum transmission cavity is not higher than 10 -4 Torr. Since the vacuum transfer involves the operations S120, S130 and S150 described above, all wafer vacuum transfers in the vacuum transfer chamber need to maintain the transfer vacuum pressure. Therefore, the invention adopts the ultra-high vacuum transmission technology, and effectively avoids oxidation and secondary pollution after cleaning and smoothing the surface of the wafer.
In the embodiment of the present invention, the smoothing scan angle and the activation scan angle may be adjusted by any one of the following methods: changing the incidence angle of the ion beam through the rotating shaft; alternatively, the wafer is rotated by a stage.
Further, the bonding temperature in the above operation S140 is normal temperature, and the specific bonding temperature may be-20 ℃ to 50 ℃.
It should be noted that, at present, the bonding conditions for the wafer generally need to be under high temperature conditions, so that not only bonding efficiency is low, but also bonding cost of the wafer is increased, and materials and structures still have obvious thermal expansion and thermal stress. The embodiment of the invention enables the wafer to be bonded at normal temperature without traditional high-temperature annealing, thereby improving the bonding efficiency of the wafer and reducing the thermal expansion and thermal stress between materials or structures.
In addition, since the surface cleanliness of two wafers bonded determines whether bonding is successful or not and bonding strength, if dust particles exist between bonding surfaces, bonding is difficult to be successful, and even if bonding is successful, dust particles on the bonding surfaces can form bonding cavities, so that the application of the bonding cavities is directly affected. In view of this, the preset conditions for wafer bonding in operation S140 described above may be set as: the roughness of the surface of the transition layer arranged opposite to the two wafers is lower than 1nm.
Therefore, the wafer is bonded at normal temperature, so that the surface roughness of the wafer is reduced to a level below 1nm, and high-quality normal-temperature wafer heterogeneous fusion is realized.
Fig. 2 schematically illustrates a cavity arrangement and an operational flow diagram of a wafer hetero-fusion method according to an embodiment of the present invention.
As shown in fig. 2, alternatively, the slide cavity is adjacent to the upper side of the vacuum transfer cavity, and the surface smoothing cavity and the bonding cavity are adjacent to the left and right sides of the vacuum transfer cavity, respectively, whereby all cavities are formed in an inverted T shape, facilitating various surface treatment operations and vacuum transfer.
The above is merely an exemplary illustration, and the present embodiment is not limited thereto. For example, under normal temperature, the activated wafers are bonded, and a certain pressure is applied to exhaust the air of the interface, so that the whole bonding surface is fully contacted and the bonding is more compact. Thus, the preset conditions may further include, for example: a certain initial pressure is applied, and a specific initial pressure range can be set according to the operation requirement of actual bonding, and the invention is not limited in particular.
As another example, the means for internal or external placement of all of the slide chamber, vacuum transfer chamber, surface smoothing chamber, and bonding chamber as shown in fig. 2 are not fixed and can be set by one skilled in the art as desired, as the invention is not limited in this regard.
It should be further noted that the "wafer" mentioned in the present invention may include silicon, wide bandgap semiconductor, carbon-based material, and other compound semiconductor materials. Therefore, the invention provides an innovative solution for heterogeneous fusion of high-quality wafers such as silicon-based materials, wide-bandgap semiconductor materials and carbon-based materials.
In summary, the embodiment of the invention provides a wafer heterogeneous fusion method, which develops a novel ion beam scanning technology to treat the surface of a wafer in situ so as to reduce the roughness to a level below 1nm, adopts a vacuum transmission technology to solve the ultra-clean transmission problem of the surface of the wafer, combines the novel ion beam scanning technology and an element compensation technology to solve the problems of activation and re-bonding of elements on the surface of the wafer, ultra-thin damaged layers and transition layers, and finally realizes normal-temperature wafer bonding through wafer alignment and lamination. The invention integrates the surface ion beam cleaning, the surface smoothing, the sample transmission in the anaerobic vacuum environment, the argon ion beam surface activation combined with the additional element ions and the wafer bonding technology, realizes the high-quality heterogeneous fusion of normal-temperature wafers, and provides an innovative solution for the heterogeneous fusion of high-quality wafers such as silicon-based materials, wide-forbidden-band semiconductor materials, carbon-based materials and the like.
It should be understood that the specific order or hierarchy of steps in the processes disclosed are examples of exemplary approaches. Based on design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged without departing from the scope of the present invention. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Like elements are denoted by like or similar reference numerals throughout the drawings. Conventional structures or constructions will be omitted when they may cause confusion in the understanding of the invention. And the shape, size and position relation of each component in the figure do not reflect the actual size, proportion and actual position relation.
Similarly, in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. The description of the terms "one embodiment," "some embodiments," "example," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
While the foregoing is directed to embodiments of the present invention, other and further details of the invention may be had by the present invention, it should be understood that the foregoing description is merely illustrative of the present invention and that no limitations are intended to the scope of the invention, except insofar as modifications, equivalents, improvements or modifications are within the spirit and principles of the invention.
Claims (12)
1. The wafer heterogeneous fusion method is characterized by comprising the following steps of:
loading two wafers into a slide cavity, and vacuumizing the slide cavity;
the wafer is conveyed to a surface smoothing cavity through a vacuum conveying cavity, and surface ion beam cleaning and surface smoothing treatment are sequentially carried out on the wafer;
transmitting the wafer to a bonding cavity through a vacuum transmission cavity, performing ion beam surface activation on the wafer, synchronously compensating surface bonding states by adopting composite elements, and forming transition layers at the relative positions of the surfaces of the two wafers respectively;
aligning the transition layers of the two wafers, and bonding the two wafers under preset conditions;
and conveying the bonded wafer to the slide cavity through the vacuum conveying cavity.
2. The wafer fusion method of claim 1, wherein the vacuum pressure to evacuate the slide cavity is no higher than 10 -5 Torr。
3. The wafer heterojunction method of claim 1, wherein a transmission vacuum pressure of the vacuum transmission chamber is not higher than 10 -4 Torr。
4. The method of claim 1, wherein the ion source for cleaning the surface ion beam comprises an Ar ion beam or an O ion beam, a cleaning scan angle between the ion beam and the wafer is 60 ° to 90 °, and a vacuum pressure is not higher than 10 ° -5 Torr。
5. The method according to claim 1The wafer heterogeneous fusion method is characterized in that the ion source for the surface smoothing treatment comprises an Ar ion beam or an O ion beam, a smoothing scanning included angle between the ion beam and a wafer is 1-20 degrees, and the vacuum pressure is not higher than 10 -5 Torr。
6. The wafer fusion method of claim 5, wherein the smoothing scan angle is specifically 1 ° to 10 °.
7. The method of claim 5, wherein the ion source for activating the surface of the ion beam comprises an integrated ion beam carrying additional ions by Ar ions, the activation scan angle between the ion beam and the wafer is 1-20 degrees, and the vacuum pressure is not higher than 10 degrees -5 Torr。
8. The wafer heterojunction method of claim 7, wherein the additional ions comprise Si ions or Al ions, and the activation scan angle is specifically 1 ° to 10 °.
9. The wafer heterojunction method of claim 7, wherein the smoothing scan angle and the activation scan angle are adjustable by any one of:
changing the incidence angle of the ion beam through the rotating shaft; or alternatively
And rotating the wafer through the slide holder.
10. The wafer heterojunction method of claim 7, wherein the Ar ions and the additional ions are both ejected from the same device.
11. The wafer fusion process of claim 1, wherein the bonding temperature is-20 ℃ to 50 ℃.
12. The wafer heterofusion method of claim 1, wherein the slide cavity is adjacent to an upper side of the vacuum transfer cavity, and the surface smoothing cavity and the bonding cavity are adjacent to left and right sides of the vacuum transfer cavity, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210228762.1A CN116779428A (en) | 2022-03-09 | 2022-03-09 | Wafer heterogeneous fusion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210228762.1A CN116779428A (en) | 2022-03-09 | 2022-03-09 | Wafer heterogeneous fusion method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116779428A true CN116779428A (en) | 2023-09-19 |
Family
ID=88010347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210228762.1A Pending CN116779428A (en) | 2022-03-09 | 2022-03-09 | Wafer heterogeneous fusion method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116779428A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117316837A (en) * | 2023-11-29 | 2023-12-29 | 武汉大学 | Vacuum interconnection equipment and digital twin system for wafer hybrid bonding process |
-
2022
- 2022-03-09 CN CN202210228762.1A patent/CN116779428A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117316837A (en) * | 2023-11-29 | 2023-12-29 | 武汉大学 | Vacuum interconnection equipment and digital twin system for wafer hybrid bonding process |
| CN117316837B (en) * | 2023-11-29 | 2024-03-08 | 武汉大学 | Hybrid bonding continuity simulation model establishment method, system and equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3975944B2 (en) | HOLDER FOR SEMICONDUCTOR OR LIQUID CRYSTAL MANUFACTURING DEVICE AND SEMICONDUCTOR OR LIQUID CRYSTAL MANUFACTURING DEVICE WITH THE SAME | |
| JP3537269B2 (en) | Multi-chamber sputtering equipment | |
| CN1253286C (en) | Electrostatic adsorption table and substrate processing apparatus | |
| KR101019901B1 (en) | Substrate processing apparatus | |
| KR20150094685A (en) | Substrate support assembly having metal bonded protective layer | |
| JP6076486B2 (en) | Handle substrate for composite substrates for semiconductors | |
| TW201225203A (en) | Apparatus for manufacturing semiconductor devices | |
| JP2002313899A (en) | Substrate holding structure and substrate processor | |
| WO2014174946A1 (en) | Handle substrate for composite substrate for semiconductor | |
| CN116779428A (en) | Wafer heterogeneous fusion method | |
| KR102333477B1 (en) | Method of manufacturing and modularizing assembled thermal management material based on diamond-graphene hybrid structure | |
| US9469571B2 (en) | Handle substrates of composite substrates for semiconductors | |
| JP6290222B2 (en) | Method for coating substrates and method for bonding substrates | |
| JP7423099B2 (en) | Method for manufacturing silicon carbide tray for plasma etching and silicon carbide tray | |
| CN107527851B (en) | Ceramic electrostatic chuck device and preparation process thereof | |
| CN113937043A (en) | Vacuum transfer device and substrate processing system | |
| JPH10107124A (en) | Substrate processing device | |
| KR101642671B1 (en) | Handle substrates of composite substrates for semiconductors, and composite substrates for semiconductors | |
| CN206022339U (en) | ceramic electrostatic chuck device | |
| CN220856514U (en) | Automatic communication pipeline for wafer bonding | |
| CN118486704A (en) | Semiconductor composite material, preparation method thereof and device | |
| JPH11278919A (en) | Plasma-resistant member | |
| CN117777862A (en) | Chemical mechanical polishing solution and preparation method of piezoelectric single crystal composite substrate with cavity | |
| WO2020196011A1 (en) | Bonding device and bonding method | |
| JPH11238780A (en) | Semiconductor silicon wafer carrying retention tool and semiconductor process device using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |