CN116776808A - Layout design method for reducing SAR ADC capacitance mismatch - Google Patents
Layout design method for reducing SAR ADC capacitance mismatch Download PDFInfo
- Publication number
- CN116776808A CN116776808A CN202310563828.7A CN202310563828A CN116776808A CN 116776808 A CN116776808 A CN 116776808A CN 202310563828 A CN202310563828 A CN 202310563828A CN 116776808 A CN116776808 A CN 116776808A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- sar adc
- layout
- design method
- layout design
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013461 design Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000003990 capacitor Substances 0.000 claims abstract description 104
- 230000003071 parasitic effect Effects 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims description 45
- 238000004088 simulation Methods 0.000 claims description 4
- 238000012795 verification Methods 0.000 claims description 3
- 230000006872 improvement Effects 0.000 abstract description 3
- 238000007405 data analysis Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a layout design method for reducing SAR ADC capacitance mismatch, which comprises the following steps: and determining the number of unit capacitors contained in each capacitor according to the capacitor array structure, extracting parasitic capacitors for capacitor array layout and wiring, performing data analysis, and determining whether the designed layout meets the requirements according to the data analysis result. According to the design method, the relation between the parasitic capacitances is subjected to data processing, so that the influence of the parasitic capacitances on mismatch can be intuitively displayed, and the direction is indicated for improvement of the layout. Compared with the traditional method for increasing the unit capacitance size, the layout designed by the invention can improve the matching property of the capacitor without increasing the area of the capacitor array, thereby reducing the influence of parasitic capacitance on SAR ADC results and improving the dynamic performance of an ADC system.
Description
Technical Field
The invention belongs to the technical field of integrated circuit layout design, and particularly relates to a layout design method for reducing SAR ADC capacitance mismatch.
Background
The successive approximation analog-to-digital converter (SAR ADC, successive Approximation Register Analog-to-Digital Converter) is a common type in the ADC, has the characteristics of high precision, simple structure, low power consumption and the like, is widely applied to various fields, and mainly has a resistor type, a capacitor type and a resistor-capacitor hybrid type. The capacitive SAR ADC mainly comprises a sample hold circuit, a DAC array, successive approximation logic and a comparator, as shown in figure 1.
The core idea of the operating principle of SAR ADC is the dichotomy: the output voltage of DAC before the nth comparison will change according to the last comparison resultSuccessive approximation of the input voltage is achieved, and analog-to-digital conversion is finally completed. In this process, the output voltage of the DAC is used as a reference for comparison, and the accuracy thereof has a direct influence on the output result. The parasitic capacitance makes the adjacent capacitance in the capacitor array of the DAC no longer maintain the 2 times relation, and further the variation of the output voltage no longer changes according to the 2 times relation, which directly results in the deterioration of the static performance and the dynamic performance of the ADC system.
In order to increase the matching degree between the capacitors and reduce the influence of the parasitic capacitors on the chip, it is common practice to increase the size of the unit capacitors as much as possible, thereby reducing the proportion of the parasitic capacitors in the actual capacitors. But this approach can significantly increase the area of the capacitive array, increasing the cost of a single chip. Therefore, the layout design method for reducing the capacitance mismatch is found on the premise of not sacrificing the area, and is a design difficulty.
Disclosure of Invention
In view of the above, the invention provides a layout design method for reducing the capacitor mismatch of the SAR ADC, and the wiring of the upper polar plate and the lower polar plate of the capacitor is changed, so that the relation between parasitic capacitors on each bit can meet 2 times of relation as much as possible, and the influence of the capacitor mismatch on the ADC performance is reduced on the premise of not increasing the capacitor size.
A layout design method for reducing SAR ADC capacitance mismatch comprises the following steps:
1) Determining the number of unit capacitors contained in each capacitor according to the designed capacitor array structure;
2) Layout and wiring are carried out on the capacitor array;
3) Extracting parasitic capacitance, and calculating multiple K (i) between the parasitic capacitances of adjacent bit capacitors, wherein i is more than or equal to 1 and less than or equal to N-1, and N represents the total bit number of the capacitor array;
4) Calculating the MSE of K (1) -K (N-1), if the MSE is smaller than the expected value, completing the design, performing post simulation verification, if the MSE is larger than the expected value, changing the length of the lower polar plate metal wire and the number of the crossing points of the lower polar plate metal wire and the upper polar plate metal wire, and returning to the step 4 until the MSE is smaller than the expected value;
preferably, in the step 1), each bit capacitor of the capacitor array is composed of an integer multiple of unit capacitors;
preferably, in the step 2), the layout of the capacitor array is centrosymmetric as much as possible, and the interval between the capacitors is not smaller than the minimum width required by the top metal routing, and the capacitors are used as the routing channels of the lower polar plate;
preferably, in the step 2), during wiring, upper electrode plates of all capacitors are connected together by using a top metal wire, and lower electrode plates of all unit capacitors belonging to the same capacitor are connected together by using a metal wire;
preferably, in the step 3), when the multiple relation is calculated, the upper parasitic capacitance is a divisor, and the lower parasitic capacitance is a divisor;
preferably, in the step 4), the true value adopted in calculating the MSE is 2;
preferably, the lower electrode plate is routed to a channel, only one metal wire is routed to one channel, and the blank area is filled with redundant metal wires, so that all areas of all channels are uniformly distributed with the metal wires;
preferably, when the wires are routed, the metal wires connected with the lower polar plate are uniformly distributed on the routing channel, and different metal layers are selected for the horizontal metal wires and the vertical metal wires.
The invention has the following beneficial effects:
the capacitor array layout obtained through the design of the steps can greatly reduce the capacitor proportion mismatch error caused by parasitic capacitance on the premise of ensuring the unchanged area, thereby improving the matching performance of the capacitor array, and finally improving the effective digit of the SAR ADC chip, and has good economic benefit.
Drawings
Fig. 1 is a schematic diagram of the architecture of a capacitive SAR ADC.
Fig. 2 is a flow chart of a layout design method for reducing capacitor mismatch of an SAR ADC according to the invention.
Fig. 3 is a schematic diagram of a capacitive array of a 3-bit SAR ADC.
Fig. 4 is a schematic diagram of a unit capacitor structure used in the present invention.
Fig. 5 is a schematic diagram of a capacitor array layout and upper plate wiring of a 3-bit SAR ADC.
Fig. 6 is a schematic diagram of the bottom plate connection of a 3-bit SAR ADC.
Fig. 7 is a schematic diagram of the layout of the bottom plate of the capacitor array of the improved 3-bit SAR ADC according to the invention.
Detailed Description
The invention is illustrated and described below with reference to the drawings and examples, which are not intended to limit the invention.
Fig. 2 is a flow chart of a layout design method for reducing capacitor mismatch of an SAR ADC, comprising:
step one, determining the number of unit capacitors contained in each capacitor according to a designed capacitor array structure;
step two, carrying out layout and wiring on the capacitor array;
extracting parasitic capacitance, and calculating multiple K (i) between the parasitic capacitances of adjacent bit capacitors, wherein i is more than or equal to 1 and less than or equal to N-1, and N represents the total bit number of the capacitor array;
calculating the mean square error MSE of K (1) -K (N-1), if the mean square error MSE is smaller than the expected value, completing design, performing post simulation verification, if the mean square error MSE is larger than the expected value, changing the length of the metal wire of the lower polar plate and the number of crossing points of the metal wire of the upper polar plate, and returning to the step 4 until the MSE is smaller than the expected value;
the present design method will be described in detail with reference to fig. 2, taking a capacitor array layout design of a 3-bit SAR ADC as an example.
In step one, the structure of the capacitor array and the number of capacitors per bit need to be specified. The DAC part of the 3-bit SAR ADC is shown in FIG. 3, and the whole capacitor array consists of 8 unit capacitors C u Composition is prepared. Wherein the first bit capacitor C 1 ＝C u Second bit capacitance C 2 ＝2C u Third bit capacitor C 3 ＝4C u Redundant bit capacitance c=c u . The upper polar plates of all the capacitors are connected together and then connected to the input end of the comparator, and the lower polar plate of each bit is respectively connected to the corresponding control switch S 1 ,S 2 ,S 3 And (3) upper part.
Unit capacitance C u The layout shown in fig. 4 is adopted, and the dotted line part in the middle of the layout represents the top metal and is used as the upper polar plate of the capacitor; the black parts around the layout represent the lower metal layer and serve as the lower electrode plate of the capacitor. In order to facilitate the wiring of the subsequent lower polar plate, the lower polar plate can adopt a plurality of metal layers except the top metal layer, and the metal layers are connected by using through holes.
And step two, preliminarily determining the layout and the wiring of the capacitor array. Fig. 5 shows the layout of the capacitor array and upper plate wiring of a 3-bit SAR ADC: selecting 9-bit capacitors to form a 3×3 capacitor layout array, wherein the first-bit capacitor only comprises one unit capacitor, and is arranged in the middle of the array and is marked as 1; the second bit capacitor comprises two unit capacitors which are arranged at two sides of the first bit capacitor and are marked as 2; the third capacitor comprises 4 unit capacitors which are arranged at four corners of the array and are marked as 3; one of the remaining two capacitors is selected as a redundant bit capacitor and the last is selected as a matching capacitor in order to maintain consistency of the environment around all capacitors in the array. The upper plate connection line also maintains symmetry as much as possible, and is shown by a dotted line in fig. 5, so that the upper plates of all capacitors in the circuit are connected together.
Further, the lower plate is threaded, as shown in fig. 6. The gaps between rows and between columns are used as wiring channels, only one metal wire is arranged on each wiring channel, and the horizontal metal wires and the vertical metal wires belong to different metal layers and are respectively represented by black wires and white wires. The connection is performed in the order from the low-order capacitor to the high-order capacitor, and the specific wiring mode is shown in fig. 6. It should be noted that only one line around each capacitor is connected to the channel trace, and the crossing point where the horizontal line and the vertical line need to be connected is connected by a via.
Step three, extracting the parasitic capacitance C of the 1 st to 3 rd bits p1 ，C p2 ，C p3 And calculating the magnitude of the multiple between the parasitic capacitances of adjacent bit capacitances:
K 1 ＝C p2 /C p1
K 2 ＝C p3 /C p2
based on the operating principle of SAR ADC, the relationship between each bit of capacitor array should be theoretically
C 3 ＝2C 2 ＝4C 1 #(1)
The capacitance in the actual layout is C 'due to the influence of parasitic capacitance' 1 ＝C u +C P1 ，C′ 2 ＝2C u +C p2 ，C′ 3 ＝4C u +C p3 . In order for the actual capacitance value to still satisfy the relationship in expression (1), then:
C p3 ＝2C p2 ＝4C p1 #(2)
namely: the adjacent parasitic capacitances should also satisfy a 2-fold increase relationship.
The principle of the fourth step is as follows: in order to obtain the difference between the multiple of the parasitic capacitance and 2, so as to reflect the influence of the parasitic capacitance on the theoretical capacitance value, the visual description can be performed by adopting the mean square error MSE:
wherein, the liquid crystal display device comprises a liquid crystal display device,represents a multiple relationship between adjacent parasitic capacitances, and θ represents a true value 2 times. If the calculated MSE is small enough, this indicates that the closer the parasitic capacitance increases by a factor of 2The smaller the influence on the conversion result of the ADC; conversely, the parasitic capacitance affects the linearity of the capacitor array to a large extent, which results in degradation of the ADC system performance.
If the calculated MSE is too large, the length of the metal wire connected to the lower electrode plate and the number of the metal wire crossing points of the lower electrode plate and the upper electrode plate need to be changed. The parasitic capacitance of the corresponding position can be reduced by shortening the length of the metal wire connected with the lower polar plate or reducing the number of connecting line intersections of the upper polar plate and the lower polar plate; otherwise, the length of the metal wire connected with the lower polar plate is increased, or the number of the connecting line crossing points of the upper polar plate and the lower polar plate is increased, so that the parasitic capacitance of the corresponding capacitance bit can be increased. The improvement of the lower electrode plate connection line of the capacitor array shown in fig. 6 is as shown in fig. 7: when the parasitic capacitance of the first bit and the second bit is found to be too large, the metal wire at A, B is disconnected, so that the parasitic capacitance is reduced; meanwhile, the parasitic capacitance of the third bit is found to be too small, and the length of the metal wire of the lower polar plate of the third bit capacitor is increased by adding the through hole at the C position, so that the parasitic capacitance of the third bit is increased.
And correcting the metal wire routing according to the method until the MSE value is lower than the set value, thereby completing the design of the capacitor array layout.
Table 1 provides the post-simulation significant bit number variation for a 12-bit SAR ADC at different MSE values. It can be seen that as the MSE decreases, the number of active bits of the ADC increases.
TABLE 1
| Capacitance array layout | MSE | Number of significant bits/bit |
| Layout 1 | 0.510 | 10.64 |
| Layout 2 | 0.360 | 11.10 |
| Layout 3 | 0.118 | 11.17 |
| Layout 4 | 0.085 | 11.51 |
| Layout 5 | 0.006 | 11.89 |
The embodiments are described above in order to facilitate a person skilled in the art to understand and apply the present invention, and are not intended to limit the spirit and scope of the present invention. Any equivalent replacement, modification, improvement, etc. made by those skilled in the art to the technical scheme of the present invention should be regarded as the protection scope of the present invention without departing from the design concept of the present invention. The scope of the invention should be defined by the appended claims.
Claims (8)
1. A layout design method for reducing SAR ADC capacitance mismatch is characterized by comprising the following steps:
1) Determining the number of unit capacitors contained in each capacitor according to the designed capacitor array structure;
2) Layout and wiring are carried out on the capacitor array;
3) Extracting parasitic capacitance, calculating multiple size K (i,
1i is less than or equal to N-1, wherein N represents the total bit number of the capacitor array;
4) Calculating the MSE of K (1) -K (N-1), if the MSE is smaller than the expected value, completing the design,
and (3) performing post simulation verification, if the length of the lower polar plate metal wire is larger than the expected value, changing the length of the lower polar plate metal wire and the number of the crossing points of the lower polar plate metal wire and the upper polar plate metal wire, and returning to the step (4), until the MSE is smaller than the expected value.
2. The layout design method for reducing capacitor mismatch of SAR ADC according to claim 1, wherein in said step 1), each bit capacitor of said capacitor array is comprised of an integer multiple of unit capacitors.
3. The layout design method for reducing capacitor mismatch of the SAR ADC according to claim 1, wherein in step 2), the layout of the capacitor array is centrosymmetric as much as possible, and the interval between the capacitors is not smaller than the minimum width required by the top metal routing, and the capacitors are used as the routing channels of the bottom plate.
4. The layout design method for reducing capacitor mismatch of SAR ADC according to claim 1, wherein in step 2), the upper plates of all capacitors are connected together by a top metal wire, and the lower plates of all unit capacitors belonging to the same capacitor are connected together by a metal wire.
5. The layout design method for reducing capacitor mismatch of SAR ADC according to claim 1, wherein in said step 3), when the multiple is calculated, the higher parasitic capacitance is a divisor, and the lower parasitic capacitance is a divisor.
6. The layout design method for reducing capacitor mismatch of SAR ADC according to claim 1, wherein in said step 4), the true value used in calculating MSE is 2.
7. The layout design method for reducing capacitor mismatch of SAR ADC as set forth in claim 3, wherein said lower plate is routed through a channel with only one metal wire, and the blank area is filled with redundant metal wires, so that all areas of all channels are uniformly distributed with metal wires.
8. The layout design method for reducing capacitor mismatch of SAR ADC as set forth in claim 4, wherein during said routing, metal wires connected to the lower plate are uniformly distributed on the routing channel, and the horizontal metal wires and the vertical metal wires are different metal layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310563828.7A CN116776808A (en) | 2023-05-18 | 2023-05-18 | Layout design method for reducing SAR ADC capacitance mismatch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310563828.7A CN116776808A (en) | 2023-05-18 | 2023-05-18 | Layout design method for reducing SAR ADC capacitance mismatch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116776808A true CN116776808A (en) | 2023-09-19 |
Family
ID=87986919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310563828.7A Pending CN116776808A (en) | 2023-05-18 | 2023-05-18 | Layout design method for reducing SAR ADC capacitance mismatch |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116776808A (en) |
-
2023
- 2023-05-18 CN CN202310563828.7A patent/CN116776808A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101097913B (en) | Capacitor array, capacitor and capacitor array layout method | |
| US10453791B2 (en) | Metal-on-metal capacitors | |
| CN1953181B (en) | Analog-digital converter | |
| CN109214130B (en) | Layout design method for sampling MOM capacitor of SARADC system | |
| US7873191B2 (en) | Capacitive array | |
| CN107565969A (en) | Capacitor array, gradual approaching A/D converter and capacitor array plate | |
| CN102571098B (en) | Layout arrangement structure for D/A converter current source array and wiring method | |
| CN105007677B (en) | D/A converting circuit and method for AMOLED column drive circuits | |
| US20190189350A1 (en) | Fringe Capacitor for High Resolution ADC | |
| CN111446262A (en) | Array substrate, manufacturing method thereof and display panel | |
| CN108365847A (en) | For the calibration method of charge type SAR-ADC parasitic capacitances | |
| CN107612549B (en) | Twisted-pair type shared central capacitor array and layout design method thereof | |
| US9418788B2 (en) | Precision half cell for sub-FEMTO unit cap and capacitive DAC architecture in SAR ADC | |
| CN115329714A (en) | Agile design method for analog-to-digital converter based on digital-analog mixed standard cell library | |
| CN116776808A (en) | Layout design method for reducing SAR ADC capacitance mismatch | |
| JP2007142379A (en) | Analog/digital converter | |
| CN102638270B (en) | Design and method of domain layout of 14-bit integrated circuit DAC (Digital to Analog Converter) current source array | |
| WO2020036479A1 (en) | Binary weighted capacitor array with split capacitor layout | |
| CN111129304B (en) | MOM capacitor, capacitor array structure and layout design method thereof | |
| CN115802599A (en) | Layout structure and related chip | |
| US11928412B2 (en) | Method | |
| Burcea et al. | Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis | |
| Chen et al. | A 1.23 μJ/Inference, All-Digital Shuffle-Type Group-CNN Accelerator in 28nm CMOS With 85.8% Accuracy on CIFAR-10 | |
| US20210028159A1 (en) | Symmetrical layout structure of semiconductor device | |
| CN116094523B (en) | Compact capacitor arrangement method suitable for binary capacitor DAC |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |