CN116776782A - Metal level EDA display module and method in integrated circuit process manual - Google Patents

Metal level EDA display module and method in integrated circuit process manual Download PDF

Info

Publication number
CN116776782A
CN116776782A CN202311075960.XA CN202311075960A CN116776782A CN 116776782 A CN116776782 A CN 116776782A CN 202311075960 A CN202311075960 A CN 202311075960A CN 116776782 A CN116776782 A CN 116776782A
Authority
CN
China
Prior art keywords
metal
metal layer
layers
layer
rule
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202311075960.XA
Other languages
Chinese (zh)
Other versions
CN116776782B (en
Inventor
黄国勲
黄艳
唐明帅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ningbo Lianfang Electronic Technology Co ltd
Original Assignee
Ningbo Lianfang Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ningbo Lianfang Electronic Technology Co ltd filed Critical Ningbo Lianfang Electronic Technology Co ltd
Priority to CN202311075960.XA priority Critical patent/CN116776782B/en
Publication of CN116776782A publication Critical patent/CN116776782A/en
Application granted granted Critical
Publication of CN116776782B publication Critical patent/CN116776782B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention discloses a metal level EDA display module and a display method in an integrated circuit process manual, comprising the following steps: the basic structure setting module: setting different technological parameters to set the metal layer structure; the rule generation module: according to the combination generation rule, the metal layers are arranged and combined to generate different metal layer combinations; a metal option display module; and counting and displaying different metal layer structures according to the metal layer combinations. Through set up the metal layer structure in foundation structure setting module to in rule generation module to the metal layer is arranged and is combined, generates different metal layer combinations, and demonstrate different metal layer combinations through the metal option display module, reduce data processing cost and inquiry degree of difficulty.

Description

Metal level EDA display module and method in integrated circuit process manual
Technical Field
The invention relates to the field of integrated circuit design, in particular to a metal-level EDA display module in an integrated circuit process manual and a display method.
Background
The modes of presentation in integrated circuit process manuals for metal level combinations are typically presented by numerical combination plus checkpointing. The number of the metal layer combinations is tens of, more than hundreds, the combinations are manually checked, the data processing is complicated, errors are easy to occur, the readability is very poor, and a user is very difficult to inquire the required layer combinations when referring to the use.
Disclosure of Invention
The invention aims to provide a metal-level EDA display module and a display method in an integrated circuit process manual, which can automatically generate different metal layer combinations for display, thereby reducing the data processing cost and the query difficulty.
The invention provides a metal level EDA display module in an integrated circuit process manual, comprising:
the basic structure setting module: inputting different technological parameters to set the metal layer structure;
the rule generation module: according to the combination generation rule, arranging and combining the metal layers to generate different metal layer combinations;
a metal option display module; and counting and displaying different metal layer combinations to obtain different metal layer structures.
Further, the process parameters include at least one of the number and thickness of the inner metal layers, the number and thickness of the top metal layers, the structure of the capacitor layers, and the number and thickness of the aluminum plasma metal layers.
Further, the system also comprises a filling display module, wherein the filling display module divides different graphic primitive displays for the metal layers with different process parameters.
Further, the metal layer with any thickness corresponds to one primitive color and primitive height.
Further, the combination generation rule comprises a basic combination generation rule;
and obtaining the basic arrangement combination of the metal layers by taking the technological parameters as the reference according to the basic combination generation rule.
Further, the combination generation rule further comprises a layer-dropping rule;
after the basic arrangement and combination of the metal layers are obtained by taking the technological parameters as the reference,
deleting the internal metal layer according to the layer-reducing rule to obtain 2 n -1 group of internal metal layer combinations, wherein n is the number of internal metal layers;
deleting the top metal layer according to the layer descending rule to obtain m groups of top metal layer combinations, wherein m is the number of layers of the top metal layer;
combining the internal metal layer combination processed by the layer-reducing rule with the top metal layer combination to obtainAnd combining the group metal layers.
Further, the combination generation rule further comprises an insertion rule;
and sequentially inserting capacitor layers between the inner metal layers and the top metal layers which are processed by the layer-lowering rule based on the insertion rule, wherein the number of the inserted capacitor layers is n-1, and n is the number of layers of the inner metal layers.
The invention also provides a metal level EDA display method in the integrated circuit process manual, which adopts the metal level EDA display module in the integrated circuit process manual, and comprises the following steps:
inputting different technological parameters to set the metal layer structure;
according to the combination generation rule, arranging and combining the metal layers to generate different metal layer combinations;
and counting and displaying different metal layer combinations to obtain different metal layer structures.
Further, the number and thickness of the internal metal layers, the number and thickness of the top metal layer, the structure supported by the capacitor layer, and the thickness of the aluminum plasma metal layer are set, respectively.
Further, after the metal layer structures are set by inputting different process parameters, the filling display module divides different graphic elements for displaying the metal layers with different structures, and a connecting layer is automatically filled between every two metal layers.
Further, the following operation steps are adopted to arrange and combine the metal layers;
defining corresponding level information according to the metal layer structure;
obtaining basic arrangement combination of the metal layers by taking different technological parameters of the metal layers as references;
performing layer-reducing treatment on the basic arrangement combination;
if the capacitor layer exists, inserting the capacitor layer into the metal layer after the delamination treatment according to an insertion rule;
and after the metal layers are arranged and combined according to the combination generation rule, importing the result into a metal option display module.
Further, deleting the internal metal layers according to the layer-dropping rule, allowing any one of the internal metal layers to be deleted, wherein the number of the remaining internal metal layers is greater than or equal to 1, and obtaining 2 n -1 group of internal metal layer combinations, wherein n is the number of internal metal layers;
deleting the top metal layer according to the layer descending rule, and deleting from the top layer of the top metal layer to obtain m groups of top metal layer combinations, wherein m is the number of layers of the top metal layer;
combining the internal metal layer combination processed by the layer-reducing rule with the top metal layer combination to obtainAnd combining the group metal layers.
Further, the capacitor layers are sequentially inserted between the inner metal layers and the top metal layers after being processed by the layer-dropping rule based on the insertion rule, wherein the number of the capacitor layers allowed to be inserted is n-1, and n is the number of layers of the inner metal layers.
Further, in any of the metal layer structures, the thickness of the metal layer located above is greater than the thickness of the metal layer located below.
Compared with the prior art, the invention has at least the following technical effects:
according to the invention, the metal layer structure is arranged in the basic structure setting module, the metal layers are arranged and combined in the rule generating module to generate different metal layer combinations, and the different metal layer combinations are displayed through the metal option display module, so that the metal layer structure is finally derived, and the data processing cost and the query difficulty are reduced.
According to the invention, the metal layer with any thickness corresponds to one primitive color and primitive height, and the metal layers with different thicknesses are classified in the metal option display module by different colors, so that the readability of the metal hierarchy combination display is improved.
Drawings
Fig. 1 is a schematic structural diagram of a filling display module for displaying primitives according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram showing the structure of a metal option display module according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a metal level EDA display method in an integrated circuit process manual according to a second embodiment of the present invention;
fig. 4 is another schematic diagram of a metal level EDA display method in an integrated circuit process manual according to a second embodiment of the present invention.
Detailed Description
The metal-level EDA display module and display method of the integrated circuit process manual of the present invention will be described in more detail with reference to the drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Example 1
The embodiment provides a metal level EDA display module in an integrated circuit process manual, comprising:
the basic structure setting module: different process parameters are set to set the metal layer structure.
The rule generation module: and (5) arranging and combining the metal layers according to a combination generation rule to generate different metal layer combinations.
A metal option display module; and counting and displaying different metal layer combinations to obtain different metal layer structures.
Specifically, thickness information and other process parameters need to be set for each metal layer. The technological parameters include: the number and thickness of the Inner Metal layer (Inner Metal), the number and thickness of the Top Metal layer (Top Metal), where the Inner Metal layer and Top Metal layer allow the same Metal layer to set multiple thickness information, the structure of the capacitor layer (MIM), including single layer masking and double layer masking, and the number and thickness of the aluminum plasma Metal layer (ALPA). Further, the infrastructure setting module automatically fills parameters such as a connection layer (Via), a connection Contact (Contact), a flat electrode layer (Plate), and a thin film protection layer (Poly).
According to the embodiment, the metal layer structure is arranged in the base structure setting module, the metal layers are arranged and combined in the rule generating module, different metal layer combinations are generated, and the different metal layer combinations are displayed through the metal option display module, so that the data processing cost and the query difficulty are reduced.
Further, the system also comprises a filling display module, wherein the filling display module divides different primitives for the metal layers with different process parameters.
In the filling display module, the height of the metal layer is in a certain relation with the thickness of the metal layer, and the larger the thickness is, the higher the primitive height is; the filling color of the graphic primitive also has a relation with the set thickness, each thickness corresponds to one color, and the color of Via is consistent with the color of the corresponding metal layer. It can be understood that different graphic element display modes are set according to specific needs to distinguish metal layers with different thicknesses or other different parameters.
Referring to fig. 1, after process parameters are set in the infrastructure setting module, the filling display module displays a Metal layer structure having 4 layers of Inner Metal (Metal 1, metal2, metal3, and Metal 4), 3 layers of Top Metal (Top Metal1, top Metal2, and Top Metal 3), two MIMs, and ALPA. The Inner Metal layer and the Top Metal layer have different thicknesses, and are displayed in the filling display module in different colors, the Via layer is consistent with the corresponding Inner Metal layer or Top Metal layer in color, and the ALPA, MIN, plate and Poly layers can be displayed in colors different from the Inner Metal layer and the Top Metal layer.
And in the rule generation module, corresponding level information is defined according to the metal layer structure. For example, the inner metal layers are set to A1, A2, A3, and the top metal layers are set to B1, B2, B3. Different metal layers can be corresponding to different hierarchical numbers according to actual conditions.
And obtaining basic arrangement and combination of the metal layers according to basic combination generation rules and taking different technological parameters of the metal layers as references.
In a specific example, let a refer to the inner metal layer and B refer to the top metal layer. The combination between the inner metal layer and the top metal layer of the foundation, from which the foundation can be derived, is as follows: a1 A2, A3, A4, B1, B2, B3 (the self-filling connection layer will fill between the inner metal layer and the top metal layer).
After the system displays the basic permutation and combination, the basic permutation and combination is subjected to layer-reducing treatment, and the specific operation steps are as follows:
after the basic arrangement combination of the metal layers is obtained by taking the technological parameters as the reference, deleting the internal metal layers according to the layer-reducing rule to obtain 2 n -1 group of internal metal layer combinations, wherein n is the number of internal metal layers.
And deleting the top metal layer according to the layer-dropping rule to obtain m groups of top metal layer combinations, wherein m is the number of layers of the top metal layer.
Combining the internal metal layer combination processed by the layer-reducing rule with the top metal layer combination to obtainAnd combining the group metal layers.
And inserting any capacitor layer between the inner metal layer and the top metal layer according to the insertion rule, wherein the number of the inserted capacitor layers is n-1, and n is the number of the inner metal layers. Sequentially inserting the capacitor layer positions into the Metal combined data generated by the layer-reducing rule, wherein the inserted positions are required to meet the position requirements, and skipping if the capacitor layer positions are not met or are not existed.
If the metal layers have multiple thicknesses, different metal layer thicknesses are brought into the combination generation rule, and different metal layer combinations can be generated.
And finally, in the obtained metal layer structure, the thickness of the metal layer positioned above is larger than that of the metal layer positioned below. Ensuring good connection between the metal layers and being able to conduct current and signals efficiently.
After the rule production module is set to finish different metal layer combinations, a metal option display module is used; different combinations of metal layers are divided and shown.
In this example, the metal option display module includes a metal option display table. In a specific example, referring to fig. 2, the first column (Metal Select) of the Metal option display table may pick up the required Metal layer structure, the second column (Combination Total Metal) represents the total number of Metal layers, the third column (Combination Top Metal) represents the total number of top Metal layers, the fourth column (Metal/Via thin), the fifth column (Metal/Via thin 2), the sixth column (Metal/Via thin 3), the seventh column (Metal/Via thin 4) and the eighth column (ALPA thin 1) represent the number of the respective automatic filling connection layers and the aluminum plasma Metal layers with different thicknesses with different colors, respectively, and the ninth column displays the Metal layer combinations with different thicknesses. (wherein M1 represents a first layer Inner Metal, M2 represents a second layer Inner Metal, and so on, V1 represents a first layer Via, V2 represents a second layer Via, and so on, P1 represents a first layer flat electrode layer.) whereby the number of Metal option display table rows represents the number of combinations of Metal layers of different thicknesses. It will be appreciated that the structure of the metal option display is not limited to the above, and may be set according to specific needs. In addition, setting different process parameters will control each column to derive different parameters, ultimately controlling the generation of different metal layer structures.
In this embodiment, the metal layers with any thickness correspond to one primitive color and primitive height, and the metal layers with different thicknesses are classified in the metal option display module by different colors, so as to improve the readability of the metal hierarchy during combined display.
Example two
The present embodiment provides a metal level EDA display method in an integrated circuit process manual, which adopts the metal level EDA display module in the integrated circuit process manual in the first embodiment, please refer to FIG. 3, and the method includes:
s1, setting different process parameters to set the metal layer structure.
S2, arranging and combining the metal layers according to a combination generation rule to generate different metal layer combinations.
S3, a metal option display module; and counting and displaying different metal layer combinations to obtain different metal layer structures.
Further, the metal layer structure will be displayed within a filled display module that divides different primitives for the metal layers of different structures. The metal layer of any thickness corresponds to one primitive color and primitive height.
After setting related parameters, inputting different technological parameters to set a metal layer structure, dividing different graphic elements for different metal layers by a filling display module, and automatically filling a connecting layer between every two metal layers.
And the rule generating module automatically performs permutation and combination on the metal layers according to the combination generating rule to generate different metal layer combinations. Referring to fig. 4, the steps are as follows:
s11, defining corresponding level information according to the metal layer structure.
S22, obtaining basic arrangement combination of the metal layers by taking different technological parameters of the metal layers as references.
S33, carrying out layer reduction treatment on the basic arrangement combination.
S44, if the capacitor layer exists, inserting the capacitor layer into the metal layer after the delamination treatment according to an insertion rule.
S55, after the metal layers are arranged and combined according to the combination generation rule, the result is led into a metal option display module.
The specific operation steps are as described in the first embodiment, and will not be described herein.
Finally, the metal layer structure is derived by the metal option display module.
In summary, in this embodiment, a metal layer structure is set in the base structure setting module, and the metal layers are arranged and combined in the rule generating module, so as to generate different metal layer combinations, and the different metal layer combinations are displayed by the metal option display module, so that the data processing cost and the query difficulty are reduced. Furthermore, in this embodiment, the metal layers with any thickness correspond to one primitive color and primitive height, and the metal layers with different thicknesses are classified in the metal option display module by different colors, so that the readability of the metal hierarchy combination display is improved.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (14)

1. A metal level EDA display module in an integrated circuit process manual comprising:
the basic structure setting module: inputting different technological parameters to set the metal layer structure;
the rule generation module: according to the combination generation rule, arranging and combining the metal layers to generate different metal layer combinations;
a metal option display module; and counting and displaying different metal layer combinations to obtain different metal layer structures.
2. The integrated circuit process manual metal level EDA display module of claim 1,
the process parameters include at least one of the number and thickness of the inner metal layers, the number and thickness of the top metal layers, the structure of the capacitor layers, and the number and thickness of the aluminum plasma metal layers.
3. The metal-level EDA display module of claim 1 further comprising a fill display module dividing different primitive displays for the metal layers of different process parameters.
4. The metal level EDA display module of claim 3 wherein the metal layer of any thickness corresponds to one primitive color and primitive height.
5. The metal-level EDA display module of claim 1 or 2, wherein the combinatorial generation rules comprise basic combinatorial generation rules;
and obtaining the basic arrangement combination of the metal layers by taking the technological parameters as the reference according to the basic combination generation rule.
6. The metal-level EDA display module of claim 5, wherein the combinatorial generation rule further comprises a de-layering rule;
after the basic arrangement and combination of the metal layers are obtained by taking the technological parameters as the reference,
deleting the internal metal layer according to the layer-reducing rule to obtain 2 n -1 group of internal metal layer combinations, wherein n is the number of internal metal layers;
deleting the top metal layer according to the layer descending rule to obtain m groups of top metal layer combinations, wherein m is the number of layers of the top metal layer;
the internal metal layer processed by the layer-reducing rule is processedCombining the combination with the top metal layer combination to obtainAnd combining the group metal layers.
7. The metal-level EDA display module in an integrated circuit process book of claim 6, wherein the combinatorial generation rule further comprises an insertion rule;
and sequentially inserting capacitor layers between the inner metal layers and the top metal layers which are processed by the layer-lowering rule based on the insertion rule, wherein the number of the inserted capacitor layers is n-1, and n is the number of layers of the inner metal layers.
8. A metal level EDA display method in an integrated circuit process manual employing a metal level EDA display module in an integrated circuit process manual according to any one of claims 1 to 7, the method comprising:
inputting different technological parameters to set the structure of the metal layer;
according to the combination generation rule, arranging and combining the metal layers to generate different metal layer combinations;
and counting and displaying different metal layer combinations to obtain different metal layer structures.
9. The method for metal level EDA display in an integrated circuit process manual according to claim 8,
the number of layers and thickness of the inner metal layer, the number of layers and thickness of the top metal layer, the capacitor layer structure and the number of layers and thickness of the aluminum plasma metal layer are respectively set.
10. The method for metal level EDA display in an integrated circuit process manual according to claim 8,
after the metal layer structures are set by inputting different technological parameters, the filling display module divides different graphic elements for the metal layers with different structures for display, and a connecting layer is automatically filled between every two metal layers.
11. The method of claim 8, wherein the metal layers are arranged and combined using the following steps;
defining corresponding level information according to the metal layer structure;
obtaining basic arrangement combination of the metal layers by taking different technological parameters of the metal layers as references;
performing layer-reducing treatment on the basic arrangement combination;
if the capacitor layer exists, inserting the capacitor layer into the metal layer after the delamination treatment according to an insertion rule;
and after the metal layers are arranged and combined according to the combination generation rule, importing the result into a metal option display module.
12. The method for metal level EDA display in an integrated circuit process manual according to claim 11,
deleting the inner metal layers according to the layer-dropping rule, allowing any one of the inner metal layers to be deleted, wherein the number of the remaining inner metal layers is greater than or equal to 1, and obtaining 2 n -1 group of internal metal layer combinations, wherein n is the number of internal metal layers;
deleting the top metal layer according to the layer descending rule, and deleting from the top layer of the top metal layer to obtain m groups of top metal layer combinations, wherein m is the number of layers of the top metal layer;
combining the internal metal layer combination processed by the layer-reducing rule with the top metal layer combination to obtainAnd combining the group metal layers.
13. The method for metal level EDA display in an integrated circuit process manual according to claim 11,
and sequentially inserting the capacitor layers between the inner metal layers and the top metal layers which are processed by the layer descending rule based on the insertion rule, wherein the number of the capacitor layers which are allowed to be inserted is n-1, and n is the number of layers of the inner metal layers.
14. The method of claim 8, wherein in any of the metal layer structures, the thickness of the metal layer above is greater than the thickness of the metal layer below.
CN202311075960.XA 2023-08-25 2023-08-25 Metal level EDA display device and method in integrated circuit process manual Active CN116776782B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311075960.XA CN116776782B (en) 2023-08-25 2023-08-25 Metal level EDA display device and method in integrated circuit process manual

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311075960.XA CN116776782B (en) 2023-08-25 2023-08-25 Metal level EDA display device and method in integrated circuit process manual

Publications (2)

Publication Number Publication Date
CN116776782A true CN116776782A (en) 2023-09-19
CN116776782B CN116776782B (en) 2023-11-10

Family

ID=88013800

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311075960.XA Active CN116776782B (en) 2023-08-25 2023-08-25 Metal level EDA display device and method in integrated circuit process manual

Country Status (1)

Country Link
CN (1) CN116776782B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060064656A1 (en) * 2004-09-22 2006-03-23 Viswanathan Lakshmanan Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design
CN103164568A (en) * 2012-12-04 2013-06-19 天津蓝海微科技有限公司 Vector testing reusable generating method aimed at different processes of metal layer in territory validation rule
US8954913B1 (en) * 2013-10-01 2015-02-10 Globalfoundries Inc. Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules
CN109459910A (en) * 2018-11-22 2019-03-12 上海华力集成电路制造有限公司 For the Sub-resolution assist features setting method of metal layer process hot spot
CN113051868A (en) * 2021-04-02 2021-06-29 黄国勳 DRC automatic interface realization method for integrated circuit manufacturing process rule verification
CN115117016A (en) * 2021-05-27 2022-09-27 台湾积体电路制造股份有限公司 Integrated circuit and method of manufacturing the same
CN116487362A (en) * 2022-12-30 2023-07-25 苏州华太电子技术股份有限公司 Encapsulation structure of electronic device and manufacturing method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060064656A1 (en) * 2004-09-22 2006-03-23 Viswanathan Lakshmanan Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design
CN103164568A (en) * 2012-12-04 2013-06-19 天津蓝海微科技有限公司 Vector testing reusable generating method aimed at different processes of metal layer in territory validation rule
US8954913B1 (en) * 2013-10-01 2015-02-10 Globalfoundries Inc. Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules
CN109459910A (en) * 2018-11-22 2019-03-12 上海华力集成电路制造有限公司 For the Sub-resolution assist features setting method of metal layer process hot spot
CN113051868A (en) * 2021-04-02 2021-06-29 黄国勳 DRC automatic interface realization method for integrated circuit manufacturing process rule verification
CN115117016A (en) * 2021-05-27 2022-09-27 台湾积体电路制造股份有限公司 Integrated circuit and method of manufacturing the same
CN116487362A (en) * 2022-12-30 2023-07-25 苏州华太电子技术股份有限公司 Encapsulation structure of electronic device and manufacturing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
卢普生;李雪;范忠;吕冬琴;李天真;张立夫;: "一种能提高DRC友好性和CMP形貌的冗余金属填充方法", 中国集成电路, no. 06 *

Also Published As

Publication number Publication date
CN116776782B (en) 2023-11-10

Similar Documents

Publication Publication Date Title
JP5851607B2 (en) Kanji composition method and apparatus, character composition method and apparatus, and font library construction method
US11630534B2 (en) Wiring structure, manufacturing method thereof, and display device
CN109686307B (en) Gamma reference voltage generation method and device, display panel and display device
US20050015740A1 (en) Design for manufacturability
CN104238885B (en) The method and device that a kind of autoplacement shown suitable for more equipment contents and content are shown
JP6263897B2 (en) Information processing apparatus, information processing method, and program
WO2006013582A2 (en) A method and system for pixel based rendering of multi-lingual characters from a combination of glyphs
WO2019126032A1 (en) Integrated circuit (ic) design methods using engineering change order (eco) cell architectures
Nguyen et al. Visualizing tags with spatiotemporal references
US20140320539A1 (en) Semantic zoom-in or drill-down in a visualization having cells with scale enlargement and cell position adjustment
EP3905125A2 (en) Method and apparatus for recommending chart, electronic device, and storage medium
CN116776782B (en) Metal level EDA display device and method in integrated circuit process manual
CN110706313A (en) Method for dynamically generating picture
CN106129065A (en) A kind of array base palte and preparation method thereof, display floater
CN106055535A (en) Method and device for generating charts
CN1906617A (en) Method and apparatus for performing power routing on a voltage island within an integrated circuit chip
CN106874543B (en) LEF graph processing method of layout
CN103838898A (en) New arc-shaped wiring method
CN112256255A (en) Dynamic configuration display method and system for map layer of electronic map
CN105487684B (en) The output intent of Chinese-character phonetic letter character and the output device of Chinese-character phonetic letter character
CN109544661B (en) Area map drawing method, apparatus, computer device and storage medium
JP2002216143A (en) Display method of digital map and digital map system
TWI792750B (en) Correction coefficient compression method for self-luminous display screen, display driver chip, display device and information processing device
CN103425627A (en) Method for generating stroke and method for generating font
CN116719597B (en) Self-adaptive view rendering method and creation method based on grid layout

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant