CN116774014A - Multi-task chip test system and multi-task chip test method - Google Patents
Multi-task chip test system and multi-task chip test method Download PDFInfo
- Publication number
- CN116774014A CN116774014A CN202311047723.2A CN202311047723A CN116774014A CN 116774014 A CN116774014 A CN 116774014A CN 202311047723 A CN202311047723 A CN 202311047723A CN 116774014 A CN116774014 A CN 116774014A
- Authority
- CN
- China
- Prior art keywords
- test
- control module
- task
- chip
- tested
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 778
- 238000010998 test method Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 47
- 238000004891 communication Methods 0.000 claims abstract description 27
- 238000004364 calculation method Methods 0.000 claims description 35
- 238000013135 deep learning Methods 0.000 claims description 12
- 238000012549 training Methods 0.000 claims description 5
- 238000009434 installation Methods 0.000 claims description 3
- 238000012795 verification Methods 0.000 description 10
- 238000013528 artificial neural network Methods 0.000 description 2
- 238000013527 convolutional neural network Methods 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The application provides a multi-task chip testing system, comprising: the first control module is pre-provided with a first database and a first task set; the second control module is provided with a second database and a second task set; acquiring the type and the characteristic of a chip to be tested, and presetting test tasks corresponding to the type and the characteristic of the chip to be tested in a first task set and a second task set; the first control module and the second control module read the types and the characteristics of the chip to be tested, acquire test tasks from the first task set and the second task set, read test data of a first database and a second database corresponding to the test tasks, drive the test tasks to test according to the test data, and send test results to the upper computer through the communication module. The first control module and the second control module respectively execute different test tasks, so that mutual interference in the process that a single control module executes a plurality of test tasks is avoided.
Description
Technical Field
The application relates to the field of chip testing, in particular to a multi-task chip testing system and a multi-task chip testing method.
Background
In recent decades, the performance of a chip can be doubled every 18 months in the semiconductor industry according to moore's law, and along with the continuous improvement of the performance of the chip, the quality requirement on the chip is more and more strict, especially the high-end chip is often lower in yield, so that the chip also needs to be detected after production, and various prior art schemes exist in the field of chip testing.
The chip detection scheme of a single calculation control unit is the most widely used scheme at present, and the scheme adopts the single calculation control unit to control the whole chip detection process, including the control of measurement items and measurement progress.
Although this approach is simple to operate, it is inefficient in handling complex test tasks because a single computational control unit needs to control multiple tasks simultaneously.
Disclosure of Invention
The embodiment of the application aims to provide a multi-task chip testing system and a multi-task chip testing method, which are used for achieving the technical effect of improving the testing efficiency of multiple testing tasks of a chip to be tested.
The embodiment of the application provides a multi-task chip testing system, which comprises a first control module, a second control module and a first control module, wherein the first control module is pre-provided with a first database and a first task set; the second control module is preset with a second database and a second task set, and the setting mode of the first task set and the second task set is as follows: acquiring the type and the characteristic of a chip to be tested, and presetting test tasks corresponding to the type and the characteristic of the chip to be tested in the first task set and the second task set, wherein the first database is different from the second database, and the first task set is different from the second task set; the circuit board is provided with an installation groove of a chip to be tested, is provided with a communication module and is in communication connection with the upper computer; the first control module reads the type and the characteristic of the chip to be tested and acquires a specified first test task from the first task set, the first control module reads first test data of the first database corresponding to the first test task, and the first control module drives the first test task to test according to the first test data; the second control module reads the type and the characteristic of the chip to be tested and acquires a specified second test task from the second task set, the second control module reads second test data of the second test task corresponding to the second database, the second control module drives the second test task to test according to the second test data, and the first control module and the second control module send test results to the upper computer through the communication module.
In the implementation process, the type and the characteristic of the chip to be tested are obtained first, the test tasks corresponding to the type and the characteristic of the chip to be tested are respectively preset in the first task set and the second task set, and the characteristic of the chip to be tested comprises: performance metrics, interface standards, power consumption characteristics, etc. The first database is preset with first test data required by the first task set, the second database is preset with second test data required by the second task set, the first database is different from the second database, and the first task set is different from the second task set. The first control module and the second control module are arranged on the circuit board and can be detachably connected with the circuit board, the circuit board is also provided with a mounting groove of a chip to be tested, and the upper computer is communicated with the circuit board through a communication module on the circuit board. Before starting the test, the first control module and the second control module are required to be inserted on the circuit board, after the chip to be tested, the first control module and the second control module are respectively connected with the circuit board, the upper computer issues a start test instruction to the first control module and the second control module, the first control module and the second control module read the type and the characteristic of the chip to be tested, and the first test task and the second test task corresponding to the first test task set and the second test task set are acquired respectively. The first control module and the second control module acquire corresponding required first test data and second test data from a first database and a second database respectively according to respective test tasks, the first control module and the second control module drive the corresponding test tasks to start testing according to the respective test data, the test mode is that the test data is input to the chip to be tested, the chip to be tested runs the test data and outputs the data, the upper computer compares the output data with preset verification data to verify whether the output data is consistent with the verification data, and if so, the test of the test task is proved to be correct. The first control module and the second control module send the test results to the upper computer in real time through the communication module, and all the test results are not required to be transmitted after the test tasks are completed. Different test tasks are respectively executed through the first control module and the second control module, the condition that mutual interference occurs in the process that a single control module executes a plurality of test tasks is avoided, the test efficiency can be improved through the plurality of control modules, the first control module and the second control module are configured to complete the test tasks corresponding to various chip types and characteristics, when different chips are tested, the corresponding control modules are only needed to be inserted, execution of the different test tasks is achieved, the control modules are not needed to be reconfigured, the configuration efficiency is improved, and accordingly the improvement of the test efficiency is jointly achieved.
In one possible implementation manner, the multi-task chip test system further includes: the storage module is arranged on the circuit board; the first control module transmits first test data, a first test task and a first test progress to the storage module, and the second control module transmits second test data, a second test task and a second test progress to the storage module; when the first control module is detached from the circuit board, the upper computer records the current first test progress, after the second test task is completed, the second control module reads the first test data, the first test task and the first test progress from the storage module, if the second control module can drive the first test task to test according to the first test data, the information for determining the execution can be sent to the upper computer, and the upper computer controls the second control module to continuously execute the rest first test tasks.
In the implementation process, the multi-task chip test system further comprises a storage module arranged on the circuit board, after the test is started, the first control module transmits the first test data, the first test task and the first test progress to the storage module, and the second control module transmits the second test data, the second test task and the second test progress to the storage module. When the first control module is detached from the circuit board, the upper computer records the current first test progress, after the second control module finishes the second test task of the upper computer, the second control module reads the first test data, the first test task and the first test progress from the storage module, as the hardware selection of the first control module and the hardware selection of the second control module may be different, such as a CPU (Central processing Unit), an FPGA (field programmable gate array), an MCU (micro-controller unit) and the like, the second control module may not run the first test task of the first control module, if the second control module can drive the corresponding first test task to test according to the first test data, the upper computer sends the determined executable information to the upper computer, the upper computer sends the first test progress of the first control module to the second control module, and the second control module continues to execute the rest first test tasks from the first test task disconnection position according to the first test data of the first control module. If the second control module is detached in the test process, the first control module executes the operation such as executing the steps as the second control module, that is, the first control module can continue to run the test task of the second control module under the condition of permission. In the actual test process, the situation that the first control module or the second control module is pulled out suddenly may occur, and the remaining control modules may attempt to continue to execute the test task of the pulled-out control module, so as to avoid retesting the test task of the control module after the control module is pulled out.
In one possible implementation manner, the multi-task chip test system further includes: the third control module is internally provided with a third database and a third task set in advance, and the third task set is set up in the following manner: the method comprises the steps of obtaining types and characteristics of chips to be tested, presetting test tasks corresponding to the types and the characteristics of the chips to be tested in a third task set, wherein the third database is different from the first database and the second database, the third task set is different from the first task set and the second task set, and the third control module can be multiple.
In the implementation process, the multi-task chip test system may further include a plurality of third control modules, a third database and a third task set are preset in the third control modules, a setting mode of the third task set is consistent with that of the first task set and the second task set, types and characteristics of chips to be tested are obtained, test tasks corresponding to the types and the characteristics of the chips to be tested are preset in the third task set, the third database is different from the first database and the second database, the third task set is different from the first task set and the second task set, the third control modules may be a plurality of third control modules, and test tasks executed by the plurality of third control modules may be the same or different. Through setting up a plurality of third control module, can accelerate the test to a plurality of test tasks, improve test efficiency.
In a possible implementation manner, the chip to be tested is preset with a calculation threshold, the upper computer detects that the current calculation force of the chip to be tested is higher than the calculation threshold, the third control module is connected with the circuit board, after the third control module finishes the appointed third test task, if the first control module does not complete the first test task, the third control module can drive the first test task to test according to the first test data, the upper computer sends the first test progress to the third control module, and the third control module and the first control module test the remaining first test tasks together.
In the implementation process, the power calculation threshold value is preset on the chip to be tested, when the upper computer detects that the current power calculation value of the chip to be tested is higher than the power calculation threshold value, the chip to be tested can test more test tasks at the same time, at the moment, a third control module is connected to the circuit board, and reads the type and the characteristics of the chip to be tested to obtain a corresponding third test task and third test data, and the third test task is driven according to the third test data. The first control module, the second control module and the third control module are unknown in that which one of the first control module, the second control module and the third control module completes the self-testing task at first, if the third control module completes the corresponding third testing task first, the first control module does not complete the self-testing task first, the third control module reads the first testing data, the first testing task and the first testing progress in the storage module, the third control module tries to drive the first testing task to test according to the first testing data, if the first testing task can run successfully, the upper computer sends the first testing progress to the third control module, and the third control module and the first control module test the remaining first testing tasks together. If the second control module is detached from the circuit board in the test process, the upper computer records the current test task of the second control module and the progress of the test task, after the third control module finishes the test task, the third control module reads the test data and the test task of the second control module from the storage module, if the third control module can drive the corresponding test task to test according to the test data of the second control module, the upper computer sends the progress of the test task of the second control module to the third control module, and the third control module continues to execute the residual test task from the test task disconnection position of the second control module according to the test data of the second control module. And similarly, the second control module does not complete the self-test task, and the third control module and the second control module can test the residual test task of the second control module together. After the first control module finishes the test tasks of the first control module, the first control module can also try to run the test tasks of the second control module and the third control module; after the second control module finishes the test tasks of the second control module, the second control module can also try to run the test tasks of the first control module and the third control module. When the calculation force of the chip to be tested is sufficient, more third control modules can be connected to run more test tasks, and as the time for each control module to complete the respective test tasks is different, the control module which completes the test tasks can assist other control modules to test, so that the test efficiency is further improved.
In one possible implementation manner, the multi-task chip test system further includes: acquiring the type and the characteristic of a chip to be tested; predicting a test task of the chip to be tested according to the type and the characteristic of the chip to be tested and by combining a prediction test task model constructed by a deep learning network; the method further comprises the following steps before the type and the characteristics of the chip to be tested are acquired: obtaining chip type samples to be tested of a plurality of sample test tasks, and obtaining chip characteristic samples to be tested of the plurality of sample test tasks; training the deep learning network according to the chip type samples to be tested of the sample test tasks and the chip characteristic samples to be tested of the sample test tasks to construct the prediction test task model, wherein the chip type samples to be tested, the chip characteristic samples to be tested and the prediction test task model are arranged in the first task set.
In the implementation process, the first task set may be set up through a deep learning network, for example, a convolutional neural network, a cyclic neural network, and the like, which is not limited thereto. The prediction test task model is formed by training a chip type sample to be tested and a chip characteristic sample to be tested, the chip type sample to be tested of a plurality of sample test tasks is obtained, the chip characteristic sample to be tested of the plurality of sample test tasks is obtained, a deep learning network is trained according to the chip type sample to be tested of the plurality of sample test tasks and the chip characteristic sample to be tested of the plurality of sample test tasks to construct a prediction test task model, after the prediction test task model is constructed, the type and the characteristic of the chip to be tested are obtained, the test task of the chip to be tested can be predicted by combining the prediction test task model, if the type and the characteristic of the chip to be tested are preset manually, the test task model can be predicted in a deep learning network mode, different test tasks can be tested more comprehensively, and the missing test of a certain test task can be avoided.
In one possible implementation manner, after the chip to be tested is tested, the priority order of the test tasks of the first control module is arranged, and the ordered first test tasks are stored in the first task set.
In the implementation process, after the chip to be tested is tested, the priority sequences of the test tasks of the first control module and the second control module can be arranged, parallelism and mutual influence among different test tasks need to be considered in the execution process of the test tasks, so that the execution sequence and time of the test tasks are optimized, the first test tasks arranged by the first control module are stored in the first task set, the second test tasks arranged by the second control module are stored in the second task set, and the test tasks can be sequentially tested according to the arranged task sequence when used next time, so that the mutual influence among different tasks is reduced. The arrangement of the test task sequence can be the arrangement sequence when only the first control module and the second control module exist simultaneously, and when other control modules, such as a third control module, are added, the sequence of the test tasks can be changed so as to reduce the mutual influence of the three test tasks.
In one possible implementation manner, the first control module and the second control module are detached from the circuit board after the test is completed, the third control module is connected with the circuit board, the third control module reads the type and the characteristic of the chip to be tested and obtains a specified third test task from the third task set, the third control module reads third test data of the third database corresponding to the third test task, and the third control module drives the third test task to test according to the third test data.
In the implementation process, the first control module and the second control module can be detached from the circuit board after being tested, the third control module can be inserted into the circuit board after being detached, the third control module reads the type and the characteristics of the chip to be tested and acquires the test tasks from the third task set, the third control module reads the test data of the third database corresponding to the test tasks, the third control module drives the test tasks to test according to the test data, the third control module is connected in an inserting mode, and when the test tasks of other control modules are completed, the replacement is more convenient.
In a second aspect, an embodiment of the present application provides a method for testing a multitask chip, where a first control module presets a first database and a first task set, a second control module presets a second database and a second task set, types and characteristics of chips to be tested are obtained, test tasks corresponding to the types and characteristics of the chips to be tested are preset in the first task set and the second task set, the first database is different from the second database, and the first task set is different from the second task set; the method comprises the steps that a chip to be tested is mounted on a circuit board with a communication module and a storage module and is in communication connection with an upper computer, a first control module reads the type and the characteristic of the chip to be tested and acquires a first test task from a first task set, the first control module reads first test data of a first database corresponding to the first test task, the first control module drives the first test task to test according to the first test data, a second control module reads the type and the characteristic of the chip to be tested and acquires a second test task from the second task set, the second control module reads second test data of the second database corresponding to the second test task, the second control module drives a second test task to test according to the second test data, and the first control module and the second control module send test results to the upper computer through the communication module; the first control module transmits first test data, a first test task and a first test progress to the storage module, the second control module transmits second test data, a second test task and a second test progress to the storage module, when the first control module is disassembled, the upper computer records the current first test progress, after the second test task is completed, the second control module reads the first test data, the first test task and the first test progress from the storage module and tries to run, if the first test progress can be run, the determined executable information is transmitted to the upper computer, and the upper computer controls the second control module to continuously execute the rest first test tasks; or, the power calculation threshold value is preset on the chip to be tested, the upper computer detects that the current power calculation of the chip to be tested is higher than the power calculation threshold value, the third control module is connected with the circuit board, and after the third control module finishes the appointed third test task, if the first control module does not complete the first test task, the third control module can drive the first test task to test according to the first test data, and the third control module and the first control module jointly test the residual first test task of the first control module.
In the implementation process, the type and the characteristic of the chip to be tested are obtained first, the test tasks corresponding to the type and the characteristic of the chip to be tested are respectively preset in the first task set and the second task set, and the characteristic of the chip to be tested comprises: performance metrics, interface standards, power consumption characteristics, etc. The first database is preset with first test data required by the first task set, the second database is preset with second test data required by the second task set, the first database is different from the second database, and the first task set is different from the second task set. The first control module and the second control module are arranged on the circuit board and can be detachably connected with the circuit board, the circuit board is also provided with a mounting groove of a chip to be tested, and the upper computer is communicated with the circuit board through a communication module on the circuit board. Before starting the test, the first control module and the second control module are required to be inserted on the circuit board, after the chip to be tested, the first control module and the second control module are respectively connected with the circuit board, the upper computer issues a start test instruction to the first control module and the second control module, the first control module and the second control module read the type and the characteristic of the chip to be tested, and corresponding test tasks are respectively acquired from the first test task set and the second test task set. The first control module and the second control module acquire corresponding required test data from the first database and the second database respectively according to the respective test tasks, the first control module and the second control module drive the corresponding test tasks to start testing according to the respective test data, the test mode is that the test data is input to the chip to be tested, the chip to be tested runs the test data and outputs the data, the upper computer compares the output data with preset verification data to verify whether the output data is consistent with the verification data, and the test of the test task is proved to be correct if the output data is consistent with the verification data. The first control module and the second control module send the test results to the upper computer in real time through the communication module, and all the test results are not required to be transmitted after the test tasks are completed. Different test tasks are respectively executed through the first control module and the second control module, the condition that mutual interference occurs in the process that a single control module executes a plurality of test tasks is avoided, the test efficiency can be improved through the plurality of control modules, the first control module and the second control module are configured to complete the test tasks corresponding to various chip types and characteristics, when different chips are tested, the corresponding control modules are only needed to be inserted, execution of the different test tasks is achieved, the control modules are not needed to be reconfigured, the configuration efficiency is improved, and accordingly the improvement of the test efficiency is jointly achieved. The multi-task chip test system also comprises a memory module arranged on the circuit board, after the test is started, the first control module transmits the test data in the first data and the corresponding test tasks to the memory module, and the second control module transmits the test data in the second data and the corresponding test tasks to the memory module. When the first control module is detached from the circuit board, the upper computer records the current test task of the first control module and the progress of the first test task, after the second control module finishes the test task, the second control module reads the first test data and the first test task of the first control module from the storage module, and as the selection of hardware of the first control module and the hardware of the second control module may be different, such as a CPU, an FPGA, an MCU and the like, the second control module may not operate the first test task of the first control module, if the second control module can drive the corresponding first test task to test according to the first test data of the first control module, the upper computer sends the first test task progress of the first control module to the second control module, and the second control module continues to execute the remaining first test task from the first test task disconnection position of the first control module according to the first test data of the first control module. If the second control module is detached during the test, the first control module performs the operation as described above, i.e. the first control module may also continue to run the second test task of the second control module if the conditions are available. In the actual test process, the situation that the first control module or the second control module is pulled out suddenly may occur, and the remaining control modules may attempt to continue to execute the test task of the pulled-out control module, so as to avoid retesting the test task of the control module after the control module is pulled out. The power calculation threshold value is preset on the chip to be tested, when the upper computer detects that the current power calculation value of the chip to be tested is higher than the power calculation threshold value, the chip to be tested can test more test tasks at the same time, at the moment, a third control module is connected to the circuit board, the third control module reads the type and the characteristics of the chip to be tested to obtain corresponding test tasks and test data, and the test tasks of the third control module are driven according to the test data of the third control module. The first control module transmits the first test data, the first test task and the first test progress to the storage module, the second control module transmits the second test data, the second test task and the second test progress to the storage module, and the third control module transmits the third test data, the third test task and the third test progress to the storage module. The first control module, the second control module and the third control module are unknown in that which one of the first control module, the second control module and the third control module completes the self-testing task at first, if the third control module completes the self-corresponding third testing task first, the first control module does not complete the self-corresponding third testing task, the third control module reads the first testing data of the first control module and the corresponding first testing task in the storage module, the third control module tries to drive the first testing task corresponding to the first control module according to the first testing data of the first control module, if the first control module can run successfully, the third control module reads the first testing task progress of the first control module, and the third control module and the first control module test the residual first testing task of the first control module together. If the second control module is detached from the circuit board in the test process, the upper computer records the current test task of the second control module and the progress of the test task, after the third control module finishes the test task, the third control module reads the test data and the test task of the second control module from the storage module, if the third control module can drive the corresponding test task to test according to the test data of the second control module, the upper computer sends the progress of the test task of the second control module to the third control module, and the third control module continues to execute the residual test task from the test task disconnection position of the second control module according to the test data of the second control module. And similarly, the second control module does not complete the self-test task, and the third control module and the second control module can test the residual test task of the second control module together. After the first control module finishes the test tasks of the first control module, the first control module can also try to run the test tasks of the second control module and the third control module; after the second control module finishes the test tasks of the second control module, the second control module can also try to run the test tasks of the first control module and the third control module. When the calculation force of the chip to be tested is sufficient, more third control modules can be connected to run more test tasks, and as the time for each control module to complete the respective test tasks is different, the control module which completes the test tasks can assist other control modules to test, so that the test efficiency is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a multi-task chip test system according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
In a first aspect, an embodiment of the present application provides a system for testing a multi-task chip, referring to fig. 1, a first control module is preset with a first database and a first task set; the second control module is preset with a second database and a second task set, and the setting mode of the first task set and the second task set is as follows: acquiring the type and the characteristic of a chip to be tested, presetting test tasks corresponding to the type and the characteristic of the chip to be tested in a first task set and a second task set, wherein the first database is different from the second database, and the first task set is different from the second task set; the circuit board is provided with an installation groove of a chip to be tested, is provided with a communication module and is in communication connection with the upper computer; the first control module reads the type and the characteristic of the chip to be tested and acquires a specified first test task from a first task set, the first control module reads first test data of a first database corresponding to the first test task, and the first control module drives the first test task to test according to the first test data; the second control module reads the type and the characteristic of the chip to be tested and acquires a designated second test task from the second task set, the second control module reads second test data of a second database corresponding to the second test task, the second control module drives the second test task to test according to the second test data, and the first control module and the second control module send test results to the upper computer through the communication module.
In the implementation process, the type and the characteristic of the chip to be tested are obtained first, the test tasks corresponding to the type and the characteristic of the chip to be tested are respectively preset in the first task set and the second task set, and the characteristic of the chip to be tested comprises: performance metrics, interface standards, power consumption characteristics, etc. The first database is preset with first test data required by the first task set, the second database is preset with second test data required by the second task set, the first database is different from the second database, and the first task set is different from the second task set. The first control module and the second control module are arranged on the circuit board and can be detachably connected with the circuit board, the circuit board is also provided with a mounting groove of a chip to be tested, and the upper computer is communicated with the circuit board through a communication module on the circuit board. Before starting the test, the first control module and the second control module are required to be inserted on the circuit board, after the chip to be tested, the first control module and the second control module are respectively connected with the circuit board, the upper computer issues a start test instruction to the first control module and the second control module, the first control module and the second control module read the type and the characteristic of the chip to be tested, and the first test task and the second test task corresponding to the first test task set and the second test task set are acquired respectively. The first control module and the second control module acquire corresponding required first test data and second test data from a first database and a second database respectively according to respective test tasks, the first control module and the second control module drive the corresponding test tasks to start testing according to the respective test data, the test mode is that the test data is input to the chip to be tested, the chip to be tested runs the test data and outputs the data, the upper computer compares the output data with preset verification data to verify whether the output data is consistent with the verification data, and if so, the test of the test task is proved to be correct. The first control module and the second control module send the test results to the upper computer in real time through the communication module, and all the test results are not required to be transmitted after the test tasks are completed. Different test tasks are respectively executed through the first control module and the second control module, the condition that mutual interference occurs in the process that a single control module executes a plurality of test tasks is avoided, the test efficiency can be improved through the plurality of control modules, the first control module and the second control module are configured to complete the test tasks corresponding to various chip types and characteristics, when different chips are tested, the corresponding control modules are only needed to be inserted, execution of the different test tasks is achieved, the control modules are not needed to be reconfigured, the configuration efficiency is improved, and accordingly the improvement of the test efficiency is jointly achieved.
In one possible implementation, the multi-tasking chip testing system further comprises: the storage module is arranged on the circuit board; the first control module transmits the first test data, the first test task and the first test progress to the storage module, and the second control module transmits the second test data, the second test task and the second test progress to the storage module; when the first control module is detached from the circuit board, the upper computer records the current first test progress, after the second test task is completed, the second control module reads the first test data, the first test task and the first test progress from the storage module, if the second control module can drive the first test task to test according to the first test data, the determined executable information is sent to the upper computer, and the upper computer controls the second control module to continuously execute the residual first test task.
In the implementation process, the multi-task chip test system further comprises a storage module arranged on the circuit board, after the test is started, the first control module transmits the first test data, the first test task and the first test progress to the storage module, and the second control module transmits the second test data, the second test task and the second test progress to the storage module. When the first control module is detached from the circuit board, the upper computer records the current first test progress, after the second control module completes the second test task of the upper computer, the second control module reads the first test data, the first test task and the first test progress from the storage module, and as the first control module and the second control module may have different hardware selections, such as a CPU, the field programmable gate array FPGA (Field Programmable Gate Array), the micro control unit MCU (Microcontroller Unit) and the like, the second control module may not run the first test task of the first control module, if the second control module can drive the corresponding first test task to test according to the first test data, the second control module sends the determined executable information to the upper computer, and the upper computer sends the first test progress of the first control module to the second control module, so that the second control module continues to execute the remaining first test tasks from the disconnected position of the first test task according to the first test data of the first control module. If the second control module is detached in the test process, the first control module executes the operation such as executing the steps as the second control module, that is, the first control module can continue to run the test task of the second control module under the condition of permission. In the actual test process, the situation that the first control module or the second control module is pulled out suddenly may occur, and the remaining control modules may attempt to continue to execute the test task of the pulled-out control module, so as to avoid retesting the test task of the control module after the control module is pulled out.
In one possible implementation, the multi-tasking chip testing system further comprises: the third control module is internally provided with a third database and a third task set in advance, and the third task set is set up in the following manner: the method comprises the steps of obtaining the type and the characteristic of a chip to be tested, presetting test tasks corresponding to the type and the characteristic of the chip to be tested in a third task set, wherein the third database is different from the first database and the second database, the third task set is different from the first task set and the second task set, and a plurality of third control modules can be arranged.
In the implementation process, the multi-task chip test system may further include a plurality of third control modules, a third database and a third task set are preset in the third control modules, a setting mode of the third task set is consistent with that of the first task set and the second task set, types and characteristics of chips to be tested are obtained, test tasks corresponding to the types and the characteristics of the chips to be tested are preset in the third task set, the third database is different from the first database and the second database, the third task set is different from the first task set and the second task set, the third control modules may be a plurality of third control modules, and test tasks executed by the plurality of third control modules may be the same or different. Through setting up a plurality of third control module, can accelerate the test to a plurality of test tasks, improve test efficiency.
In one possible implementation manner, the chip to be tested is preset with a calculation threshold, the upper computer detects that the current calculation force of the chip to be tested is higher than the calculation threshold, the third control module is connected with the circuit board, after the third control module finishes the appointed third test task, if the first control module does not complete the first test task, the third control module can drive the first test task to test according to the first test data, the upper computer sends the first test progress to the third control module, and the third control module and the first control module test the rest of the first test tasks together.
In the implementation process, the power calculation threshold value is preset on the chip to be tested, when the upper computer detects that the current power calculation value of the chip to be tested is higher than the power calculation threshold value, the chip to be tested can test more test tasks at the same time, at the moment, a third control module is connected to the circuit board, and reads the type and the characteristics of the chip to be tested to obtain a corresponding third test task and third test data, and the third test task is driven according to the third test data. The first control module, the second control module and the third control module are unknown in that which one of the first control module, the second control module and the third control module completes the self-testing task at first, if the third control module completes the corresponding third testing task first, the first control module does not complete the self-testing task first, the third control module reads the first testing data, the first testing task and the first testing progress in the storage module, the third control module tries to drive the first testing task to test according to the first testing data, if the first testing task can run successfully, the upper computer sends the first testing progress to the third control module, and the third control module and the first control module test the remaining first testing tasks together. If the second control module is detached from the circuit board in the test process, the upper computer records the current test task of the second control module and the progress of the test task, after the third control module finishes the test task, the third control module reads the test data and the test task of the second control module from the storage module, if the third control module can drive the corresponding test task to test according to the test data of the second control module, the upper computer sends the progress of the test task of the second control module to the third control module, and the third control module continues to execute the residual test task from the test task disconnection position of the second control module according to the test data of the second control module. And similarly, the second control module does not complete the self-test task, and the third control module and the second control module can test the residual test task of the second control module together. After the first control module finishes the test tasks of the first control module, the first control module can also try to run the test tasks of the second control module and the third control module; after the second control module finishes the test tasks of the second control module, the second control module can also try to run the test tasks of the first control module and the third control module. When the calculation force of the chip to be tested is sufficient, more third control modules can be connected to run more test tasks, and as the time for each control module to complete the respective test tasks is different, the control module which completes the test tasks can assist other control modules to test, so that the test efficiency is further improved.
In one possible implementation, the multi-tasking chip testing system further comprises: acquiring the type and the characteristic of a chip to be tested; predicting a test task of the chip to be tested according to the type and the characteristic of the chip to be tested and by combining a prediction test task model constructed by a deep learning network; the method further comprises the following steps before the type and the characteristics of the chip to be tested are acquired: obtaining chip type samples to be tested of a plurality of sample test tasks, and obtaining chip characteristic samples to be tested of the plurality of sample test tasks; training the deep learning network according to the chip type samples to be tested of the plurality of sample test tasks and the chip characteristic samples to be tested of the plurality of sample test tasks to construct a predictive test task model, wherein the chip type samples to be tested, the chip characteristic samples to be tested and the predictive test task model are arranged in a first task set.
In the implementation process, the first task set may be set up through a deep learning network, for example, a convolutional neural network, a cyclic neural network, and the like, which is not limited thereto. The prediction test task model is formed by training a chip type sample to be tested and a chip characteristic sample to be tested, the chip type sample to be tested of a plurality of sample test tasks is obtained, the chip characteristic sample to be tested of the plurality of sample test tasks is obtained, a deep learning network is trained according to the chip type sample to be tested of the plurality of sample test tasks and the chip characteristic sample to be tested of the plurality of sample test tasks to construct a prediction test task model, after the prediction test task model is constructed, the type and the characteristic of the chip to be tested are obtained, the test task of the chip to be tested can be predicted by combining the prediction test task model, if the type and the characteristic of the chip to be tested are preset manually, the test task model can be predicted in a deep learning network mode, different test tasks can be tested more comprehensively, and the missing test of a certain test task can be avoided.
In one possible implementation manner, after the chip to be tested is tested, the priority order of the test tasks of the first control module is arranged, and the ordered first test tasks are stored in the first task set.
In the implementation process, after the chip to be tested is tested, the priority sequences of the test tasks of the first control module and the second control module can be arranged, parallelism and mutual influence among different test tasks need to be considered in the execution process of the test tasks, so that the execution sequence and time of the test tasks are optimized, the first test tasks arranged by the first control module are stored in the first task set, the second test tasks arranged by the second control module are stored in the second task set, and the test tasks can be sequentially tested according to the arranged task sequence when used next time, so that the mutual influence among different tasks is reduced. The arrangement of the test task sequence can be the arrangement sequence when only the first control module and the second control module exist simultaneously, and when other control modules, such as a third control module, are added, the sequence of the test tasks can be changed so as to reduce the mutual influence of the three test tasks.
In one possible implementation manner, the first control module and the second control module are detached from the circuit board after the test is completed, the third control module is connected with the circuit board, the third control module reads the type and the characteristic of the chip to be tested and obtains the appointed third test task from the third task set, the third control module reads the third test data of the third database corresponding to the third test task, and the third control module drives the third test task to test according to the third test data.
In the implementation process, the first control module and the second control module can be detached from the circuit board after being tested, the third control module can be inserted into the circuit board after being detached, the third control module reads the type and the characteristics of the chip to be tested and acquires the test tasks from the third task set, the third control module reads the test data of the third database corresponding to the test tasks, the third control module drives the test tasks to test according to the test data, the third control module is connected in an inserting mode, and when the test tasks of other control modules are completed, the replacement is more convenient.
In a second aspect, an embodiment of the present application provides a method for testing a multitask chip, where a first control module presets a first database and a first task set, a second control module presets a second database and a second task set, types and characteristics of a chip to be tested are obtained, test tasks corresponding to the types and characteristics of the chip to be tested are preset in the first task set and the second task set, the first database is different from the second database, and the first task set is different from the second task set;
the method comprises the steps that a chip to be tested is mounted on a circuit board with a communication module and a storage module and is in communication connection with an upper computer, a first control module reads the type and the characteristic of the chip to be tested and acquires a first test task from a first task set, the first control module reads first test data of a first database corresponding to the first test task, the first control module drives the first test task to test according to the first test data, a second control module reads the type and the characteristic of the chip to be tested and acquires a second test task from a second task set, the second control module reads second test data of a second database corresponding to the second test task, the second control module drives the second test task to test according to the second test data, and the first control module and the second control module send test results to the upper computer through the communication module;
The first control module transmits the first test data, the first test task and the first test progress to the storage module, the second control module transmits the second test data, the second test task and the second test progress to the storage module, when the first control module is disassembled, the upper computer records the current first test progress, after the second test task is completed, the second control module reads the first test data, the first test task and the first test progress from the storage module and tries to run, if the operation is possible, the determined executable information is transmitted to the upper computer, and the upper computer controls the second control module to continuously execute the rest first test tasks; or, the power calculation threshold value is preset on the chip to be tested, the upper computer detects that the current power calculation of the chip to be tested is higher than the power calculation threshold value, the third control module is connected with the circuit board, and after the third control module finishes the appointed third test task, if the first control module does not complete the first test task, the third control module can drive the first test task to test according to the first test data, and the third control module and the first control module jointly test the residual first test task of the first control module.
In the implementation process, the type and the characteristic of the chip to be tested are obtained first, the test tasks corresponding to the type and the characteristic of the chip to be tested are respectively preset in the first task set and the second task set, and the characteristic of the chip to be tested comprises: performance metrics, interface standards, power consumption characteristics, etc. The first database is preset with first test data required by the first task set, the second database is preset with second test data required by the second task set, the first database is different from the second database, and the first task set is different from the second task set. The first control module and the second control module are arranged on the circuit board and can be detachably connected with the circuit board, the circuit board is also provided with a mounting groove of a chip to be tested, and the upper computer is communicated with the circuit board through a communication module on the circuit board. Before starting the test, the first control module and the second control module are required to be inserted on the circuit board, after the chip to be tested, the first control module and the second control module are respectively connected with the circuit board, the upper computer issues a start test instruction to the first control module and the second control module, the first control module and the second control module read the type and the characteristic of the chip to be tested, and corresponding test tasks are respectively acquired from the first test task set and the second test task set. The first control module and the second control module acquire corresponding required test data from the first database and the second database respectively according to the respective test tasks, the first control module and the second control module drive the corresponding test tasks to start testing according to the respective test data, the test mode is that the test data is input to the chip to be tested, the chip to be tested runs the test data and outputs the data, the upper computer compares the output data with preset verification data to verify whether the output data is consistent with the verification data, and the test of the test task is proved to be correct if the output data is consistent with the verification data. The first control module and the second control module send the test results to the upper computer in real time through the communication module, and all the test results are not required to be transmitted after the test tasks are completed. Different test tasks are respectively executed through the first control module and the second control module, the condition that mutual interference occurs in the process that a single control module executes a plurality of test tasks is avoided, the test efficiency can be improved through the plurality of control modules, the first control module and the second control module are configured to complete the test tasks corresponding to various chip types and characteristics, when different chips are tested, the corresponding control modules are only needed to be inserted, execution of the different test tasks is achieved, the control modules are not needed to be reconfigured, the configuration efficiency is improved, and accordingly the improvement of the test efficiency is jointly achieved. The multi-task chip test system also comprises a memory module arranged on the circuit board, after the test is started, the first control module transmits the test data in the first data and the corresponding test tasks to the memory module, and the second control module transmits the test data in the second data and the corresponding test tasks to the memory module. When the first control module is detached from the circuit board, the upper computer records the current test task of the first control module and the progress of the first test task, after the second control module finishes the test task, the second control module reads the first test data and the first test task of the first control module from the storage module, and as the selection of hardware of the first control module and the hardware of the second control module may be different, such as a CPU, an FPGA, an MCU and the like, the second control module may not operate the first test task of the first control module, if the second control module can drive the corresponding first test task to test according to the first test data of the first control module, the upper computer sends the first test task progress of the first control module to the second control module, and the second control module continues to execute the remaining first test task from the first test task disconnection position of the first control module according to the first test data of the first control module. If the second control module is detached in the test process, the first control module executes the operation as above, that is, the first control module can continue to run the second test task of the second control module under the condition that the condition is available. In the actual test process, the situation that the first control module or the second control module is pulled out suddenly may occur, and the remaining control modules may attempt to continue to execute the test task of the pulled-out control module, so as to avoid retesting the test task of the control module after the control module is pulled out. The power calculation threshold value is preset on the chip to be tested, when the upper computer detects that the current power calculation value of the chip to be tested is higher than the power calculation threshold value, the chip to be tested can test more test tasks at the same time, at the moment, a third control module is connected to the circuit board, the third control module reads the type and the characteristics of the chip to be tested to obtain corresponding test tasks and test data, and the test tasks of the third control module are driven according to the test data of the third control module. The first control module transmits the first test data, the first test task and the first test progress to the storage module, the second control module transmits the second test data, the second test task and the second test progress to the storage module, and the third control module transmits the third test data, the third test task and the third test progress to the storage module. The first control module, the second control module and the third control module are unknown in that which one of the first control module, the second control module and the third control module completes the self-testing task at first, if the third control module completes the self-corresponding third testing task first, the first control module does not complete the self-corresponding third testing task, the third control module reads the first testing data of the first control module and the corresponding first testing task in the storage module, the third control module tries to drive the first testing task corresponding to the first control module according to the first testing data of the first control module, if the first control module can run successfully, the third control module reads the first testing task progress of the first control module, and the third control module and the first control module test the residual first testing task of the first control module together. If the second control module is detached from the circuit board in the test process, the upper computer records the current test task of the second control module and the progress of the test task, after the third control module finishes the test task, the third control module reads the test data and the test task of the second control module from the storage module, if the third control module can drive the corresponding test task to test according to the test data of the second control module, the upper computer sends the progress of the test task of the second control module to the third control module, and the third control module continues to execute the residual test task from the test task disconnection position of the second control module according to the test data of the second control module. And similarly, the second control module does not complete the self-test task, and the third control module and the second control module can test the residual test task of the second control module together. After the first control module finishes the test tasks of the first control module, the first control module can also try to run the test tasks of the second control module and the third control module; after the second control module finishes the test tasks of the second control module, the second control module can also try to run the test tasks of the first control module and the third control module. When the calculation force of the chip to be tested is sufficient, more third control modules can be connected to run more test tasks, and as the time for each control module to complete the respective test tasks is different, the control module which completes the test tasks can assist other control modules to test, so that the test efficiency is further improved.
Claims (8)
1. A multi-tasking chip testing system comprising:
the first control module is pre-provided with a first database and a first task set;
the second control module is preset with a second database and a second task set, and the setting mode of the first task set and the second task set is as follows: acquiring the type and the characteristic of a chip to be tested, and presetting test tasks corresponding to the type and the characteristic of the chip to be tested in the first task set and the second task set, wherein the first database is different from the second database, and the first task set is different from the second task set;
the circuit board is provided with an installation groove of a chip to be tested, is provided with a communication module and is in communication connection with the upper computer;
the first control module reads the type and the characteristic of the chip to be tested and acquires a specified first test task from the first task set, the first control module reads first test data of the first database corresponding to the first test task, and the first control module drives the first test task to test according to the first test data;
the second control module reads the type and the characteristic of the chip to be tested and acquires a specified second test task from the second task set, the second control module reads second test data of the second test task corresponding to the second database, the second control module drives the second test task to test according to the second test data, and the first control module and the second control module send test results to the upper computer through the communication module.
2. The multi-tasking chip testing system of claim 1, further comprising:
the storage module is arranged on the circuit board;
the first control module transmits first test data, a first test task and a first test progress to the storage module, and the second control module transmits second test data, a second test task and a second test progress to the storage module;
when the first control module is detached from the circuit board, the upper computer records the current first test progress, after the second test task is completed, the second control module reads the first test data, the first test task and the first test progress from the storage module, if the second control module can drive the first test task to test according to the first test data, the information for determining the execution can be sent to the upper computer, and the upper computer controls the second control module to continuously execute the rest first test tasks.
3. The multi-tasking chip testing system of claim 2, further comprising:
the third control module is internally provided with a third database and a third task set in advance, and the third task set is set up in the following manner: the method comprises the steps of obtaining types and characteristics of chips to be tested, presetting test tasks corresponding to the types and the characteristics of the chips to be tested in a third task set, wherein the third database is different from the first database and the second database, the third task set is different from the first task set and the second task set, and the third control module can be multiple.
4. The multi-task chip testing system according to claim 3, wherein the chip to be tested is pre-provided with a calculation threshold, the upper computer detects that the current calculation force of the chip to be tested is higher than the calculation threshold, the third control module is connected with the circuit board, and after the third control module finishes the specified third test task, if the first control module does not complete the first test task and the third control module can drive the first test task to test according to the first test data, the upper computer sends the first test progress to the third control module, and the third control module and the first control module test the remaining first test tasks together.
5. The multi-tasking chip testing system of claim 1, further comprising:
acquiring the type and the characteristic of a chip to be tested;
predicting a test task of the chip to be tested according to the type and the characteristic of the chip to be tested and by combining a prediction test task model constructed by a deep learning network; the method further comprises the following steps before the type and the characteristics of the chip to be tested are acquired:
obtaining chip type samples to be tested of a plurality of sample test tasks, and obtaining chip characteristic samples to be tested of the plurality of sample test tasks; training the deep learning network according to the chip type samples to be tested of the sample test tasks and the chip characteristic samples to be tested of the sample test tasks to construct the prediction test task model, wherein the chip type samples to be tested, the chip characteristic samples to be tested and the prediction test task model are arranged in the first task set.
6. The system of claim 5, wherein the first test tasks are prioritized after the chip under test is tested, and the ordered first test tasks are stored in the first task set.
7. The system according to claim 4, wherein the first control module and the second control module are detached from the circuit board after the testing is completed, the third control module is connected with the circuit board, the third control module reads the type and the characteristic of the chip to be tested and obtains a specified third test task from the third task set, the third control module reads third test data of the third test task corresponding to the third database, and the third control module drives the third test task to test according to the third test data.
8. A method for testing a multi-tasking chip, comprising:
presetting a first database and a first task set in a first control module, presetting a second database and a second task set in a second control module, obtaining the type and the characteristic of a chip to be tested, presetting test tasks corresponding to the type and the characteristic of the chip to be tested in the first task set and the second task set, wherein the first database is different from the second database, and the first task set is different from the second task set;
The method comprises the steps that a chip to be tested is mounted on a circuit board with a communication module and a storage module and is in communication connection with an upper computer, a first control module reads the type and the characteristic of the chip to be tested and acquires a first test task from a first task set, the first control module reads first test data of a first database corresponding to the first test task, the first control module drives the first test task to test according to the first test data, a second control module reads the type and the characteristic of the chip to be tested and acquires a second test task from the second task set, the second control module reads second test data of the second database corresponding to the second test task, the second control module drives a second test task to test according to the second test data, and the first control module and the second control module send test results to the upper computer through the communication module;
the first control module transmits first test data, a first test task and a first test progress to the storage module, the second control module transmits second test data, a second test task and a second test progress to the storage module, when the first control module is disassembled, the upper computer records the current first test progress, after the second test task is completed, the second control module reads the first test data, the first test task and the first test progress from the storage module and tries to run, if the first test progress can be run, the determined executable information is transmitted to the upper computer, and the upper computer controls the second control module to continuously execute the rest first test tasks; or alternatively, the first and second heat exchangers may be,
The power calculation threshold value is preset on the chip to be tested, the upper computer detects that the current power of the chip to be tested is higher than the power calculation threshold value, the third control module is connected with the circuit board, and after the third control module finishes the appointed third test task, if the first control module does not complete the first test task, the third control module can drive the first test task to test according to the first test data, and the third control module and the first control module jointly test the residual first test task of the first control module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311047723.2A CN116774014B (en) | 2023-08-21 | 2023-08-21 | Multi-task chip test system and multi-task chip test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311047723.2A CN116774014B (en) | 2023-08-21 | 2023-08-21 | Multi-task chip test system and multi-task chip test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116774014A true CN116774014A (en) | 2023-09-19 |
| CN116774014B CN116774014B (en) | 2023-10-31 |
Family
ID=88011983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311047723.2A Active CN116774014B (en) | 2023-08-21 | 2023-08-21 | Multi-task chip test system and multi-task chip test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116774014B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1849588A (en) * | 2003-09-15 | 2006-10-18 | 辉达公司 | A system and method for testing and configuring semiconductor functional circuits |
| CN103713627A (en) * | 2013-12-27 | 2014-04-09 | 普华基础软件股份有限公司 | Function node test system |
| CN107831428A (en) * | 2017-12-06 | 2018-03-23 | 西安智多晶微电子有限公司 | Chip volume production test system |
| CN110634530A (en) * | 2019-09-10 | 2019-12-31 | 珠海博雅科技有限公司 | Chip testing system and method |
| CN114660436A (en) * | 2022-03-11 | 2022-06-24 | 敦泰电子（深圳）有限公司 | Chip testing equipment and chip testing method |
| CN115210589A (en) * | 2020-03-25 | 2022-10-18 | 华为技术有限公司 | Chip testing device and testing method |
| US20230204662A1 (en) * | 2021-12-28 | 2023-06-29 | Advanced Micro Devices Products (China) Co. Ltd., | On-chip distribution of test data for multiple dies |
| CN116500422A (en) * | 2023-05-08 | 2023-07-28 | 海光集成电路设计(北京)有限公司 | Chip parallel test system and test method based on system-level test platform |
-
2023
- 2023-08-21 CN CN202311047723.2A patent/CN116774014B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1849588A (en) * | 2003-09-15 | 2006-10-18 | 辉达公司 | A system and method for testing and configuring semiconductor functional circuits |
| CN103713627A (en) * | 2013-12-27 | 2014-04-09 | 普华基础软件股份有限公司 | Function node test system |
| CN107831428A (en) * | 2017-12-06 | 2018-03-23 | 西安智多晶微电子有限公司 | Chip volume production test system |
| CN110634530A (en) * | 2019-09-10 | 2019-12-31 | 珠海博雅科技有限公司 | Chip testing system and method |
| CN115210589A (en) * | 2020-03-25 | 2022-10-18 | 华为技术有限公司 | Chip testing device and testing method |
| US20230204662A1 (en) * | 2021-12-28 | 2023-06-29 | Advanced Micro Devices Products (China) Co. Ltd., | On-chip distribution of test data for multiple dies |
| CN114660436A (en) * | 2022-03-11 | 2022-06-24 | 敦泰电子（深圳）有限公司 | Chip testing equipment and chip testing method |
| CN116500422A (en) * | 2023-05-08 | 2023-07-28 | 海光集成电路设计(北京)有限公司 | Chip parallel test system and test method based on system-level test platform |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116774014B (en) | 2023-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20040239359A1 (en) | Device test apparatus and test method | |
| CN113514759B (en) | Multi-core test processor and integrated circuit test system and method | |
| EP1882956A1 (en) | Test device, test method, and test control program | |
| US20080162992A1 (en) | Method and apparatus for intelligently re-sequencing tests based on production test results | |
| CN113176493B (en) | Chip test main board, test system and test method | |
| KR102380506B1 (en) | Self diagnostic apparatus for electronic device | |
| CN110941553A (en) | Code detection method, device, equipment and readable storage medium | |
| CN112650676A (en) | Software testing method, device, equipment and storage medium | |
| CN116774014B (en) | Multi-task chip test system and multi-task chip test method | |
| US7184932B1 (en) | Reliability prediction for complex components | |
| CN112035346B (en) | Automatic test method, system and medium based on embedded DSP operating system | |
| CN117233581B (en) | Chip testing method, device, equipment and medium | |
| US7464311B2 (en) | Apparatus and method for device selective scans in data streaming test environment for a processing unit having multiple cores | |
| KR102148043B1 (en) | Flexible test site synchronization | |
| CN117572217A (en) | Integrated circuit test excitation method, device, equipment and storage medium | |
| CN117787155A (en) | Chip testability code dynamic simulation test system and test method | |
| CN108681506B (en) | Pressure testing method and device | |
| CN113990382B (en) | System-on-chip, test method and test system | |
| CN115391110A (en) | Test method of storage device, terminal device and computer readable storage medium | |
| CN109656828B (en) | Automatic testing method for pressure of virtual machine in cluster, terminal and readable storage medium | |
| CN111475398A (en) | Server NIC diagnosis method, system, terminal and storage medium | |
| US7523297B1 (en) | Shadow scan decoder | |
| CN111142410A (en) | Control method and system for automatic and orderly starting and stopping according to test requirements | |
| CN114880197A (en) | Computer software performance testing method | |
| CN117130844B (en) | Hard disk testing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |