CN116772384A

CN116772384A - Air conditioning system

Info

Publication number: CN116772384A
Application number: CN202310512631.0A
Authority: CN
Inventors: 徐鹏洋; 范雪峰; 张园园
Original assignee: Qingdao Hisense Hitachi Air Conditioning System Co Ltd
Current assignee: Qingdao Hisense Hitachi Air Conditioning System Co Ltd
Priority date: 2023-05-08
Filing date: 2023-05-08
Publication date: 2023-09-19

Abstract

The embodiment of the invention provides an air conditioning system, and relates to the technical field of electric appliances. The air conditioning system facilitates the improvement of functions by setting the pins of the main control chip to a mode with adjustable output level. An air conditioning system includes: a first bus, a second bus, and a controller; the controller includes: a main control chip; the main control chip comprises: a first pin and a second pin; the first pin is electrically connected with the first bus, and the second pin is electrically connected with the second bus. The level conversion circuit is electrically connected with the logic control module and is also electrically connected with the first voltage end and the second voltage end; the output end of the level conversion circuit is electrically connected with the first pin or the second pin; the logic control module is configured to output a control signal, and the level conversion circuit is configured to output a voltage signal of the first voltage terminal to a pin to which the logic control module is electrically connected or output a voltage signal of the second voltage terminal to a pin to which the logic control module is electrically connected under the control of the control signal.

Description

Air conditioning system

Technical Field

The invention relates to the technical field of electric appliances, in particular to an air conditioning system.

Background

With the development of scientific technology, the application of air conditioners is more and more common, and more people's daily lives are closely related to the air conditioners.

At present, a communication mode of a home bus is commonly used in the field of central air conditioning to perform communication between an indoor unit and an outdoor unit, communication between a wire controller and the indoor unit, and communication between the outdoor unit and the outdoor unit, wherein a communication chip is used in a communication loop, and the chip is a communication protocol conversion chip, and is exemplified by a 1192 communication chip. Because each internal machine, external machine or wire controller of the central air conditioning system needs to communicate, the chip has huge usage amount and higher unit price, and is not beneficial to further popularization of the air conditioner. If the main control chip is internally provided with the home bus communication function, the output voltage of the main control chip is required to be regulated, but the communication pins of the main control chip cannot be regulated at will, so that the development of subsequent new functions is not facilitated.

Disclosure of Invention

The embodiment of the invention provides an air conditioning system, which reduces the cost by disassembling the functions of a communication chip into a main control chip and an added circuit.

The air conditioning system includes: a first bus, a second bus, and a controller; the controller comprises an indoor unit, an outdoor unit and a wire controller; the controller includes: a main control chip; the main control chip comprises: a first pin and a second pin; the first pin is electrically connected with the first bus, and the second pin is electrically connected with the second bus.

The main control chip comprises: a first output module and a second output module; the first output module is electrically connected with the first pin, and the second output module is electrically connected with the second pin; at least one of the first output module and the second output module includes: logic control module and level conversion circuit.

The level conversion circuit is electrically connected with the logic control module and is also electrically connected with the first voltage end and the second voltage end; the output end of the level conversion circuit is electrically connected with the first pin or the second pin; the logic control module is configured to output a control signal, and the level conversion circuit is configured to output the voltage signal of the first voltage terminal to a pin electrically connected with the level conversion circuit or output the voltage signal of the second voltage terminal to a pin electrically connected with the level conversion circuit under the control of the control signal.

Based on the above technical scheme, the air conditioning system provided by some embodiments of the present application facilitates the improvement of the communication function of the main control chip by setting the pins of the main control chip to a mode with adjustable output level. Meanwhile, the circuit additionally arranged on the main control chip can further ensure the safe operation of the main control chip.

In some embodiments, the logic control module includes a first control terminal and a second control terminal; the first control end is configured to output a first control signal, and the second control end is configured to output a second control signal; the level shift circuit comprises a first sub-circuit and a second sub-circuit; the first sub-circuit is electrically connected with the first control end, the first voltage end and the output end; the second sub-circuit is electrically connected with the second control terminal, the second voltage terminal and the output terminal.

The logic control module is configured to output a first control signal with an on level and a second control signal with an off level to control the first sub-circuit to be turned on and the second sub-circuit to be turned off; the first sub-circuit is configured to transmit a voltage signal of the first voltage terminal to the output terminal.

The logic control module is further configured to output a first control signal having an off level and a second control signal having an on level to control the first sub-circuit to be turned off and the second sub-circuit to be turned on, the second sub-circuit being configured to transmit the voltage signal of the first voltage terminal to the output terminal.

In some embodiments, the first sub-circuit comprises: a first transistor; the control electrode of the first transistor is electrically connected with the first control end, the first electrode of the first transistor is electrically connected with the first voltage end, and the second electrode of the first transistor is electrically connected with the output end.

In some embodiments, the second sub-circuit comprises: a second transistor; the control electrode of the second transistor is electrically connected with the second control end, the first electrode of the second transistor is electrically connected with the output end, and the second electrode of the second transistor is electrically connected with the second voltage end.

In some embodiments, the logic control module is configured to output a control signal, and the level shift circuit is further configured to output a set voltage signal to a pin to which it is electrically connected under control of the control signal, the voltage of the set voltage signal being any one of the voltage of the first voltage terminal and the voltage of the second voltage terminal.

In some embodiments, the logic control module further comprises a third control terminal configured to output a third control signal; the level shift circuit further includes: a third sub-circuit, a first voltage divider sub-circuit, and a second voltage divider sub-circuit.

The first voltage division subcircuit is electrically connected between the first voltage terminal and the first subcircuit; the first end of the second voltage division subcircuit is electrically connected with the first subcircuit and the output end; the third sub-circuit is electrically connected to the third control terminal, the second voltage terminal, and the second terminal of the second voltage dividing sub-circuit.

The logic control module is configured to output a first control signal and a third control signal with an on level and a second control signal with an off level so as to control the first sub-circuit and the third sub-circuit to be on and control the second sub-circuit to be off; the level shift circuit is configured to output the set voltage signal to the output terminal.

In some embodiments, the third sub-circuit comprises: a third transistor; the control electrode of the third transistor is electrically connected with the third control end, the first electrode of the third transistor is electrically connected with the second end of the second voltage division subcircuit, and the second electrode of the third transistor is electrically connected with the second voltage end.

In some embodiments, the first sub-circuit comprises: a first transistor; the first voltage dividing sub-circuit comprises a first resistor, and the second voltage dividing sub-circuit comprises a second resistor; a first end of the first resistor is electrically connected with the first voltage end, and a second end of the first resistor is electrically connected with a first pole of the first transistor; the first end of the second resistor is electrically connected with the second pole of the first transistor, and the second end of the second resistor is electrically connected with the first pole of the third transistor.

In some embodiments, the first resistor and/or the second resistor is an adjustable resistor.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate and do not limit the invention.

Fig. 1 is a schematic diagram of an air conditioning system according to the prior art;

fig. 2 is a schematic diagram of an air conditioning system according to an embodiment of the present invention;

FIG. 3 is a system block diagram of a main control chip according to an embodiment of the present invention;

FIG. 4 is a system block diagram of an output module according to an embodiment of the present invention;

FIG. 5 is a system block diagram of another output module according to an embodiment of the present invention;

FIG. 6 is a system block diagram of yet another output module provided by an embodiment of the present invention;

FIG. 7 is a system block diagram of a first sub-circuit according to an embodiment of the present invention;

FIG. 8 is a system block diagram of a second sub-circuit according to an embodiment of the present invention;

FIG. 9 is a system block diagram of an output module according to an embodiment of the present invention;

fig. 10 is a circuit diagram of an overall output module according to an embodiment of the present invention;

FIG. 11 is a circuit diagram of an overall output module according to another embodiment of the present invention;

fig. 12 is a circuit diagram of the whole main control chip according to the embodiment of the invention;

FIG. 13 is a circuit diagram of a resistor with a part of the resistor being an adjustable resistor according to an embodiment of the present invention;

FIG. 14 is a circuit diagram of another embodiment of the present invention with a resistor portion being an adjustable resistor;

FIG. 15 is a circuit diagram of a further embodiment of the present invention with a resistor portion being an adjustable resistor;

FIG. 16 is a circuit diagram of a further embodiment of the present invention with a resistor portion being an adjustable resistor;

FIG. 17 is a circuit diagram of a further embodiment of the present invention with a resistor portion being an adjustable resistor;

FIG. 18 is a circuit diagram of a further embodiment of the present invention with a resistor portion being an adjustable resistor;

FIG. 19 is a circuit diagram of a further embodiment of the present invention with a resistor portion being an adjustable resistor;

FIG. 20 is a circuit diagram of a resistor with adjustable resistance according to another embodiment of the present invention;

FIG. 21 is a circuit diagram of an embodiment of the present invention with all resistors being adjustable resistors;

fig. 22 is a flowchart of a pin output level of a main control chip according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.

The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the description of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "connected," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art. In addition, when describing a pipeline, the terms "connected" and "connected" as used herein have the meaning of conducting. The specific meaning is to be understood in conjunction with the context.

In embodiments of the invention, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

As described in the background art, in the current air conditioning system, a communication mode of the indoor unit and the outdoor unit, a communication mode of the wire controller and the indoor unit, and a communication mode of the outdoor unit and the indoor unit are generally used, and a communication chip is used in the communication loop, where the chip is a communication protocol conversion chip, and an exemplary chip is a 1192 communication chip. The communication chip is developed by Sanmei company in Japan, and because each internal machine, external machine or wire controller of the central air conditioning system needs to communicate, the chip has huge usage amount, and the unit price of the chip is higher, so that the cost of the air conditioning system is increased, thereby being unfavorable for further popularization of the air conditioning system.

If the main control chip is internally provided with the home bus communication function, that is, the function of the communication chip is disassembled to the main control chip, the output voltage of the main control chip is required to be regulated at the moment, but the communication pins of the main control chip cannot randomly regulate the level, which is not beneficial to the development of the subsequent new functions.

As shown in fig. 1, fig. 1 is a prior art air conditioning system. The air conditioning system comprises a communication loop, wherein the communication loop comprises a communication chip. The communication chip in fig. 1 is located in the outdoor unit, and the main control chip is electrically connected with the communication chip, and the communication chip is connected with other air conditioning equipment in a communication manner through the first bus and the second bus. Other air conditioning equipment herein includes: outdoor unit, indoor unit and drive-by-wire ware.

That is, the outdoor unit is connected to the outdoor unit in communication, the outdoor unit is connected to the indoor unit in communication, and the outdoor unit is connected to the line controller in communication. It should be noted that the communication chip may also be located in the indoor unit or the line controller, so as to implement communication connection between two air conditioning devices.

Based on the above, the embodiment of the application provides an air conditioning system. The air conditioning system divides a communication chip in the prior art into two parts, firstly integrates a part of analysis functions of the communication chip onto a main control chip, and then realizes the other part of functions of the communication chip by adding a plurality of circuits into a communication loop, so that the communication loop can still complete the communication function under the condition of no communication chip.

Where parsing is understood as interpretation of signals, converting one form of communication protocol to another, similar to human interpretation.

Fig. 2 is a schematic diagram of an air conditioning system according to an embodiment of the present application. The air conditioning system comprises at least two air conditioning devices and a communication bus. It should be noted that, the air conditioning system according to the embodiment of the present application may be a common air conditioning system composed of one indoor unit and one outdoor unit, or may be a multi-split air conditioning system commonly called one-to-many. For convenience of description, different types of air conditioning systems are illustrated by way of example in the schematic structural diagram of the air conditioning system shown in fig. 2.

As shown in fig. 2, the air conditioning system 1000 includes: a controller 500; the controller 500 includes: the indoor unit 100, the outdoor unit 200, and the line controller 300.

A Home Bus System (HBS) is composed of a coaxial cable for transmitting image information and 4 twisted pairs for transmitting voice, data and control signals.

As shown in fig. 3, the air conditioning system 1000 further includes: a first bus a and a second bus B;

the controller 500 includes: a main control chip 50; the main control chip 50 includes: a first pin 51 and a second pin 52; the first pin 51 is electrically connected to the first bus a, and the second pin 52 is electrically connected to the second bus B.

The main control chip 50 includes: a first output module 10 and a second output module 20; the first output module 10 is electrically connected to the first pin 51, and the second output module 20 is electrically connected to the second pin 52.

As shown in fig. 4, at least one of the first output module 10 and the second output module 20 includes: a logic control module 1 and a level shift circuit 2.

That is, referring to fig. 4, only the logic control module 1 and the level shift circuit 2, the second output module 20 does not include: a logic control module 1 and a level conversion circuit 2; alternatively, referring to fig. 5, only the second output module 20 includes: the logic control module 1 and the level shift circuit 2, the first output module 10 does not include: a logic control module 1 and a level conversion circuit 2; alternatively, not only the first output module 10 includes: the logic control module 1 and the level shift circuit 2, the second output module 20 also includes: a logic control module 1 and a level shift circuit 2.

In some embodiments, the first output module 10 acts on the first pin 51 and the second output module 20 does not act on the second pin 52; alternatively, the second output module 20 acts on the first pin 51, and the first output module 10 does not act on the second pin 52; alternatively, the first output module 10 acts on the first pin 51 and the second output module 20 acts on the second pin 52.

The logic control module 1 comprises a first control terminal 101 and a second control terminal 102.

The level conversion circuit 2 is electrically connected with the logic control module 1 and is also electrically connected with the first voltage end VCC and the second voltage end GND; the output end of the level conversion circuit 2 is electrically connected with the first pin 51 or the second pin 52;

the logic control module 1 is configured to output a control signal, and the level conversion circuit 2 is configured to output a voltage signal of the first voltage terminal VCC to a pin to which it is electrically connected or output a voltage signal of the second voltage terminal GND to a pin to which it is electrically connected under control of the control signal.

Taking the first output module 10 as an example, if the first output module 10 includes: the logic control module 1 and the level shift circuit 2, the first output module 10 acts on the first pin 51. The logic control module 1 outputs a control signal to the level shift circuit 2, the level shift circuit 2 receives the control signal to output a voltage signal of the first voltage terminal VCC to the first pin 51 of the main control chip, or the level shift circuit 2 receives the control signal to output a voltage signal of the second voltage terminal GND to the first pin 51 of the main control chip.

It should be noted that, the voltage signal of the first voltage terminal VCC is a power supply voltage, and may be understood as a high level, where the voltage range of the first voltage terminal VCC is related to the voltage bearing range of the pin of the main control chip, and the voltage of the first voltage terminal VCC may be the maximum bearing voltage of the pin of the main control chip. The voltage signal at the second voltage terminal GND is the ground voltage and may be understood as a low level or as a zero voltage output.

In summary, in the air conditioning system provided by some embodiments of the present application, the pin of the main control chip is set to the mode with adjustable output level, so as to facilitate the improvement of the communication function of the main control chip. Meanwhile, the circuit additionally arranged on the main control chip can further ensure the safe operation of the main control chip.

As shown in fig. 6, the level shift circuit 2 includes a first sub-circuit 21 and a second sub-circuit 22; the first sub-circuit 21 is electrically connected to the first control terminal 101, the first voltage terminal VCC, and the output terminal OUT; the second sub-circuit 22 is electrically connected to the second control terminal 102, the second voltage terminal GND, and the output terminal OUT.

The first control terminal 101 is configured to output a first control signal, and the second control terminal 102 is configured to output a second control signal.

The logic control module 1 is configured to output a first control signal with an on level and a second control signal with an off level to control the first sub-circuit 21 to be turned on and the second sub-circuit 22 to be turned off; the first sub-circuit 21 is configured to transmit a voltage signal of the first voltage terminal VCC to the output terminal OUT.

The logic control module 1 is further configured to output a first control signal having an off level and a second control signal having an on level to control the first sub-circuit 21 to be turned off and the second sub-circuit 22 to be turned on, the second sub-circuit 22 being configured to transmit the voltage signal of the second voltage terminal GND to the output terminal OUT.

It should be noted that, the first control signal having the on level may be a high level or a low level; the second control signal having the off level may be either a high level or a low level.

That is, if the logic control module 1 is configured to output the first control signal having the on level and the second control signal having the off level, the first sub-circuit 21 may be operated to receive the first control signal, and the second sub-circuit 22 may be deactivated, i.e., turned off, to receive the second control signal. In the case where the first sub-circuit 21 is operated and the second sub-circuit 22 is not operated, the voltage signal of the first voltage terminal VCC may be transmitted to the output terminal OUT.

If the logic control module 1 is further configured to output a first control signal having an off level and a second control signal having an on level, the first sub-circuit 21 may not operate when receiving the first control signal, and the second sub-circuit 22 may operate when receiving the second control signal. In the case where the first sub-circuit 21 is not operated and the second sub-circuit 22 is operated, the voltage signal of the second voltage terminal GND may be transmitted to the output terminal OUT.

As shown in fig. 7, the first sub-circuit 21 includes: a first transistor Q1; the control electrode of the first transistor Q1 is electrically connected to the first control terminal 101, the first electrode of the first transistor Q1 is electrically connected to the first voltage terminal VCC, and the second electrode of the first transistor Q1 is electrically connected to the output terminal OUT.

As shown in fig. 8, the second sub-circuit 22 includes: a second transistor Q2; the control electrode of the second transistor Q2 is electrically connected to the second control terminal 102, the first electrode of the second transistor Q2 is electrically connected to the output terminal OUT, and the second electrode of the second transistor Q2 is electrically connected to the second voltage terminal.

In some embodiments, the transistor is an NPN transistor, the first control signal having an on level is high, and the second control signal having an off level is low.

In some embodiments, the transistor is a PNP transistor, the first control signal having an on level is at a low level, and the second control signal having an off level is at a high level.

That is, if the transistor is an NPN transistor, the logic control module 1 needs to output a high level to turn on the NPN transistor, that is, the sub-circuit in the level shifter 2 works; outputting low level or not outputting the level average can cut off the NPN triode, namely the sub-circuit in the level conversion circuit 2 does not work; if the transistor is a PNP transistor, the logic control module 1 needs to output a low level to turn on the PNP transistor, that is, the sub-circuit in the level conversion circuit 2 works; outputting a high level or not outputting an average may turn off the PNP transistor, i.e., the sub-circuits in the level shifter circuit 2 do not operate.

As shown in fig. 8, taking an NPN triode as an example, if the NPN triode is turned on, for example, the first transistor Q1 is turned on, the space between the first voltage terminal VCC and the output terminal OUT can be regarded as a conducting wire; the second transistor Q2 is turned on, and the second voltage terminal GND and the output terminal OUT can be regarded as a conductive line. If the first transistor Q1 is turned on, the second transistor Q2 is turned off, and the output terminal outputs the voltage of the first voltage terminal VCC; if the first transistor Q1 is turned off, the second transistor Q2 is turned on, and the output terminal outputs the voltage of the second voltage terminal GND; if the first transistor Q1 is turned on, the second transistor Q2 is also turned on, and the circuit is shorted and cannot output voltage.

The specific process is as follows:

if the logic control module 1 is configured to output a first control signal with an on level and a second control signal with an off level, the first transistor Q1 receives the first control signal to be turned on, and the second transistor Q2 receives the second control signal to be turned off. In case that the first transistor Q1 is turned on and the second transistor Q2 is turned off, the voltage signal of the first voltage terminal VCC may be transmitted to the output terminal OUT.

If the logic control module 1 is further configured to output a first control signal with an off level and a second control signal with an on level, the first transistor Q1 receives the first control signal to be turned off, and the second transistor Q2 receives the second control signal to be turned on. With the first transistor Q1 turned off and the second transistor Q2 turned on, the voltage signal of the second voltage terminal GND may be transmitted to the output terminal OUT.

In some embodiments, the logic control module 1 is configured to output a control signal, and the level shifter circuit 2 is further configured to output a set voltage signal to a pin to which it is electrically connected, the set voltage signal having a voltage that is any one of a voltage of the first voltage terminal and a voltage of the second voltage terminal, under control of the control signal.

That is, the logic control module 1 outputs a control signal to the level shifter circuit 2, and the level shifter circuit 2 receives the control signal and can output any one of the voltage signals from the first voltage terminal VCC to the second voltage terminal GND to the first pin 51 of the main control chip.

As shown in fig. 9, the logic control module 1 further includes a third control terminal 103, and the third control terminal 103 is configured to output a third control signal;

the level shift circuit 2 further includes: a third sub-circuit 23, a first voltage dividing sub-circuit 24 and a second voltage dividing sub-circuit 25.

The first voltage dividing sub-circuit 24 is electrically connected between the first voltage terminal VCC and the first sub-circuit 21; a first terminal of the second voltage dividing sub-circuit 25 is electrically connected to the first sub-circuit 21 and the output terminal OUT; the third sub-circuit 23 is electrically connected to the third control terminal 103, the second voltage terminal GND and the second terminal of the second voltage dividing sub-circuit 25.

The logic control module 1 is configured to output a first control signal and a third control signal with on levels and a second control signal with off levels to control the first sub-circuit 21 and the third sub-circuit 23 to be on and the second sub-circuit 22 to be off; the level shift circuit 2 is configured to output a set voltage signal to the output terminal OUT.

That is, the logic control module 1 is configured to output a first control signal having an on level and a third control signal, a second control signal having an off level, the first sub-circuit 21 may be operated to receive the first control signal, the second sub-circuit 22 may be deactivated, that is, turned off, and the third sub-circuit 23 may be operated to receive the third control signal. In the case where the first sub-circuit 21 is operated, the second sub-circuit 22 is not operated, and the third sub-circuit 23 is operated, any one of the voltage signals from the first voltage terminal VCC to the second voltage terminal GND may be output to the output terminal OUT.

As shown in fig. 10 and 12, the third sub-circuit 23 includes: a third transistor Q3; the control electrode of the third transistor is electrically connected with the third control end, the first electrode of the third transistor is electrically connected with the second end of the second voltage division subcircuit, and the second electrode of the third transistor is electrically connected with the second voltage end.

As shown in fig. 10, the first voltage dividing sub-circuit 24 includes a first resistor R1, and the second voltage dividing sub-circuit 25 includes a second resistor R2;

a first end of the first resistor R1 is electrically connected with the first voltage end VCC, and a second end of the first resistor R1 is electrically connected with a first pole of the first transistor Q1;

the first end of the second resistor R2 is electrically connected to the second pole of the first transistor Q1, and the second end of the second resistor R2 is electrically connected to the first pole of the third transistor.

The first resistor R1 and the second resistor R2 not only play a role in voltage division, but also can prevent short circuit, thereby better protecting the safe operation of the main control chip 50.

The voltage at the first voltage terminal VCC is 5V, the voltage at the second voltage terminal GND is 0V, the resistance of the first resistor R1 is the same as the resistance of the second resistor R2, and the voltage at the output terminal is 2.5V because the voltage at the output terminal is the voltage at the two ends of the second resistor R2; if the ratio of the resistance of the first resistor R1 to the resistance of the second resistor R2 is 4:1, the voltage output by the output end is 1V.

Accordingly, as shown in fig. 11 and 12, the circuit internal structure of the second output module 20 is the same as that of the first output module 10, except that the first output module 10 is electrically connected to the first pin 51 of the main control chip 50, and the second output module 20 is electrically connected to the second pin 52 of the main control chip 50.

Among them, to facilitate the description of the following schemes, the transistors in the second output module 20 are: the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 are in one-to-one correspondence with the first transistor Q1, the second transistor Q2, and the third transistor Q3 in the first output module 10; the resistance in the second output module 20 is: the third resistor R3 and the fourth resistor R4 are in one-to-one correspondence with the first resistor R1 and the second resistor R2 in the first output module 10.

The voltage output by the output end is the voltage at two ends of the second resistor R2, and the voltage at two ends of the second resistor R2 is related to the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2, so that the voltage output by the output end can be adjusted at will if the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2 can be changed.

As shown in fig. 13 to 21, the first output module 10 and the second output module 20 are further described below for the convenience of distinguishing the adjustable resistances.

For the first resistor R1 and/or the second resistor R2, the resistor is an adjustable resistor; for the second output module 20, the third resistor R3 and/or the fourth resistor R4 are adjustable resistors.

Wherein the logic control module 1 further comprises: a fourth control terminal 104 and a fifth control terminal 105; the fourth control terminal 104 is electrically connected to the first resistor R1 and/or the third resistor R3, and the fifth control terminal 105 is electrically connected to the second resistor R2 and/or the fourth resistor R4. The control signal output by the fourth control terminal 104 may control the resistance of the first resistor R1 and/or the third resistor R3, and similarly, the control signal output by the fifth control terminal 105 may also control the resistance of the second resistor R2 and/or the fourth resistor R4.

As shown in fig. 13, in some embodiments, the first resistor R1 and the third resistor R3 are adjustable resistors.

Referring to fig. 13, the fourth control terminal 104 of the logic control module 1 of the first output module 10 is electrically connected to the first resistor R1, and the fourth control terminal 104 of the logic control module 1 of the second output module 20 is electrically connected to the third resistor R3.

In the case where the logic control module 1 is configured to output a first control signal and a third control signal having an on level, the first control signal controlling the first transistor Q1 to be turned on, and a second control signal having an off level, the third control signal controlling the third transistor Q3 to be turned on, the second control signal controlling the second transistor Q2 to be turned off; the first transistor Q1 and the third transistor Q3 are connected, and transmit the voltage at two ends of the second resistor R2 to the output end, and meanwhile, the resistance value of the first resistor R1 can be modified, and the voltage at the output end is regulated, so that the voltage of the first pin 51 of the main control chip 50 is regulated. That is, the first transistor Q1 and the third transistor Q3 are configured to output any one of the voltage signals of the first voltage terminal VCC to the second voltage terminal GND to the output terminal OUT.

In the case where the logic control module 1 is configured to output a first control signal and a third control signal having an on level, and a second control signal having an off level, the first control signal controls the fourth transistor Q4 to be turned on, the third control signal controls the sixth transistor Q6 to be turned on, and the second control signal controls the fifth transistor Q5 to be turned off; the fourth transistor Q4 and the sixth transistor Q6 are connected to each other, so that the voltage at two ends of the fourth resistor R4 is transmitted to the output terminal OUT, and meanwhile, the resistance value of the third resistor R3 can be modified to adjust the voltage at the output terminal, thereby adjusting the voltage of the second pin 52 of the main control chip 50. That is, the fourth transistor Q4 and the sixth transistor Q6 are configured to transmit the voltage signal of the first voltage terminal VCC to the output terminal.

As shown in fig. 14, in some embodiments, the first resistor R1 and the fourth resistor R4 are adjustable resistors.

Referring to fig. 14, the fourth control terminal 104 of the logic control module 1 of the first output module 10 is electrically connected to the first resistor R1, and the fifth control terminal 105 of the logic control module 1 of the second output module 20 is electrically connected to the fourth resistor R4.

In the case where the logic control module 1 is configured to output a first control signal and a third control signal having an on level, and a second control signal having an off level, the first control signal controls the fourth transistor Q4 to be turned on, the third control signal controls the sixth transistor Q6 to be turned on, and the second control signal controls the fifth transistor Q5 to be turned off; the fourth transistor Q4 and the sixth transistor Q6 are connected to each other, so that the voltage at two ends of the fourth resistor R4 is transmitted to the output terminal OUT, and meanwhile, the resistance value of the fourth resistor R4 can be modified to adjust the voltage at the output terminal, thereby adjusting the voltage of the second pin 52 of the main control chip 50. That is, the fourth transistor Q4 and the sixth transistor Q6 are configured to transmit the voltage signal of the first voltage terminal VCC to the output terminal.

As shown in fig. 15, in some embodiments, the second resistor R2 and the third resistor R3 are adjustable resistors.

Referring to fig. 15, the fifth control terminal 105 of the logic control module 1 of the first output module 10 is electrically connected to the second resistor R2, and the fourth control terminal 104 of the logic control module 1 of the second output module 20 is electrically connected to the third resistor R3.

In the case where the logic control module 1 is configured to output a first control signal and a third control signal having an on level, the first control signal controlling the first transistor Q1 to be turned on, and a second control signal having an off level, the third control signal controlling the third transistor Q3 to be turned on, the second control signal controlling the second transistor Q2 to be turned off; the first transistor Q1 and the third transistor Q3 are connected to each other, so that the voltage at two ends of the second resistor R2 is transmitted to the output end, and meanwhile, the resistance value of the second resistor R2 can be modified to adjust the voltage at the output end, thereby adjusting the voltage of the first pin 51 of the main control chip 50. That is, the first transistor Q1 and the third transistor Q3 are configured to output any one of the voltage signals of the first voltage terminal VCC to the second voltage terminal GND to the output terminal OUT.

As shown in fig. 16, in some embodiments, the second resistor R2 and the fourth resistor R4 are adjustable resistors.

Referring to fig. 16, the fifth control terminal 105 of the logic control module 1 of the first output module 10 is electrically connected to the second resistor R2, and the fifth control terminal 105 of the logic control module 1 of the second output module 20 is electrically connected to the fourth resistor R4.

In the case where the logic control module 1 is configured to output a first control signal and a third control signal having an on level, and a second control signal having an off level, the first control signal controls the fourth transistor Q4 to be turned on, the third control signal controls the sixth transistor Q6 to be turned on, and the second control signal controls the fifth transistor Q5 to be turned off; the fourth transistor Q4 and the sixth transistor Q6 are connected to each other, so that the voltage at two ends of the fourth resistor R4 is transmitted to the output terminal OUT, and meanwhile, the resistance value of the fourth resistor R4 can be modified to adjust the voltage at the output terminal, thereby adjusting the voltage of the second pin 52 of the main control chip 50. That is, the fourth transistor Q4 and the sixth transistor Q6 are configured to transmit the voltage signal of the first voltage terminal VCC to the output terminal OUT.

As shown in fig. 17, in some embodiments, the first resistor R1, the third resistor R3, and the fourth resistor R4 are adjustable resistors.

Referring to fig. 17, the fourth control terminal 104 of the logic control module 1 of the first output module 10 is electrically connected to the first resistor R1; the fourth control terminal 104 of the logic control module 1 of the second output module 20 is electrically connected to the third resistor R3, and the fifth control terminal 105 is electrically connected to the fourth resistor R4.

In the case where the logic control module 1 is configured to output a first control signal and a third control signal having an on level, and a second control signal having an off level, the first control signal controls the fourth transistor Q4 to be turned on, the third control signal controls the sixth transistor Q6 to be turned on, and the second control signal controls the fifth transistor Q5 to be turned off; the fourth transistor Q4 and the sixth transistor Q6 are connected to each other, and transmit the voltage at both ends of the fourth resistor R4 to the output terminal OUT, and simultaneously, the resistance of the third resistor R3 and the resistance of the fourth resistor R4 can be modified, so as to adjust the voltage at the output terminal, thereby adjusting the voltage of the second pin 52 of the main control chip 50. That is, the fourth transistor Q4 and the sixth transistor Q6 are configured to transmit the voltage signal of the first voltage terminal VCC to the output terminal OUT.

As shown in fig. 18, in some embodiments, the second resistor R2, the third resistor R3, and the fourth resistor R4 are adjustable resistors.

Referring to fig. 18, the fifth control terminal 105 of the logic control module 1 of the first output module 10 is electrically connected to the second resistor R2; the fourth control terminal 104 of the logic control module 1 of the second output module 20 is electrically connected to the third resistor R3, and the fifth control terminal 105 is electrically connected to the fourth resistor R4.

As shown in fig. 19, in some embodiments, the first resistor R1, the second resistor R2, and the third resistor R3 are adjustable resistors.

Referring to fig. 19, a fourth control terminal 104 of the logic control module 1 of the first output module 10 is electrically connected to the first resistor R1, and a fifth control terminal 105 is electrically connected to the second resistor R2; the fourth control terminal 104 of the logic control module 1 of the second output module 20 is electrically connected to the third resistor R3.

In the case where the logic control module 1 is configured to output a first control signal and a third control signal having an on level, the first control signal controlling the first transistor Q1 to be turned on, and a second control signal having an off level, the third control signal controlling the third transistor Q3 to be turned on, the second control signal controlling the second transistor Q2 to be turned off; the first transistor Q1 and the third transistor Q3 are connected to each other, and transmit the voltages at two ends of the second resistor R2 to the output end, and simultaneously, the resistance value of the first resistor R1 and the resistance value of the second resistor R2 can be modified, and the voltage at the output end is adjusted, so that the voltage of the first pin 51 of the main control chip 50 is adjusted. That is, the first transistor Q1 and the third transistor Q3 are configured to output any one of the voltage signals of the first voltage terminal VCC to the second voltage terminal GND to the output terminal OUT.

In the case where the logic control module 1 is configured to output a first control signal and a third control signal having an on level, and a second control signal having an off level, the first control signal controls the fourth transistor Q4 to be turned on, the third control signal controls the sixth transistor Q6 to be turned on, and the second control signal controls the fifth transistor Q5 to be turned off; the fourth transistor Q4 and the sixth transistor Q6 are connected to each other, so that the voltage at two ends of the fourth resistor R4 is transmitted to the output end, and meanwhile, the resistance value of the third resistor R3 can be modified to adjust the voltage at the output end, thereby adjusting the voltage of the second pin 52 of the main control chip 50. That is, the fourth transistor Q4 and the sixth transistor Q6 are configured to transmit the voltage signal of the first voltage terminal VCC to the output terminal OUT.

As shown in fig. 20, in some embodiments, the first resistor R1, the second resistor R2, and the fourth resistor R4 are adjustable resistors.

Referring to fig. 20, a fourth control terminal 104 of the logic control module 1 of the first output module 10 is electrically connected to the first resistor R1, and a fifth control terminal 105 is electrically connected to the second resistor R2; the fifth control terminal 105 of the logic control module 1 of the second output module 20 is electrically connected to the fourth resistor R4.

In the case where the logic control module 1 is configured to output a first control signal and a third control signal having an on level, and a second control signal having an off level, the first control signal controls the fourth transistor Q4 to be turned on, the third control signal controls the sixth transistor Q6 to be turned on, and the second control signal controls the fifth transistor Q5 to be turned off; the fourth transistor Q4 and the sixth transistor Q6 are connected to each other, so that the voltage at two ends of the fourth resistor R4 is transmitted to the output end, and meanwhile, the resistance value of the fourth resistor R4 can be modified to adjust the voltage at the output end, thereby adjusting the voltage of the second pin 52 of the main control chip 50. That is, the fourth transistor Q4 and the sixth transistor Q6 are configured to transmit the voltage signal of the first voltage terminal VCC to the output terminal OUT.

As shown in fig. 21, in some embodiments, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are all adjustable resistors.

Referring to fig. 21, the fourth control terminal 104 of the logic control module 1 of the first output module 10 is electrically connected to the first resistor R1, and the fifth control terminal 105 is electrically connected to the second resistor R2; the fourth control terminal 104 of the logic control module 1 of the second output module 20 is electrically connected to the third resistor R3, and the fifth control terminal 105 is electrically connected to the fourth resistor R4.

At this time, the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 may be arbitrarily adjusted, and the first pin 51 and the second pin 52 of the main control chip 50 may output appropriate voltages.

In order to facilitate understanding of the scheme of the present application, the flow of transmitting signals and receiving signals in the communication loop is specifically described below through a flowchart.

As shown in fig. 22, taking the example that the first bus a outputs a low level (the voltage of the second voltage terminal GND) and the second bus B outputs a high level (the voltage of the first voltage terminal VCC), the voltage adjustment flow is specifically described as follows:

s101, the first resistor R1 and the second resistor R2 are set to the maximum resistance value.

S102, the logic control module 1 outputs a high level to the second transistor Q2, and the second transistor Q2 is conducted. At this time, the first transistor Q1 and the third transistor Q3 are turned off.

S103, the first bus A outputs a low level.

S104, the third resistor R3 and the fourth resistor R4 are set to the maximum resistance values.

S105, the logic control module 1 outputs a high level to the fourth transistor Q4, and the fourth transistor Q4 is turned on. At this time, the fifth transistor Q5 and the sixth transistor Q6 are turned off.

S106, outputting a high level by the second bus B.

The present invention is not limited to the above embodiments, and any changes or substitutions within the technical scope of the present invention should be covered by the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An air conditioning system, comprising:

a first bus and a second bus;

a controller, the controller comprising: a main control chip; the main control chip comprises: a first pin and a second pin; the first pin is electrically connected with the first bus, and the second pin is electrically connected with the second bus;

the main control chip comprises: a first output module and a second output module; the first output module is electrically connected with the first pin, and the second output module is electrically connected with the second pin;

At least one of the first output module and the second output module includes: a logic control module and a level conversion circuit;

the level conversion circuit is electrically connected with the logic control module and is also electrically connected with the first voltage end and the second voltage end; the output end of the level conversion circuit is electrically connected with the first pin or the second pin;

the logic control module is configured to output a control signal, and the level conversion circuit is configured to output the voltage signal of the first voltage terminal to a pin electrically connected with the level conversion circuit or output the voltage signal of the second voltage terminal to a pin electrically connected with the level conversion circuit under the control of the control signal.

2. The air conditioning system of claim 1, wherein the logic control module comprises a first control terminal and a second control terminal; the first control end is configured to output a first control signal, and the second control end is configured to output a second control signal;

the level shift circuit comprises a first sub-circuit and a second sub-circuit;

the first sub-circuit is electrically connected with the first control end, the first voltage end and the output end;

the second sub-circuit is electrically connected with the second control end, the second voltage end and the output end;

The logic control module is configured to output a first control signal with an on level and a second control signal with an off level to control the first sub-circuit to be turned on and the second sub-circuit to be turned off; the first sub-circuit is configured to transmit a voltage signal of the first voltage terminal to the output terminal;

the logic control module is further configured to output a first control signal having an off level and a second control signal having an on level to control the first sub-circuit to turn off and the second sub-circuit to turn on, the second sub-circuit being configured to transmit a voltage signal of the second voltage terminal to the output terminal.

3. An air conditioning system according to claim 2, wherein,

the first sub-circuit includes: a first transistor;

the control electrode of the first transistor is electrically connected with the first control end, the first electrode of the first transistor is electrically connected with the first voltage end, and the second electrode of the first transistor is electrically connected with the output end.

4. An air conditioning system according to claim 3, wherein,

the second sub-circuit includes: a second transistor;

The control electrode of the second transistor is electrically connected with the second control end, the first electrode of the second transistor is electrically connected with the output end, and the second electrode of the second transistor is electrically connected with the second voltage end.

5. The air conditioning system according to any one of claims 2 to 4, wherein the logic control module is configured to output a control signal, and the level shift circuit is further configured to output a set voltage signal to a pin to which it is electrically connected, the set voltage signal having a voltage that is any one of a voltage of the first voltage terminal and a voltage of the second voltage terminal, under control of the control signal.

6. The air conditioning system of claim 5, wherein the logic control module further comprises a third control terminal configured to output a third control signal;

the level shift circuit further includes: a third sub-circuit, a first voltage divider sub-circuit, and a second voltage divider sub-circuit;

the first voltage division subcircuit is electrically connected between the first voltage terminal and the first subcircuit;

the first end of the second voltage division subcircuit is electrically connected with the first subcircuit and the output end;

The third sub-circuit is electrically connected with the third control end, the second voltage end and the second end of the second voltage division sub-circuit;

7. An air conditioning system according to claim 6, wherein,

the third sub-circuit includes: a third transistor;

the control electrode of the third transistor is electrically connected with the third control end, the first electrode of the third transistor is electrically connected with the second end of the second voltage division subcircuit, and the second electrode of the third transistor is electrically connected with the second voltage end.

8. The air conditioning system of claim 7, wherein the first sub-circuit comprises: a first transistor;

the first voltage dividing sub-circuit comprises a first resistor, and the second voltage dividing sub-circuit comprises a second resistor;

a first end of the first resistor is electrically connected with the first voltage end, and a second end of the first resistor is electrically connected with a first pole of the first transistor;

The first end of the second resistor is electrically connected with the second pole of the first transistor, and the second end of the second resistor is electrically connected with the first pole of the third transistor.

9. The air conditioning system of claim 8, wherein the first resistor and/or the second resistor is an adjustable resistor.