CN113836076B - Exchanger capable of self-defining protocol line sequence - Google Patents
Exchanger capable of self-defining protocol line sequence Download PDFInfo
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- CN113836076B CN113836076B CN202111121734.1A CN202111121734A CN113836076B CN 113836076 B CN113836076 B CN 113836076B CN 202111121734 A CN202111121734 A CN 202111121734A CN 113836076 B CN113836076 B CN 113836076B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention discloses a self-definable protocol line sequence exchanger, which comprises a first interface and a second interface, wherein the first interface and the second interface are respectively arranged at two ends of a protocol line; the at least two relay groups are respectively connected with the first interface and the second interface, and the first interface and the second interface are connected according to a custom line sequence through the relay groups; the control unit is connected with the relay group and controls the relay group to work; the upper computer is connected and communicated with the control unit, and the line sequence between the first interface and the second interface is set by the upper computer in a self-defining mode. The exchanger capable of customizing the protocol line sequence has the advantages of high safety, stable communication and difficult occurrence of short circuit phenomenon caused by wiring error. When the line sequence needs to be replaced, the line sequence is only required to be set by the upper computer in a self-defined mode, the wiring reliability and efficiency are high, the compatibility is good, and the line sequence automatic switching device is applicable to different non-standardized application scenes. The invention has no miscellaneous wires, and the product is beautiful and easy to maintain.
Description
[ field of technology ]
The invention relates to a wiring device, in particular to a switch capable of customizing a protocol line sequence.
[ background Art ]
The protocol line generally uses network port hardware to communicate with the standard interface, wherein when the industrial bus such as RS485, 232, CAN and the like uses the network port hardware to communicate with the standard interface, the corresponding line sequence between the network port and the standard interface is required to be selected for connection so as to realize the transmission and the reception of information. The existing wiring method between the network port and the standard interface is to convert the standard interface into a wiring terminal, then to connect the wires in a manual mode, and then to fix the wires by screws after the wires are connected. When the network port or the interface needs to be replaced, the network port or the interface needs to be rewiring, so that the efficiency is low, and short circuit or open circuit is caused by easy misconnection. On the other hand, the conventional manual wiring method is also prone to poor contact and communication interruption. In addition, in the existing wiring method, redundant miscellaneous wires exist, and the appearance of the product is affected.
[ invention ]
The invention aims to solve the problems and provides a self-definable protocol line sequence exchanger which has good compatibility, high safety, stable communication and convenient use.
The invention relates to a switch capable of customizing protocol line sequence, which comprises:
the first interface and the second interface are respectively arranged at two ends of the protocol line;
the at least two relay groups are respectively connected with the first interface and the second interface, and the first interface and the second interface are connected through the relay groups according to a self-defined line sequence;
the control unit is connected with the relay group and controls the relay group to work;
the upper computer is connected and communicated with the control unit, and the line sequence between the first interface and the second interface is set by the upper computer in a self-defining mode;
the control unit comprises a USB interface, a USB-to-serial circuit, a processing module, at least two relay group driving circuits and a power module, wherein the USB interface is respectively connected with the upper computer and the USB-to-serial circuit, the processing module is respectively connected with the USB-to-serial circuit and the relay group driving circuits, each relay group driving circuit is respectively connected with one relay group, and the power module is respectively connected with the USB interface, the USB-to-serial circuit, the processing module and the relay group driving circuits;
the USB-to-serial circuit comprises a third chip U3, a sixth capacitor C6, a first diode D1 and a second diode D2, wherein a first pin of the third chip U3 is connected with a third pin of the USB interface, a second pin of the third chip U3 is connected with a second pin of the USB interface, the third pin of the third chip is grounded, a fifth pin of the third chip is connected with a 5V power supply, a sixth pin of the sixth chip is connected with a cathode of the second diode D2, a seventh pin of the seventh chip is connected with an anode of the first diode D1, an eighth pin of the seventh chip is connected with one end of the sixth capacitor C6, an anode of the second diode D2 and a cathode of the first diode D1 are respectively connected with the processing module, and the other end of the sixth capacitor C6 is grounded;
the processing module comprises a fourth chip U4 and a peripheral circuit, wherein the fourth chip U4 is respectively connected with the relay set driving circuit and the peripheral circuit, and the peripheral circuit comprises a reset circuit, a power supply filter circuit and a crystal oscillator circuit. The reset circuit includes a second resistor R2 and a seventh capacitor C7, wherein one end of the second resistor R2 is connected to the ninth pin of the fourth chip U4 and the 3.3V power supply, and the other end of the second resistor R2 is connected to the fourth pin of the fourth chip U4 and one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded. The power supply filter circuit comprises an eighth capacitor C8, one end of the eighth capacitor C8 is connected with an eighth pin of the fourth chip U4, and the other end of the eighth capacitor C8 is connected with a seventh pin of the fourth chip U4 and is grounded. The crystal oscillator circuit provides clock signals for the fourth chip U4 and comprises a ninth capacitor C9, a tenth capacitor C10 and a first crystal oscillator X1, one end of the first crystal oscillator X1 is respectively connected with an eleventh pin of the fourth chip U4 and one end of the ninth capacitor C9, the other end of the first crystal oscillator X1 is respectively connected with a twelfth pin of the fourth chip U4 and one end of the tenth capacitor C10, and the other end of the ninth capacitor C9 is connected with the other end of the tenth capacitor C10 and grounded. The first, second, thirteenth, fourteenth, fifteenth, sixteenth, nineteenth and twentieth pins of the fourth chip U4 are respectively connected with the relay group driving circuit;
the relay group driving circuit comprises a plurality of push-pull circuits, each push-pull circuit comprises a base electrode driving resistor, a current limiting resistor, an NPN triode and a PNP triode, one end of each base electrode driving resistor is connected with the processing module, the other end of each base electrode driving resistor is connected with bases of the NPN triode and the PNP triode, an emitting electrode of each NPN triode and an emitting electrode of each PNP triode are connected with the relay group, a collecting electrode of each NPN triode is connected with one end of the corresponding current limiting resistor, a collecting electrode of each PNP triode is grounded, and the other end of each current limiting resistor is connected with a power supply. In a relay group driving circuit, the output ends of any two push-pull circuits control the on/off of two relays.
The invention relates to a switch capable of customizing protocol line sequence, which comprises:
the first interface and the second interface are respectively arranged at two ends of the protocol line;
the at least two relay groups are respectively connected with the first interface and the second interface, and the first interface and the second interface are connected through the relay groups according to a self-defined line sequence;
the control unit is connected with the relay group and controls the relay group to work;
the upper computer is connected and communicated with the control unit, and the line sequence between the first interface and the second interface is set by the upper computer in a self-defining mode.
The number of the relay groups is the same as the number of pins of the first interface, each relay group comprises a plurality of relays, the number of the relays in each relay group is the same as the number of pins of the second interface, after the common ends of the plurality of relay contacts in each relay group are in short circuit, the common ends of the plurality of relay contacts in each relay group are sequentially connected with one pin of the first interface, and normally open contacts of the plurality of relays in each relay group are sequentially connected with one pin of the second interface.
The control unit comprises a USB interface, a USB-to-serial circuit, a processing module, at least two relay group driving circuits and a power module, wherein the USB interface is respectively connected with an upper computer and the USB-to-serial circuit, the processing module is respectively connected with the USB-to-serial circuit and the relay group driving circuits, each relay group is respectively connected with one relay group driving circuit, and the power module is respectively connected with the USB interface, the USB-to-serial circuit, the processing module and the relay group driving circuits.
Further, the processing module includes a fourth chip U4 and a peripheral circuit, where the fourth chip U4 is connected to the relay set driving circuit and the peripheral circuit, and the peripheral circuit includes a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a second resistor R2, and a first crystal oscillator X1.
Further, the number of the relay group driving circuits is the same as that of the relay groups, each relay group driving circuit is correspondingly connected with each relay group, each relay group driving circuit comprises a plurality of push-pull circuits, each push-pull circuit comprises a base driving resistor, a current limiting resistor, an NPN type triode and a PNP type triode, one end of each base driving resistor is connected with the processing module, the other end of each base driving resistor is respectively connected with bases of the NPN type triode and the PNP type triode, an emitter of each NPN type triode and an emitter of each PNP type triode are respectively connected with the relay groups, a collector of each NPN type triode is connected with one end of each current limiting resistor, a collector of each PNP type triode is grounded, and the other end of each current limiting resistor is connected with a power supply.
In each relay group driving circuit, the number N of the push-pull circuits meets the number of relay group relays corresponding to N (N-1) or more.
In a relay group driving circuit, the output ends of any two push-pull circuits control the on/off of two relays.
The power module comprises a rechargeable battery, a charging management circuit and a power conversion circuit, wherein the charging management circuit is respectively connected with the USB interface, the rechargeable battery and the power conversion circuit, and the power conversion circuit is respectively connected with the USB-to-serial circuit, the processing module and the relay group driving circuit.
Further, the rechargeable battery is a lithium ion battery, and the power supply conversion circuit outputs a 3.3V power supply.
The beneficial effects of the invention are as follows: the switch capable of customizing the protocol line sequence connects the first interface and the second interface according to the customized line sequence through the relay group, so that the switch is high in safety, stable in communication and not easy to cause short circuit phenomenon caused by wiring errors. When the line sequence needs to be replaced, the line sequence is only required to be set by the upper computer in a self-defined mode, disassembly or rewiring is not required, the wiring reliability and efficiency are high, the compatibility is good, and the line sequence automatic wire replacement device is applicable to different non-standardized application scenes. In addition, the invention has no miscellaneous wires, and the product is beautiful and easy to maintain.
[ description of the drawings ]
Fig. 1 is a functional block diagram of the present invention.
Fig. 2 is a schematic diagram of the wiring of the present invention.
Fig. 3 is a functional block diagram of a control unit of the present invention.
Fig. 4 is a circuit diagram of the control unit of the present invention.
Fig. 5 is a control flow chart of the present invention.
FIG. 6 is a software flow diagram of a serial port of a fourth chip in the processing module of the present invention receiving interrupts.
Fig. 7 is a software process flow diagram of a fourth chip in the processing module of the present invention.
[ detailed description ] of the invention
The following examples are further illustrative and supplementary of the present invention and are not intended to limit the invention in any way.
As shown in fig. 1, the switch capable of customizing the protocol line sequence of the present invention includes a first interface 11, a second interface 12, a relay set 20, a control unit 30 and an upper computer 40. The first interface 11 and the second interface 12 are respectively disposed at two ends of the protocol line, the relay set 20 is respectively connected with the first interface 11 and the second interface 12, and the control unit 30 is respectively connected with the relay set 20 and the host computer 40. The device CAN be used in non-standardized application scenes generated by communication of industrial buses such as RS485, 232 and CAN (controller area network) and standard interfaces by using network port hardware, and CAN also be used in other scenes needing to change line sequences.
As shown in fig. 1, the first interface 11 and the second interface 12 are respectively connected with interfaces of different devices to enable connection and/or communication from one device to another. The first interface 11 is provided with at least one pin and the second interface 12 is provided with at least two pins. The first interface 11 and the second interface 12 may be one of various interfaces, such as a USB interface, a DB9 interface, an RJ45 network interface, and the like. In addition, the first interface 11 and the second interface 12 may be the same or different, which may be determined according to the actual usage scenario. In the embodiment shown in fig. 4, the first interface 11 is a DB9 standard interface provided with nine pins and the second interface 12 is an RJ45 network port provided with eight pins.
As shown in fig. 1, the relay set 20 is connected to the first interface 11 and the second interface 12, respectively, and is used for customizing the line sequence between the first interface 11 and the second interface 12. The relay group 20 is provided with at least one of the same number as the number of pins of the first interface 11, for example, when the number of pins of the first interface 11 is two, the number of relay groups 20 is also two. In practical application, only a part of pins in the first interface 11 need to be wired, and at this time, the number of relay groups 20 is the same as the number of pins in the first interface 11 that need to be wired. In the embodiment shown in fig. 4, only the second pin and the third pin are connected in the first interface, and the number of relay sets 20 is two. Each relay group 20 includes a plurality of relays 21, and the number of relays 21 in each relay group 20 is the same as the number of pins of the second interface 12, for example, when the number of pins of the second interface 12 is three, the number of relays 21 in each relay group 20 is three. The relay 21 is a miniature solid state signal relay. After the common contact ends of the plurality of relays 21 in each relay group 20 are shorted, the common contact ends are sequentially connected with one pin of the first interface 11, normally open contacts of the plurality of relays 21 in each relay group 20 are sequentially connected with one pin of the second interface 12 respectively, any pin of the second interface can be controlled to be connected to the pin of the first interface through the suction or disconnection of the relays 21, and finally, any connection between the first interface 11 and the second interface 12 is realized. Specifically, in the embodiment shown in fig. 2, the number of relay groups 20 is nine, and the number of relays 21 in each relay group 20 is eight. The common ends of the contacts of the eight relays 21 in each relay group 20 are connected to nine pins of the first interface 11 in sequence after being short-circuited, normally open contacts of the eight relays 21 in the nine relay groups 20 are respectively connected to eight pins of the second interface in sequence, and any pin of the second interface 12 can be controlled to be connected to any pin of the first interface 11 through the suction or disconnection of each relay 21, so that any connection between the first interface 11 and the second interface 12 is realized.
As shown in fig. 1, the control unit 30 is connected to the relay unit 20 and the host computer 40, respectively, and is used for controlling the on/off of the relay 21 in the relay unit 20. As shown in fig. 3, the control unit 30 includes a USB interface 31, a USB-to-serial circuit 32, a processing module 33, a relay set driving circuit 34, and a power module 35. The USB interface 31 is connected to the host computer 40 and the USB serial port circuit 32, and is used for transmitting data of the host computer 40 to the USB serial port circuit 32. The processing module 33 is connected to the USB-to-serial circuit 32 and the relay set driving circuit 34, respectively, and receives the data from the USB-to-serial circuit 32, processes the data, and outputs a control signal to the relay set driving circuit 34. The relay group driving circuits 34 are connected with the relay groups 20, wherein the number of the relay group driving circuits 34 is the same as that of the relay groups 20, that is, each relay group driving circuit 34 corresponds to one relay group 20, and the relay group driving circuits 34 are used for controlling the relays 21 in the relay groups 20 to be closed or opened. The power module 35 is connected to the USB interface 31, the USB-to-serial circuit 32, the processing module 33, and the relay set driving circuit 34, and is used for supplying power to the USB interface 31, the USB-to-serial circuit 32, the processing module 33, and the relay set driving circuit 34.
Specifically, as shown in fig. 4, the USB-to-serial circuit 32 includes a third chip U3, a sixth capacitor C6, a first diode D1 and a second diode D2, wherein a first pin of the third chip U3 is connected to a third pin of the USB interface 31, a second pin of the third chip U is connected to a second pin of the USB interface 31, a third pin of the third chip is grounded, a fifth pin of the third chip is connected to a 5V power supply, a sixth pin of the sixth chip is connected to a cathode of the second diode D2, a seventh pin of the sixth chip is connected to an anode of the first diode D1, an eighth pin of the eighth chip is connected to one end of the sixth capacitor C6, an anode of the second diode D2 and a cathode of the first diode D1 are respectively connected to the processing module 33, and another end of the sixth capacitor C6 is grounded. In this embodiment, the specific model of the third chip U3 is CH340N.
As shown in fig. 4, the processing module 33 includes a fourth chip U4 and a peripheral circuit, wherein the fourth chip U4 is connected to the relay set driving circuit 34 and the peripheral circuit, and the peripheral circuit includes a reset circuit, a power filter circuit and a crystal oscillator circuit. The reset circuit includes a second resistor R2 and a seventh capacitor C7, wherein one end of the second resistor R2 is connected to the ninth pin of the fourth chip U4 and the 3.3V power supply, and the other end of the second resistor R2 is connected to the fourth pin of the fourth chip U4 and one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded. The power supply filter circuit comprises an eighth capacitor C8, one end of the eighth capacitor C8 is connected with an eighth pin of the fourth chip U4, and the other end of the eighth capacitor C8 is connected with a seventh pin of the fourth chip U4 and is grounded. The crystal oscillator circuit provides clock signals for the fourth chip U4 and comprises a ninth capacitor C9, a tenth capacitor C10 and a first crystal oscillator X1, one end of the first crystal oscillator X1 is respectively connected with an eleventh pin of the fourth chip U4 and one end of the ninth capacitor C9, the other end of the first crystal oscillator X1 is respectively connected with a twelfth pin of the fourth chip U4 and one end of the tenth capacitor C10, and the other end of the ninth capacitor C9 is connected with the other end of the tenth capacitor C10 and grounded. The first, second, thirteenth, fourteenth, fifteenth, sixteenth, nineteenth and twentieth pins of the fourth chip U4 are connected to the relay group driving circuit 34, respectively. In this embodiment, the specific model of the fourth chip U4 is HC32L110C6PA.
As shown in fig. 4, the relay group driving circuit 34 includes a plurality of push-pull circuits 341, and in each relay group driving circuit 34, the number N of push-pull circuits 341 satisfies the number n×n (N-1) > of relay 21 in the corresponding relay group 20, and in the embodiment shown in fig. 4, the number of push-pull circuits 341 is four if the number of relays 21 in each relay group is eight, so as to simplify the circuit structure. Each push-pull circuit 341 has the same structure and is respectively connected with the relay 21 in the corresponding relay group 20, and each push-pull circuit 341 comprises a base electrode driving resistor, a current limiting resistor, an NPN triode and a PNP triode, wherein one end of the base electrode driving resistor is connected with the processing module 33, the other end of the base electrode driving resistor is respectively connected with bases of the NPN triode and the PNP triode, an emitting electrode of the NPN triode and an emitting electrode of the PNP triode are respectively connected with the relay group 20, a collecting electrode of the NPN triode is connected with one end of the current limiting resistor, a collecting electrode of the PNP triode is grounded, and the other end of the current limiting resistor is connected with a power supply. In one relay group drive circuit 34, the output terminals of any two push-pull circuits 341 control the on or off of two relays 21. The present embodiment is described taking the structure of one of the push-pull circuits 341 as an example, and the other push-pull circuits 341 are different in the structure only in that the connected relay 21 is different. The push-pull circuit 341 includes a third resistor R3, a fourth resistor R4, a first triode Q1, and a second triode Q2, where the third resistor R3 is a base driving resistor, the fourth resistor R4 is a current limiting resistor, the first triode Q1 is an NPN type triode, and the second triode Q2 is a PNP type triode. The push-pull circuit 341 is configured to improve the driving capability of the IO port of the fourth chip U4. Specifically, in the embodiment shown in fig. 4, one end of the third resistor R3 is connected to the processing module 33, the other ends thereof are respectively connected to the bases of the first transistor Q1 and the second transistor Q2, the emitter of the first transistor Q1 and the emitter of the second transistor Q2 are respectively connected to the input anode of the first relay RL11, the input cathode of the second relay RL12, the input anode of the third relay RL13, the input cathode of the fourth relay RL14, the input anode of the fifth relay RL15 and the input cathode of the sixth relay RL16 in the relay group 20, the collector of the first transistor Q1 is connected to one end of the fourth resistor R4, the collector of the second transistor Q2 is grounded, and the other end of the fourth resistor R4 is connected to a power supply, which is a 3.3V power supply. The push-pull circuit 341 is configured to improve the driving capability of the IO port of the fourth chip U4, the output current of the IO port of the fourth chip U4 is typically several milliamperes, and the relay 21 normally needs several tens of milliamperes of current for actuation, taking JK16 type solid state relay as an example, when the eleventh relay RL11 is actuated, the output signal AOUT1 of the first pin of the fourth chip U4 is at a high level, the first triode Q1 is turned on, the second triode Q2 is turned off, the output signal AOUT2 of the second pin of the fourth chip U4 is at a low level, the third triode Q3 is turned off, the fourth triode Q4 is turned on, the current at this time flows from the 3.3V power supply to the first triode Q1 through the fourth resistor R4, and then flows from the input anode of the eleventh relay RL11 to the input cathode thereof, and then flows to the ground through the fourth triode Q4, where the calculation formula of the current flowing through the input diode of the eleventh relay RL11 is as follows:
I＝(VCC–Vce(Q1)–Vce(Q4)–Vf(RL11))/R4；
wherein VCC is 3.3V, vce (Q1) is a saturation voltage drop of the first transistor Q1 is 0.3V, vce (Q4) is a saturation voltage drop of the fourth transistor Q4 is 0.3V, vf (RL 11) is a conduction voltage drop of the input diode of the eleventh relay RL11, generally between 1.2V and 1.5V, and R4 is a resistance value of the fourth resistor R4, which is 36 ohms. I= (3.3-0.3-0.3-1.5)/36=0.033A, i.e. 33mA, when the on-voltage drop of the input diode of the eleventh relay RL11 is 1.2V, i= (3.3-0.3-0.3-1.2)/36=0.0417A, i.e. 41.7 mA.
As shown in fig. 4, when AOUT1 of the fourth chip U4 outputs a high level, the first transistor Q1 of the push-pull circuit 341 is turned on, the second transistor Q2 is turned off, and AO1 is a high level; when the AOUT1 of the fourth chip U4 outputs a low level, the second transistor Q2 of the push-pull circuit 341 is turned on, the first diode Q1 is turned off, and AO1 is a low level; when the AOUT1 output of the fourth chip U4 is in a high-impedance state, the first transistor Q1 and the second transistor Q2 of the push-pull circuit 341 are turned off, and the AO1 outputs a high-impedance state. Similarly, the third triode Q3 and the fourth triode Q4, the fifth triode Q5 and the sixth triode Q6, the seventh triode Q7 and the eighth triode Q8 form a push-pull output circuit, the push-pull circuit can output three states of high level, low level and high resistance, the four groups of push-pull circuits can control twelve relays at most, when one relay needs to be sucked, the push-pull circuit corresponding to the anode of the input end of the relay is output as high level, the push-pull circuit corresponding to the cathode of the input end of the relay is output as low level, and other push-pull circuits are output as high resistance. For example, when the first relay RL1 is required to be attracted, the output AO1 of the first group push-pull circuit is set to a high level, the output AO2 of the second group push-pull circuit is set to a low level, and the output AO3 of the third group push-pull circuit and the output AO4 of the fourth group push-pull circuit are set to a high resistance state.
As shown in fig. 3 and 4, the power module 35 is configured to supply power, and includes a rechargeable battery 351, a charging management circuit 352 and a power conversion circuit 353, wherein the charging management circuit 352 is connected to the USB interface 31, the rechargeable battery 351 and the power conversion circuit 353, and the power conversion circuit 353 is connected to the USB serial port circuit 32, the processing module 33 and the relay set driving circuit 34. Specifically, as shown in fig. 4, the rechargeable battery 351 is a lithium ion battery, but other types of rechargeable batteries are also possible, and the embodiment is not limited thereto. The charge management circuit 352 includes an input end filter circuit, a first resistor R1 and a first chip U1, where the input end filter circuit filters an input power supply of the first chip U1, the input end filter circuit includes a third capacitor C3 and a fourth capacitor C4, the fourth capacitor C4 is an electrolytic capacitor, one end of the third capacitor C3 is connected with an anode of the fourth capacitor C4, a fourth pin of the first chip U1 and a 5V power supply, the other end of the third capacitor C3 is connected with a cathode of the fourth capacitor C4, one end of the first resistor R1 is grounded, the other end of the first resistor R1 is connected with a fifth pin of the first chip U1, the first pin and the second pin of the first chip U1 are grounded, and the third pin of the first chip U1 is connected with an anode of the rechargeable battery 351. In this embodiment, the specific model of the first chip U1 is TP4055. The power conversion circuit 353 includes an input end filter circuit, an output end filter circuit and a second chip U2, wherein the input end filter circuit includes a first capacitor C1 and a second capacitor C2, one end of the first capacitor C1 is respectively connected with the positive electrode of the second capacitor C2, the first pin and the third pin of the second chip U2, and the positive electrode of the rechargeable battery 351, and the other end of the first capacitor C1, the negative electrode of the second capacitor C2 and the second pin of the second chip U2 are respectively grounded. The output end filter circuit comprises a fifth capacitor C5, one end of the fifth capacitor C5 and a fifth pin of the second chip U2 are respectively connected with a 3.3V power supply, and the other end of the fifth capacitor C5 and a fourth pin of the second chip U2 are respectively grounded. In this embodiment, the specific model of the second chip U2 is TPS78233.
As shown in fig. 1, the upper computer 40 is connected to and communicates with the control unit 30, and is used for customizing the line sequence between the first interface 11 and the second interface 12, and sending the set data to the control unit 30. For example, when the first interface 11 and the second interface 12 need to be connected, the line sequence of the first interface 11 and the second interface 12 can be set through the upper computer; when the line sequence of the first interface 11 and the second interface 12 needs to be replaced, the line sequence between the first interface 11 and the second interface 12 needs to be reset on the upper computer 40, so as to meet the requirement of self-defined wiring. The host computer 40 may be an industrial personal computer or a computer, and is connected to and communicates with the control unit 30 through a USB interface.
As shown in fig. 3 and 4, the working principle of the invention is as follows: when the upper computer 40 is connected with the control unit 30 through the USB, the 5V power supply of the USB interface charges the rechargeable battery 351 through the charging management circuit 352, and simultaneously generates 3.3V power supply through the power conversion circuit 353 to supply power to the USB serial port conversion circuit 32, the processing module 33 and the relay set driving circuit 34, meanwhile, the upper computer 40 converts line serial data between the set first interface 11 and the set second interface 12 into serial data through the USB serial port conversion circuit 32 to be communicated with the processing module 33, and the processing module 33 controls the relay set driving circuit 34 according to the received data. When the host computer 40 is disconnected from the control unit 30, the rechargeable battery 351 generates 3.3V power through the power conversion circuit 353, and supplies power to the USB serial port circuit 32, the processing module 33 and the relay set driving circuit 34, so as to maintain the control of the control unit 30 on the relay set 20. That is, when the control unit 30 is disconnected from the host computer 40, the rechargeable battery 351 can generate 3.3V power through the power conversion circuit 353 to meet the power supply requirement.
As shown in fig. 5, the control flow of the present invention is: the upper computer 40 sends a control frame, the control unit 30 receives the command of the upper computer 40 to send the control frame and then responds to the control frame, then the upper computer 40 sends a parameter frame, the parameter frame data comprises parameters for connecting a certain pin of the first jack 11 with a certain pin of the second jack 12, the control unit 30 receives the command of the parameter frame sent by the upper computer 40 and then responds to the parameter frame, finally, the upper computer 40 sends an end frame, the control unit 30 receives the command of the end frame sent by the upper computer 40 and then returns to the end frame, and simultaneously, the relay group is controlled to act, so that a certain pin of the first jack 11 is connected with a certain pin of the second jack 12. The command tables of the control frame, the response control frame, the parameter frame, the response parameter frame, the end frame and the response end frame are shown in table 1.
TABLE 1 Command Table
As shown in fig. 6, after receiving the data sent by the upper computer 40, the fourth chip U4 enters into the serial port to receive the interrupt, and after entering into the interrupt, it first determines whether the received frame header is correct, if the frame header is incorrect, it indicates that an interference signal is received, and exits from the interrupt, if the received frame header is correct, it then determines whether the frame end is correct, if the frame end is incorrect, it indicates that the received data is incomplete or incorrect, and exits from the interrupt, and if the received frame end is correct, it indicates that a complete set of data is received, then it sets a flag bit, and exits from the interrupt program.
As shown in fig. 7, the software processing flow of the fourth chip U4 is: the fourth chip U4 circularly detects whether the serial port interrupt has a flag bit, if so, the fourth chip U4 receives the data sent by the upper computer 40, after receiving the data, if the data is in a state of waiting to receive a control frame, the fourth chip U4 judges whether the data is the control frame data, if the data is the control frame data, the control frame is sent to the upper computer 40 in a response mode, and the current state is switched to the state of waiting to receive a parameter frame; if the current state is the state of waiting to receive the parameter frame, judging whether the data is the parameter frame data, if the data is the parameter frame data, sending the parameter frame to the upper computer 40 in a response mode, and switching the current state to the state of waiting to receive the end frame; if the state of waiting to receive the end frame is present, judging whether the data is the end frame data, if the data is the end frame data, sending the end frame to the upper computer 40, switching the present state to the state of waiting to receive the control frame, controlling the relay group 20 to act, and adjusting the line sequence between the first interface 11 and the second interface 12, thereby realizing the connection of the first interface 11 and the second interface 12.
Although the present invention has been disclosed by the above embodiments, the scope of the present invention is not limited thereto, and modifications, substitutions, etc. made to the above components will fall within the scope of the claims of the present invention without departing from the spirit of the present invention.
Claims (8)
1. A customizable protocol line sequence switch, the switch comprising:
the first interface (11) and the second interface (12), the first interface (11) and the second interface (12) are respectively arranged at two ends of the protocol line;
at least two relay groups (20) respectively connected with the first interface (11) and the second interface (12), wherein the first interface (11) and the second interface (12) are connected according to a self-defined line sequence through the relay groups (20);
a control unit (30) connected to the relay group (20), the control unit (30) controlling the operation of the relay group (20);
the upper computer (40) is connected and communicated with the control unit (30), and the line sequence between the first interface (11) and the second interface (12) is set by the upper computer (40) in a self-defining mode;
the control unit (30) comprises a USB interface (31), a USB-to-serial circuit (32), a processing module (33), at least two relay group driving circuits (34) and a power module (35), wherein the USB interface (31) is respectively connected with an upper computer (40) and the USB-to-serial circuit (32), the processing module (33) is respectively connected with the USB-to-serial circuit (32) and the relay group driving circuits (34), each relay group driving circuit (34) is respectively connected with one relay group (20), and the power module (35) is respectively connected with the USB interface (31), the USB-to-serial circuit (32), the processing module (33) and the relay group driving circuits (34);
the USB-to-serial circuit (32) comprises a third chip U3, a sixth capacitor C6, a first diode D1 and a second diode D2, wherein a first pin of the third chip U3 is connected with a third pin of the USB interface (31), a second pin of the third chip U is connected with a second pin of the USB interface (31), the third pin of the third chip is grounded, a fifth pin of the third chip is connected with a 5V power supply, a sixth pin of the sixth chip is connected with a cathode of the second diode D2, a seventh pin of the sixth chip is connected with an anode of the first diode D1, an eighth pin of the seventh pin of the sixth diode is connected with one end of the sixth capacitor C6, an anode of the second diode D2 and a cathode of the first diode D1 are respectively connected with the processing module (33), and the other end of the sixth capacitor C6 is grounded;
the processing module (33) comprises a fourth chip U4 and a peripheral circuit, the fourth chip U4 is respectively connected with the relay set driving circuit (34) and the peripheral circuit, and the peripheral circuit comprises a reset circuit, a power supply filter circuit and a crystal oscillator circuit; the reset circuit comprises a second resistor R2 and a seventh capacitor C7, wherein one end of the second resistor R2 is connected with a ninth pin of the fourth chip U4 and a 3.3V power supply, the other end of the second resistor R2 is connected with one end of the fourth pin of the fourth chip U4 and the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded; the power supply filter circuit comprises an eighth capacitor C8, one end of the eighth capacitor C8 is connected with an eighth pin of the fourth chip U4, and the other end of the eighth capacitor C8 is connected with a seventh pin of the fourth chip U4 and is grounded; the crystal oscillator circuit provides clock signals for the fourth chip U4 and comprises a ninth capacitor C9, a tenth capacitor C10 and a first crystal oscillator X1, one end of the first crystal oscillator X1 is respectively connected with an eleventh pin of the fourth chip U4 and one end of the ninth capacitor C9, the other end of the first crystal oscillator X1 is respectively connected with a twelfth pin of the fourth chip U4 and one end of the tenth capacitor C10, and the other end of the ninth capacitor C9 is connected with the other end of the tenth capacitor C10 and grounded; the first, second, thirteenth, fourteenth, fifteenth, sixteenth, nineteenth and twentieth pins of the fourth chip U4 are respectively connected with a relay group driving circuit (34);
the relay group driving circuit (34) comprises a plurality of push-pull circuits (341), wherein the push-pull circuits (341) comprise base electrode driving resistors, current limiting resistors, NPN type triodes and PNP type triodes, one ends of the base electrode driving resistors are connected with the processing module (33), the other ends of the base electrode driving resistors are respectively connected with bases of the NPN type triodes and the PNP type triodes, emitting electrodes of the NPN type triodes and emitting electrodes of the PNP type triodes are respectively connected with the relay group (20), collecting electrodes of the NPN type triodes are connected with one ends of the current limiting resistors, collecting electrodes of the PNP type triodes are grounded, and the other ends of the current limiting resistors are connected with a power supply; in a relay group driving circuit (34), the output ends of any two push-pull circuits (341) control the on/off of the two relays (21).
2. A customizable protocol line sequence switch, the switch comprising:
the first interface (11) and the second interface (12), the first interface (11) and the second interface (12) are respectively arranged at two ends of the protocol line;
at least two relay groups (20) respectively connected with the first interface (11) and the second interface (12), wherein the first interface (11) and the second interface (12) are connected according to a self-defined line sequence through the relay groups (20);
a control unit (30) connected to the relay group (20), the control unit (30) controlling the operation of the relay group (20);
the upper computer (40) is connected and communicated with the control unit (30), and the line sequence between the first interface (11) and the second interface (12) is set by the upper computer (40) in a self-defining mode;
the number of the relay groups (20) is the same as that of pins of the first interface (11), each relay group (20) comprises a plurality of relays (21), the number of the relays (21) in each relay group (20) is the same as that of pins of the second interface (12), after common ends of the plurality of the relays (21) in each relay group (20) are in short circuit, the common ends of the plurality of the relays are sequentially connected with one pin of the first interface (11), and normally open contacts of the plurality of the relays (21) in each relay group (20) are sequentially connected with one pin of the second interface (12);
the control unit (30) comprises a USB interface (31), a USB-to-serial circuit (32), a processing module (33), at least two relay group driving circuits (34) and a power module (35), wherein the USB interface (31) is respectively connected with an upper computer (40) and the USB-to-serial circuit (32), the processing module (33) is respectively connected with the USB-to-serial circuit (32) and the relay group driving circuits (34), each relay group driving circuit (34) is respectively connected with one relay group (20), and the power module (35) is respectively connected with the USB interface (31), the USB-to-serial circuit (32), the processing module (33) and the relay group driving circuits (34).
3. The switch of claim 2, wherein the processing module (33) includes a fourth chip U4 and a peripheral circuit, the fourth chip U4 is connected to the relay set driving circuit (34) and the peripheral circuit, and the peripheral circuit includes a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a second resistor R2 and a first crystal oscillator X1.
4. The switch of claim 2, wherein the number of the relay group driving circuits (34) is the same as the number of the relay groups (20), each relay group driving circuit (34) is respectively and sequentially connected with each relay group (20), each relay group driving circuit (34) comprises a plurality of push-pull circuits (341), each push-pull circuit (341) comprises a base driving resistor, a current limiting resistor, an NPN transistor and a PNP transistor, one end of the base driving resistor is connected with the processing module (33), the other end of the base driving resistor is respectively connected with bases of the NPN transistor and the PNP transistor, an emitter of the NPN transistor and an emitter of the PNP transistor are respectively connected with the relay groups (20), a collector of the NPN transistor is connected with one end of the current limiting resistor, a collector of the PNP transistor is grounded, and the other end of the current limiting resistor is connected with a power supply.
5. The customizable protocol line sequence switch of claim 4, wherein the number N of push-pull circuits (341) in each relay group drive circuit (34) satisfies the number of relay group relays (21) corresponding to N x (N-1) > or more.
6. The customizable protocol line sequence switch of claim 4, wherein in one relay group drive circuit (34), the output of any two push-pull circuits (341) controls the on or off of two relays (21).
7. The customizable protocol line-sequential switch of claim 2, wherein the power module (35) comprises a rechargeable battery (351), a charge management circuit (352) and a power conversion circuit (353), the charge management circuit (352) is respectively connected with the USB interface (31), the rechargeable battery (351) and the power conversion circuit (353), and the power conversion circuit (353) is respectively connected with the USB serial port circuit (32), the processing module (33) and the relay group driving circuit (34).
8. The customizable protocol line-sequential switch of claim 7, wherein the rechargeable battery (351) is a lithium ion battery, and the power conversion circuit (353) outputs a 3.3V power supply.
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| CN102136664A (en) * | 2010-01-27 | 2011-07-27 | 鸿富锦精密工业（深圳）有限公司 | Communication interface switching device |
| EP2530850A3 (en) * | 2011-06-03 | 2015-07-08 | Samsung Electronics Co., Ltd. | Repeater connected to a gateway and a client device via the Wi-Fi protocol with filtering of different frequency bands. |
| EP3575900B1 (en) * | 2017-12-27 | 2021-03-10 | Shanghai Chenzhu Instrument Co., Ltd. | Intelligent safety relay and circuit applied thereby |
| CN215581226U (en) * | 2021-09-24 | 2022-01-18 | 深圳达人高科电子有限公司 | Exchanger capable of customizing protocol line sequence |
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