CN116760958B

CN116760958B - Image processing apparatus, system, component, device, and method

Info

Publication number: CN116760958B
Application number: CN202311054856.2A
Authority: CN
Inventors: 司学迁
Original assignee: Beijing Xiangdixian Computing Technology Co Ltd
Current assignee: Beijing Xiangdixian Computing Technology Co Ltd
Priority date: 2023-08-22
Filing date: 2023-08-22
Publication date: 2023-12-19
Anticipated expiration: 2043-08-22
Also published as: CN116760958A

Abstract

The present disclosure provides an image processing apparatus, system, component, device, and method. The device comprises a lookup table storage module, a correction module and a correction module, wherein the lookup table storage module is configured to store a lookup table required by image gamma calibration or degamma calibration, and the lookup table is used for describing the mapping relation between an input gray value before calibration and an output gray value after calibration; and the judging module is configured to judge whether the output R value, the output G value and the output B value in a group of output gray values in the lookup table are completely equal, and if not, the corresponding error signals are output. In the scheme, the lookup table required by the image gamma calibration or the degamma calibration can be subjected to error lookup, and a group of output gray values corresponding to the error signals in the lookup table can be checked and checked according to the error signals, so that the debugging and debugging speed and efficiency of the lookup table are improved to a certain extent.

Description

Image processing apparatus, system, component, device, and method

Technical Field

The present disclosure relates to the field of image processing technologies, and in particular, to an image processing apparatus, system, component, device, and method.

Background

Because human eyes are nonlinear to the perception of brightness and are sensitive to dark information, the nonlinear brightness information is often stored in a gamma storage mode in engineering so as to achieve the effect of storing more dark information. After the graphics processor (Graphics Processing Unit, GPU) reads the nonlinear read-through information, degamma operation is performed to restore the nonlinear read-through information to linear brightness information, which is degamma calibration (degamma calibration).

When the image information is output through the display, the brightness of the display is shown as a gamma function to darken the original image, such as the dark gray line in fig. 1. Gamma calibration (Gamma calibration) techniques to solve this problem, the image information output to the display is subjected to Gamma inverse function (i.e., gamma calibration function) operation, so as to first lighten the brightness of the image, thereby counteracting the process of darkening the image of the display, such as the light gray lines in fig. 1.

The input image format of the degamma calibration (or gamma calibration) module is in RGB form, and in order to reduce the amount of hardware calculation, degamma calibration (or gamma calibration) operation is calculated in advance through software and written into the LUT, and the graphics processor applies the LUT to perform degamma calibration (or gamma calibration). Errors may occur during the software calculation of the degamma function (or the degamma inverse function), i.e. during the calculation of the degamma calibration value (or the gamma calibration value), or during the configuration of the respective Look-Up Table (LUT) via Advanced High-performance Bus (AHB), for example, during the write address offset, resulting in the possible errors of the values stored in the LUT. In practical applications, performing degamma calibration or gamma calibration by applying an incorrect LUT may cause calibration anomalies such as color distortion and gray scale deviation of the output image.

Disclosure of Invention

The disclosure aims to provide an image processing device, an image processing system, an image processing assembly, an image processing device, an image processing assembly, an image processing device and an image processing method, and the technical problem that in the prior art, degamma calibration or LUT input errors corresponding to gamma calibration are solved.

According to one aspect of the present disclosure, there is provided an image processing apparatus including:

the lookup table storage module is configured to store a lookup table required by image gamma calibration or degamma calibration, and the lookup table is used for describing the mapping relation between an input gray value before calibration and an output gray value after calibration; the input gray values comprise equal input R values, input G values and input B values, and the corresponding output R values, output G values and output B values form a group of output gray values;

and the judging module is configured to judge whether the output R value, the output G value and the output B value in a group of output gray values in the lookup table are completely equal, and if not, the corresponding error signals are output.

In some embodiments, in the image processing apparatus, the judging module includes a comparing unit and a buffering unit:

the comparison unit is configured to compare whether the output R value, the output G value and the output B value in a group of output gray values in the lookup table are completely equal, and if not, the corresponding error signals are output to the buffer unit;

And the buffer unit is configured to buffer the input gray value corresponding to the error signal when the error signal is received.

In some embodiments, in the above-described image processing apparatus, the comparing unit includes a first equivalent comparator, a second equivalent comparator, and a nand gate operator;

a first equal value comparator configured to compare whether an output R value and an output B value in a set of output gray values in the lookup table are equal, and a second equal value comparator configured to compare whether an output G value and an output B value in the set of output gray values are equal; or, a first equal value comparator configured to compare whether an output R value and an output B value in a set of output gray values in the lookup table are equal, and a second equal value comparator configured to compare whether an output R value and an output G value in the set of output gray values are equal; or, a first equal value comparator configured to compare whether an output R value and an output G value in a set of output gray values in the lookup table are equal, and a second equal value comparator configured to compare whether an output G value and an output B value in the set of output gray values are equal;

the first equal value comparator and the second equal value comparator are configured to output a high-level signal to the NAND gate operator if the two are equal, and output a low-level signal to the NAND gate operator if the two are not equal;

The NAND gate operator is configured to conduct NAND operation on signals output by the first equivalent comparator and the second equivalent comparator, and a first judgment signal is obtained and output;

wherein the error signal is a first judgment signal of high level.

In some embodiments, in the image processing apparatus, the buffer unit includes a first register and a second register;

the first register is configured to enable the flag bit of the first register to be enabled and output a second judging signal when the error signal is received and the flag bit of the first register is disabled;

and the second register is configured to buffer the input gray value corresponding to the second judgment signal under the triggering of the second judgment signal.

In some embodiments, in the image processing apparatus, the error signal is a high level signal, and the buffer unit includes a first register, a second register, a first multiplexer, and a second multiplexer; the initial values of the first register and the second register are low level;

the first multiplexer is provided with a first input end connected with the output end of the comparison unit, a second input end and a control end connected with the output end of the first register, an output end connected with the input end of the first register, and is configured to output information acquired by the first input end of the first multiplexer to the first register when the output end of the first register is at a low level, and output information acquired by the second input end of the first multiplexer to the first register when the output end of the first register is at a high level;

The first input end of the second multiplexer acquires the input gray value corresponding to the group of output gray values currently being compared by the comparison unit, the second input end of the second multiplexer is connected with the output end of the second register, the control end of the second multiplexer is connected with the output end of the first register, the output end of the second multiplexer is connected with the input end of the second register, the second multiplexer is configured to output the information acquired by the first input end of the second multiplexer to the second register when the output end of the first register is in a low level, and output the information acquired by the second input end of the second multiplexer to the second register when the output end of the first register is in a high level;

when information is written into the second register, the original data in the second register is covered.

In some embodiments, the image processing apparatus further includes: the calibration value calculation module and the writing control module;

the calibration value calculation module is configured to calculate an output gray value corresponding to each input gray value according to a gamma calibration function or a degamma calibration function;

the writing control module is configured to sequentially write the mapping relation between the output gray values calculated by the calibration value calculation module and the corresponding input gray values into the lookup table according to groups, and output a group of output gray values to the judging module when the group of output gray values are written into the lookup table;

The judging module is specifically configured to:

when a group of output gray values output by the writing control module is received, whether the output R value, the output G value and the output B value in the group of output gray values are completely equal is judged, and if not, a corresponding error signal is output.

In some embodiments, the image processing apparatus further includes: a third register;

the write control module is specifically configured to: the mapping relation between the output gray values calculated by the calibration value calculation module and the corresponding input gray values is sequentially written into the lookup table according to groups, and when one group of output gray values is written into the lookup table, the group of output gray values is written into the third register; when one group of output gray values are written into the third register, the original data in the third register are covered;

the judging module is specifically configured to:

and judging whether the output R value, the output G value and the output B value in the group of output gray values currently cached in the third register are completely equal, and if not, outputting a corresponding error signal.

In some embodiments, in the image processing apparatus, the third register includes a first sub-register, a second sub-register, and a third sub-register;

The write control module is specifically configured to:

the mapping relation between the output gray values calculated by the calibration value calculation module and the corresponding input gray values is sequentially written into the lookup table according to groups, and when one group of output gray values are written into the lookup table, the output R value, the output G value and the output B value in the group of output gray values are respectively written into the first sub-register, the second sub-register and the third sub-register; when the output R value, the output G value and the output B value in the group of output gray values are respectively written into the first sub-register, the second sub-register and the third sub-register, original data in the first sub-register, the second sub-register and the third sub-register are respectively covered;

the judging module is specifically configured to:

and judging whether the output R value, the output G value and the output B value respectively cached in the first sub-register, the second sub-register and the third sub-register are completely equal, and if not, outputting a corresponding error signal.

In some embodiments, the image processing apparatus further includes: a fourth register;

the write control module is specifically configured to: the mapping relation between the output gray values calculated by the calibration value calculation module and the corresponding input gray values is sequentially written into the lookup table according to groups, when one group of output gray values are written into the lookup table, the group of output gray values are output to the judgment module, and the input gray values corresponding to the group of output gray values are written into the fourth register; when an input gray value is written into the fourth register, the original data in the fourth register is covered;

The judging module is specifically configured to:

when a group of output gray values output by the writing control module is received, judging whether the output R value, the output G value and the output B value in the group of output gray values are completely equal, and if not, outputting an error signal corresponding to the input gray value currently cached in the fourth register.

In some embodiments, in the image processing apparatus, the fourth register includes a fourth sub-register, a fifth sub-register, and a sixth sub-register;

the write control module is specifically configured to: the mapping relation between the output gray values calculated by the calibration value calculation module and the corresponding input gray values is sequentially written into the lookup table according to groups, when one group of output gray values are written into the lookup table, the group of output gray values are output to the judgment module, when the output R values in the group of output gray values are written into the lookup table, the corresponding input R values are written into the fourth sub-register, when the output G values in the group of output gray values are written into the lookup table, the corresponding input G values are written into the fifth sub-register, and when the output B values in the group of output gray values are written into the lookup table, the corresponding input B values are written into the sixth sub-register; when an input R value is written into the fourth sub-register, the original data in the fourth sub-register is covered, when an input G value is written into the fifth sub-register, the original data in the fifth sub-register is covered, and when an input B value is written into the sixth sub-register, the original data in the sixth sub-register is covered;

The judging module is specifically configured to:

when the input gray values buffered in the fourth sub-register, the fifth sub-register and the sixth sub-register are equal, judging whether the output R value, the output G value and the output B value in a group of output gray values corresponding to the input gray values output by the writing control module are completely equal, and if not, outputting an error signal corresponding to the input gray values.

In some embodiments, in the image processing apparatus, the writing control module is specifically configured to:

and taking the corresponding input gray values as write pointers, sequentially writing the output gray values calculated by the calibration value calculation module into the lookup table according to groups, and outputting the groups of output gray values to the judgment module when the groups of output gray values are written into the lookup table.

In some embodiments, in the image processing apparatus, the lookup table includes a first sub-lookup table, a second sub-lookup table, and a third sub-lookup table;

the first sub-lookup table is configured to describe the mapping relation between the input R value before calibration and the output R value after calibration;

the second sub-lookup table is configured to describe the mapping relation between the input G value before calibration and the output G value after calibration;

The third sub-lookup table is configured to describe the mapping relation between the input B value before calibration and the output B value after calibration;

the write control module is specifically configured to:

respectively taking the corresponding input R value, input G value and input B value as write pointers, and sequentially writing each group of output R value, output G value and output B value obtained by calculation of the calibration value calculation module into a first sub-lookup table, a second sub-lookup table and a third sub-lookup table according to the groups;

when one group of output gray values is written into the lookup table, the group of output gray values is output to the judging module.

the lookup table storage module includes a fifth register, a sixth register, and a seventh register configured to store a first sub-lookup table, a second sub-lookup table, and a third sub-lookup table, respectively.

In some embodiments, the image processing apparatus further includes:

and the image processing module is configured to map the gray values in the image data input into the image processing module into corresponding gamma calibrated or degamma calibrated output gray values by using a lookup table and output the corresponding gamma calibrated or degamma calibrated output gray values.

According to another aspect of the present disclosure, there is provided a graphic processing system including the image processing apparatus of any one of the above embodiments.

According to another aspect of the present disclosure, there is provided an electronic assembly comprising the image processing system of any of the embodiments described above.

According to another aspect of the present disclosure, there is provided an electronic device comprising the electronic assembly of any of the above embodiments.

According to another aspect of the present disclosure, there is provided a graphic processing method including:

judging whether the output R value, the output G value and the output B value in a group of output gray values in the lookup table stored in the lookup table storage module are completely equal, and if not, outputting an error signal;

the lookup table is a lookup table required by image gamma calibration or degamma calibration, and is used for describing the mapping relation between an input gray value before calibration and an output gray value after calibration; the input gray values comprise equal input R values, input G values and input B values, and the corresponding output R values, output G values and output B values form a group of output gray values.

In some embodiments, in the above image processing method, it is determined whether the output R value, the output G value, and the output B value in a set of output gray values in a lookup table stored in a lookup table storage module are completely equal, and if not, an error signal is output, including the steps of:

and judging whether the output R value, the output G value and the output B value in a group of output gray values in the lookup table stored in the lookup table storage module are completely equal or not through the comparison unit, if not, outputting an error signal, and caching the input gray value corresponding to the error signal into the cache unit.

Drawings

FIG. 1 is a schematic diagram of a gamma calibration process;

fig. 2 is a schematic diagram of a connection structure of an image processing apparatus according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a connection structure of another image processing apparatus according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a connection structure of a judging module in an image processing apparatus according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a connection structure of a judging module in another image processing apparatus according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a connection structure of a judging module in another image processing apparatus according to an embodiment of the present disclosure;

FIG. 7 is a timing diagram of a corresponding node in the structure shown in FIG. 6;

fig. 8 is a flowchart of an image processing method according to an embodiment of the disclosure.

Detailed Description

Before describing embodiments of the present disclosure, it should be noted that:

some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.

The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.

It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

An object of the present disclosure is to provide an image processing apparatus, system, component, device and method, the apparatus including a look-up table storage module configured to store a look-up table required for image gamma calibration or degamma calibration, the look-up table describing a mapping relationship between an input gray value before calibration and an output gray value after calibration; the input gray values comprise equal input R values, input G values and input B values, and the corresponding output R values, output G values and output B values form a group of output gray values; and the judging module is configured to judge whether the output R value, the output G value and the output B value in a group of output gray values in the lookup table are completely equal, and if not, the corresponding error signals are output.

In the scheme, the error lookup can be performed on the lookup table required by the image gamma calibration (gamma calibration) or the degamma calibration (degamma calibration), and a group of output gray values corresponding to the error signals in the lookup table can be checked and checked according to the error signals, so that the debugging and debugging (debug) speed and efficiency of the lookup table are accelerated to a certain extent.

One embodiment of the present disclosure provides an image processing apparatus including:

In some embodiments, as shown in fig. 2, the image processing apparatus further includes: the calibration value calculation module and the writing control module;

The judging module is specifically configured to:

In some embodiments, taking as an example that a gamma calibration function (gamma calibration function) calculates a calibrated R component (output R value) corresponding to a pre-calibrated R component (input R value) of RGB with a color depth of 10bit, let an input R value be X (X is in a range of 0 to 1023), an output R value be Y, and the gamma calibration function corresponding thereto is:

in the above-mentioned method, the step of,normalizing the 10bit 2-system value, and performing power operation on the normalized valueFinally, the processed value is converted into a 2-system value of 10 bits by multiplying 1024, wherein the parameter gamma in the above formula can be selected to be 2.2, 2.4 or 2.6 according to the requirement.

The degamma calibration function (degamma calibration function) corresponding to the gamma calibration function is:

in the above formula, X is the input gray value before degamma calibration, and X is the output gray value after degamma calibration.

If a fractional part is to be reserved, when the fractional part is required to be multiplied by 1024, the fractional part is adjusted to be a power of 2 larger, for example 4096, the calculated Y value is 12 bits in total, wherein the high 10 bits are integer parts, the low 2 bits are fractional parts, and the corresponding gamma calibration function and degamma calibration function are respectively:

In some embodiments, the write control module is specifically configured to:

It can be understood that when writing, the corresponding input gray value is used as a writing pointer, after the output gray values calculated by the calibration value calculation module are written into the lookup table in sequence according to groups, the mapping relationship between the input gray value and the output gray value is formed in the lookup table, and when reading, the corresponding output gray value can be read by using the input gray value as a reading pointer.

In some embodiments, the lookup table includes a first sub-lookup table, a second sub-lookup table, and a third sub-lookup table;

a first sub-lookup table configured to describe a mapping relationship of an input R value before calibration and an output R value after calibration;

a second sub-lookup table configured to describe a mapping relationship of the input G value before calibration and the output G value after calibration;

a third sub-lookup table configured to describe a mapping relationship of the input B value before calibration and the output B value after calibration;

The write control module is specifically configured to:

It may be understood that, in order to improve the lookup efficiency (reading efficiency) of the lookup table, R, G, B may respectively correspond to one sub-lookup table, when writing, respectively take the corresponding input R value, the corresponding input G value, and the corresponding input B value as write pointers, write the corresponding output R value, the corresponding output G value, and the corresponding output B value calculated by the calibration value calculation module into the first sub-lookup table, the second sub-lookup table, and the third sub-lookup table, and after writing, form a mapping relationship between the input R value and the output R value in the first sub-lookup table, form a mapping relationship between the input G value and the output G value in the second sub-lookup table, and form a mapping relationship between the input B value and the output B value in the third sub-lookup table. When reading, the input gray value is used as a read pointer, and the corresponding output gray value can be read out.

Correspondingly, three sub-lookup tables corresponding to R, G, B respectively need to be built for degamma calibration, and three sub-lookup tables corresponding to R, G, B respectively need to be built for gamma calibration.

In some embodiments, the write pointer may be equal to the Entry identification (Entry ID) of the corresponding sub-lookup table, i.e., the output gray value may be written into the Entry (Entry) corresponding to the Entry ID corresponding to the input gray value. For example, an output R value corresponding to an input R value of X is written into an Entry (Entry) of Entry ID X in the first sub-lookup table, an output G value corresponding to an input G value of X is written into an Entry (Entry) of Entry ID X in the second sub-lookup table, and an output B value corresponding to an input B value of X is written into an Entry (Entry) of Entry ID X in the third sub-lookup table.

In some embodiments, the output R value, the output G value, and the output B value in the set of output gray values may be written into the first sub-lookup table, the second sub-lookup table, and the third sub-lookup table at the same time, or may be written into the first sub-lookup table, the second sub-lookup table, and the third sub-lookup table in a certain writing order, for example, in a set of output gray values, the output R value may be written into the first sub-lookup table, the output G value may be written into the second sub-lookup table, and the output B value may be written into the first sub-lookup table, the second sub-lookup table, and the third sub-lookup table in the order in which the output R value is written into the third sub-lookup table.

In some embodiments, the look-up table storage module is a register, i.e., the look-up table may be stored in a register.

In some embodiments, the lookup table storage module includes a fifth register, a sixth register, and a seventh register configured to store the first sub-lookup table, the second sub-lookup table, and the third sub-lookup table, respectively.

It will be appreciated that in order to further avoid errors in writing of the first, second and third sub-lookup tables, and also to further improve the lookup efficiency (reading efficiency) of the lookup tables, the first, second and third sub-lookup tables may be stored in different registers.

In some embodiments, further comprising:

It will be appreciated that when the image processing process corresponds to gamma calibration (gamma calibration), the lookup table used is the lookup table corresponding to the gamma calibration function (gamma calibration function), and when the image processing process corresponds to degamma calibration (degamma calibration), the lookup table used is the lookup table corresponding to the degamma calibration function (degamma calibration function).

In some embodiments, in order to implement debug (debug) of the lookup table during writing, the speed and efficiency of debug (debug) of the lookup table may be further increased, as shown in fig. 3, where the image processing apparatus further includes: a third register;

the judging module is specifically configured to:

It can be understood that when each set of output gray values is written into the lookup table, the set of output gray values is temporarily stored in the third register at the same time, so that the judging module judges whether the output R value, the output G value and the output B value in the set of output gray values are completely equal, and if not, a corresponding error signal is output to remind the engineer that the set of output gray values in the lookup table have errors.

In some embodiments, in order to facilitate the determination module to quickly distinguish between the output R value, the output G value, and the output B value in the third register, quickly perform a numerical comparison, further speed and efficiency of debugging and debug of the lookup table, the third register includes a first sub-register, a second sub-register, and a third sub-register;

the write control module is specifically configured to:

the mapping relation between the output gray values calculated by the calibration value calculation module and the corresponding input gray values is sequentially written into the lookup table according to groups, and when one group of output gray values are written into the lookup table, the output R value, the output G value and the output B value in the group of output gray values are respectively written into the first sub-register, the second sub-register and the third sub-register; when the output R value, the output G value and the output B value in the group of output gray values are respectively written into the first sub-register, the second sub-register and the third sub-register, original data in the first sub-register, the second sub-register and the third sub-register are respectively covered.

That is, the output R value in the set of output gray values is written into the first sub-register when the output R value is written into the lookup table, the output G value in the set of output gray values is written into the second sub-register when the output G value is written into the lookup table, and the output B value in the set of output gray values is written into the third sub-register when the output B value is written into the lookup table, so that the judging module can quickly distinguish the output R value, the output G value and the output B value in the third register, and quickly perform the numerical comparison.

Correspondingly, the judging module is specifically configured to:

That is, the judging module reads the output R value, the output G value, and the output B value from the first sub-register, the second sub-register, and the third sub-register respectively to judge each time the output R value, the output G value, and the output B value in the group of output gray values currently cached in the third register are completely equal.

In some embodiments, in order to facilitate the determination module to determine that the determination result is an input gray value corresponding to the output gray value that is not completely equal, so as to instruct an engineer to quickly find an error entry in the lookup table, the image processing apparatus further increases the speed and efficiency of debugging and debug of the lookup table, and further includes: a fourth register;

The judging module is specifically configured to:

It can be understood that when the judging module judges a group of output gray values, the input gray values corresponding to the group of output gray values are recorded in the fourth register, so that when the judging result of the group of output gray values is not completely equal, an error signal corresponding to the input gray value currently cached in the fourth register can be output.

In combination with the embodiment that the write-in control module uses the corresponding input gray value as the write pointer, the output gray values calculated by the calibration value calculation module are sequentially written into the lookup table according to groups, when the judgment module outputs an error signal, an entry (entry) of the write-in error in the lookup table can be found according to the input gray value currently cached in the fourth register, so that the speed and efficiency of debugging and debugging (debug) of the lookup table are further improved.

In some embodiments, to further ensure that the determination module determines the output R value, the output G value, and the output B value in the set of output gray values, instead of determining the output R value, the output G value, and the output B value from different sets of output gray values, the fourth register includes a fourth sub-register, a fifth sub-register, and a sixth sub-register;

the judging module is specifically configured to:

It can be understood that when the input gray values buffered in the fourth sub-register, the fifth sub-register and the sixth sub-register are equal, it is indicated that the output R value, the output G value and the output B value in the set of output gray values corresponding to the input gray values have all been written into the lookup table, and at this time, the set of output gray values output by the write control module is the set of output gray values corresponding to the input gray values.

In an embodiment in which the image processing apparatus includes both a third register and a fourth register, and the third register includes a first sub-register, a second sub-register, and a third sub-register, and the fourth register includes a fourth sub-register, a fifth sub-register, and a sixth sub-register, the write control module is specifically configured to: the mapping relation between the output gray values calculated by the calibration value calculation module and the corresponding input gray values is sequentially written into a lookup table according to groups, when an output R value in a group of output gray values is written into the lookup table, the output R value and the corresponding input R value are respectively written into a first sub-register and a fourth sub-register, when an output G value in a group of output gray values is written into the lookup table, the output G value and the corresponding input G value are respectively written into a second sub-register and a fifth sub-register, and when an output B value in a group of output gray values is written into the lookup table, the output B value and the corresponding input B value are respectively written into a third sub-register and a sixth sub-register;

The judging module is specifically configured to:

when the input gray values cached in the fourth sub-register, the fifth sub-register and the sixth sub-register are equal, judging whether the output R value, the output G value and the output B value cached in the first sub-register, the second sub-register and the third sub-register are completely equal or not, and if not, outputting corresponding error signals.

It may be understood that in the scheme that the image processing apparatus includes the third register and the fourth register at the same time, when the input gray values buffered in the fourth sub-register, the fifth sub-register and the sixth sub-register are equal, it is explained that the output R value, the output G value and the output B value currently buffered in the first sub-register, the second sub-register and the third sub-register respectively belong to the same group of output gray values (i.e. correspond to the same input gray value), so the determining module determines whether the output R value, the output G value and the output B value buffered in the first sub-register, the second sub-register and the third sub-register are completely equal at this time, and it may be further realized that the determining module determines the output R value, the output G value and the output B value in a group of output gray values instead of determining the output R value, the output G value and the output B value from different groups of output gray values.

In the embodiment in which the image processing apparatus includes a fourth register, the fourth register includes a fourth sub-register, a fifth sub-register, and a sixth sub-register, and the write control module uses the corresponding input R value, input G value, and input B value as write pointers, respectively, and sequentially writes the respective sets of output R value, output G value, and output B value calculated by the calibration value calculation module into the first sub-lookup table, the second sub-lookup table, and the third sub-lookup table according to the sets, the fourth sub-register, the fifth sub-register, and the sixth sub-register may be registers for buffering current write pointers of the first sub-lookup table, the second sub-lookup table, and the third sub-lookup table, respectively.

In some embodiments, as shown in fig. 4, the determining module includes a comparing unit and a buffering unit:

It can be understood that, according to the input gray value cached in the cache unit, the corresponding position of the write pointer with the writing error in the lookup table (the entry with the error in the lookup table) can be quickly found, so as to further increase the speed and efficiency of debugging and debugging (debug) of the lookup table.

The buffer unit may be a register or a first-in first-out buffer unit, that is, the buffer unit may buffer a certain number of input gray values (input gray values with wrong output gray values).

In an embodiment in which the image processing apparatus comprises a fourth register and the determination module comprises a comparison unit and a buffering unit, the buffering unit is configured to buffer the currently buffered input gray value in the fourth register upon receipt of the error signal.

That is, when the comparison unit outputs an error signal, it is explained that the input gray-scale value buffered in the fourth register at this time is the input gray-scale value corresponding to the error signal. According to the input gray value, the position (the error entry in the lookup table) corresponding to the write pointer with the error written in the lookup table can be quickly found, so that the debugging and debugging (debug) speed and efficiency of the lookup table are further improved.

In some embodiments, as shown in fig. 4, the comparison unit includes a first equal value comparator, a second equal value comparator, and a nand gate operator;

wherein the error signal is a first judgment signal of high level.

It is understood that when the first determination signal output from the nand gate operator is at the high level, it is indicated that the output R value, the output G value, and the output B value in the set of output gray values currently input to the first equivalent comparator and the second equivalent comparator are not exactly equal (are not exactly identical), which is indicative of an error in the set of output gray values. Correspondingly, when receiving the error signal, the buffer unit buffers the input gray value corresponding to the error signal, so as to instruct the engineer to quickly find the position (the error entry in the lookup table) corresponding to the write pointer for writing the error in the lookup table, thereby further accelerating the debugging and debugging (debug) speed and efficiency of the lookup table.

In an embodiment in which the comparing unit comprises a first equivalue comparator, a second equivalue comparator and a nand gate operator, and the processing apparatus further comprises a third register, and the third register comprises a first sub-register, a second sub-register and a third sub-register, when the first equivalue comparator is configured to compare whether the output R value and the output B value in a set of output gray values in the lookup table are equal, the second equivalue comparator is configured to compare whether the output G value and the output B value in the set of output gray values are equal, two input terminals of the first equivalue comparator are respectively connected to the first sub-register and the third sub-register, and two input terminals of the second equivalue comparator are respectively connected to the second sub-register and the third sub-register; when the first equivalue comparator is configured to compare whether the output R value and the output B value in a group of output gray values in the lookup table are equal, and the second equivalue comparator is configured to compare whether the output R value and the output G value in the group of output gray values are equal, two input ends of the first equivalue comparator are respectively connected with the first sub-register and the third sub-register, and two input ends of the second equivalue comparator are respectively connected with the first sub-register and the second sub-register; when the first equivalue comparator is configured to compare whether the output R value and the output G value in a group of output gray values in the lookup table are equal, and the second equivalue comparator is configured to compare whether the output G value and the output B value in the group of output gray values are equal, two input ends of the first equivalue comparator are respectively connected with the first sub-register and the second sub-register, and two input ends of the second equivalue comparator are respectively connected with the second sub-register and the third sub-register.

Further, in the embodiment in which the comparing unit includes a first equivalent comparator, a second equivalent comparator, and a nand gate operator, the processing device further includes a third register and a fourth register, where the third register includes a first sub-register, a second sub-register, and a third sub-register, and the fourth register includes a fourth sub-register, a fifth sub-register, and a sixth sub-register, in order to implement the determining module, when input gray values buffered in the fourth sub-register, the fifth sub-register, and the sixth sub-register are equal, it is determined whether output R values, output G values, and output B values in a first group of output gray values corresponding to the input gray values output by the writing control module are completely equal and output error signals when the output R values, the output G values, and the output B values are not completely equal, and a switch is connected between an input terminal of the first equivalent comparator and the second equivalent comparator and the first sub-register, and an input trigger switch of the fifth sub-register and the sixth sub-register when input gray values buffered in the fourth sub-register, the fifth sub-register and the sixth sub-register are equal, and the first equivalent comparator and the first equivalent register are turned on.

In another embodiment, in which the comparing unit includes a first equal value comparator, a second equal value comparator, and a nand gate operator, the processing apparatus further includes a third register and a fourth register, where the third register includes a first sub-register, a second sub-register, and a third sub-register, and the fourth register includes a fourth sub-register, a fifth sub-register, and a sixth sub-register, in order to implement the determining module, when the input gray values buffered in the fourth sub-register, the fifth sub-register, and the sixth sub-register are equal, the determining module may determine whether the output R value, the output G value, and the output B value in a set of output gray values corresponding to the input gray values output by the writing control module are completely equal and output an error signal when they are not completely equal, and as shown in fig. 6, the comparing unit may further include an and gate operator configured to perform and operation on a signal output from the nand gate operator and a fourth register value determining signal, to obtain a third determining signal and output; the error signal is a third judgment signal of high level, and the fourth register value judgment signal is a judgment signal obtained by judging the input gray values buffered in the fourth sub-register, the fifth sub-register and the sixth sub-register (the high level is completely equal, and the low level is not completely equal). Correspondingly, when the and gate operator outputs the third judgment signal (i.e., the error signal) with the high level, it indicates that the input gray values buffered in the fourth sub-register, the fifth sub-register and the sixth sub-register are equal, and at the same time, a group of output gray values buffered in the first sub-register, the second sub-register and the third sub-register are not completely equal (i.e., the output gray values respectively corresponding to the input gray values buffered in the fourth sub-register, the fifth sub-register and the sixth sub-register are not completely equal), and at this time, the buffer unit is triggered to buffer the corresponding input gray values.

In some embodiments, the generation of the fourth register value determining signal may be implemented by a comparison circuit, where the comparison circuit includes two equivalent comparators and an and gate operator, the two equivalent comparators are connected to the fourth sub-register, the fifth sub-register and the sixth sub-register (refer to a manner that the two equivalent comparators in the comparison unit are connected to the first sub-register, the second sub-register and the third sub-register), and an input end of the and gate operator is connected to an output end of the two equivalent comparators, and the and gate operator is configured to perform an and operation on signals output by the two equivalent comparators in the comparison circuit to obtain the fourth register value determining signal and output the fourth register value determining signal, and specific working principles are not described herein.

In some embodiments, the cache unit includes a first register and a second register;

Wherein, at the beginning, the initial values of the first register and the second register are both low level (both set 0), i.e. the flag bit is invalid.

It can be understood that, during the writing process of the previous round (Entry 0 to Entry) of the lookup table, when an error occurs for the first time, the corresponding input gray value will be cached in the second register, but when an error occurs at the back, the flag bit of the first register is already valid, the second judgment signal will not be triggered, the corresponding input gray value will not be recorded in the second register any more, which is to avoid the data confusion caused by storing a plurality of input gray values in the cache unit, and thus unnecessary trouble is caused, and the accuracy of debugging and debugging (debug) of the lookup table is improved.

That is, in the process of writing in one round (Entry 0-Entry) of the lookup table, the first input gray value with an error is recorded through two registers, after debugging and debugging (debug) are performed on the Entry (Entry) corresponding to the corresponding input gray value, when the next round of writing in the lookup table is restarted, the first register and the second register are reset, the first input gray value with an error in the round of writing is recorded, and so on until the writing is completed in the process of writing in one round of the lookup table, and the data of the lookup table written in the previous round can be used in gamma calibration or degamma calibration.

In an embodiment in which the image processing apparatus includes a fourth register and the buffer unit includes a first register and a second register, the second register may be connected to the fourth register, and the second register is configured to buffer the input gray value currently buffered in the fourth register under the triggering of the second determination signal.

In some embodiments, the error signal is a high level signal, and as shown in fig. 5, the buffer unit includes a first register, a second register, a first multiplexer Mux1, and a second multiplexer Mux2; the initial values of the first register and the second register are low level;

the first multiplexer Mux1, the first input end (input end 0) of which is connected with the output end of the comparing unit, the second input end (input end 1) and the control end of which are both connected with the output end of the first register, the output end of which is connected with the input end of the first register, is configured to output the information acquired by the first input end (input end 0) of the first multiplexer Mux1 to the first register when the output end of the first register is at a low level, and output the information acquired by the second input end (input end 1) of the first multiplexer Mux1 to the first register when the output end of the first register is at a high level;

A second multiplexer Mux2, a first input end (input end 0) of which obtains an input gray value corresponding to a group of output gray values currently being compared by the comparison unit, a second input end (input end 1) of which is connected with the output end of the second register, a control end of which is connected with the output end of the first register, and an output end of which is connected with the input end of the second register, and is configured to output the information obtained by the first input end (input end 0) to the second register when the output end of the first register is at a low level, and output the information obtained by the second input end (input end 1) to the second register when the output end of the first register is at a high level

It can be understood that, in the initial state, the initial values of the first register and the second register are both low, the first input terminal (input terminal 0) of the first multiplexer Mux1 is conducted with the output terminal thereof, and the first input terminal (input terminal 0) of the second multiplexer Mux2 is conducted with the output terminal thereof;

when the signal output by the comparing unit is at low level (non-error signal), the first input end (input end 0) of the first multiplexer Mux1 is conducted with the output end thereof, the first register maintains low level, the first input end (input end 0) of the second multiplexer Mux2 is conducted with the output end thereof, and the value in the second register is refreshed according to the update of the information (the input gray value corresponding to the group of output gray values currently being compared by the comparing unit) acquired by the first input end (input end 0) thereof;

When the signal output by the comparing unit is changed from low level to high level (i.e. error signal), the first input end (input end 0) of the first multiplexer Mux1 is still conducted with the output end of the first multiplexer Mux1 due to the fact that the first register is still low level in the current clock period Tn, the high level signal output by the comparing unit is written into the first register, after the first register is set to high level, the first multiplexer Mux1 is switched to the second input end (input end 1) to be conducted with the output end of the first multiplexer Mux1, and after the first register is maintained to be high level (after the next clock periods tn+1 and tn+1), the states of the first multiplexer Mux1 and the first register are not changed even if the error signal is received again before the first register is reset; and since the first register of the current clock cycle Tn is still low, the first input terminal (input terminal 0) of the second multiplexer Mux2 of the current clock cycle Tn is conducted with its output terminal, the input gray value corresponding to the error signal is already written into the second register through the first input terminal (input terminal 0) of the second multiplexer Mux2 before the current clock cycle Tn (even before Tn), after the next clock cycles tn+1 and tn+1, the first register is high so that the second input terminal (input terminal 1) of the second multiplexer Mux2 is conducted with its output terminal, and the value written in the clock cycle Tn is maintained in the second register, that is, the input gray value corresponding to the error signal is locked in the second register.

That is, this scheme can also be implemented in such a way that, during the writing process of the previous round (Entry 0 to Entry) of the lookup table, when an error occurs for the first time, the corresponding input gray value is cached in the second register, but when an error occurs later, the corresponding input gray value is not recorded in the second register.

In the embodiment in which the image processing apparatus includes the fourth register and the buffer unit includes the buffer unit including the first register, the second register, the first multiplexer Mux1 and the second multiplexer Mux2, the first input terminal (input terminal 0) of the second multiplexer Mux2 is connected to the fourth register (as shown in fig. 6) to obtain the input gray value currently buffered in the fourth register (i.e., the input gray value corresponding to the set of output gray values currently being compared by the comparing unit).

Fig. 7 shows a timing diagram of corresponding nodes in the structure, where CLK is the timing of the clock cycle of the whole image processing apparatus, r_pointer, g_pointer, b_pointer are the timings of the write pointers of the first sub-lookup table, the second sub-lookup table, and the third sub-lookup table, r_reg, g_reg, b_reg are the timings of the first sub-register, the second sub-register, and the third sub-register, thread_point_e is the timing of the fourth register value determination signal, a is the timing of the output terminal of the and gate operator in the comparison unit, and Q1 and Q2 are the timings of the output terminals of the first register and the second register, respectively. In the embodiment corresponding to fig. 7, a set of output gray values is written according to the sequence of writing the output R value into the first sub-lookup table, writing the output G value into the second sub-lookup table, and writing the output B value into the third sub-lookup table, so that the timing of g_pointer is one clock cycle later than r_pointer and the timing of b_pointer is one clock cycle later than g_pointer; the timing of G_reg is one clock cycle later than R_reg, and the timing of B_reg is one clock cycle later than G_reg.

As can be seen from fig. 7, when the output Q1 of the lookup table write error (e.g., the output B value corresponding to the write pointer2 is in error, and the output b_data2_error) register goes high, the input gray value corresponding to the error signal (the input gray value corresponding to the write pointer 2) is already written into the second register in advance, and then the second register latches the input gray value corresponding to the write pointer 2.

In some embodiments, the image processing apparatus may be a Graphics Processor (GPU).

Based on the same inventive concept, the embodiments of the present disclosure also provide a graphics processing system including the image processing apparatus of any one of the above embodiments;

the graphics processing System may be a die, a SOC (System on Chip) with multiple die interconnects, or other organization.

Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic component including the graphics processing system of any of the above embodiments.

In some use scenarios, the product form of the electronic assembly is embodied as a graphics card; in other use cases, the product form of the electronic assembly is embodied as a CPU motherboard.

Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic device including the above-described electronic component. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.

Based on the same inventive concept, the embodiments of the present disclosure further provide an image processing method, as shown in fig. 8, including:

step S110: judging whether the output R value, the output G value and the output B value in a group of output gray values in the lookup table stored in the lookup table storage module are completely equal, and if not, outputting an error signal;

the lookup table is a lookup table required by image gamma calibration or degamma calibration, and is used for describing the mapping relation between an input gray value before calibration and an output gray value after calibration; the input gray values comprise equal input R value, input G value and input B value, and the corresponding output R value, output G value and output B value form a group of output gray values

The device for implementing the method is the image processing device of any of the embodiments, and the specific implementation of the device may refer to the implementation of the image processing device, which is not described herein.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. An image processing apparatus comprising: the device comprises a lookup table storage module, a judging module, a calibration value calculating module and a writing control module;

the lookup table storage module is configured to store a lookup table required by image gamma calibration or degamma calibration; the lookup table comprises a first sub-lookup table, a second sub-lookup table and a third sub-lookup table; the first sub-lookup table is configured to describe the mapping relation between the input R value before calibration and the output R value after calibration; the second sub-lookup table is configured to describe the mapping relation between the input G value before calibration and the output G value after calibration; the third sub-lookup table is configured to describe the mapping relation between the input B value before calibration and the output B value after calibration; the input gray values comprise equal input R values, input G values and input B values, and the corresponding output R values, output G values and output B values form a group of output gray values;

the writing control module is configured to sequentially write the output gray values calculated by the calibration value calculation module into the lookup table according to groups by taking the corresponding input gray values as writing pointers, and output a group of output gray values to the judging module when the group of output gray values are written into the lookup table; wherein the write pointer is equal to an entry identification of the corresponding sub-lookup table;

The judging module is configured to judge whether the output R value, the output G value and the output B value in the group of output gray values are completely equal when receiving the group of output gray values output by the writing control module, and if not, the corresponding error signals are output.

2. The image processing apparatus according to claim 1, the judgment module comprising a comparison unit and a buffer unit:

the buffer unit is configured to buffer the input gray value corresponding to the error signal when the error signal is received.

3. The image processing apparatus according to claim 2, the comparing unit comprising a first equivalent comparator, a second equivalent comparator, and a nand gate operator;

the first equivalue comparator is configured to compare whether an output R value and an output B value in a group of output gray values in the lookup table are equal, and the second equivalue comparator is configured to compare whether an output G value and an output B value in the group of output gray values are equal; or, the first equal value comparator is configured to compare whether an output R value and an output B value in a set of output gray values in the lookup table are equal, and the second equal value comparator is configured to compare whether an output R value and an output G value in the set of output gray values are equal; or, the first equal value comparator is configured to compare whether an output R value and an output G value in a set of output gray values in the lookup table are equal, and the second equal value comparator is configured to compare whether an output G value and an output B value in the set of output gray values are equal;

the NAND gate operator is configured to perform NAND operation on signals output by the first equivalent comparator and the second equivalent comparator to obtain a first judgment signal and output the first judgment signal;

wherein the error signal is the first judgment signal of high level.

4. The image processing apparatus according to claim 2, the buffer unit comprising a first register and a second register;

the first register is configured to, when the error signal is received and the flag bit of the first register is invalid, set the flag bit of the first register to be valid and output a second judgment signal;

the second register is configured to buffer the input gray value corresponding to the second judgment signal under the triggering of the second judgment signal.

5. The image processing apparatus according to claim 2, the error signal being a high level signal, the buffer unit including a first register, a second register, a first multiplexer, and a second multiplexer; the initial values of the first register and the second register are low level;

The first multiplexer is configured to output information acquired by the first input end of the first multiplexer to the first register when the output end of the first register is at a low level, and output information acquired by the second input end of the first multiplexer to the first register when the output end of the first register is at a high level;

the first input end of the second multiplexer acquires an input gray value corresponding to a group of output gray values which are currently being compared by the comparison unit, the second input end of the second multiplexer is connected with the output end of the second register, the control end of the second multiplexer is connected with the output end of the first register, the output end of the second multiplexer is connected with the input end of the second register, the second multiplexer is configured to output information acquired by the first input end of the second multiplexer to the second register when the output end of the first register is in a low level, and output information acquired by the second input end of the second multiplexer to the second register when the output end of the first register is in a high level;

6. The image processing apparatus according to claim 1, further comprising: a third register;

the judging module is specifically configured to:

7. The image processing apparatus according to claim 6, the third register comprising a first sub-register, a second sub-register, and a third sub-register;

the write control module is specifically configured to:

the mapping relation between the output gray values calculated by the calibration value calculation module and the corresponding input gray values is sequentially written into the lookup table according to groups, and when one group of output gray values are written into the lookup table, the output R value, the output G value and the output B value in the group of output gray values are respectively written into the first sub-register, the second sub-register and the third sub-register; when the output R value, the output G value and the output B value in a group of output gray values are respectively written into the first sub-register, the second sub-register and the third sub-register, original data in the first sub-register, the second sub-register and the third sub-register are respectively covered;

The judging module is specifically configured to:

8. The image processing apparatus according to claim 1, further comprising: a fourth register;

the judging module is specifically configured to:

9. The image processing apparatus according to claim 8, the fourth register comprising a fourth sub-register, a fifth sub-register, and a sixth sub-register;

the write control module is specifically configured to: the mapping relation between the output gray values calculated by the calibration value calculation module and the corresponding input gray values is sequentially written into the lookup table according to groups, when one group of output gray values is written into the lookup table, the group of output gray values is output to the judgment module, when the output R value in the group of output gray values is written into the lookup table, the corresponding input R value is written into the fourth sub-register, when the output G value in the group of output gray values is written into the lookup table, the corresponding input G value is written into the fifth sub-register, and when the output B value in the group of output gray values is written into the lookup table, the corresponding input B value is written into the sixth sub-register; when an input R value is written into the fourth sub-register, the original data in the fourth sub-register is covered, when an input G value is written into the fifth sub-register, the original data in the fifth sub-register is covered, and when an input B value is written into the sixth sub-register, the original data in the sixth sub-register is covered;

The judging module is specifically configured to:

10. The image processing apparatus according to claim 1, the write control module being specifically configured to:

respectively taking corresponding input R value, input G value and input B value as write pointers, and sequentially writing each group of output R value, output G value and output B value obtained by calculation of the calibration value calculation module into the first sub-lookup table, the second sub-lookup table and the third sub-lookup table according to groups;

and when one group of output gray values is written into the lookup table, outputting the group of output gray values to the judging module.

11. The image processing apparatus of claim 1, the lookup table storage module comprising a fifth register, a sixth register, and a seventh register configured to store the first sub-lookup table, the second sub-lookup table, and the third sub-lookup table, respectively.

12. The image processing apparatus according to claim 1, further comprising:

and the image processing module is configured to map gray values in the image data input into the image processing module into corresponding gamma calibrated or degamma calibrated output gray values by utilizing the lookup table and output the corresponding gamma calibrated or degamma calibrated output gray values.

13. A graphics processing system comprising the image processing apparatus of any one of claims 1 to 12.

14. An electronic assembly comprising the graphics processing system of claim 13.

15. An electronic device comprising the electronic assembly of claim 14.