CN116759311B - Manufacturing method of semiconductor avalanche high-voltage diode - Google Patents
Manufacturing method of semiconductor avalanche high-voltage diode Download PDFInfo
- Publication number
- CN116759311B CN116759311B CN202311028168.9A CN202311028168A CN116759311B CN 116759311 B CN116759311 B CN 116759311B CN 202311028168 A CN202311028168 A CN 202311028168A CN 116759311 B CN116759311 B CN 116759311B
- Authority
- CN
- China
- Prior art keywords
- manufacturing
- semiconductor
- flow
- voltage diode
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 391
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 52
- 238000004088 simulation Methods 0.000 claims abstract description 49
- 230000008569 process Effects 0.000 claims abstract description 26
- 238000013507 mapping Methods 0.000 claims abstract description 15
- 239000013598 vector Substances 0.000 claims description 22
- 239000011159 matrix material Substances 0.000 claims description 21
- 238000011112 process operation Methods 0.000 claims description 17
- 238000004458 analytical method Methods 0.000 claims description 12
- 230000007704 transition Effects 0.000 claims description 12
- 239000000969 carrier Substances 0.000 claims description 11
- 238000012544 monitoring process Methods 0.000 claims description 10
- 238000000429 assembly Methods 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 5
- 238000003491 array Methods 0.000 claims description 4
- 238000009826 distribution Methods 0.000 claims description 4
- 230000010355 oscillation Effects 0.000 claims description 4
- 238000007405 data analysis Methods 0.000 claims description 3
- 238000012216 screening Methods 0.000 claims description 3
- 101100134058 Caenorhabditis elegans nth-1 gene Proteins 0.000 claims description 2
- 238000007711 solidification Methods 0.000 abstract description 3
- 230000008023 solidification Effects 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 description 9
- 238000000137 annealing Methods 0.000 description 6
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 5
- 238000012937 correction Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 241000695274 Processa Species 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66113—Avalanche diodes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67276—Production flow monitoring, e.g. for increasing throughput
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Computational Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Data Mining & Analysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Manufacturing & Machinery (AREA)
- Computing Systems (AREA)
- Algebra (AREA)
- Ceramic Engineering (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, which comprises the following steps: step 1: acquiring an initial manufacturing flow of the avalanche high-voltage diode, and acquiring a step manufacturing standard and a standard allowable error range of each manufacturing step in the initial manufacturing flow; step 2: obtaining the manufacturing requirement of the avalanche high-voltage diode, carrying out manufacturing mapping on the manufacturing requirement and each manufacturing step, and determining step adjustment information by combining step manufacturing standards and standard allowable error ranges; step 3: optimizing the initial manufacturing flow according to the step adjustment information to obtain the current manufacturing flow, and simulating the semiconductor to be prepared; step 4: and when the simulation result is qualified, performing semiconductor manufacturing according to a final manufacturing flow. The solidification of the process is avoided, the reliability of subsequent actual manufacture is further ensured through simulation, and the satisfaction degree of the requirement is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor avalanche high-voltage diode.
Background
An avalanche diode is a diode designed to undergo avalanche breakdown at a specific reverse bias voltage, the junction of the diode primarily serving to prevent current concentration, making the diode safe in breakdown. Avalanche diodes are used for semiconductor devices operating in the reverse breakdown region, these diodes acting as safety valves for controlling the system pressure to protect the electrical system from excess voltages, which are of the same sign as zener diodes.
The avalanche high-voltage diode is a semiconductor photoelectric device with internal gain, has higher sensitivity and response speed than other photovoltaic devices, and has good prospect in the fields of communication, radar and the like.
Because the diode uses corresponding to different manufacturing demands are different, but the planned diode is common at present, the required diode is obtained for application by matching the performance of the diode with the demands, and the process parameters are too solidified, so that the manufacturing demands cannot be well attached, and the demand satisfaction degree is reduced.
Accordingly, the present invention provides a method of manufacturing the subject avalanche high voltage diode.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, which is used for optimizing a flow by determining the standard and the range of manufacturing steps and determining adjustment information through a demand manufacturing map, avoiding the solidification of the flow, further ensuring the reliability of subsequent actual manufacturing through simulation and improving the satisfaction degree of demands.
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, which comprises the following steps:
step 1: acquiring an initial manufacturing flow of the avalanche high-voltage diode, and acquiring a step manufacturing standard and a standard allowable error range of each manufacturing step in the initial manufacturing flow;
step 2: obtaining the manufacturing requirement of the avalanche high-voltage diode, carrying out manufacturing mapping on the manufacturing requirement and each manufacturing step, and determining step adjustment information by combining step manufacturing standards and standard allowable error ranges;
step 3: optimizing the initial manufacturing flow according to the step adjustment information to obtain a current manufacturing flow, and simulating a semiconductor to be prepared;
step 4: and when the simulation result is qualified, performing semiconductor manufacturing according to a final manufacturing flow.
Preferably, the initial manufacturing process for obtaining the avalanche high voltage diode comprises the following steps:
acquiring an original scheme consistent with each manufacturing type from a type-scheme database based on all manufacturing types of the avalanche high-voltage diode;
step intersection processing is carried out on the original scheme to obtain an intersection step;
and obtaining an initial manufacturing flow based on the intersection step and the step sequence of the intersection step.
Preferably, the step manufacturing criteria for each manufacturing step in the initial manufacturing flow is obtained, including:
sequentially carrying out step analysis on the manufacturing type of each manufacturing step to obtain a plurality of basic manufacturing parameters of the same manufacturing step based on each manufacturing type, and constructing a step matrix X1 of the same manufacturing step;
；
wherein,an element value representing an n1 st base manufacturing parameter under an n2 nd manufacturing type, n2 representing a total number of manufacturing types; n1 represents the total number of basic manufacturing parameters corresponding to the same manufacturing step; />Element values representing the 1 st base manufacturing parameter for the 1 st manufacturing type; />An element value representing an nth 1 base manufacturing parameter for a 1 st manufacturing type; />Element values representing the 1 st base manufacturing parameter for the n2 nd manufacturing type;
according to the manufacturing type, locking the salient elements and the non-salient elements of each row of vectors in the step matrix, and determining the salient frequency of the parameters in each column of vectors in the step matrix according to the distribution of the salient elements and the non-salient elements based on the step matrix;
determining a parameter importance value of each basic manufacturing parameter according to the acquired result and the highlighting result;
；
wherein,representing the element weight of the i1 st salient element in the corresponding column vector based on the corresponding manufacturing type; u01 represents the total number of salient elements existing in the corresponding column vector, namely, the salient frequency; u02 represents the total number of non-salient elements present in the corresponding column vector; max represents the maximum value symbol; z1 represents a parameter importance value of the basic manufacturing parameter to which the corresponding column vector matches, and u01+u02=n2;
and according to the parameter importance value, importance adjustment is carried out on basic manufacturing parameters of corresponding manufacturing step types, and step manufacturing standards are constructed and obtained.
Preferably, the method further comprises: building standard allowable error ranges, including:
locking a matching element closest to a parameter importance value of the basic manufacturing parameter in a corresponding column vector of each basic manufacturing parameter from the step matrix, and screening a first element in adjacent relation with the matching element and a second element in upper adjacent relation with the matching element;
calculating a current reasonable value of the matching element according to the first element, the second element and the corresponding matching element;
；
wherein H0 represents the current reasonable value of the matching element;a value representing a match to said matching element +.>A value of a second element having an upper adjacency; />A value representing a match to said matching element +.>The value of the first element of the adjacency in presence, wherein +.>；
Determining an adjustment coefficient T0 according to the following formula;
；
wherein,representing a preset reasonable value; />Representing the adjustment quantity of the preset reasonable value; />Representing the adjustment variable coefficient;
according to the adjustment coefficient, determining a standard allowable error range of the corresponding matching element:
；
wherein,representing a first error factor; />Representing a second error factor;
if it isThe corresponding standard allowable error range is；
Otherwise, the corresponding standard allowable error range is。
Preferably, obtaining a manufacturing requirement for the avalanche high voltage diode, and performing manufacturing mapping on the manufacturing requirement and each manufacturing step includes:
extracting a manufacturing description in the manufacturing requirements of the avalanche high voltage diode;
and matching the manufacturing description with the description-step list to obtain a matching step of each manufacturing description, and performing manufacturing mapping.
Preferably, determining the step adjustment information in combination with the step manufacturing criteria and the standard tolerance ranges includes:
according to the manufacturing mapping result, the matching steps are in one-to-one correspondence with the manufacturing steps, and whether redundant steps exist is determined;
the redundant steps and the step manufacturing standard and standard allowable error range of each manufacturing step are used as step adjustment information.
Preferably, the initial manufacturing process is optimized according to the step adjustment information, so as to obtain a current manufacturing process, which comprises the following steps:
obtaining redundant steps in the step adjustment information, and inserting the redundant steps into corresponding positions in the initial manufacturing flow;
and simultaneously, standardizing the step manufacturing standard and the corresponding manufacturing step in the step adjustment information, and setting allowable variation parameters to the corresponding manufacturing step according to the standard allowable error range to obtain the current manufacturing flow.
Preferably, the simulation of the semiconductor to be prepared comprises:
determining the initial simulation time of each sub-process in the current manufacturing process, and constructing the shortest simulation line and the longest simulation line;
determining a manufacturing process set of each sub-process, monitoring based on a monitoring tool which is pre-bound with the corresponding manufacturing process, and determining process operation time lengths of different manufacturing processes in the corresponding sub-process, an operation position set of each operation time point under the same manufacturing process and operation parameters based on a monitoring result to obtain process operation characteristics of the corresponding manufacturing process under different operation time points;
determining a first manufacturing time period of the corresponding sub-assembly based on a process operation duration of each manufacturing process in the same sub-flow;
comparing each first manufacturing time period with the shortest simulation line and the corresponding simulation period in the longest simulation line in sequence according to the manufacturing sequence of all the subassemblies;
if it isReserving the corresponding sub-assembly;
otherwise, comparing each process operation characteristic of each manufacturing process in the corresponding sub-assembly with the standard operation characteristic respectively to determine a corresponding difference factor;
；
wherein Zc represents a difference factor of the c-th manufacturing process in the corresponding subassembly, and the value range of c is [1, m1]The method comprises the steps of carrying out a first treatment on the surface of the n represents an operation time point corresponding to a manufacturing process;representing process operating characteristics of the c-th manufacturing process based on the n-th operating time point; />Representing standard operating characteristics of the c-th manufacturing process based on the n-th operating time point; />Represents the process operation characteristic of the c-th manufacturing process based on the j 1-th operation time point, and the value range of j1 is [1, n ]]；/>Representation ofThe c-th manufacturing process is based on standard operating characteristics at the j-1-th operating time point;
taking all the difference factors related in the same sub-assembly as manufacturing differences, and correcting and reserving the corresponding sub-assemblies;
based on the simulation sequence of the sub-processes, sequentially constructing the reserved sub-assemblies to obtain a simulated semiconductor;
injecting preset carriers with different concentrations into the analog semiconductor by utilizing avalanche breakdown, recording the transit time of the different preset carriers based on the analog semiconductor, and constructing a transit array set;
carrying out data analysis on the transit array, and judging whether the oscillation condition of the analog semiconductor meets the following constraint condition or not;
；
wherein,representing the concentration of preset carriers in the corresponding transit array; />The expression is based on concentration +.>Standard transit times of (2); />The expression is based on concentration +.>Is set, the actual transit time of (a); />The expression is based on concentration +.>Is a first error value of (a); />The expression is based on concentration +.>A second error value of (2);
if the number of the transition array sets meeting the constraint condition exceedsAnd judging that the analog semiconductor is qualified, wherein M represents the number of transition arrays in the transition array set.
Preferably, when the simulation result is qualified, the semiconductor manufacturing is performed according to a final manufacturing flow, including:
obtaining a final manufacturing flow with qualified simulation results;
and sequentially manufacturing according to the flow sequence of the final manufacturing flow to obtain the required semiconductor.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a flow chart of a method for manufacturing a semiconductor avalanche high voltage diode in accordance with an embodiment of the present invention;
FIG. 2 is a comparative diagram of simulated lines in an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
The invention provides a method for manufacturing a semiconductor avalanche high-voltage diode, which is shown in fig. 1 and comprises the following steps:
step 1: acquiring an initial manufacturing flow of the avalanche high-voltage diode, and acquiring a step manufacturing standard and a standard allowable error range of each manufacturing step in the initial manufacturing flow;
step 2: obtaining the manufacturing requirement of the avalanche high-voltage diode, carrying out manufacturing mapping on the manufacturing requirement and each manufacturing step, and determining step adjustment information by combining step manufacturing standards and standard allowable error ranges;
step 3: optimizing the initial manufacturing flow according to the step adjustment information to obtain a current manufacturing flow, and simulating a semiconductor to be prepared;
step 4: and when the simulation result is qualified, performing semiconductor manufacturing according to a final manufacturing flow.
In this embodiment, the avalanche high voltage diode is: the manufacturing flow of type 1 is: flow 1, flow 2, flow 3, flow 4, flow 5, type 2 manufacturing flow is: flow 1, flow 2, flow 3, flow 4, type 3 manufacturing flow is: in the process 1, the process 2, the process 3, and the process 5, the process 1, the process 2, and the process 3 are taken as initial manufacturing processes, and corresponding manufacturing standards and standard errors exist in the process 1, the process 2, and the process 3, for example, the process 2 is photolithography, and in the photolithography process, corresponding standard parameters include: the photolithographic thickness is 1.5um, the baking temperature is 100 ℃, the baking time is 90 seconds, the error range for the thickness is [ -0.12um,0.10um ], the error range for the temperature is [ -2 ℃,0 ℃ and the error range for the time is [ -5 seconds, 3 seconds ].
In this embodiment, the manufacturing requirement refers to the manufacturing intention required by the user, for example, an avalanche high voltage diode with good vibration effect and high vibration frequency is required, and at this time, the manufacturing steps need to be mapped, for example, a new flow is supplemented between the flows 1 and 2, and an error range to be present in the flow 2 is added.
In this embodiment, the manufacturing map includes 01, 02 and 03 intents as needed, and the intent 01 corresponds to the flow 1, and the intents 02 and 03 correspond to the flows 2,3 and 12, and the manufacturing map is: intent 01- -flow 1, intent 02, 03- -flows 2,3, 12, at which time flow 12 is a newly added step, located between flow 1 and flow 2, and the step adjustment information is: new step + step manufacturing standard + standard tolerance.
In this embodiment, after the initial manufacturing flow is optimized: flow 1, flow 12, flow 2, and flow 3 are the current manufacturing flow.
In this embodiment, the simulation of the semiconductor is performed on the matlab simulation platform based on different processes to ensure the reliability of the subsequent actual production.
In this embodiment, some parameters may be adjusted in the current manufacturing process during the simulation, so that after the simulation is qualified, the process corresponding to the simulation is regarded as the final manufacturing process to perform the semiconductor manufacturing.
The beneficial effects of the technical scheme are as follows: the standard and the range of the manufacturing steps are determined, the adjustment information is determined through the demand manufacturing mapping, the optimization of the process is realized, the solidification of the process is avoided, the reliability of the subsequent actual manufacturing is further ensured through simulation, and the satisfaction degree of the demand is improved.
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, which obtains an initial manufacturing flow of the avalanche high-voltage diode and comprises the following steps:
acquiring an original scheme consistent with each manufacturing type from a type-scheme database based on all manufacturing types of the avalanche high-voltage diode;
step intersection processing is carried out on the original scheme to obtain an intersection step;
and obtaining an initial manufacturing flow based on the intersection step and the step sequence of the intersection step.
In this embodiment, the type-scheme database includes different types of avalanche high voltage diodes and manufacturing processes for the diodes, such as: primary lithography-ICP etching-deposition passivation-secondary lithography-etching-tertiary lithography-sputtering-lift-off-annealing.
In this embodiment, the original schema is directly matched from the database according to the type.
In this embodiment, the intersection processing is the intersection of steps, and the manufacturing flow of type 1 is: flow 1, flow 2, flow 3, flow 4, flow 5, type 2 manufacturing flow is: flow 1, flow 2, flow 3, flow 4, type 3 manufacturing flow is: in the process 1, the process 2, the process 3, and the process 5, the process 1, the process 2, and the process 3 are used as initial manufacturing processes.
The beneficial effects of the technical scheme are as follows: the initial manufacturing flow is obtained effectively through acquiring schemes of different manufacturing types from the database and through intersection processing and flow sequencing, and a foundation is provided for meeting the requirements.
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, which acquires the step manufacturing standard of each manufacturing step in the initial manufacturing flow, and comprises the following steps:
sequentially carrying out step analysis on the manufacturing type of each manufacturing step to obtain a plurality of basic manufacturing parameters of the same manufacturing step based on each manufacturing type, and constructing a step matrix X1 of the same manufacturing step;
；
wherein,an element value representing an n1 st base manufacturing parameter under an n2 nd manufacturing type, n2 representing a total number of manufacturing types; n1 represents the total number of basic manufacturing parameters corresponding to the same manufacturing step; />Element values representing the 1 st base manufacturing parameter for the 1 st manufacturing type; />Representing the n1 st basic manufacturing parameter for the 1 st manufacturing typeElement values; />Element values representing the 1 st base manufacturing parameter for the n2 nd manufacturing type;
according to the manufacturing type, locking the salient elements and the non-salient elements of each row of vectors in the step matrix, and determining the salient frequency of the parameters in each column of vectors in the step matrix according to the distribution of the salient elements and the non-salient elements based on the step matrix;
determining a parameter importance value of each basic manufacturing parameter according to the acquired result and the highlighting result;
；
wherein,representing the element weight of the i1 st salient element in the corresponding column vector based on the corresponding manufacturing type; u01 represents the total number of salient elements existing in the corresponding column vector, namely, the salient frequency; u02 represents the total number of non-salient elements present in the corresponding column vector; max represents the maximum value symbol; z1 represents a parameter importance value of the basic manufacturing parameter to which the corresponding column vector matches, and u01+u02=n2;
and according to the parameter importance value, importance adjustment is carried out on basic manufacturing parameters of corresponding manufacturing step types, and step manufacturing standards are constructed and obtained.
In this embodiment, the step analysis is performed based on retrieving the analysis model from the analysis database related to the manufacturing type, and the analysis database includes analysis models under different manufacturing types, and the analysis model is based on different manufacturing steps and analysis results of each manufacturing step by an expert, so that efficient analysis of the corresponding manufacturing steps can be achieved, that is, a same manufacturing step may correspond to a plurality of manufacturing types, and because the analysis models are applied in different manufacturing flows, a matrix for the same manufacturing step is constructed.
In this embodiment, the same row in the step matrix indicates n1 basic manufacturing parameters under the same manufacturing type, and the same column indicates n2 manufacturing types corresponding to the same basic manufacturing parameters.
In this embodiment, the salient elements are the corresponding elements with weights greater than or equal to the preset weights under the corresponding manufacturing class type, and otherwise are the non-salient elements, such as under manufacturing class 1The weight of (2) is 0.3, the preset weight is 0.1, at this time,namely, the salient element.
In this embodiment, the distribution is that of the salient elements and the non-salient elements based on the matrix, and refers to the situation of position arrangement in the matrix.
In this embodiment, the weights of the parameters related to the same manufacturing steps are different under different manufacturing types, but for planning the standard, a distinction between salient and non-salient is made, so that the parameter importance value of each basic manufacturing parameter is conveniently determined, and the parameter importance is conveniently readjusted.
In this embodiment, for example, in the manufacturing step 1, there are parameters 1, 2 and 3, and the importance of parameter 1 > the importance of parameter 2 > the importance of parameter 3, at this time, the standard of the manufacturing step can be obtained.
The beneficial effects of the technical scheme are as follows: step matrixes are constructed by analyzing steps under different manufacturing types, and the salient and non-salient elements in row vectors are locked, so that important values of different parameters are determined according to the frequency of columns, step manufacturing standards are conveniently constructed and obtained, an effective basis is provided for simulation of subsequent semiconductors, and the requirement satisfaction of the semiconductor is further guaranteed.
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, which further comprises the following steps: building standard allowable error ranges, including:
locking a matching element closest to a parameter importance value of the basic manufacturing parameter in a corresponding column vector of each basic manufacturing parameter from the step matrix, and screening a first element in adjacent relation with the matching element and a second element in upper adjacent relation with the matching element;
calculating a current reasonable value of the matching element according to the first element, the second element and the corresponding matching element;
；
wherein H0 represents the current reasonable value of the matching element;a value representing a match to said matching element +.>A value of a second element having an upper adjacency; />A value representing a match to said matching element +.>The value of the first element of the adjacency in presence, wherein +.>；
Determining an adjustment coefficient T0 according to the following formula;
；
wherein,representing a preset reasonable value; />Representing the adjustment quantity of the preset reasonable value; />Representing the adjustment variable coefficient;
according to the adjustment coefficient, determining a standard allowable error range of the corresponding matching element:
；
wherein,representing a first error factor; />Representing a second error factor;
if it isThe corresponding standard allowable error range is；
Otherwise, the corresponding standard allowable error range is。
In this embodiment, each basic parameter in the step matrix originally has a predetermined importance value according to the corresponding manufacturing type, so after the parameter importance value of each parameter is calculated, the parameter importance value is compared with the predetermined importance value of different elements in the corresponding column to lock the closest matching element, and the matching element is an element having an adjacent relation with the parameter importance value and an element having an adjacent relation with the existence, that is, two side elements located at the parameter importance value and closest to the parameter importance value, if one side element does not exist, the matching element is the same as the parameter importance value by default.
For example, if the parameter importance value is 0.4 and 3 elements exist in the corresponding column, the predetermined importance value of each element is 0.2,0.3,0.5, and at this time, the first element closest to 0.4 is the element corresponding to 0.3 (lower adjacent relationship), and the second element closest to 0.4 is the element corresponding to 0.5 (upper adjacent relationship).
In this embodiment, the preset reasonable value is 0.1, the adjustment amount is 0.02, and the adjustment variable coefficient is n2.
The beneficial effects of the technical scheme are as follows: the upper adjacent element and the lower adjacent element which are closest to the matching element are locked from the step matrix, so that the current reasonable value of the matching element is calculated, the adjustment coefficient and the error factor are calculated, the standard allowable error range of the corresponding parameter is effectively obtained, and the reliability of subsequent manufacturing is ensured.
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, which acquires the manufacturing requirement of the avalanche high-voltage diode, and carries out manufacturing mapping on the manufacturing requirement and each manufacturing step, and the manufacturing method comprises the following steps:
extracting a manufacturing description in the manufacturing requirements of the avalanche high voltage diode;
and matching the manufacturing description with the description-step list to obtain a matching step of each manufacturing description, and performing manufacturing mapping.
In this embodiment, the description-step list includes different manufacturing descriptions and associated matching steps, such as annealing time (description) corresponding to the annealing step, which is the manufacturing map.
The beneficial effects of the technical scheme are as follows: by matching the description with the steps, the manufacturing map is facilitated, providing a basis for the subsequent simulation of the semiconductor.
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, which combines a step manufacturing standard and a standard allowable error range to determine step adjustment information, and comprises the following steps:
according to the manufacturing mapping result, the matching steps are in one-to-one correspondence with the manufacturing steps, and whether redundant steps exist is determined;
the redundant steps and the step manufacturing standard and standard allowable error range of each manufacturing step are used as step adjustment information.
In this embodiment, for example, there are: step 1, step 12, step 2 and step 3 exist after the matching manufacture, and step 12 is an unnecessary step at this time.
In this embodiment, the standard allowable error range is an error based on different parameters.
The beneficial effects of the technical scheme are as follows: and by manufacturing the mapping result, redundant steps are convenient to determine, and step adjustment information is convenient to obtain by combining the standard allowable error range, so that a foundation is provided for subsequent simulation manufacturing.
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, which optimizes the initial manufacturing flow according to the step adjustment information to obtain the current manufacturing flow, and comprises the following steps:
obtaining redundant steps in the step adjustment information, and inserting the redundant steps into corresponding positions in the initial manufacturing flow;
and simultaneously, standardizing the step manufacturing standard and the corresponding manufacturing step in the step adjustment information, and setting allowable variation parameters to the corresponding manufacturing step according to the standard allowable error range to obtain the current manufacturing flow.
In this embodiment, for example, step 12 is required to be placed between step 1 and step 2, and the position between step 1 and step 2 is the determined position of the redundant step.
In this embodiment, for example, the annealing time of the parameter 1 is 90 seconds, and the standard allowable range related to the time is [ -3 seconds, 2 seconds ] and the allowable variation parameter is [87 seconds, 92 seconds ] and the allowable variation parameter is set to the corresponding annealing process.
The beneficial effects of the technical scheme are as follows: by determining the location of the redundant steps and setting the allowable variation parameters for the different steps, efficient acquisition of the current manufacturing flow is facilitated.
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, which simulates a semiconductor to be prepared, and comprises the following steps:
determining the initial simulation time of each sub-process in the current manufacturing process, and constructing the shortest simulation line and the longest simulation line;
determining a manufacturing process set of each sub-process, monitoring based on a monitoring tool which is pre-bound with the corresponding manufacturing process, and determining process operation time lengths of different manufacturing processes in the corresponding sub-process, an operation position set of each operation time point under the same manufacturing process and operation parameters based on a monitoring result to obtain process operation characteristics of the corresponding manufacturing process under different operation time points;
determining a first manufacturing time period of the corresponding sub-assembly based on a process operation duration of each manufacturing process in the same sub-flow;
comparing each first manufacturing time period with the shortest simulation line and the corresponding simulation period in the longest simulation line in sequence according to the manufacturing sequence of all the subassemblies;
if it isThe corresponding sub-assembly is reserved, wherein +.>Representing the shortest simulation segment corresponding to the b1 sub-process in the shortest simulation line; />A first manufacturing time period representing a b1 th sub-process; />Representing the longest simulation segment corresponding to the b1 sub-process in the longest simulation line;
otherwise, comparing each process operation characteristic of each manufacturing process in the corresponding sub-assembly with the standard operation characteristic respectively to determine a corresponding difference factor;
；
wherein Zc represents a difference factor of the c-th manufacturing process in the corresponding subassembly, and the value range of c is [1, m1]The method comprises the steps of carrying out a first treatment on the surface of the n represents the operation time of the corresponding manufacturing processA dot;representing process operating characteristics of the c-th manufacturing process based on the n-th operating time point; />Representing standard operating characteristics of the c-th manufacturing process based on the n-th operating time point; />Represents the process operation characteristic of the c-th manufacturing process based on the j 1-th operation time point, and the value range of j1 is [1, n ]]；/>Representing standard operating characteristics of the c-th manufacturing process based on the j 1-th operating time point;
taking all the difference factors related in the same sub-assembly as manufacturing differences, and correcting and reserving the corresponding sub-assemblies;
based on the simulation sequence of the sub-processes, sequentially constructing the reserved sub-assemblies to obtain a simulated semiconductor;
injecting preset carriers with different concentrations into the analog semiconductor by utilizing avalanche breakdown, recording the transit time of the different preset carriers based on the analog semiconductor, and constructing a transit array set;
carrying out data analysis on the transit array, and judging whether the oscillation condition of the analog semiconductor meets the following constraint condition or not;
；
wherein,representing the concentration of preset carriers in the corresponding transit array; />The expression is based on concentration +.>Standard transit times of (2); />The expression is based on concentration +.>Is set, the actual transit time of (a); />The expression is based on concentration +.>Is a first error value of (a); />The expression is based on concentration +.>A second error value of (2);
if the number of the transition array sets meeting the constraint condition exceedsAnd judging that the analog semiconductor is qualified, wherein M represents the number of transition arrays in the transition array set.
In this embodiment, each sub-process in the current manufacturing process has an error range, so that there is a time error, for example, the annealing time range is 87 seconds to 92 seconds, and the shortest analog line and the longest analog line are obtained, where each sub-process is considered as a manufacturing step.
In this embodiment, as shown in fig. 2, p1 is the shortest analog line, for example, p1 includes p11, p12, and p13, p2 is the longest analog line, for example, p2 includes p21, p22, and p23, and the total duration of the process operation duration of the manufacturing process of the sub-flow corresponding to p11 and p21 is p3, which is regarded as the first manufacturing period.
In this example, manufacturing variations:the corresponding sub-assemblies are corrected according to manufacturing differences, and the correction schemes corresponding to the difference factors are acquired from a difference-correction scheme database to correct the corresponding processes, so that reasonable correction of the sub-assemblies is realized, for example,
in this example, the lithographic thickness was 1.4um, and the correlation between the difference and the thickness was determined to be that the thickness was required to be weakened by 0.03um, and the corrected lithographic thickness was 1.37um.
In this embodiment, the simulated semiconductor is obtained after sequential construction of the subassemblies.
In this embodiment, the transition array: the transition array set comprises arrays related to preset carriers at different concentrations and matched transition time.
In this embodiment, the first error value and the second error value at different concentrations are predetermined.
In this embodiment, the monitoring tool is pre-bound, and mainly monitors the simulation process to determine the operation duration, the operation object, and the operation parameters, where the operation parameters are related to the manufacturing parameters related to the corresponding sub-process, and the operation corresponds to, for example, the substrate.
The beneficial effects of the technical scheme are as follows: by making a comparison of the analog durations. Whether the corresponding sub-assembly needs to be reserved or not is preliminarily determined, a difference factor is obtained by calculating standard operation characteristics and process operation characteristics of different manufacturing processes in the same assembly, the existing manufacturing difference is further determined, and the reliability of semiconductor manufacturing is further ensured by carrying out injection test of carriers with different concentrations and further judging oscillation conditions.
The invention provides a manufacturing method of a semiconductor avalanche high-voltage diode, when the simulation result is qualified, the manufacturing method carries out semiconductor manufacturing according to the final manufacturing flow, and the manufacturing method comprises the following steps:
obtaining a final manufacturing flow with qualified simulation results;
and sequentially manufacturing according to the flow sequence of the final manufacturing flow to obtain the required semiconductor.
In this embodiment, the final manufacturing process is obtained based on the qualification of the simulation result, and the manufacturing is performed based on the final manufacturing process.
The beneficial effects of the technical scheme are as follows: by performing semiconductor fabrication in accordance with the final fabrication flow, reliability of the fabrication is ensured.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. A method of manufacturing a semiconductor avalanche high voltage diode, comprising:
step 1: acquiring an initial manufacturing flow of the avalanche high-voltage diode, and acquiring a step manufacturing standard and a standard allowable error range of each manufacturing step in the initial manufacturing flow;
step 2: obtaining the manufacturing requirement of the avalanche high-voltage diode, carrying out manufacturing mapping on the manufacturing requirement and each manufacturing step, and determining step adjustment information by combining step manufacturing standards and standard allowable error ranges;
step 3: optimizing the initial manufacturing flow according to the step adjustment information to obtain a current manufacturing flow, and simulating a semiconductor to be prepared;
step 4: when the simulation result is qualified, semiconductor manufacturing is carried out according to the final manufacturing flow;
wherein, to wait to prepare the semiconductor and simulate, include:
determining the initial simulation time of each sub-process in the current manufacturing process, and constructing the shortest simulation line and the longest simulation line;
determining a manufacturing process set of each sub-process, monitoring based on a monitoring tool which is pre-bound with the corresponding manufacturing process, and determining process operation time lengths of different manufacturing processes in the corresponding sub-process, an operation position set of each operation time point under the same manufacturing process and operation parameters based on a monitoring result to obtain process operation characteristics of the corresponding manufacturing process under different operation time points;
determining a first manufacturing time period of the corresponding sub-assembly based on a process operation duration of each manufacturing process in the same sub-flow;
comparing each first manufacturing time period with the shortest simulation line and the corresponding simulation period in the longest simulation line in sequence according to the manufacturing sequence of all the subassemblies;
if Ld j1 ≤L j1 ≤Lc j1 Reserving the corresponding sub-assembly;
otherwise, comparing each process operation characteristic of each manufacturing process in the corresponding sub-assembly with the standard operation characteristic respectively to determine a corresponding difference factor;
wherein Zc represents a difference factor of the c-th manufacturing process in the corresponding subassembly, and the value range of c is [1, m1]The method comprises the steps of carrying out a first treatment on the surface of the n represents an operation time point corresponding to a manufacturing process; s is(s) n Representing process operating characteristics of the c-th manufacturing process based on the n-th operating time point; r is (r) n Representing standard operating characteristics of the c-th manufacturing process based on the n-th operating time point; s is(s) j1 Represents the process operation characteristic of the c-th manufacturing process based on the j 1-th operation time point, and the value range of j1 is [1, n ]]；r j1 Representing standard operating characteristics of the c-th manufacturing process based on the j 1-th operating time point;
taking all the difference factors related in the same sub-assembly as manufacturing differences, and correcting and reserving the corresponding sub-assemblies;
based on the simulation sequence of the sub-processes, sequentially constructing the reserved sub-assemblies to obtain a simulated semiconductor;
injecting preset carriers with different concentrations into the analog semiconductor by utilizing avalanche breakdown, recording the transit time of the different preset carriers based on the analog semiconductor, and constructing a transit array set;
carrying out data analysis on the transit array, and judging whether the oscillation condition of the analog semiconductor meets the following constraint condition or not;
wherein F is Y Representing the concentration of preset carriers in the corresponding transit array;the representation is based on concentration F Y Standard transit times of (2); t (T) S The representation is based on concentration F Y Is set, the actual transit time of (a); />The representation is based on concentration F Y Is a first error value of (a); />The representation is based on concentration F Y A second error value of (2);
if the number of the transition array sets meeting the constraint condition exceedsAnd judging the analog semiconductor to be qualified, wherein M represents the number of transition arrays in the transition array set.
2. The method of manufacturing a semiconductor avalanche high voltage diode according to claim 1, wherein obtaining an initial manufacturing flow of the avalanche high voltage diode comprises:
acquiring an original scheme consistent with each manufacturing type from a type-scheme database based on all manufacturing types of the avalanche high-voltage diode;
step intersection processing is carried out on the original scheme to obtain an intersection step;
and obtaining an initial manufacturing flow based on the intersection step and the step sequence of the intersection step.
3. The method of manufacturing a semiconductor avalanche high voltage diode according to claim 1, wherein obtaining step manufacturing criteria for each manufacturing step in said initial manufacturing flow comprises:
sequentially carrying out step analysis on the manufacturing type of each manufacturing step to obtain a plurality of basic manufacturing parameters of the same manufacturing step based on each manufacturing type, and constructing a step matrix X1 of the same manufacturing step;
wherein y1 n2,n1 An element value representing an n1 st base manufacturing parameter under an n2 nd manufacturing type, n2 representing a total number of manufacturing types; n1 represents the total number of basic manufacturing parameters corresponding to the same manufacturing step; y1 1,1 Element values representing the 1 st base manufacturing parameter for the 1 st manufacturing type; y1 1,n1 An element value representing an nth 1 base manufacturing parameter for a 1 st manufacturing type; y1 n2,1 Element values representing the 1 st base manufacturing parameter for the n2 nd manufacturing type;
according to the manufacturing type, locking the salient elements and the non-salient elements of each row of vectors in the step matrix, and determining the salient frequency of the parameters in each column of vectors in the step matrix according to the distribution of the salient elements and the non-salient elements based on the step matrix;
determining a parameter importance value of each basic manufacturing parameter according to the acquired result and the highlighting result;
wherein r1 i1 Representing the i1 st salient element in the corresponding column vector based on the element under the corresponding manufacturing typeA prime weight; u01 represents the total number of salient elements existing in the corresponding column vector, namely, the salient frequency; u02 represents the total number of non-salient elements present in the corresponding column vector; max represents the maximum value symbol; z1 represents a parameter importance value of the basic manufacturing parameter to which the corresponding column vector matches, and u01+u02=n2;
and according to the parameter importance value, importance adjustment is carried out on basic manufacturing parameters of corresponding manufacturing step types, and step manufacturing standards are constructed and obtained.
4. The method for manufacturing a semiconductor avalanche high voltage diode according to claim 3, further comprising: building standard allowable error ranges, including:
locking a matching element closest to a parameter importance value of the basic manufacturing parameter in a corresponding column vector of each basic manufacturing parameter from the step matrix, and screening a first element in adjacent relation with the matching element and a second element in upper adjacent relation with the matching element;
calculating a current reasonable value of the matching element according to the first element, the second element and the corresponding matching element;
wherein H0 represents the current reasonable value of the matching element; p01 1 Representing a value p01 of the matching element 2 A value of a second element having an upper adjacency; p01 3 Representing a value p01 of the matching element 2 The value of the first element in the adjacent relationship in the presence, where p01 1 ＞p01 2 ＞p01 3 ；
Determining an adjustment coefficient T0 according to the following formula;
wherein Δ1 representsPresetting a reasonable value; ε 1 represents the adjustment amount for the preset reasonable value;representing the adjustment variable coefficient;
according to the adjustment coefficient, determining a standard allowable error range of the corresponding matching element:
δ1＝p01 1 -p01 2 +T0；
δ2＝p01 2 -p01 3 +T0；
wherein δ1 represents a first error factor; δ2 represents a second error factor;
if p01 1 -p01 2 ≥p01 2 -p01 3 The corresponding standard allowable error range is (- (max (δ1, δ2)), min (δ1, δ2));
otherwise, the corresponding standard allowable error range is (- (min (δ1, δ2)), max (δ1, δ2)).
5. The method of manufacturing a semiconductor avalanche high voltage diode according to claim 1, wherein obtaining manufacturing requirements for said avalanche high voltage diode, mapping said manufacturing requirements with each manufacturing step, comprises:
extracting a manufacturing description in the manufacturing requirements of the avalanche high voltage diode;
and matching the manufacturing description with the description-step list to obtain a matching step of each manufacturing description, and performing manufacturing mapping.
6. The method of manufacturing a semiconductor avalanche high voltage diode according to claim 1, wherein said determining step adjustment information includes, in combination with step manufacturing criteria and standard allowable error ranges:
according to the manufacturing mapping result, the matching steps are in one-to-one correspondence with the manufacturing steps, and whether redundant steps exist is determined;
the redundant steps and the step manufacturing standard and standard allowable error range of each manufacturing step are used as step adjustment information.
7. The method of manufacturing a semiconductor avalanche high voltage diode according to claim 6, wherein optimizing said initial manufacturing process based on said step adjustment information results in a current manufacturing process comprising:
obtaining redundant steps in the step adjustment information, and inserting the redundant steps into corresponding positions in the initial manufacturing flow;
and simultaneously, standardizing the step manufacturing standard and the corresponding manufacturing step in the step adjustment information, and setting allowable variation parameters to the corresponding manufacturing step according to the standard allowable error range to obtain the current manufacturing flow.
8. The method for manufacturing the semiconductor avalanche high voltage diode according to claim 1, wherein when the simulation result is qualified, the semiconductor manufacturing is performed according to a final manufacturing flow, comprising:
obtaining a final manufacturing flow with qualified simulation results;
and sequentially manufacturing according to the flow sequence of the final manufacturing flow to obtain the required semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311028168.9A CN116759311B (en) | 2023-08-16 | 2023-08-16 | Manufacturing method of semiconductor avalanche high-voltage diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311028168.9A CN116759311B (en) | 2023-08-16 | 2023-08-16 | Manufacturing method of semiconductor avalanche high-voltage diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116759311A CN116759311A (en) | 2023-09-15 |
| CN116759311B true CN116759311B (en) | 2023-11-14 |
Family
ID=87959455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311028168.9A Active CN116759311B (en) | 2023-08-16 | 2023-08-16 | Manufacturing method of semiconductor avalanche high-voltage diode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116759311B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105931952A (en) * | 2016-05-17 | 2016-09-07 | 中航（重庆）微电子有限公司 | Manufacturing method for avalanche diode structure |
| CN107092760A (en) * | 2017-05-05 | 2017-08-25 | 中国科学院半导体研究所 | The method of adjustment of avalanche photodide device and its structural parameters |
| CN111276555A (en) * | 2019-11-04 | 2020-06-12 | 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 | Structure optimization method based on InGaAs/InAlAs/InP avalanche photodetector |
| CN114284144A (en) * | 2021-11-10 | 2022-04-05 | 扬州大学 | Diode manufacturing method and diode |
| CN114429311A (en) * | 2022-02-17 | 2022-05-03 | 广州志橙半导体有限公司 | Dynamic monitoring method and system for semiconductor manufacturing process |
| CN114497342A (en) * | 2022-01-25 | 2022-05-13 | 龙蔚电子技术有限公司 | Implementation method based on semiconductor refrigeration sheet |
| CN114580280A (en) * | 2022-03-02 | 2022-06-03 | 北京市商汤科技开发有限公司 | Model quantization method, device, apparatus, computer program and storage medium |
| CN116130561A (en) * | 2023-04-14 | 2023-05-16 | 山西创芯光电科技有限公司 | Preparation method of superlattice infrared detector |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11526808B2 (en) * | 2019-05-29 | 2022-12-13 | The Board Of Trustees Of The Leland Stanford Junior University | Machine learning based generation of ontology for structural and functional mapping |
-
2023
- 2023-08-16 CN CN202311028168.9A patent/CN116759311B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105931952A (en) * | 2016-05-17 | 2016-09-07 | 中航（重庆）微电子有限公司 | Manufacturing method for avalanche diode structure |
| CN107092760A (en) * | 2017-05-05 | 2017-08-25 | 中国科学院半导体研究所 | The method of adjustment of avalanche photodide device and its structural parameters |
| CN111276555A (en) * | 2019-11-04 | 2020-06-12 | 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 | Structure optimization method based on InGaAs/InAlAs/InP avalanche photodetector |
| CN114284144A (en) * | 2021-11-10 | 2022-04-05 | 扬州大学 | Diode manufacturing method and diode |
| CN114497342A (en) * | 2022-01-25 | 2022-05-13 | 龙蔚电子技术有限公司 | Implementation method based on semiconductor refrigeration sheet |
| CN114429311A (en) * | 2022-02-17 | 2022-05-03 | 广州志橙半导体有限公司 | Dynamic monitoring method and system for semiconductor manufacturing process |
| CN114580280A (en) * | 2022-03-02 | 2022-06-03 | 北京市商汤科技开发有限公司 | Model quantization method, device, apparatus, computer program and storage medium |
| CN116130561A (en) * | 2023-04-14 | 2023-05-16 | 山西创芯光电科技有限公司 | Preparation method of superlattice infrared detector |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116759311A (en) | 2023-09-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111008502B (en) | Fault prediction method for complex equipment driven by digital twin | |
| US20200063665A1 (en) | Aero-engine full flight envelope model adaptive modification method based on deep learning algorithm | |
| US5245543A (en) | Method and apparatus for integrated circuit design | |
| CN109873457B (en) | Multi-time scale cascading failure prediction method for power system under typhoon weather condition | |
| CN111080477A (en) | Household power load prediction method and system | |
| CN105008946A (en) | Method for determining a control observer for the soc | |
| US8781614B2 (en) | Semiconductor processing dispatch control | |
| CN108387837B (en) | Chip testing method | |
| CN110334865B (en) | Power equipment fault rate prediction method and system based on convolutional neural network | |
| CN105974495A (en) | Method for pre-judging future average cloud amount of target area by using classification fitting method | |
| CN116759311B (en) | Manufacturing method of semiconductor avalanche high-voltage diode | |
| CN114266223B (en) | Method, device, equipment and computer readable storage medium for determining faults of machine | |
| CN114490905A (en) | Clear sky surface net long wave radiation integrated inversion method and system | |
| CN112685958B (en) | SiC MOSFET blocking voltage determination method based on neural network | |
| JPH08279446A (en) | Method of manufacturing semiconductor device | |
| CN1333312C (en) | Method and apparatus for scheduling production lots based on lot and tool health metrics | |
| CN117371303A (en) | Prediction method for effective wave height under sea wave | |
| US8406904B2 (en) | Two-dimensional multi-products multi-tools advanced process control | |
| CN101477582B (en) | Model modification method for a semiconductor device | |
| CN107436957A (en) | A kind of chaos polynomial construction method | |
| CN115496279A (en) | Temperature forecast correction method based on dynamic weight integration | |
| CN114004405A (en) | Photovoltaic power prediction method and system based on Elman neural network and satellite cloud picture | |
| US20070072315A1 (en) | Method and system for reliability similarity of semiconductor devices | |
| Bakbergenuly et al. | Simulation study of estimating between-study variance and overall effect in meta-analysis of odds-ratios | |
| CN117293817B (en) | Power generation parameter prediction method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |