CN116759302A - Semiconductor structure with PN junction and preparation method thereof - Google Patents

Semiconductor structure with PN junction and preparation method thereof Download PDF

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Publication number
CN116759302A
CN116759302A CN202310756018.3A CN202310756018A CN116759302A CN 116759302 A CN116759302 A CN 116759302A CN 202310756018 A CN202310756018 A CN 202310756018A CN 116759302 A CN116759302 A CN 116759302A
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Prior art keywords
region
photoresist layer
ion implantation
semiconductor substrate
conductivity type
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CN202310756018.3A
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Chinese (zh)
Inventor
廖黎明
仇峰
胡林辉
张蔷
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GTA Semiconductor Co Ltd
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GTA Semiconductor Co Ltd
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Priority to CN202310756018.3A priority Critical patent/CN116759302A/en
Publication of CN116759302A publication Critical patent/CN116759302A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]

Abstract

The application provides a semiconductor structure with PN junction and a preparation method thereof. According to the semiconductor structure with the PN junction, the appearance of the photoresist layer is changed, the thickness of the photoresist layer at the edge of the opening is smaller than that of the photoresist layer in other areas, so that the ion implantation concentration of the corresponding local area at the edge of the opening is smaller due to the smaller thickness of the photoresist layer, the ion implantation of the central area of the opening is normal, and the normal ion implantation concentration is obtained, so that the ion implantation concentration of the PN junction is lower, the reverse withstand voltage of the PN junction can be effectively improved, and the occupied area of the PN junction is not increased; meanwhile, the ion implantation concentration of other areas of the well region is normal, and the electrical change of other devices is avoided.

Description

Semiconductor structure with PN junction and preparation method thereof
Technical Field
The application relates to the field of semiconductors, in particular to a semiconductor structure with PN junctions and a preparation method thereof.
Background
With the continuous progress of semiconductor integrated circuit manufacturing technology, the performance of semiconductor devices is continuously improved. PN junction is the most basic structural unit in semiconductor device, and has unidirectional conductive characteristics of forward conduction and reverse cut-off, which is the characteristic utilized by many devices (such as semiconductor diode and bipolar transistor) in electronic technology, and is mainly applied to rectifying, amplifying, switching, isolating and other application occasions.
Please refer to fig. 1, which is a schematic diagram of a typical PN junction. As shown in fig. 1, between isolation structures 19 of a semiconductor substrate 10 (typically silicon or germanium or silicon carbide, etc.), different doping processes are used, one side is implanted with N-type ions to form an N-well region 11, and the other side is implanted with P-type ions to form a P-well region 12; space charge regions, called PN junctions (PN junctions) 13, are formed on both sides of the contact surface 101 of the P-well region 12 and the N-well region 11. The thickness of the space charge region is dependent on the dopant concentration.
The reverse withstand voltage of the PN junction is one of the important parameters, and the improvement of the reverse withstand voltage of the PN junction is the key point in the development of semiconductors. The reverse withstand voltage of the PN junction is generally improved as follows: 1. reducing ion implantation concentrations of P-type ions and N-type ions; 2. increasing the spacing 209 of the P-well region 12 and the N-well region 11 as shown in fig. 2; 3. the ion implantation region is partially divided to form a plurality of slits (slots) 311, 321, and then homogenized by thermal diffusion, as shown in fig. 3.
The method can effectively improve the reverse withstand voltage of PN junctions by adopting a mode of reducing the ion implantation concentration of P-type ions and N-type ions, but can simultaneously cause the electrical property change of other devices; such as changes in resistance, capacitance, transistor channel threshold voltage, etc. of the related type implant; and the mode of reducing the ion implantation concentration is difficult to unify the concentration requirements of different devices on the same ion implantation. The reverse voltage resistance can also be effectively improved by adopting the mode of increasing the spacing shown in fig. 2, but the mode can greatly increase the occupied area of the PN junction for the requirement of high voltage resistance. By adopting the mode shown in fig. 3, the reverse voltage resistance can be effectively improved without increasing the occupied area of the PN junction, and even for the semiconductor structure with small size, finer region division can not be performed, so that the implementation process is limited.
Disclosure of Invention
The technical problem to be solved by the application is to provide the semiconductor structure with the PN junction and the preparation method thereof, so that the PN junction with local lower concentration can be obtained on the basis of the existing technology without adding an additional technology, and the reverse voltage resistance of the PN junction is effectively improved.
In order to solve the above problems, the present application provides a method for manufacturing a semiconductor structure having a PN junction, comprising the steps of: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first region and a second region which are separated by a plurality of isolation structures, and the surfaces of all the isolation structures are basically flush with the surface of the semiconductor substrate; forming a first photoresist layer on the surface of the semiconductor substrate, wherein the first photoresist layer is provided with a first opening, the first opening exposes the first region, the first photoresist layer is provided with a first auxiliary photoresist layer positioned at the edge of the first opening and a first main photoresist layer adjacent to the first auxiliary photoresist layer, and the thickness of the first auxiliary photoresist layer is smaller than that of the first main photoresist layer; performing first conductivity type ion implantation on the semiconductor substrate by using the first photoresist layer as a mask to form a first well region and removing the first photoresist layer, wherein the first well region comprises the first region and a third region after ion implantation, the third region is positioned at one side of the isolation structure far away from the surface of the semiconductor substrate and is adjacent to the first region, and the ion implantation concentration of the third region is smaller than that of the first region; forming a second photoresist layer on the surface of the semiconductor substrate, wherein the second photoresist layer is provided with a second opening, the second opening exposes the second region, the second photoresist layer is provided with a second auxiliary photoresist layer positioned at the edge of the second opening and a second main photoresist layer adjacent to the second auxiliary photoresist layer, and the thickness of the second auxiliary photoresist layer is smaller than that of the second main photoresist layer; and performing second conductivity type ion implantation on the semiconductor substrate by using the second photoresist layer as a mask to form a second well region and removing the second photoresist layer, wherein the second well region comprises a second region and a fourth region after ion implantation, the fourth region is positioned at one side of the isolation structure far away from the surface of the semiconductor substrate and is adjacent to the second region, the ion implantation concentration of the fourth region is smaller than that of the second region, the fourth region is contacted with the third region, so that PN junctions are formed at two side regions of a contact surface, and the first conductivity type is opposite to the second conductivity type.
In order to solve the above problems, the present application also provides a semiconductor structure having a PN junction, comprising: a semiconductor substrate having a first region and a second region separated by a plurality of isolation structures therein; a first well region having a first conductivity type, the first well region including the first region after ion implantation and a third region located at a side of the isolation structure away from the surface of the semiconductor substrate and adjacent to the first region, the third region having a concentration of ion implantation less than a concentration of ion implantation of the first region; a second well region having a second conductivity type, the second well region including the second region after ion implantation and a fourth region located on a side of the isolation structure away from the surface of the semiconductor substrate and adjacent to the second region, the fourth region having a lower ion implantation concentration than the second region, the first conductivity type being opposite to the second conductivity type; PN junction formed on two side areas of contact surface between the fourth region and the third region.
According to the technical scheme, the shape of the photoresist layer is changed, so that the ion implantation concentration of the PN junction is low, the reverse withstand voltage of the PN junction can be effectively improved, and the occupied area of the PN junction is not increased; meanwhile, the ion implantation concentration of other areas of the well region is normal, and the electrical change of other devices is avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described. It is apparent that the drawings in the following description are only some specific embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a typical PN junction;
FIG. 2 is a schematic diagram of an embodiment of improving reverse withstand voltage of PN junction in the prior art;
FIG. 3 is a schematic diagram of another embodiment of improving reverse withstand voltage of PN junction in the prior art;
fig. 4 is a flowchart illustrating steps of a method for fabricating a semiconductor structure with a PN junction according to an embodiment of the present application;
fig. 5 to 10 are process flow diagrams of a method for manufacturing a semiconductor structure with a PN junction according to an embodiment of the present application.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
Referring to fig. 4 to 10, fig. 4 is a flowchart illustrating steps of a method for manufacturing a semiconductor structure with a PN junction according to an embodiment of the present application, and fig. 5 to 10 are process flowcharts of a method for manufacturing a semiconductor structure with a PN junction according to an embodiment of the present application.
As shown in fig. 4, the method for preparing the semiconductor structure with the PN junction according to the present application includes the following steps: step S41, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first region and a second region which are separated by a plurality of isolation structures, and the surfaces of all the isolation structures are basically level with the surface of the semiconductor substrate; step S42, forming a first photoresist layer on the surface of the semiconductor substrate, wherein the first photoresist layer is provided with a first opening, the first opening exposes the first region, the first photoresist layer is provided with a first auxiliary photoresist layer positioned at the edge of the first opening and a first main photoresist layer adjacent to the first auxiliary photoresist layer, and the thickness of the first auxiliary photoresist layer is smaller than that of the first main photoresist layer; step S43, performing first conductivity type ion implantation on the semiconductor substrate by using the first photoresist layer as a mask to form a first well region and removing the first photoresist layer, wherein the first well region comprises the first region and a third region after ion implantation, the third region is positioned at one side of the isolation structure far away from the surface of the semiconductor substrate and is adjacent to the first region, and the ion implantation concentration of the third region is smaller than that of the first region; step S44, forming a second photoresist layer on the surface of the semiconductor substrate, wherein the second photoresist layer is provided with a second opening, the second opening exposes the second region, the second photoresist layer is provided with a second auxiliary photoresist layer positioned at the edge of the second opening and a second main photoresist layer adjacent to the second auxiliary photoresist layer, and the thickness of the second auxiliary photoresist layer is smaller than that of the second main photoresist layer; and step S45, performing second conductivity type ion implantation on the semiconductor substrate by using the second photoresist layer as a mask to form a second well region and removing the second photoresist layer, wherein the second well region comprises the second region and a fourth region after ion implantation, the fourth region is positioned at one side of the isolation structure far away from the surface of the semiconductor substrate and is adjacent to the second region, the ion implantation concentration of the fourth region is smaller than that of the second region, the fourth region is contacted with the third region, so that PN junctions are formed in the regions at two sides of a contact surface, and the first conductivity type and the second conductivity type are opposite.
Referring to fig. 5 and step S41, a semiconductor substrate 40 is provided, wherein the semiconductor substrate 40 has a first region 401 and a second region 402 separated by a plurality of isolation structures 49.
In the present embodiment, the semiconductor substrate 40 may be any one of a silicon (Si) substrate, silicon carbide (SiC), or silicon nitride (SiN). The semiconductor substrate 40 may also be a stacked structure such as a silicon/germanium/silicon stack or the like. In this embodiment, a semiconductor substrate 40 is taken as an example of a silicon substrate.
In this embodiment, the semiconductor substrate 40 is provided with the isolation structures 49, and two adjacent isolation structures 49 may define the corresponding first region 401 and the second region 402 in the semiconductor substrate 40. In this embodiment, the surface of all the isolation structures 49 is substantially flush with the surface of the semiconductor substrate 40, and the width of the isolation structures 49 between the first region 401 and the second region 402 is greater than the width of the isolation structures 49 on the other side of the first region 401 and the other side of the second region 402. In this embodiment, the isolation structure 49 may be a shallow trench isolation (Shallow Trench Isolation, STI) structure. A trench is formed by depositing, patterning and etching a silicon substrate by utilizing a silicon nitride mask, and a shallow trench isolation structure is formed by filling deposited oxide in the trench for insulating isolation between adjacent areas. The isolation structure 49 may be a single layer or a multi-layer composite structure, for example, in some embodiments the isolation structure 49 is an oxide isolation structure, in other embodiments the isolation structure 49 is a composite of a silicon oxide isolation structure and a nitride isolation structure.
Referring to fig. 6 and step S42, a first photoresist layer 41 is formed on the surface of the semiconductor substrate 40, the first photoresist layer 41 has a first opening 410, the first opening 410 exposes the first region 401, the first photoresist layer 41 has a first auxiliary photoresist layer 411 located at an edge of the first opening 410 and a first main photoresist layer 412 adjacent to the first auxiliary photoresist layer 411, and a thickness of the first auxiliary photoresist layer 411 is smaller than a thickness of the first main photoresist layer 412. Wherein the thickness of the photoresist layer is defined as its height in a direction perpendicular to the surface of the semiconductor substrate 40.
According to the embodiment, the appearance of the photoresist layer is changed, the thickness of the photoresist layer at the edge of the opening is smaller than that of the photoresist layer in other areas, so that the ion implantation concentration of the corresponding local area at the edge of the opening is smaller due to the smaller thickness of the photoresist layer, the ion implantation of the central area of the opening is normal, and the normal ion implantation concentration is obtained, so that the purposes that the ion implantation concentration of the local area at the edge of the opening is reduced and the ion implantation concentration of the central area of the opening is not influenced are achieved.
In this embodiment, the bottom 4101 of the first opening 410 is the semiconductor substrate 40, the opposite sides 4102, 4103 of the first opening 410 are the first photoresist layer 41, and the sides 4102, 4103 extend away from the semiconductor substrate 40 at an acute angle to the surface of the semiconductor substrate 40. The acute included angle (e.g., θ in fig. 6) may be 45 degrees to 75 degrees. The first opening 410 thus formed has a portion that completely penetrates and a portion that has a gradual cross-sectional thickness. The completely penetrated portion corresponds to the first region 401, and can form a well region with normal concentration during subsequent ion implantation; the cross-sectional thickness gradient portion, due to the partial retention of the first photoresist layer 41, blocks the implantation of partial ions during the subsequent ion implantation, so that a well region with a lower concentration is formed therein. The specific parameters of the first opening 410 may be adjusted according to the well parameters and the process conditions, which are not limited herein.
In the present embodiment, the cross section of the first opening 410 is inverted trapezoid in a direction perpendicular to the surface of the semiconductor substrate 40. That is, the opposite sides 4102, 4103 of the first opening 410 are smoothly sloped, so that the ion implantation concentration of the corresponding regions of the opposite sides 4102, 4103 of the first opening 410 is gradually changed.
In this embodiment, the thickness of the first auxiliary photoresist layer 411 gradually decreases in a direction away from the first main photoresist layer 412; so that the ion implantation concentration of the corresponding region of the subsequent first auxiliary photoresist layer 411 gradually decreases in a direction away from the first region. In other embodiments, the first auxiliary photoresist layer 411 and the first main photoresist layer 412 may also have different thicknesses, so that the blocking of the ion implantation by the subsequent first auxiliary photoresist layer 411 is smaller than that of the first main photoresist layer 412, and thus the corresponding region of the first auxiliary photoresist layer 411 has a lower ion implantation concentration.
In some embodiments, the step of forming the first photoresist layer 41 on the semiconductor substrate 40 further includes: (1) Forming a first photoresist layer on the semiconductor substrate; (2) Forming a pattern of the first opening on the first photoresist layer through a photolithography process; (3) And developing the first photoresist material layer to form the first photoresist layer. Specifically, a layer of photoresist is paved on the surface of a semiconductor substrate, then a defined mask plate (the pattern of the first opening is defined on the mask plate) is placed on the surface of the semiconductor substrate, finally, after the light with a specific wavelength is irradiated, the activated photoresist is washed away by using a specific liquid, the photoresist is left as a photoresist layer at the place where ion implantation is not needed, and the photoresist is removed at the place where ion implantation is needed. Photoresists, also known as PR, are organic compounds that are sensitive to light and change in solubility in a particular liquid (e.g., a developer) when exposed to light of a particular wavelength (e.g., ultraviolet light). Specifically, the photoresist becomes activated in the irradiated places, and the activated photoresist is particularly easy to wash off by specific chemical liquid; the areas blocked by the mask are not activated because they are not illuminated by the light source, and the photoresist that is not activated cannot be washed away.
Referring to fig. 7 and step S43, the first photoresist layer 41 is used as a mask to perform a first conductivity type ion implantation on the semiconductor substrate 40 to form a first well region 43, and the first photoresist layer 41 is removed. Wherein the first well region 43 includes the first region 401 and the third region 431 after ion implantation; the third region 431 is located at a side of the isolation structure 49 away from the surface of the semiconductor substrate 40 and adjacent to the first region 401, and the ion implantation concentration of the third region 431 is smaller than that of the first region 401.
Because the shape of the photoresist layer is changed, the thickness of the photoresist layer at the edge of the opening is smaller than that of the photoresist layer in other areas, so that the ion implantation concentration of the third area 431 corresponding to the edge of the opening is smaller, and the ion implantation concentration of the first area 401 corresponding to the central area of the opening is normal (is the conventional concentration required by the well area of the semiconductor device); the third region 431 is used as a region for forming a PN junction subsequently, and the reverse voltage withstand of the PN junction can be effectively improved due to the reduction of the ion implantation concentration, and the occupied area of the PN junction cannot be increased in the mode; while the ion implantation concentration of the first region 401 is normal, electrical changes to other devices are avoided.
In the present embodiment, the ion implantation concentration of the third region 431 gradually decreases in a direction away from the first region 401. In other embodiments, the ion implantation concentration of the third region 431 may be uniform and smaller than that of the first region 401.
In this embodiment, the first conductivity type is N-type. In other embodiments, the first conductivity type may also be P-type.
Referring to fig. 8 and step S44, a second photoresist layer 42 is formed on the surface of the semiconductor substrate 40, the second photoresist layer 42 has a second opening 420, the second opening 420 exposes the second region 402, the second photoresist layer 42 has a second auxiliary photoresist layer 421 located at an edge of the second opening 402 and a second main photoresist layer 422 adjacent to the second auxiliary photoresist layer 421, and a thickness of the second auxiliary photoresist layer 421 is smaller than a thickness of the second main photoresist layer 422. The second photoresist layer 42 may be prepared by the same process as the first photoresist layer 41, and the second opening 420 may have substantially the same shape as the first opening 410.
Referring to fig. 9 and step S45, a second well region 44 is formed by performing a second conductivity type ion implantation on the semiconductor substrate 40 using the second photoresist layer 42 as a mask, and the second photoresist layer 42 is removed. Wherein the second well region 44 includes the second region 402 and the fourth region 441 after ion implantation; the fourth region 441 is located on a side of the isolation structure 49 away from the surface of the semiconductor substrate 40 and adjacent to the second region 402, the ion implantation concentration of the fourth region 441 is smaller than that of the second region 402, and the fourth region 441 contacts the third region 431, thereby forming PN junctions 45 in regions on both sides of the contact surface 450. Wherein the first conductivity type is opposite to the second conductivity type.
Because of the changed shape of the photoresist layer, the ion implantation concentrations of the fourth region 441 and the third region 431 are smaller, so that the ion implantation concentration of the PN junction 45 formed in the two side regions of the contact surface 450 between the fourth region 441 and the third region 431 is reduced, the reverse withstand voltage of the PN junction can be effectively improved, and the occupied area of the PN junction is not increased in this way; meanwhile, the ion implantation concentrations of the first region 401 and the second region 402 are normal, and electrical changes to other devices are avoided.
In the present embodiment, the ion implantation concentration of the fourth region 441 gradually decreases in a direction away from the second region 402. In other embodiments, the ion implantation concentration of the fourth region 441 may also be uniform and less than the ion implantation concentration of the second region 402.
In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the first conductivity type may also be P-type and the second conductivity type N-type.
Specifically, after the P-well region and the N-well region are combined, since free electrons in the N-well region are multi-electrons, holes are almost zero and called minority carriers, holes in the P-well region are multi-electrons, free electrons are minority carriers, and a concentration difference between electrons and holes occurs at the junction of the free electrons and the N-well region. Due to the difference in concentration of free electrons and holes, some electrons diffuse from the N-well region to the P-well region and some holes diffuse from the P-well region to the N-well region. As a result of their diffusion, holes are lost on the P-well region side, leaving negatively charged impurity ions, electrons are lost on the N-well region side, leaving positively charged impurity ions. Ions in the semiconductor in the open circuit cannot move arbitrarily and therefore do not participate in conduction. These immobile charged particles form a space charge region near the contact surface of the P-well region and the N-well region, and the thickness of the space charge region is related to the dopant concentration. After the space charge region is formed, an internal electric field is formed in the space charge region due to the interaction between positive and negative charges, which is directed from the positively charged N-well region to the negatively charged P-well region. Obviously, the direction of the internal electric field is opposite to the direction of the carrier diffusion movement, and diffusion is prevented. On the other hand, this internal electric field will drift the minority carrier holes of the N-well region towards the P-well region, and the minority carrier electrons of the P-well region towards the N-well region, the direction of the drift movement being exactly opposite to the direction of the diffusion movement. Holes drifting from the N well region to the P well region supplement holes lost by the P well region on the original contact surface, electrons drifting from the P well region to the N well region supplement electrons lost by the N well region on the original contact surface, space charge is reduced, and an internal electric field is weakened. As a result of this drift movement, the space charge region is narrowed and the diffusion movement is intensified. Finally, the diffusion of the multifeeds and the drift of the minority carriers reach dynamic balance. On both sides of the contact surface of the P well region and the N well region, an ion thin layer is left, and a space charge region formed by the ion thin layer is called a PN junction. The direction of the internal electric field of the PN junction points to the P well region from the N well region. The PN junction presents low resistance when the forward voltage is added, and has larger forward diffusion current; the PN junction exhibits high resistance when a reverse voltage is applied, and has a small reverse drift current, i.e., the PN junction has unidirectional conductivity.
In some embodiments, the method further comprises: heavily doping a portion of the first well region 43 with ions of the first conductivity type from the surface of the first well region 43 to form a first heavily doped region 432 to serve as a first extraction electrode; and heavily doping a portion of the second well region 44 with ions of the second conductivity type from the surface of the second well region 44 to form a second heavily doped region 442 to serve as a second extraction electrode. Specifically, the first heavily doped region 432 is located in the first region 401 after ion implantation, and the surface of the first heavily doped region 431 is substantially flush with the surface of the isolation structure 49, the doping type of the first heavily doped region 432 is the same as the doping type of the first region 401 (the conductivity type of the implanted ions), and the doping concentration of the first heavily doped region 432 is greater than the doping concentration of the first region 401, so as to be used as the extraction electrode of the first well region 43. The second heavily doped region 442 is located in the second region 402, and the surface of the second heavily doped region 442 is substantially flush with the surface of the isolation structure 49, the doping type of the second heavily doped region 442 is the same as the doping type (the conductivity type of the implanted ions) of the second region 402, and the doping concentration of the second heavily doped region 442 is greater than the doping concentration of the second region 402, so as to be used as an extraction electrode of the second well region 44. The parameters of heavy doping can be adjusted according to the parameters of the extraction electrode and the process conditions, and are not particularly limited herein.
Based on the same inventive concept, an embodiment of the present application further provides a semiconductor structure having a PN junction, where the ion implantation concentration of the PN junction is low, the reverse withstand voltage of the PN junction can be effectively improved, and the occupied area of the PN junction is not increased; meanwhile, the ion implantation concentration of other areas of the well region is normal, and the electrical change of other devices is avoided.
Fig. 10 is a schematic cross-sectional view of a semiconductor structure with a PN junction according to an embodiment of the application. The semiconductor structure with a PN junction according to the present embodiment includes: a semiconductor substrate 40, a first well region 43 having a first conductivity type, a second well region 44 having a second conductivity type, and a PN junction 45.
Specifically, the semiconductor substrate has a first region 401 and a second region 402 separated by a plurality of isolation structures 49. The first well region 43 includes the first region 401 after ion implantation and a third region 431, the third region 431 is located on a side of the isolation structure 49 away from the surface of the semiconductor substrate 40 and is adjacent to the first region 401, and the ion implantation concentration of the third region 431 is smaller than that of the first region 401. The second well region 44 includes the second region 402 and a fourth region 441 after ion implantation; the fourth region 441 is located on a side of the isolation structure 49 away from the surface of the semiconductor substrate 40 and adjacent to the second region 402, and the fourth region 441 has a lower ion implantation concentration than the second region 402. The PN junction 45 is formed at both side regions of the contact surface 450 where the fourth region 441 contacts the third region 431. Wherein the first conductivity type is opposite to the second conductivity type. With specific reference to the description of the method for fabricating the semiconductor structure with the PN junction shown in fig. 4 to 10, the description thereof will not be repeated here.
In the present embodiment, the ion implantation concentration of the third region 431 gradually decreases in a direction away from the first region 401. In some embodiments, the ion implantation concentration of the fourth region 441 decreases gradually in a direction away from the second region 402.
In this embodiment, the semiconductor structure with a PN junction further includes: a first heavily doped region 432 of a first conductivity type and a second heavily doped region 442 of a second conductivity type. The first heavily doped region 432 is located in the first region 401 after ion implantation, and the surface of the first heavily doped region 431 is substantially flush with the surface of the isolation structure 49, the doping type of the first heavily doped region 432 is the same as the doping type of the first region 401 (the conductivity type of the implanted ions), and the doping concentration of the first heavily doped region 432 is greater than the doping concentration of the first region 401, so as to serve as the first extraction electrode of the first well region 43. The second heavily doped region 442 is located in the second region 402, and the surface of the second heavily doped region 442 is substantially flush with the surface of the isolation structure 49, the doping type of the second heavily doped region 442 is the same as the doping type (the conductivity type of the implanted ions) of the second region 402, and the doping concentration of the second heavily doped region 442 is greater than the doping concentration of the second region 402, so as to be used as the second extraction electrode of the second well region 44. The parameters of heavy doping can be adjusted according to the parameters of the extraction electrode and the process conditions, and are not particularly limited herein.
In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the first conductivity type may also be P-type and the second conductivity type N-type.
It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Generally, the terms may be understood, at least in part, from the usage in the context. For example, the term "one or more" as used herein, depending at least in part on the context, may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a feature, structure, or combination of features in a plural sense. Similarly, terms such as "a," "an," or "the" may also be construed to express singular usage or plural usage depending at least in part on the context. In addition, the term "based on" may be understood as not necessarily intended to express a set of exclusive factors, but may instead, depending at least in part on the context, allow for other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected/coupled" means not only that one component is directly coupled to another component, but also that one component is indirectly coupled to another component through intervening components.
It should be noted that the terms "comprising" and "having" and their variants are referred to in the document of the present application and are intended to cover non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. In addition, the embodiments of the present application and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present application. In the foregoing embodiments, each embodiment is mainly described for differences from other embodiments, and the same/similar parts between the embodiments are referred to each other.
The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.

Claims (12)

1. The preparation method of the semiconductor structure with the PN junction is characterized by comprising the following steps of:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first region and a second region which are separated by a plurality of isolation structures, and the surfaces of all the isolation structures are basically flush with the surface of the semiconductor substrate; forming a first photoresist layer on the surface of the semiconductor substrate, wherein the first photoresist layer is provided with a first opening, the first opening exposes the first region, the first photoresist layer is provided with a first auxiliary photoresist layer positioned at the edge of the first opening and a first main photoresist layer adjacent to the first auxiliary photoresist layer, and the thickness of the first auxiliary photoresist layer is smaller than that of the first main photoresist layer;
performing first conductivity type ion implantation on the semiconductor substrate by using the first photoresist layer as a mask to form a first well region and removing the first photoresist layer, wherein the first well region comprises the first region and a third region after ion implantation, the third region is positioned at one side of the isolation structure far away from the surface of the semiconductor substrate and is adjacent to the first region, and the ion implantation concentration of the third region is smaller than that of the first region;
forming a second photoresist layer on the surface of the semiconductor substrate, wherein the second photoresist layer is provided with a second opening, the second opening exposes the second region, the second photoresist layer is provided with a second auxiliary photoresist layer positioned at the edge of the second opening and a second main photoresist layer adjacent to the second auxiliary photoresist layer, and the thickness of the second auxiliary photoresist layer is smaller than that of the second main photoresist layer;
and performing second conductivity type ion implantation on the semiconductor substrate by using the second photoresist layer as a mask to form a second well region and removing the second photoresist layer, wherein the second well region comprises a second region and a fourth region after ion implantation, the fourth region is positioned at one side of the isolation structure far away from the surface of the semiconductor substrate and is adjacent to the second region, the ion implantation concentration of the fourth region is smaller than that of the second region, the fourth region is contacted with the third region, so that PN junctions are formed at two side regions of a contact surface, and the first conductivity type is opposite to the second conductivity type.
2. The method of claim 1, wherein the step of forming a first photoresist layer on the semiconductor substrate further comprises:
forming a first photoresist layer on the semiconductor substrate;
forming a pattern of the first opening on the first photoresist layer through a photolithography process;
and developing the first photoresist material layer to form the first photoresist layer.
3. The method of claim 1, wherein a bottom of the first opening is the semiconductor substrate, and opposite sides of the first opening are the first photoresist layer and extend away from the semiconductor substrate at an acute included angle to a surface of the semiconductor substrate;
the shape of the second opening is substantially the same as the shape of the first opening.
4. The method of claim 1, wherein the first opening and the second opening are each inverted trapezoidal in cross-section in a direction perpendicular to a surface of the semiconductor substrate.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the thickness of the first auxiliary photoresist layer gradually decreases along the direction away from the first main photoresist layer, so that the ion implantation concentration of the third region gradually decreases along the direction away from the first region;
the thickness of the second auxiliary photoresist layer gradually decreases in a direction away from the second main photoresist layer, so that the ion implantation concentration of the fourth region gradually decreases in a direction away from the second region.
6. The method according to claim 1, wherein the method further comprises:
heavily doping part of the first well region with first conductive type ions from the surface of the first well region to form a first heavily doped region to serve as a first extraction electrode;
and carrying out second conductive type ion heavy doping on part of the second well region from the surface of the second well region so as to form a second heavy doped region to serve as a second extraction electrode.
7. The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
8. The method of claim 1, wherein the material of the semiconductor substrate is any one of silicon, silicon carbide, or silicon nitride.
9. A semiconductor structure having a PN junction, comprising:
a semiconductor substrate having a first region and a second region separated by a plurality of isolation structures therein;
a first well region having a first conductivity type, the first well region including the first region after ion implantation and a third region located at a side of the isolation structure away from the surface of the semiconductor substrate and adjacent to the first region, the third region having a concentration of ion implantation less than a concentration of ion implantation of the first region;
a second well region having a second conductivity type, the second well region including the second region after ion implantation and a fourth region located on a side of the isolation structure away from the surface of the semiconductor substrate and adjacent to the second region, the fourth region having a lower ion implantation concentration than the second region, the first conductivity type being opposite to the second conductivity type;
PN junction formed on two side areas of contact surface between the fourth region and the third region.
10. The semiconductor structure with a PN junction of claim 9, wherein an ion implantation concentration of said third region gradually decreases in a direction away from said first region;
the ion implantation concentration of the fourth region gradually decreases in a direction away from the second region.
11. The semiconductor structure with a PN junction of claim 9, further comprising:
a first heavily doped region of a first conductivity type, the first heavily doped region being located in the first region with a surface of the first heavily doped region substantially flush with a surface of the isolation structure to serve as a first extraction electrode;
and a second heavily doped region of a second conductivity type, the second heavily doped region being located in the second region and having a surface substantially flush with a surface of the isolation structure to serve as a second extraction electrode.
12. The semiconductor structure of claim 9, wherein the first conductivity type is N-type and the second conductivity type is P-type.
CN202310756018.3A 2023-06-25 2023-06-25 Semiconductor structure with PN junction and preparation method thereof Pending CN116759302A (en)

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