CN116757146B - Distributed random walk parasitic capacitance extraction method, device, equipment and medium - Google Patents
Distributed random walk parasitic capacitance extraction method, device, equipment and medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5083—Techniques for rebalancing the load in a distributed system
Abstract
The application relates to a method, a device, equipment and a medium for extracting a distributed random walk parasitic capacitance, wherein the method comprises the following steps: cutting the target full-circuit layout to obtain a plurality of square areas with equal size, and obtaining RWCAP calculation subtasks of parasitic capacitance extraction corresponding to each square area; inputting RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine to obtain parasitic capacitance independent results corresponding to each RWCAP calculation subtask; and merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask based on a preset capacitance value merging rule to obtain a final parasitic capacitance result of the whole circuit layout. Therefore, the problems that the storage space, CPU time and other computing resources are excessively consumed and the like when the traditional RWCAP parasitic capacitance extraction technology extracts a large-scale layout and parasitic capacitance containing a large number of conductors are solved.
Description
Technical Field
The application relates to the technical field of parasitic parameter extraction and simulation analysis, in particular to a method, a device, equipment and a medium for extracting parasitic capacitance of distributed random walk.
Background
In the integrated circuit design and verification stage, a computer numerical program is required to simulate the actual operation of the designed circuit to verify whether the circuit design correctly realizes the expected function and achieves the expected electrical performance, and meanwhile, the original design of the integrated circuit is correspondingly adjusted according to the simulation result to exclude errors or optimize the performance, and the numerical simulation is called integrated circuit simulation.
Integrated circuit simulation is divided into two types, front simulation and back simulation. The pre-simulation only simulates the running logic of the circuit to check whether the logic function of the circuit is correct or not; and then the simulation needs to synthesize the semiconductor manufacturing process to construct the physical configuration of the integrated circuit, extract the parasitic parameters (parasitic capacitance and parasitic resistance) in the physical configuration, and further simulate the running waveform of the circuit by using the parasitic parameter netlist so as to analyze the delay characteristics, the electrical characteristics and the like of the circuit.
At present, the following three methods are mainly used for extracting the parasitic capacitance of the circuit:
(1) A method for directly solving an electrostatic field equation for the physical configuration of an integrated circuit to calculate parasitic capacitance. The method comprises the following steps of: FDM (Finite DifferenceMethod, spatial finite difference method), BEM (Boundary Element Method ), FEM (Finite Element Method, finite element method), and the like. The algorithm can realize parasitic capacitance calculation with any precision, but the calculation resources consumed by the calculation are very high, and the resource consumption can be rapidly increased along with the improvement of the calculation scale or the precision;
(2) Extraction method based on circuit layout pattern matching. The method comprises the steps of firstly splitting a circuit design into a series of basic physical configurations with smaller scale, and calculating parasitic capacitance of the basic configurations by using the method to form a mode capacitance library; and then, applying a pattern matching method to the circuit layout, searching basic configuration with similar structures, and applying parasitic capacitance results in a pattern capacitance library. The method has the highest calculation performance, can be directly used for extracting the full-version parasitic capacitance of the large-scale integrated circuit, but has relatively low calculation precision;
(3) A random walk capacitance extraction method. The method is based on a random walk algorithm, is one of Monte Carlo random algorithms, and estimates the electrostatic capacitance value between conductors by releasing and counting the space random jump route between conductor blocks in a circuit. The method can realize moderate resolving performance (the resolving performance is higher than that of the method (1) but lower than that of the method (2)), and can realize the calculating precision close to that of the method (1). Thus, the method can be applied to the direct extraction of the parasitic capacitance of a medium-scale circuit or the rapid construction of the mode capacitor bank required by the method (2).
At present, a domestic leading parasitic parameter extraction tool Supercap relies on a leading random walking full three-dimensional parasitic capacitance extraction algorithm in the industry, wherein the Supercap mainly comprises the following components:
1. DFM (Design For Manufacturing, manufacturability design) physical process modeling engine to precisely construct the true three-dimensional physical configuration (metal wire, device, dielectric layer) of an integrated circuit;
2. RWCAP full three-dimensional capacitance solving engine is used for solving parasitic capacitance with high performance and high precision on three-dimensional configuration of integrated circuit.
At present, the RWCAP advanced calculation engine can achieve the calculation precision similar to that of an electrostatic field equation solver based on a random walk capacitance extraction method, and consumes relatively low calculation resources.
However, for large layouts and parasitic capacitance extraction including a large number of conductors, the RWCAP parasitic capacitance extraction technology still consumes a large amount of computation resources, including occupying a large amount of storage (building geometric data structures for the large layout and the large number of conductors) and consuming a large amount of CPU (Central Processing Unit ) time (running accuracy converges on the large number of conductors), which is to be solved.
Disclosure of Invention
The application provides a method, a device, equipment and a medium for extracting parasitic capacitance of distributed random walk, which are used for solving the problems that the computing resources such as storage space, CPU time and the like are excessively consumed when the parasitic capacitance of a large-scale layout and a large number of conductors are extracted by the existing RWCAP parasitic capacitance extraction technology.
An embodiment of a first aspect of the present application provides a method for extracting X from a distributed random walk parasitic capacitance, including the steps of: cutting the target full-circuit layout to obtain a plurality of square areas with equal size, and obtaining RWCAP calculation subtasks of parasitic capacitance extraction corresponding to each square area; inputting the RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine to obtain independent parasitic capacitance results corresponding to each RWCAP calculation subtask; and merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask based on a preset capacitance value merging rule to obtain a final parasitic capacitance result of the whole circuit layout.
Optionally, in an embodiment of the present application, the cutting the target full circuit layout to obtain a plurality of square areas with equal sizes includes: and obtaining the slicing window, the slicing window expansion size and the expansion window corresponding to each square area.
Optionally, in an embodiment of the present application, the RWCAP calculation subtask for obtaining parasitic capacitance extraction corresponding to each square area includes: acquiring a first calculation region and a second calculation region corresponding to each square region; determining a three-dimensional calculation space range of the RWCAP calculation subtask corresponding to each square region according to the first calculation region and the second calculation region; generating the RWCAP computation subtasks corresponding to each square area based on all flat layer media of each three-dimensional computation space range, conductor blocks in each square area, environment conductor blocks and medium blocks with intersections of extension windows corresponding to each square area.
Optionally, in an embodiment of the present application, inputting the RWCAP computation subtasks corresponding to each square area to a preset RWCAP computation engine to obtain independent parasitic capacitance results corresponding to each RWCAP computation subtask includes: calculating the RWCAP calculation subtasks corresponding to each square area by using the preset RWCAP calculation engine to obtain capacitance values of each wire mesh pair corresponding to each RWCAP calculation subtask, first capacitance standard deviation values corresponding to the capacitance values of each wire mesh pair and coupling capacitance of each pair of conductor blocks; and obtaining independent parasitic capacitance results corresponding to each RWCAP calculation subtask according to each wire mesh pair capacitance value corresponding to each RWCAP calculation subtask, the first capacitance standard deviation value corresponding to each wire mesh pair capacitance value and each pair of conductor block coupling capacitances.
Optionally, in an embodiment of the present application, the merging, based on a preset capacitance value merging rule, the parasitic capacitance independent result corresponding to each RWCAP calculation subtask, to obtain a final parasitic capacitance result of the full circuit layout, includes: screening the coupling capacitance of each pair of conductor blocks based on the type of the initial conductor block of the coupling capacitance of each pair of conductor blocks in each parasitic capacitance independent result, and attributing the coupling capacitance of the conductor blocks meeting a first preset condition into a capacitance statistics total set; placing the capacitance value of each wire mesh pair and the corresponding first capacitance standard deviation value in the parasitic capacitance independent result into the capacitance statistics total set, and determining a second capacitance standard deviation value corresponding to the capacitance value of each wire mesh pair based on the occurrence times of the capacitance value of each wire mesh pair in the capacitance statistics total set; accumulating the capacitance value of the coupling capacitance of each pair of conductor blocks in the capacitance statistics total set to the total capacitance value of the wire mesh pair to which each pair of conductor blocks belongs; obtaining a final capacitance value of each wire net pair through a preset calculation strategy for all wire net pairs meeting a second preset condition; and accumulating the final capacitance value of each wire net pair to the lumped capacitance value of the corresponding wire net to obtain the lumped capacitance values of all the wire nets so as to obtain the final parasitic capacitance result.
An embodiment of a second aspect of the present application provides a distributed random walk parasitic capacitance extraction apparatus, including: the acquisition module is used for cutting the target full-circuit layout to obtain a plurality of square areas with equal size, and acquiring RWCAP calculation subtasks extracted from parasitic capacitance corresponding to each square area; the input module is used for inputting the RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine to obtain a parasitic capacitance independent result corresponding to each RWCAP calculation subtask; and the merging module is used for merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask based on a preset capacitance value merging rule to obtain a final parasitic capacitance result of the whole circuit layout.
Optionally, in one embodiment of the present application, the acquiring module includes: the expansion unit is used for acquiring the slicing window, the slicing window expansion size and the expansion window corresponding to each square area.
Optionally, in one embodiment of the present application, the acquiring module further includes: a first area determining unit, configured to obtain a first calculation area and a second calculation area corresponding to each square area; the second region determining unit is used for determining a three-dimensional calculation space range of the RWCAP calculation subtask corresponding to each square region according to the first calculation region and the second calculation region; the generating unit is used for generating the RWCAP computing subtasks corresponding to each square area based on all flat-layer media of each three-dimensional computing space range, the conductor blocks in each square area, the environment conductor blocks and the medium blocks, wherein the environment conductor blocks and the medium blocks have intersections of the expansion windows corresponding to each square area.
Optionally, in one embodiment of the present application, the input module includes: the resolving unit is used for resolving the RWCAP computing subtasks corresponding to each square area by utilizing the preset RWCAP computing engine so as to obtain a capacitance value of each wire net corresponding to each RWCAP computing subtask, a first capacitance standard deviation value corresponding to the capacitance value of each wire net and a coupling capacitance of each pair of conductor blocks; the first calculation unit is used for obtaining the parasitic capacitance independent result corresponding to each RWCAP calculation subtask according to the capacitance value of each wire mesh corresponding to each RWCAP calculation subtask, the first capacitance standard deviation value corresponding to the capacitance value of each wire mesh and the coupling capacitance of each pair of conductor blocks.
Optionally, in one embodiment of the present application, the combining module includes: the screening unit is used for screening the coupling capacitance of each pair of conductor blocks based on the type of the initial conductor block of the coupling capacitance of each pair of conductor blocks in each parasitic capacitance independent result, and attributing the coupling capacitance of the conductor blocks meeting the first preset condition into a capacitance statistics total set; the statistics unit is used for putting the capacitance value of each wire mesh pair and the corresponding first capacitance standard deviation value in each parasitic capacitance independent result into the capacitance statistics total set, and determining a second capacitance standard deviation value corresponding to the capacitance value of each wire mesh pair based on the occurrence times of the capacitance value of each wire mesh pair in the capacitance statistics total set; the first accumulation unit is used for accumulating the capacitance value of the coupling capacitance of each pair of conductor blocks in the capacitance statistics total set to the total value of the capacitance of the wire mesh pair to which each pair of conductor blocks belongs; the second calculation unit is used for obtaining the final capacitance value of each wire net pair through a preset calculation strategy for all wire net pairs meeting a second preset condition; and the second accumulation unit is used for accumulating the final capacitance value of each wire net pair to the lumped capacitance value of the corresponding wire net to obtain the lumped capacitance value of all the wire nets so as to obtain the final parasitic capacitance result.
An embodiment of a third aspect of the present application provides an electronic device, including: the system comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor executes the program to realize the distributed random walk parasitic capacitance extraction method as described in the embodiment.
A fourth aspect of the present application provides a computer readable storage medium storing a computer program which when executed by a processor implements the distributed random walk parasitic capacitance extraction method as above.
Thus, embodiments of the present application have the following beneficial effects:
according to the embodiment of the application, a plurality of square areas with equal size can be obtained by cutting the target full-circuit layout, and RWCAP calculation subtasks for extracting parasitic capacitance corresponding to each square area are obtained; inputting RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine to obtain parasitic capacitance independent results corresponding to each RWCAP calculation subtask; and merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask based on a preset capacitance value merging rule to obtain a final parasitic capacitance result of the whole circuit layout. According to the application, the distributed multi-machine is used for jointly solving a random walk parasitic capacitance extraction task, so that the consumption of storage space, CPU time and other computing resources is reduced, the application range of the RWCAP random walk engine can be effectively expanded to a large circuit layout, and even the whole layout parasitic capacitance extraction can be realized. Therefore, the problems that the storage space, CPU time and other computing resources are excessively consumed and the like when the traditional RWCAP parasitic capacitance extraction technology extracts a large-scale layout and parasitic capacitance containing a large number of conductors are solved.
Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
fig. 1 is a flowchart of a method for extracting parasitic capacitance of distributed random walk according to an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating a distributed RWCAP computation task cut provided in accordance with an embodiment of the present application;
FIG. 3 is a schematic diagram of a visual perspective view of RWCAP input geometry according to an embodiment of the present application;
FIG. 4 is an xz cross-sectional view of RWCAP input geometry, according to an embodiment of the present application;
fig. 5 is an exemplary diagram of a distributed random walk parasitic capacitance extraction apparatus according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
The system comprises a 10-distributed random walk parasitic capacitance extraction device, a 100-acquisition module, a 200-input module, a 300-merging module, a 601-memory, a 602-processor and 603-communication interfaces.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.
The following describes a method, a device, equipment and a medium for extracting a distributed random walk parasitic capacitance according to an embodiment of the present application with reference to the accompanying drawings. Aiming at the problems in the background art, the application provides a distributed random walk parasitic capacitance extraction method, in the method, a plurality of square areas with equal size are obtained by cutting a target full circuit layout, and RWCAP calculation subtasks for parasitic capacitance extraction corresponding to each square area are obtained; inputting RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine to obtain parasitic capacitance independent results corresponding to each RWCAP calculation subtask; and merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask based on a preset capacitance value merging rule to obtain a final parasitic capacitance result of the whole circuit layout. According to the application, the distributed multi-machine is used for jointly solving a random walk parasitic capacitance extraction task, so that the consumption of storage space, CPU time and other computing resources is reduced, the application range of the RWCAP random walk engine can be effectively expanded to a large circuit layout, and even the whole layout parasitic capacitance extraction can be realized. Therefore, the problems that the storage space, CPU time and other computing resources are excessively consumed and the like when the traditional RWCAP parasitic capacitance extraction technology extracts a large-scale layout and parasitic capacitance containing a large number of conductors are solved.
Specifically, fig. 1 is a flowchart of a method for extracting a distributed random walk parasitic capacitance according to an embodiment of the present application.
As shown in fig. 1, the method for extracting the parasitic capacitance of the distributed random walk comprises the following steps:
in step S101, a target full circuit layout is cut to obtain a plurality of square areas with equal dimensions, and RWCAP calculation subtasks for extracting parasitic capacitance corresponding to each square area are obtained.
According to the embodiment of the application, the whole layout can be cut into a plurality of square areas which are completely independent and have equal sizes in the plane (xy plane) of the circuit layout, each square area corresponds to one distributed RWCAP computing subtask, and the distributed RWCAP computing subtask does not cut in the z axis, namely each computing subtask has the original whole z axis space.
Optionally, in an embodiment of the present application, cutting the target full circuit layout to obtain a plurality of square areas with equal dimensions includes: and obtaining the slicing window, the slicing window expansion size and the expansion window corresponding to each square area.
Specifically, the rule of cutting the full layout according to the embodiment of the application is as follows:
1. each conductor block belongs to only one square area:
(1) When the conductor block completely falls into a certain square area, the conductor block belongs to a corresponding square area, as shown in fig. 2, conductor block 0 and conductor block 1 in fig. 2 belong to a left square area, and conductor block 2 belongs to a right square area;
(2) When the conductor block crosses a plurality of square area boundaries, the conductor block is cut through all the crossed square area boundaries, fragments formed after cutting become new conductor blocks (different numerical numbers are respectively allocated to count capacitance values) and belong to the square areas where the conductor block falls (if the conductor block 3 crosses the square area boundaries in fig. 2, the conductor block is cut into two new conductor blocks of the conductor block 3 and the conductor block 3' by the boundaries and belongs to left and right square areas);
2. each square area is expanded from four sides to a certain size, which is called a slice window expansion size, and as shown in fig. 2, the expanded range is called an expansion window: because the expansion size of the split window corresponds to the furthest distance for solving the capacitance, when the distance between two conductor blocks exceeds the expansion size of the split window, the embodiment of the application can ignore the coupling capacitance, so that for all the conductor blocks in a square area, the embodiment of the application only needs to give out all the conductor blocks in the expansion window of the square area for solving the capacitance.
As shown in fig. 2, the xy full space is divided into square regions of equal size (as indicated by gray dotted lines) based on the above-described cutting rule, wherein a dark solid line frame encloses a dicing window in which two square regions, each referred to as a corresponding square region, are enclosed.
Thus, embodiments of the present application provide reliable theoretical support for generating independent RWCAP computation subtasks for each square region by defining the conductor block home region for each and expanding outward for each square region.
Optionally, in one embodiment of the present application, the RWCAP calculation subtask for obtaining the parasitic capacitance extraction corresponding to each square area includes: acquiring a first calculation region and a second calculation region corresponding to each square region; determining a three-dimensional calculation space range of the RWCAP calculation subtask corresponding to each square region according to the first calculation region and the second calculation region; and generating RWCAP computation subtasks corresponding to each square area based on all flat-layer media of each three-dimensional computation space range, conductor blocks in each square area, environment conductor blocks with intersections of extended windows corresponding to each square area and the media blocks.
It should be noted that, the process of generating the independent RWCAP calculation subtask for each square area according to the embodiment of the present application is as follows:
1. taking the current square area as the center, taking the square array area with the periphery of 3 multiplied by 3, namely the first calculation area as an xy plane calculation area; taking the second calculation region, namely the original full z-axis space as a z-axis calculation region, so that the embodiment of the application can construct a three-dimensional calculation space range of the RWCAP calculation subtask according to the xy plane calculation region and the z-axis calculation region;
2. taking the 3 multiplied by 3 square area array calculation area as the geometric dimension, and outputting all flat layer media to the current RWCAP calculation subtask;
3. all the conductor blocks belonging to the current square area (the conductor blocks which are cut by the square area boundary and fall into the current square area) are taken as main conductor blocks of the current square area and output to the current calculation subtask; if the conductor blocks enter the segmentation window expansion size area of the current square area, namely when the conductor blocks are completely in the segmentation window expansion size area or overlap with the boundary of the expansion window, the conductor blocks can be used as environment conductor blocks of the current square area and output to the current calculation task;
4. All the medium blocks entering the expansion window of the current square area (completely entering the expansion window area or overlapping the boundary of the expansion window) are used as the medium blocks of the current square area and output to the current computing subtask.
Therefore, the embodiment of the application divides the layout space of the circuit into a plurality of mutually completely independent square areas, and generates an independent RWCAP calculation subtask for each square area, thereby providing basis for extracting the parasitic capacitance of the distributed RWCAP.
In step S102, the RWCAP computation subtasks corresponding to each square area are input to a preset RWCAP computation engine, and the parasitic capacitance independent result corresponding to each RWCAP computation subtask is obtained.
After the RWCAP calculation subtasks corresponding to each square area and extracted by the parasitic capacitance are obtained, further, the embodiment of the application can further utilize the RWCAP calculation engine to perform apportionment calculation on the calculation subtasks corresponding to each square area through a distributed multi-machine.
In an embodiment of the application, the input data of the RWCAP calculation engine is as follows:
1. calculating the three-dimensional space range of the task:
the three-dimensional space range can be expressed by a three-dimensional space cube (based on the maximum and minimum coordinates of the cube in the x, y and z axes, six coordinate values are taken together), and the three-dimensional space range envelopes all conductor geometries which appear in the calculation task, namely, the coordinates of no conductor geometry exceed the space range; among the three coordinate axes, the xy coordinate plane corresponds to the circuit layout plane, and the z axis corresponds to the longitudinal thickness direction of the circuit;
2. Flat layer medium:
the computing task can comprise a plurality of flat layer media, each flat layer medium needs to fill all computing space on an xy coordinate plane, each flat layer medium has a certain thickness on a z axis, but the flat layer media cannot overlap on the z axis, and all the flat layer media need to fill all the z axis space; the flat layer medium is a background medium in the calculation space, and when a certain position in the calculation space is not occupied by other geometric blocks, the dielectric constant of the position is determined by the flat layer medium;
3. conductor block:
the conductor blocks distributed in space are prismatic, which are described together by polygons in the xy plane and thickness in the z axis; based on the current requirements of RWCAP engines, the number of top points of the xy plane graph of the conductor blocks must not exceed four, i.e., the graph can be rectangular, triangular or trapezoid, and each conductor block has a unique digital number to identify parasitic capacitance results; each conductor block must belong to and only one wire mesh; meanwhile, each wire net can contain any number of conductor blocks, and is named by unique character string names, and parasitic capacitance results are counted by taking the wire net as a unit.
4. Medium block:
Each calculation task can comprise any number of dielectric blocks, and the geometric description of the dielectric blocks is completely consistent with that of the conductor blocks, namely, not more than four vertexes on an xy plane and a prism with fixed thickness on a z axis; when a spatial location is occupied by a dielectric block, the dielectric constant of the dielectric block will cover the dielectric constant of the background flat layer medium, and the dielectric block is not numbered or any other identification, nor is it organized as a wire mesh.
FIG. 3 is a schematic diagram of a visual oblique view structure of RWCAP input geometric data, as shown in FIG. 3, a dark opaque pattern is a conductor block, and a transparent pattern depicted by gray lines is a dielectric block (a conformal medium wrapping the conductor block); FIG. 4 is an xz cross-sectional view of RWCAP input geometry, with gray levels at different z-coordinate locations as shown in FIG. 4, i.e., a level medium (background medium).
Therefore, the embodiment of the application effectively ensures the smooth extraction of the parasitic capacitance of the large circuit layout by combining the input data with the RWCAP calculation engine.
Optionally, in an embodiment of the present application, inputting the RWCAP computation subtasks corresponding to each square area to a preset RWCAP computation engine to obtain the parasitic capacitance independent result corresponding to each RWCAP computation subtask includes: resolving RWCAP calculation subtasks corresponding to each square area by using a preset RWCAP calculation engine to obtain capacitance values of each wire mesh pair corresponding to each RWCAP calculation subtask, first capacitance standard deviation values corresponding to the capacitance values of each wire mesh pair and coupling capacitances of each pair of conductor blocks; and obtaining independent parasitic capacitance results corresponding to each RWCAP calculation subtask according to each wire mesh pair capacitance value corresponding to each RWCAP calculation subtask, the first capacitance standard deviation value corresponding to each wire mesh pair capacitance value and each pair of conductor block coupling capacitance.
It should be noted that, in the embodiment of the present application, after data such as a conductor block is input to the RWCAP calculation engine, the RWCAP engine may be operated by the RWCAP calculation subtasks corresponding to each square area, so as to calculate each RWCAP calculation subtask, thereby obtaining capacitance data corresponding to each calculation subtask.
The capacitance data output by the RWCAP calculation engine comprises:
1) Coupling capacitance between each pair of nets (directed pairs);
2) Standard deviation of coupling capacitance values (percentage relative to coupling capacitance values);
3) Coupling capacitance between each pair of conductor blocks (directed pair).
Furthermore, the embodiment of the application can obtain the independent result of the parasitic capacitance based on the capacitance output data such as the coupling capacitance between each pair of wires, the standard deviation of the coupling capacitance value, the coupling capacitance between each pair of conductor blocks and the like obtained by the RWCAP calculation subtasks corresponding to each square area, thereby providing reliable data basis for combining the calculation results of all calculation subtasks, realizing the parasitic capacitance extraction of a large-scale layout, effectively reducing the resource consumption of RWCAP calculation and improving the calculation efficiency.
In step S103, based on a preset capacitance value merging rule, merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask, and obtaining a final parasitic capacitance result of the full circuit layout.
In actual implementation, due to the existence of the tile window extended size region, coupling capacitance between the same pair of conductor blocks (directed pair) may occur in the results of multiple RWCAP computation sub-tasks (conductor blocks within the tile window extended size region are repeatedly allocated to multiple adjacent square regions).
Therefore, the embodiment of the application can combine the parasitic capacitance independent results of the RWCAP calculation subtasks corresponding to each square area based on the capacitance combining rule so as to correctly process the consistency problem of the capacitance, thereby obtaining the final capacitance result.
Optionally, in an embodiment of the present application, merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask based on a preset capacitance value merging rule to obtain a final parasitic capacitance result of the full circuit layout, including: screening the coupling capacitance of each pair of conductor blocks based on the type of the initial conductor block of the coupling capacitance of each pair of conductor blocks in each parasitic capacitance independent result, and attributing the coupling capacitance of the conductor blocks meeting the first preset condition into a capacitance statistics total set; placing the capacitance value of each wire mesh pair and the corresponding first capacitance standard deviation value in each parasitic capacitance independent result into a capacitance statistics total set, and determining a second capacitance standard deviation value corresponding to the capacitance value of each wire mesh pair based on the occurrence times of the capacitance value of each wire mesh pair in the capacitance statistics total set; accumulating the capacitance value of the coupling capacitance of each pair of conductor blocks in the capacitance statistics total set to the total capacitance value of the wire mesh pair to which each pair of conductor blocks belongs; obtaining a final capacitance value of each wire net pair through a preset calculation strategy for all wire net pairs meeting a second preset condition; and accumulating the final capacitance value of each wire mesh pair to the lumped capacitance value of the corresponding wire mesh to obtain the lumped capacitance values of all the wire meshes so as to obtain a final parasitic capacitance result.
It should be noted that, the capacitance value combination rule in the embodiment of the present application is as follows:
1. traversing the parasitic capacitance independent results of each RWCAP computation task and coupling capacitance for each pair of conductor blocks (directed pairs) in the resultsAnalysis was performed as follows:
(1) If the initial conductor block A of the coupling pair meets the first preset condition, namely when the initial conductor block A of the coupling pair is the main conductor block of the square area, the coupling capacitor is put into a total capacitance statistics set;
(2) If A is the environmental conductor block of the square area, the coupling capacitor is directly discarded.
Because each main conductor block belongs to only one square area, the coupling capacitance put into the final capacitance statistics total set does not have repeated items (the directional pair coupling capacitance appears more than once);
2. traversing the independent parasitic capacitance results of each RWCAP calculation task, and putting all the wire mesh pair (with relative) capacitance values and corresponding capacitance standard deviation values in the results into a final capacitance statistics total set; all net pairs (directed pairs) present in the final capacitance statistics aggregate are analyzed as follows:
(1) If the net pair capacitance value appears more than once (the directed net pair capacitance value can be calculated in RWCAP subtasks of a plurality of square areas), the net pair capacitance value is used as weight, the corresponding standard deviation value is calculated and weighted average is carried out, and the weighted average result is used as the standard deviation value of the net pair capacitance;
(2) If the capacitance value of the wire mesh appears only once, directly using the corresponding capacitance standard deviation value;
3. traversing all conductor block pair (directed pair) coupling capacitors in the final capacitance statistics total set, and accumulating the capacitance value of each conductor block pair (directed pair) coupling capacitor to the net pair (directed pair) capacitance total value of the conductor blocks of both sides;
4. for all wire mesh pairs (undirected pairs), if the second preset condition is met, that is, if the directional pair capacitance values of the two wire meshes in all wire mesh pairs exist in the positive and negative directions, taking the standard difference value of the capacitance in the two directions as a weight, and calculating according to a preset calculation strategy, that is, the following calculation formula, so as to obtain the final capacitance value of the wire mesh pair (undirected pair):
wherein, the liquid crystal display device comprises a liquid crystal display device,、/>respectively positive and negative bidirectional capacitance values, < >>、/>Respectively two-way capacitance standard deviation values (relative values); if the directional capacitance value in the positive and negative directions is only one, the final capacitance value of the net pair (undirected pair) is directly used;
5. and accumulating the capacitance values of all the wire net pairs (undirected pairs) to the lumped capacitance values of the belonged wire net, thereby obtaining the lumped capacitance values of all the wire nets.
Therefore, the embodiment of the application obtains the final parasitic capacitance result of the original calculation task (the whole circuit layout) by combining the parasitic capacitance independent results of the RWCAP calculation subtasks corresponding to all square areas, wherein the final parasitic capacitance result comprises the capacitance values of all wire mesh pairs (undirected pairs) and the lumped capacitance values of all wire meshes, thereby effectively combining the capacitance results of the distributed subtasks and realizing the parasitic capacitance extraction of the large-scale layout.
According to the distributed random walk parasitic capacitance extraction method provided by the embodiment of the application, a plurality of square areas with equal size are obtained by cutting a target full-circuit layout, and RWCAP calculation subtasks for parasitic capacitance extraction corresponding to each square area are obtained; inputting RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine to obtain parasitic capacitance independent results corresponding to each RWCAP calculation subtask; and merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask based on a preset capacitance value merging rule to obtain a final parasitic capacitance result of the whole circuit layout. According to the application, the distributed multi-machine is used for jointly solving a random walk parasitic capacitance extraction task, so that the consumption of storage space, CPU time and other computing resources is reduced, the application range of the RWCAP random walk engine can be effectively expanded to a large circuit layout, and even the whole layout parasitic capacitance extraction can be realized.
Next, a distributed random walk parasitic capacitance extraction apparatus according to an embodiment of the present application will be described with reference to the accompanying drawings.
Fig. 5 is a block diagram of a distributed random walk parasitic capacitance extraction device according to an embodiment of the present application.
As shown in fig. 5, the distributed random walk parasitic capacitance extraction device 10 includes: the device comprises an acquisition module 100, an input module 200 and a combination module 300.
The obtaining module 100 is configured to cut the target full circuit layout to obtain a plurality of square areas with equal sizes, and obtain RWCAP calculation subtasks for extracting parasitic capacitance corresponding to each square area.
And the input module 200 is configured to input the RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine, so as to obtain independent parasitic capacitance results corresponding to each RWCAP calculation subtask.
And the merging module 300 is used for merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask based on a preset capacitance value merging rule to obtain a final parasitic capacitance result of the whole circuit layout.
Optionally, in one embodiment of the present application, the acquiring module 100 includes: and an expansion unit.
The expansion unit is used for acquiring the slicing window, the slicing window expansion size and the expansion window corresponding to each square area.
Optionally, in one embodiment of the present application, the obtaining module 100 further includes: a first region determining unit, a second region determining unit and a generating unit.
The first area determining unit is used for acquiring a first calculation area and a second calculation area corresponding to each square area.
And the second region determining unit is used for determining the three-dimensional calculation space range of the RWCAP calculation subtask corresponding to each square region according to the first calculation region and the second calculation region.
The generating unit is used for generating RWCAP computation subtasks corresponding to each square area based on all flat layer media of each three-dimensional computation space range, conductor blocks in each square area, environment conductor blocks with intersections of extension windows corresponding to each square area and medium blocks.
Optionally, in one embodiment of the present application, the input module 200 includes: a resolving unit and a first computing unit.
The resolving unit is used for resolving the RWCAP computing subtasks corresponding to each square area by utilizing a preset RWCAP computing engine so as to obtain the capacitance value of each wire mesh corresponding to each RWCAP computing subtask, the first capacitance standard deviation value corresponding to each wire mesh capacitance value and the coupling capacitance of each pair of conductor blocks.
The first calculation unit is used for obtaining the parasitic capacitance independent result corresponding to each RWCAP calculation subtask according to the capacitance value of each wire mesh corresponding to each RWCAP calculation subtask, the first capacitance standard deviation value corresponding to the capacitance value of each wire mesh and the coupling capacitance of each pair of conductor blocks.
Optionally, in one embodiment of the present application, the merging module 300 includes: the device comprises a screening unit, a statistics unit, a first accumulation unit, a second calculation unit and a second accumulation unit.
The screening unit is used for screening the coupling capacitance of each pair of conductor blocks based on the type of the initial conductor block of the coupling capacitance of each pair of conductor blocks in each parasitic capacitance independent result, and attributing the coupling capacitance of the conductor blocks meeting the first preset condition into the capacitance statistics total set.
And the statistics unit is used for putting the capacitance value of each wire mesh pair and the corresponding first capacitance standard deviation value in each parasitic capacitance independent result into a capacitance statistics total set, and determining the corresponding second capacitance standard deviation value of each wire mesh pair capacitance value based on the occurrence times of the capacitance value of each wire mesh pair in the capacitance statistics total set.
And the first accumulation unit is used for accumulating the capacitance value of the coupling capacitance of each pair of conductor blocks in the capacitance statistics total set to the total value of the pair of wire mesh capacitance of each pair of conductor blocks.
And the second calculation unit is used for obtaining the final capacitance value of each wire net pair through a preset calculation strategy for all wire net pairs meeting a second preset condition.
And the second accumulation unit is used for accumulating the final capacitance value of each wire net pair to the lumped capacitance value of the corresponding wire net to obtain the lumped capacitance value of all the wire nets so as to obtain a final parasitic capacitance result.
It should be noted that the foregoing explanation of the embodiment of the method for extracting the distributed random walk parasitic capacitance is also applicable to the device for extracting the distributed random walk parasitic capacitance of the embodiment, and will not be repeated here.
The device for extracting the parasitic capacitance of the distributed random walk provided by the embodiment of the application comprises the following components: the acquisition module is used for cutting the target full-circuit layout to obtain a plurality of square areas with equal size, and acquiring RWCAP calculation subtasks extracted from parasitic capacitance corresponding to each square area; the input module is used for inputting the RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine to obtain independent parasitic capacitance results corresponding to each RWCAP calculation subtask; and the merging module is used for merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask based on a preset capacitance value merging rule to obtain a final parasitic capacitance result of the whole circuit layout. According to the application, the distributed multi-machine is used for jointly solving a random walk parasitic capacitance extraction task, so that the consumption of storage space, CPU time and other computing resources is reduced, the application range of the RWCAP random walk engine can be effectively expanded to a large circuit layout, and even the whole layout parasitic capacitance extraction can be realized.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device may include:
a memory 601, a processor 602, and a computer program stored on the memory 601 and executable on the processor 602.
The processor 602 implements the distributed random walk parasitic capacitance extraction method provided in the above embodiment when executing a program.
Further, the electronic device further includes:
a communication interface 603 for communication between the memory 601 and the processor 602.
A memory 601 for storing a computer program executable on the processor 602.
The memory 601 may comprise a high-speed RAM memory or may further comprise a non-volatile memory (non-volatile memory), such as at least one disk memory.
If the memory 601, the processor 602, and the communication interface 603 are implemented independently, the communication interface 603, the memory 601, and the processor 602 may be connected to each other through a bus and perform communication with each other. The bus may be an industry standard architecture (Industry Standard Architecture, abbreviated ISA) bus, an external device interconnect (Peripheral Component, abbreviated PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, abbreviated EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in fig. 6, but not only one bus or one type of bus.
Alternatively, in a specific implementation, if the memory 601, the processor 602, and the communication interface 603 are integrated on a chip, the memory 601, the processor 602, and the communication interface 603 may perform communication with each other through internal interfaces.
The processor 602 may be a central processing unit (Central Processing Unit, abbreviated as CPU) or an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC) or one or more integrated circuits configured to implement embodiments of the present application.
The embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the distributed random walk parasitic capacitance extraction method as above.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, "N" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order from that shown or discussed, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or N wires, a portable computer cartridge (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the N steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like. While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (6)
1. The method for extracting the parasitic capacitance of the distributed random walk is characterized by comprising the following steps of:
cutting the target full-circuit layout to obtain a plurality of square areas with equal size, and obtaining RWCAP calculation subtasks of parasitic capacitance extraction corresponding to each square area; cutting the target full-circuit layout to obtain a plurality of square areas with equal sizes, wherein the method comprises the following steps: obtaining a slicing window and a slicing window expansion size corresponding to each square area, and obtaining an expansion window of each square area based on the slicing window and the slicing window expansion size;
inputting the RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine to obtain independent parasitic capacitance results corresponding to each RWCAP calculation subtask; and
Based on a preset capacitance value merging rule, merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask to obtain a final parasitic capacitance result of the whole circuit layout;
inputting the RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine to obtain parasitic capacitance independent results corresponding to each RWCAP calculation subtask, including:
calculating the RWCAP calculation subtasks corresponding to each square area by using the preset RWCAP calculation engine to obtain capacitance values of each wire mesh pair corresponding to each RWCAP calculation subtask, first capacitance standard deviation values corresponding to the capacitance values of each wire mesh pair and coupling capacitance of each pair of conductor blocks;
obtaining independent parasitic capacitance results corresponding to each RWCAP calculation subtask according to each wire mesh pair capacitance value corresponding to each RWCAP calculation subtask, a first capacitance standard deviation value corresponding to each wire mesh pair capacitance value and each pair of conductor block coupling capacitances;
and combining the parasitic capacitance independent results corresponding to each RWCAP calculation subtask based on a preset capacitance value combining rule to obtain a final parasitic capacitance result of the whole circuit layout, wherein the method comprises the following steps:
Screening the coupling capacitance of each pair of conductor blocks based on the type of the initial conductor block of the coupling capacitance of each pair of conductor blocks in each parasitic capacitance independent result, and attributing the coupling capacitance of the conductor blocks meeting a first preset condition into a capacitance statistics total set;
placing the capacitance value of each wire mesh pair and the corresponding first capacitance standard deviation value in the parasitic capacitance independent result into the capacitance statistics total set, and determining a second capacitance standard deviation value corresponding to the capacitance value of each wire mesh pair based on the occurrence times of the capacitance value of each wire mesh pair in the capacitance statistics total set;
accumulating the capacitance values of the coupling capacitances of each pair of conductor blocks in the capacitance statistics total set to the total capacitance value of the wire mesh pair to which each pair of conductor blocks belongs, so as to obtain the lumped capacitance value of the corresponding wire mesh;
based on all wire net pairs meeting a second preset condition and the second capacitance standard deviation value, calculating a final capacitance value of each wire net pair according to a preset calculation strategy;
and accumulating the final capacitance value of each wire net pair to the lumped capacitance value of the corresponding wire net to obtain the lumped capacitance values of all the wire nets so as to obtain the final parasitic capacitance result.
2. The method for extracting parasitic capacitance of distributed random walk according to claim 1, wherein the RWCAP calculation subtask for obtaining the parasitic capacitance extraction corresponding to each square region comprises:
acquiring a first calculation region and a second calculation region corresponding to each square region;
determining a three-dimensional calculation space range of the RWCAP calculation subtask corresponding to each square region according to the first calculation region and the second calculation region;
generating the RWCAP computation subtasks corresponding to each square area based on all flat layer media of each three-dimensional computation space range, conductor blocks in each square area, environment conductor blocks and medium blocks with intersections of extension windows corresponding to each square area.
3. The utility model provides a distributing type random walk parasitic capacitance extraction element which characterized in that includes:
the acquisition module is used for cutting the target full-circuit layout to obtain a plurality of square areas with equal size, and acquiring RWCAP calculation subtasks extracted from parasitic capacitance corresponding to each square area; cutting the target full-circuit layout to obtain a plurality of square areas with equal sizes, wherein the method comprises the following steps: obtaining a slicing window and a slicing window expansion size corresponding to each square area, and obtaining an expansion window of each square area based on the slicing window and the slicing window expansion size;
The input module is used for inputting the RWCAP calculation subtasks corresponding to each square area to a preset RWCAP calculation engine to obtain a parasitic capacitance independent result corresponding to each RWCAP calculation subtask; and
the merging module is used for merging the independent parasitic capacitance results corresponding to each RWCAP calculation subtask based on a preset capacitance value merging rule to obtain a final parasitic capacitance result of the whole circuit layout;
wherein the input module comprises:
the resolving unit is used for resolving the RWCAP computing subtasks corresponding to each square area by utilizing the preset RWCAP computing engine so as to obtain a capacitance value of each wire net corresponding to each RWCAP computing subtask, a first capacitance standard deviation value corresponding to the capacitance value of each wire net and a coupling capacitance of each pair of conductor blocks;
the first calculation unit is used for obtaining a parasitic capacitance independent result corresponding to each RWCAP calculation subtask according to each wire mesh pair capacitance value corresponding to each RWCAP calculation subtask, a first capacitance standard deviation value corresponding to each wire mesh pair capacitance value and each pair of conductor block coupling capacitances;
the merging module comprises:
The screening unit is used for screening the coupling capacitance of each pair of conductor blocks based on the type of the initial conductor block of the coupling capacitance of each pair of conductor blocks in each parasitic capacitance independent result, and attributing the coupling capacitance of the conductor blocks meeting the first preset condition into a capacitance statistics total set;
the statistics unit is used for putting the capacitance value of each wire mesh pair and the corresponding first capacitance standard deviation value in each parasitic capacitance independent result into the capacitance statistics total set, and determining a second capacitance standard deviation value corresponding to the capacitance value of each wire mesh pair based on the occurrence times of the capacitance value of each wire mesh pair in the capacitance statistics total set;
the first accumulation unit is used for accumulating the capacitance value of the coupling capacitance of each pair of conductor blocks in the capacitance statistics total set to the total capacitance value of the wire mesh pair to which each pair of conductor blocks belongs, so as to obtain the lumped capacitance value of the corresponding wire mesh;
the second calculation unit is used for calculating the final capacitance value of each wire mesh pair according to a preset calculation strategy based on all wire mesh pairs meeting a second preset condition and the second capacitance standard deviation value;
and the second accumulation unit is used for accumulating the final capacitance value of each wire net pair to the lumped capacitance value of the corresponding wire net to obtain the lumped capacitance values of all the wire nets so as to obtain the final parasitic capacitance result.
4. The distributed random walk parasitic capacitance extraction device of claim 3, wherein the acquisition module further comprises:
a first area determining unit, configured to obtain a first calculation area and a second calculation area corresponding to each square area;
the second region determining unit is used for determining a three-dimensional calculation space range of the RWCAP calculation subtask corresponding to each square region according to the first calculation region and the second calculation region;
the generating unit is used for generating the RWCAP computing subtasks corresponding to each square area based on all flat-layer media of each three-dimensional computing space range, the conductor blocks in each square area, the environment conductor blocks and the medium blocks, wherein the environment conductor blocks and the medium blocks have intersections of the expansion windows corresponding to each square area.
5. An electronic device, comprising: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor executing the program to implement the distributed random walk parasitic capacitance extraction method of any of claims 1-2.
6. A computer readable storage medium having stored thereon a computer program, characterized in that the program is executed by a processor for implementing the distributed random walk parasitic capacitance extraction method according to any of claims 1-2.
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|---|
| 重叠组合法的芯片级三维寄生电容提取及其并行实现;尹航;喻文健;陆涛涛;王泽毅;;计算机辅助设计与图形学学报(02);第238-243页 * |
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