CN116755537A - Server power supply circuit and method - Google Patents

Abstract

The application discloses a server power supply circuit and a method, comprising the following steps: the power supply module is connected with the voltage regulation module, and the voltage regulation module is respectively connected with the kernel power supply and the auxiliary power supply; the power supply module is used for transmitting the power supply voltage to the voltage regulation module under the condition of receiving a power-on instruction of the server; the voltage regulating module is used for regulating the power supply voltage to obtain a first voltage and a second voltage, wherein the first voltage is used for supplying power to the kernel power supply, and the second voltage is used for supplying power to the auxiliary power supply; the kernel power supply is used for supplying power to the server kernel according to the first voltage; and the auxiliary power supply is used for supplying power to the server according to the second voltage. According to the application, the power supply voltage is used as the input of the voltage regulating module, and the voltage regulating module is used for regulating the power supply voltage, so that the voltages of the core power supply and the auxiliary power supply are controlled, and the power-on and power-off control of the core power supply and the auxiliary power supply is realized.

Description

Server power supply circuit and method

Technical Field

The application relates to the field of server power supply, in particular to a server power supply circuit and a method.

Background

In the existing server power supply architecture, the power supply unit provides two groups of outputs of P12V_PSU and 12V_PSU_STBY, wherein the 12V_PSU_STBY is used as the power supply input of an auxiliary power supply of the server, and in a DC shutdown state, the power supply requirements of components such as a baseboard management controller and a programmable logic device are limited by the power supply limitation of the power supply unit, and the current which can be provided by the power supply unit is smaller, so that the power supply input of the auxiliary power supply is immediately switched to the P12V_PSU after the system is started. The P12V_PSU is used as the core power supply output of the power supply unit, and is used as the power supply input of the server core power supply and the auxiliary power supply at the same time after the power is started, so that the power supply requirements of all components such as a CPU, a memory and the like and a board card in the starting state are met.

At present, in the current power supply architecture, the baseboard management controller can perform power-on and power-off control by controlling the power-on and power-off operation of the kernel power supply and the input switching of the auxiliary power supply, namely, DC power-on and power-off control is performed, and the auxiliary power supply of the power supply source of the baseboard management controller is kept stable in the power-on and power-off process, so that the power-on and power-off process of DC is completely controlled; however, the baseboard management controller cannot control the power-on and power-off of the auxiliary power supply through instructions, and when the baseboard management controller loses power supply, the auxiliary power supply can only recover power supply and power-off of the baseboard management controller by manually powering on and powering off the power supply unit. In this way, the power-on and power-off is performed manually, which results in inefficiency in the power-on and power-off process.

Disclosure of Invention

In view of the above, the embodiment of the application provides a server power supply circuit to solve the problem of low efficiency in the power up and power down process caused by a manual power up and power down mode.

In a first aspect, an embodiment of the present application provides a server power supply circuit, including: the power supply module is connected with the voltage regulation module, and the voltage regulation module is respectively connected with the core power supply and the auxiliary power supply;

the power supply module is used for transmitting power supply voltage to the voltage regulation module under the condition of receiving a power-on instruction of the server;

the voltage regulating module is used for regulating the power supply voltage to obtain a first voltage and a second voltage, wherein the first voltage is used for supplying power to the kernel power supply, and the second voltage is used for supplying power to the auxiliary power supply;

the kernel power supply is used for supplying power to the server kernel according to the first voltage;

and the auxiliary power supply is used for supplying power to the server according to the second voltage.

Further, the server power supply circuit further includes: the input end of the reset module is connected with the power supply module, and the output end of the reset module is connected with the voltage regulating module;

and the reset module is used for resetting the kernel power supply and the auxiliary power supply when the server runs.

Further, the reset module includes: the power supply device comprises a power supply module, a first buffer and a reset chip, wherein a first input end of the first buffer is connected with the power supply module, a second input end of the first buffer is connected with the reset chip, and an output end of the first buffer is connected with the voltage regulating module.

Further, a first input end of the first buffer receives the power supply voltage, a second input end of the first buffer receives a first high-level signal transmitted by the reset chip, the first buffer is in a conducting state, and an output end of the first buffer outputs a second high-level signal based on the first high-level signal and the power supply voltage and transmits the second high-level signal to the voltage regulating module;

the voltage regulating module is used for outputting the first voltage and the second voltage according to the second high-level signal.

Further, the auxiliary power supply is connected with a baseboard management controller of the server and a programmable logic device, the baseboard management controller is connected with a first input end of a second buffer, the programmable logic device is connected with a second input end of the second buffer, and an output end of the second buffer is connected with the reset chip.

Further, the baseboard management controller is configured to transmit a first low-level signal to the first input end of the second buffer through the received reset instruction, and transmit the reset instruction to the programmable logic device;

the programmable logic device is used for transmitting a third high-level signal to the second input end of the second buffer according to the reset instruction;

the first input end of the second buffer receives the first low-level signal, the second input end of the second buffer receives the third high-level signal sent by the programmable logic device, and the output end of the first buffer sends a first target signal to the reset chip, wherein the first target signal is used for controlling the reset chip to output a second low-level signal within a set time, and reset operation is executed after the set time.

Further, the reset chip receives the first target signal and transmits a second low-level signal to the second input end of the first buffer based on the first target signal;

the first input end of the first buffer receives the power supply voltage, the second input end of the first buffer receives a second low-level signal transmitted by the reset chip, and the first buffer is in a non-conduction state so that the voltage regulating module is in a failure state.

Further, when the set duration is reached, the baseboard management controller is configured to transmit a fourth high-level signal to the first input end of the second buffer;

the programmable logic device is used for transmitting a fifth high-level signal to the second input end of the second buffer;

the first input end of the second buffer receives the fourth high-level signal, the second input end of the second buffer receives the fifth high-level signal sent by the programmable logic device, and the output end of the first buffer sends a second target signal to the reset chip, wherein the second target signal is used for controlling the reset chip to be conducted.

Further, the reset chip is configured to transmit a sixth high-level signal to the second input end of the first buffer according to the second target signal;

the first input end of the first buffer receives the power supply voltage, the second input end of the first buffer receives the sixth high-level signal transmitted by the reset chip, the first buffer is in a conducting state, and the output end of the first buffer transmits the power supply voltage to the voltage regulating module.

In a second aspect, an embodiment of the present application provides a server power supply method, applied to a circuit as described above, the method including:

receiving a power-on instruction of a server;

responding to the server power-on instruction to acquire a power supply voltage;

adjusting the power supply voltage to obtain a first voltage and a second voltage, wherein the first voltage is used for supplying power to a core power supply, and the second voltage is used for supplying power to an auxiliary power supply;

and controlling the kernel power supply to supply power for the server kernel according to the first voltage, and controlling the auxiliary power supply to supply power for the server according to the service power supply.

In a third aspect, an embodiment of the present application provides a computer apparatus, including: the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions to perform the method of the first aspect or any implementation manner corresponding to the first aspect.

In a fourth aspect, an embodiment of the present application provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of the first aspect or any of its corresponding embodiments.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a server power supply circuit according to some embodiments of the application;

FIG. 2 is a block diagram of a server power supply circuit according to some embodiments of the application;

FIG. 3 is a flow chart of a server power method according to some embodiments of the application;

fig. 4 is a block diagram of a server power supply apparatus according to an embodiment of the present application;

fig. 5 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In this embodiment, a server power supply circuit is provided, fig. 1 is a structural diagram of a server power supply circuit according to an embodiment of the present application, and as shown in fig. 1, the circuit includes: the power supply module 100, the voltage regulation module 200, the kernel power supply 300 and the auxiliary power supply 400, the power supply module 100 is connected with the voltage regulation module 200, and the voltage regulation module 200 is respectively connected with the kernel power supply 300 and the auxiliary power supply 400.

The power supply module 100 is configured to transmit a power supply voltage to the voltage adjustment module when receiving a power-on instruction of the server;

the voltage adjusting module 200 is configured to perform an adjusting operation on a power supply voltage to obtain a first voltage and a second voltage, where the first voltage is used to supply power to the kernel power supply, and the second voltage is used to supply power to the auxiliary power supply;

a core power supply 300 for supplying power to the server core according to the first voltage;

an auxiliary power supply 400 for powering the server according to the second voltage.

In the embodiment of the application, the power supply module (Power Supply Unit, abbreviated PSU) uniformly takes the p12v_psu as the power supply voltage, and provides the power supply voltage to the voltage regulating module (Voltage Regulator, abbreviated VR), and the power supply voltage is regulated by the voltage regulating module and then is output to the kernel power supply and the auxiliary power supply.

The embodiment of the application uniformly takes the power supply voltage of the P12V_PSU as the input of the voltage regulating module, and regulates the power supply voltage through the voltage regulating module, thereby controlling the voltages of the core power supply and the auxiliary power supply and finally realizing the power-on and power-off control of the core power supply and the auxiliary power supply.

In the prior art, when the baseboard management controller loses the power supply voltage (namely after the auxiliary power supply is powered down), the system is not in reset starting design, is completely uncontrolled, and cannot automatically power up and power down.

Based on this, the server power supply circuit provided by the embodiment of the application further includes a reset module 500, as shown in fig. 2, an input end of the reset module 500 is connected with the power supply module, and an output end of the reset module 500 is connected with the voltage regulating module; and the reset module 500 is used for resetting the kernel power supply and the auxiliary power supply when the server runs.

In an embodiment of the present application, the reset module 500 includes: the voltage regulator comprises a first buffer 5001 and a reset chip 5002, wherein a first input end of the first buffer 5001 is connected with a power supply module, a second input end of the first buffer 5001 is connected with the reset chip 5002, and an output end of the first buffer 5001 is connected with the voltage regulating module 200.

In the embodiment of the present application, a first input end of the first buffer 5001 receives the power supply voltage, and a second input end of the first buffer 5001 receives the first high level signal transmitted by the reset chip, the first buffer is in a conductive state, and an output end of the first buffer 5001 outputs the second high level signal based on the first high level signal and the power supply voltage, and transmits the second high level signal to the voltage adjusting module 200.

The voltage adjusting module 200 is configured to output a first voltage and a second voltage according to the second high level signal.

It should be noted that, when the power supply module 100 inserts alternating current (Alternating Current, abbreviated as AC), the power supply module 100 outputs p12v_psu_stby by default, and the p12v_psu control signal ps_on is grounded, and is enabled at this time, the power supply module 100 directly transmits the output p12v_psu (power supply voltage) to the first input terminal of the first buffer 5001.

In the reset module 500, as shown in fig. 2, p12v_psu_stby is converted into a conventional 3.3V power source p3v3_psu_stby, and each device of the reset module is powered by p3v3_psu_stby, and the input terminal of the reset chip is pulled up by default (when the baseboard management controller and the programmable logic device are in an inactive state), so the reset chip 5002 transmits a first high level signal to the second input terminal of the first buffer 5001.

Based on this, the first input terminal of the first buffer 5001 receives the supply voltage transmitted by the power supply module 100, and at this time, the first buffer 5001 is enabled. When the second input terminal of the first buffer 5001 receives the first high level signal transmitted by the reset chip 5002, the first buffer is in a conductive state, and outputs the second Gao Dianping signal based on the first high level signal and the supply voltage.

In an embodiment of the present application, the voltage adjustment module 200 outputs the first voltage and the second voltage according to the second high level signal. Wherein the first voltage is transmitted to the core power supply 300 and the second voltage is transmitted to the auxiliary power supply 400. The core power supply 300 supplies power to the server core based on the first voltage, and the auxiliary power supply 400 supplies power to the server based on the second voltage, that is, supplies power to the baseboard management controller and the programmable logic device based on the second voltage.

In the embodiment of the application, when the server is powered down, after alternating current (Alternating Current, abbreviated as AC) is pulled out from the power supply module, the power supply module does not output power supply voltage, at this time, the first input end of the first buffer is not input, and the first buffer is closed, so that the power down is completed.

The resetting process in the embodiment of the application is as follows:

in the embodiment of the present application, as shown in fig. 2, the auxiliary power supply 400 is connected to the baseboard management controller 600 and the programmable logic device 700 of the server, and the auxiliary power supply 400 supplies power to the baseboard management controller and the programmable logic device based on the second power transmission.

In the embodiment of the present application, the baseboard management controller 600 is connected to a first input terminal of the second buffer 800, the programmable logic device 700 is connected to a second input terminal of the second buffer 800, and an output terminal of the second buffer 800 is connected to the reset chip 5002.

Specifically, the baseboard management controller 600 is configured to transmit the first low level signal to the first input terminal of the second buffer through the received reset command, and transmit the reset command to the programmable logic device 700. The programmable logic device 700 is configured to transmit a third high level signal to the second input terminal of the second buffer according to the reset command.

It should be noted that, when the server normally works, the core power supply and the auxiliary power supply are reset, that is, the user can remotely send a reset instruction to the server, and when the baseboard management controller of the server receives the reset instruction, the reset signal rst_stby (that is, the first low level signal) is pulled down first, and the reset signal rst_stby (that is, the first low level signal) is transmitted to the first input end of the second buffer. Meanwhile, the baseboard management controller informs the programmable logic device of the pull-up enable signal rst_en (i.e., the third high level signal) through the I2C bus between the baseboard management controller and the programmable logic device, and the programmable logic device transmits the enable signal rst_en (i.e., the third high level signal) to the second input terminal of the second buffer. So that the second buffer controls the reset chip to perform a reset operation based on the reset signal rst_stby (i.e., the first low level signal) and the enable signal rst_en (i.e., the third high level signal).

Specifically, as shown in fig. 2, a first input terminal of the second buffer 800 receives a first low level signal, and a second input terminal of the second buffer 800 receives a third high level signal sent by the programmable logic device 700, and an output terminal of the first buffer 5001 sends a first target signal to the reset chip 5002, where the first target signal is used to control the reset chip to output a second low level signal in a set time, and perform a reset operation after a set duration.

The reset chip 5002 receives the first target signal and transmits a second low level signal to the second input terminal of the first buffer based on the first target signal.

The first input end of the first buffer receives the power supply voltage, the second input end of the first buffer receives the second low-level signal transmitted by the reset chip, and the first buffer is in a non-conducting state so that the voltage regulating module is in a failure state.

It should be noted that, after the reset chip receives the first target signal, the output terminal of the reset chip is pulled down, that is, the second low level signal is transmitted to the first buffer. Because the first target signal is used for controlling the reset chip to output the second low-level signal within the set time, the reset chip can always transmit the second low-level signal to the first buffer within the set time, wherein the set time can be set through an external capacitor of the reset chip. During the period that the reset chip outputs the second low-level signal, the first buffer is in a non-conducting state so as to disable the enabling of the voltage regulating module, and at the moment, the P12V_STBY is powered down, so that the power of the kernel power supply and the auxiliary power supply is synchronously powered down.

In the embodiment of the present application, as shown in fig. 2, when a set period of time is reached, the baseboard management controller 600 is configured to transmit a fourth high level signal to the first input terminal of the second buffer 800;

a programmable logic device 700 for transmitting a fifth high level signal to a second input terminal of the second buffer 800;

the first input end of the second buffer 800 receives the fourth high level signal, and the second input end of the second buffer 800 receives the fifth high level signal sent by the programmable logic device, and the output end of the first buffer 5001 sends a second target signal to the reset chip, where the second target signal is used to control the reset chip to be turned on.

In the embodiment of the present application, the reset chip 5002 is configured to transmit a sixth high level signal to the second input end of the first buffer according to the second target signal;

the first input end of the first buffer 5001 receives the power supply voltage, the second input end of the first buffer 5001 receives the sixth high level signal transmitted by the reset chip, the first buffer is in a conducting state, and the output end of the first buffer transmits the power supply voltage to the voltage regulating module.

It should be noted that, in the set time, since the reset chip outputs a low level signal all the time, the voltage adjusting module fails and cannot output voltage, so that the baseboard management controller and the programmable logic device start to be powered down.

When the set time is reached, the baseboard management control and the programmable logic device transmit high-level signals to the second buffer at the same time, so that the second buffer outputs the high-level signals to the reset chip (namely, the second target signals), at the moment, the input end of the reset chip is pulled up again, the reset chip outputs the high-level signals to the first buffer, meanwhile, the power supply module supplies power supply voltage to the first buffer, the first buffer resumes outputting the high-level signals to the voltage regulation module, at the moment, the input level and the enabling signals of the voltage regulation module are effective, and the system is powered on again to complete reset.

In the embodiment of the application, in order to ensure that the reset chip outputs high after the system is completely powered down, the setting time of the reset chip for outputting the low-level signal is longer than the power-down time of the conventional system.

In a second aspect, an embodiment of the present application provides a server power supply method, applied to a circuit as described above, as shown in fig. 3, where the method includes:

step S11, a power-on instruction of the server is received.

Step S12, responding to a power-on instruction of the server, and acquiring a power supply voltage.

Step S13, adjusting the power supply voltage to obtain a first voltage and a second voltage, wherein the first voltage is used for supplying power to the core power supply, and the second voltage is used for supplying power to the auxiliary power supply.

Step S14, controlling the kernel power supply to supply power for the server kernel according to the first voltage, and controlling the auxiliary power supply to supply power for the server according to the service power supply.

According to the method provided by the embodiment of the application, after the server is electrified, the power supply voltage is used as the input of the voltage regulating module, and the voltage regulating module is used for regulating the power supply voltage, so that the voltages of the core power supply and the auxiliary power supply are controlled, and finally the power-on and power-off control of the core power supply and the auxiliary power supply is realized.

In the embodiment of the application, the method further comprises the following steps: and receiving a reset instruction, and responding to the reset instruction, and resetting the kernel power supply and the auxiliary power supply within a set time so as to enable the kernel power supply and the auxiliary power supply to start to be powered off.

In the embodiment of the application, the method further comprises the following steps: and when the set time is reached, recovering the power supply to the kernel power supply and the auxiliary power supply.

According to the method provided by the embodiment of the application, after the server sends the reset instruction, the reset chip responds to the reset instruction, and outputs the low-level signal within the set time so as to enable the voltage regulating module to fail, and after the set time is reached, the reset chip is controlled to recover and output the high-level signal so as to enable the voltage regulating module to be effective, so that the self-starting of the core power supply and the auxiliary power supply after the controlled closing is realized.

In this embodiment, a server power supply device is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and will not be described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present embodiment provides a server power supply device, as shown in fig. 4, including:

a receiving module 41, configured to receive a server power-on instruction;

the response module 42 is configured to obtain a power supply voltage in response to a power-on instruction of the server;

the adjusting module 43 is configured to perform an adjusting operation on a power supply voltage to obtain a first voltage and a second voltage, where the first voltage is used to supply power to the core power supply, and the second voltage is used to supply power to the auxiliary power supply;

the control module 44 is configured to control the kernel power supply to supply power to the server kernel according to the first voltage, and control the auxiliary power supply to supply power to the server according to the service power supply.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a computer device according to an alternative embodiment of the present application, as shown in fig. 5, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system).

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.

The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created from the use of the computer device of the presentation of a sort of applet landing page, and the like. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

The embodiments of the present application also provide a computer readable storage medium, and the method according to the embodiments of the present application described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although embodiments of the present application have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the application, and such modifications and variations fall within the scope of the application as defined by the appended claims.

Claims (10)

1. A server power supply circuit, the circuit comprising: the power supply module is connected with the voltage regulation module, and the voltage regulation module is respectively connected with the core power supply and the auxiliary power supply;

the power supply module is used for transmitting power supply voltage to the voltage regulation module under the condition of receiving a power-on instruction of the server;

the voltage regulating module is used for regulating the power supply voltage to obtain a first voltage and a second voltage, wherein the first voltage is used for supplying power to the kernel power supply, and the second voltage is used for supplying power to the auxiliary power supply;

the kernel power supply is used for supplying power to the server kernel according to the first voltage;

and the auxiliary power supply is used for supplying power to the server according to the second voltage.

2. The circuit of claim 1, wherein the server power supply circuit further comprises: the input end of the reset module is connected with the power supply module, and the output end of the reset module is connected with the voltage regulating module;

and the reset module is used for resetting the kernel power supply and the auxiliary power supply when the server runs.

3. The circuit of claim 2, wherein the reset module comprises: the power supply device comprises a power supply module, a first buffer and a reset chip, wherein a first input end of the first buffer is connected with the power supply module, a second input end of the first buffer is connected with the reset chip, and an output end of the first buffer is connected with the voltage regulating module.

4. The circuit of claim 3, wherein a first input of the first buffer receives the supply voltage and a second input of the first buffer receives a first high level signal transmitted by the reset chip, the first buffer is in a conductive state, an output of the first buffer outputs a second high level signal based on the first high level signal and the supply voltage, and the second high level signal is transmitted to the voltage regulation module;

the voltage regulating module is used for outputting the first voltage and the second voltage according to the second high-level signal.

5. A circuit according to claim 3, wherein the auxiliary power supply is connected to a baseboard management controller of the server and to a programmable logic device, the baseboard management controller being connected to a first input of a second buffer, the programmable logic device being connected to a second input of the second buffer, and an output of the second buffer being connected to the reset chip.

6. The circuit of claim 5, wherein the baseboard management controller is configured to transmit a first low level signal to the first input terminal of the second buffer through the received reset command, and transmit the reset command to the programmable logic device;

the programmable logic device is used for transmitting a third high-level signal to the second input end of the second buffer according to the reset instruction;

the first input end of the second buffer receives the first low-level signal, the second input end of the second buffer receives the third high-level signal sent by the programmable logic device, and the output end of the first buffer sends a first target signal to the reset module, wherein the first target signal is used for controlling the reset chip to output the second low-level signal within a set time, and reset operation is executed after the set time.

7. The circuit of claim 6, wherein the reset chip receives the first target signal and transmits a second low level signal to a second input of the first buffer based on the first target signal;

the first input end of the first buffer receives the power supply voltage, the second input end of the first buffer receives a second low-level signal transmitted by the reset chip, and the first buffer is in a non-conduction state so that the voltage regulating module is in a failure state.

8. The circuit of claim 7, wherein the baseboard management controller is configured to transmit a fourth high level signal to the first input of the second buffer when the set time period is reached;

the programmable logic device is used for transmitting a fifth high-level signal to the second input end of the second buffer;

the first input end of the second buffer receives the fourth high-level signal, the second input end of the second buffer receives the fifth high-level signal sent by the programmable logic device, and the output end of the first buffer sends a second target signal to the reset chip, wherein the second target signal is used for controlling the reset chip to be conducted.

9. The circuit of claim 8, wherein the reset chip is configured to pass a sixth high signal to the second input of the first buffer according to the second target signal;

the first input end of the first buffer receives the power supply voltage, the second input end of the first buffer receives the sixth high-level signal transmitted by the reset chip, the first buffer is in a conducting state, and the output end of the first buffer transmits the power supply voltage to the voltage regulating module.

10. A server power supply method, applied to the circuit of any one of claims 1-9, the method comprising:

receiving a power-on instruction of a server;

responding to the server power-on instruction to acquire a power supply voltage;

adjusting the power supply voltage to obtain a first voltage and a second voltage, wherein the first voltage is used for supplying power to a core power supply, and the second voltage is used for supplying power to an auxiliary power supply;

and controlling the kernel power supply to supply power for the server kernel according to the first voltage, and controlling the auxiliary power supply to supply power for the server according to the service power supply.