CN116742942A - Multifunctional pin for soft start and current limitation of voltage converter - Google Patents

Abstract

The application relates to a multifunctional pin for soft start and current limitation of a voltage converter. The circuit and the system comprise: a parallel resistor-capacitor RC network (108) coupled between the pin (106) and ground (108); and first and second transistors (M _N1 M and M _N2 ) Coupled with a common gate coupling in a source follower configuration. The first transistor (M _N1 ) Is coupled to the pin (106). A first switch (S1) switches the first transistor (M) during a soft start SS _N1 ) Is coupled to the common gate coupling and is atThe connection is decoupled during over-current limited OCL sensing, and a second switch (S2) decouples the second transistor (M _N2 ) Is coupled to the common gate coupling and decouples the connection during SS.

Description

Multifunctional pin for soft start and current limitation of voltage converter

Cross reference to related applications

The present application claims priority from indian patent application 202241013346 filed on day 11, 3, 2022 in accordance with 35u.s.c. ≡119. The entire contents of this indian patent application are incorporated herein by reference.

Technical Field

The present disclosure relates to improvements in voltage converters, and more particularly, to providing single or multi-function pins for soft start and over-current limiting functions in voltage converters (e.g., DC-DC converters).

Background

DC-DC converters typically require programmable Soft Start (SS) and over-current limiting (OCL) functionality. In a conventional DC-DC converter, two separate pins are provided, one for each function. During SS, a main Field Effect Transistor (FET) current (I _FET ) Slowly ramp from zero to maximum current in a programmable time. The ramp voltage is obtained by pumping a constant internal current to an external capacitor (C _EXT ) Until the voltage across it reaches a certain value. The time required to charge the external capacitor can be controlled (i.e., programmed) by selecting an appropriate capacitance value. After SS is completed, the external resistor (R _EXT ) The steady state OCL is programmed.

In the existing method, C during both the SS phase and the OCL phase _EXT R is R _EXT The two are coupled in parallel between the same pin and ground, and are based on a bandgap voltage (V _BG ) And the resistance value of the internal resistor of the circuit is driven with the same constant current. Crossing R _EXT C _EXT The voltage of the circuit increases exponentially to a peak stable value, where the exponentially rising portion of the curve represents the SS phase and the stable portion of the curve represents the OCL phase. Pin voltage (V) _PIN ) And voltage (I) _FET *R _SNS ) Comparison is performed to switch on I _FET A flow-through FET, wherein R _SNS Representation I _FET Resistance of the sensor resistor in the path of (a). By varying the time constant R _EXT C _EXT To change the stability. However, C _EXT Cannot be used independently for programming the settling time because R _EXT Is determined based on the desired OCL limit sensed by the final regulated voltage. DC accuracy depends on internal resistance and R _SNS Each of which is a product ofOne can vary widely.

In another prior approach, a separate pin is used for the bias resistor, which essentially replaces the internal resistor. In this configuration, the external bias resistor (R _BIAS ) Coupled to an applied voltage (V _BIAS ) Wherein the other end is connected with C _EXT R is R _EXT Is commonly coupled to ground. Here, for driving R _EXT C _EXT The constant current of the circuit is V _BIAS /R _BIAS A function of the value. While this approach improves accuracy over other prior approaches described above, it comes at the cost of additional pins.

In this context, aspects of the present disclosure aim to provide better solutions for SS and OCL functions in voltage converters (e.g., DC-DC converters).

Disclosure of Invention

In an example, a circuit includes a first resistor (e.g., R _EXT ) And a capacitor (e.g., C _EXT ) Each having one end coupled to a pin of the circuit and each having the other end coupled to a common node (e.g., ground) to form a parallel resistor-capacitor (RC) network. The circuit further includes first and second transistors each having a first current terminal, a second current terminal, and a control terminal. The control terminals of the first and second transistors are coupled together to form a common control terminal, and the second terminal of the first transistor is coupled to the pin. The first switch of the circuit is configured to couple the first current terminal of the first transistor to the common control terminal during Soft Start (SS) of the circuit and decouple the first current terminal of the first transistor from the common control terminal during over-current limit (OCL) sensing of the circuit. The second switch of the circuit is configured to couple the first current terminal of the second transistor to the common control terminal during OCL sensing and decouple the first current terminal of the second transistor from the common control terminal during SS. The circuit further includes first and second current sources. The first current source is coupled withIs coupled to the first transistor and is configured to source a constant current (e.g., I _INT ) To the pins. The second current source is coupled to the second transistor and configured to generate a reference voltage at the second current terminal of the second transistor when enabled during OCL sensing. A comparator of the circuit is configured to control the first and second switches to switch from SS to OCL sensing, a comparator output signal being based on a comparison of a voltage at the pin to a threshold voltage.

In an example, a circuit includes: a parallel resistance-capacitance (RC) network coupled between a pin of the circuit and ground; first and second transistors each having a drain terminal, a source terminal, and a gate terminal, the gate terminals of the first and second transistors coupled together to form a common gate terminal, the source terminal of the first transistor coupled to the pin; current mirror circuitry configured to be based on a threshold voltage V _THRESH A constant current at least five times divided by a minimum resistance of a resistor of the RC network to generate a first reference current (e.g., I _SS ) And generates a second reference current (e.g., I _{REF_OCL} ) The method comprises the steps of carrying out a first treatment on the surface of the And a switch to configure the circuit for the SS operation for a first period of time and to configure the circuit for the OCL sensing operation for a second period of time.

In an example, a method includes performing an SS operation on a circuit, and then performing an OCL sensing operation on the circuit. The SS operation includes: constant current (e.g. I _INT ) Pins to the circuit; charging a capacitor of a resistor-capacitor (RC) network of the circuit to increase a voltage at the pin to a set voltage; and generating a first reference current (e.g., I _SS ). The OCL operation includes: activating an internal current source to generate a reference voltage; and generating a second reference current (e.g., I _REF )。

In an example, oneThe system comprises: a semiconductor chip having circuitry thereon and a pin coupled to the circuitry and configured for external access, the circuitry configured to perform both a Soft Start (SS) operation and an over-current limit (OCL) sensing operation on the system using the pin; and an external resistor and an external capacitor coupled in parallel between the pin and ground. The circuit comprises: current mirror circuitry configured to generate a first reference current (e.g., I _SS ) And generates a second reference current (e.g., I _{REF_OCL} ) The method comprises the steps of carrying out a first treatment on the surface of the And a plurality of switches to configure the circuit for the SS operation in a first period of time and to configure the circuit for the OCL sensing operation in a second period of time.

These and other features will be better understood from the following detailed description with reference to the drawings.

Drawings

Features of the present disclosure may be understood from the following drawings, which are to be taken in conjunction with the detailed description.

Fig. 1A, 1B, and 1C are diagrams illustrating the use of a single pin (or node) of a voltage converter to perform both Soft Start (SS) and Over Current Limit (OCL) sensing functions of the voltage converter.

Fig. 2A and 2B are circuit diagrams of example circuits for performing both SS and OCL sensing functions of a voltage converter using a single pin, with example circuits configured for SS in fig. 2A and OCL sensing in fig. 2B.

Fig. 3 is a circuit diagram of an example circuit configured to perform both SS and OCL functions using a single pin.

FIG. 4 is a flow chart of an example of a method of operating a circuit (e.g., a voltage converter) to perform SS and OCL sensing operations.

Fig. 5 is a diagram of an example system (e.g., voltage converter) with circuitry for performing both SS and OCL sensing using a single pin.

FIG. 6 is a diagram for limiting I _FET FET limit of (c)Circuit diagram of the circuit.

The same reference numbers are used throughout the drawings to reference like or similar (structural and/or functional) features.

Detailed Description

Specific examples are described in detail below with reference to the accompanying drawings. These examples are not intended to be limiting. In the drawings, corresponding numerals and symbols generally refer to corresponding parts unless otherwise indicated. The objects depicted in the drawings are not necessarily drawn to scale.

In an example arrangement, during SS operation, a constant current is delivered to charge a capacitor of a resistor-capacitor (RC) network coupled between a pin and a common node (e.g., ground), where the amount of such constant current is large enough such that a period of time for performing SS operation is primarily dependent on the capacitance of the capacitor of the RC network and primarily independent of the resistance of the resistor of the RC network, thereby enabling capacitive sensing. The current mirror and source follower transistor are configured to convert the voltage at the pin to a proportional reference current during SS operation and, after SS operation, to generate and transfer a reference voltage to the pin during OCL operation to sense the resistance of the resistor of the RC network. The source follower transistor configuration is stable and independent of the capacitance of the capacitor of the RC network. The reference current for OCL sensing is based on the reference voltage and the resistance value of the external resistor. In an example, the constant current delivered during SS operation is greater than five times the division of the threshold voltage by the minimum resistance of the resistor of the RC network. This configuration advantageously enables integration of both SS and OCL sensing operations using the same circuit and a single pin, while achieving improved accuracy.

Fig. 1A and 1B are diagrams illustrating concepts of performing both Soft Start (SS) and Over Current Limit (OCL) sensing operations of a voltage converter using a single pin (or node) of the voltage converter. Fig. 1A shows the circuit 100 configured in SS mode (i.e., for SS operation), while fig. 1B shows the circuit 100 configured in OCL sensing mode (i.e., for OCL sensing operation). FIG. 1C is (i) pin voltage (V _PIN ) Graph of output (TO) versus time of (ii) comparator for marking transition from SS operation TO OCL sensing operation. During SS operation, the capacitance of the capacitor of the RC network is sensed, and during OCL sensing operation, the resistance of the resistor of the RC network is sensed.

Referring to fig. 1a, a circuit 101 of ss mode configuration includes a current source 102 coupled to a supply voltage terminal 104, the supply voltage terminal 104 configured to be coupled to a voltage supply (VDD). The current source 102 is configured to source a constant current (I during SS operation _INT ) To the pins 106. Circuit 101 also has a parallel resistor-capacitor (RC) network 108 coupled between pin 106 and ground 110. RC network 108 includes capacitor C _EXT Resistor R _EXT Which is typically external to the chip or package embodying additional circuitry for performing SS and OCL sensing operations, as well as other functions. During SS operation, I is delivered in a sufficiently large amount _INT To form a time period (denoted as T in fig. 1C) for performing SS operations _PRG ) The operation includes C _EXT Is mainly dependent on C _EXT Is mainly independent of R _EXT Is a resistance value of (a). In the example, I _INT >5V _THRESH /R _EXT (min), wherein V _THRESH Representing the sum V during SS operation _PIN Threshold voltage for comparison, and R _EXT (min) represents R _EXT Is a minimum resistance value of (a). R is R _EXT (min) is set based on the maximum current limit supported by the programming according to the system design and/or specification. V (V) _REF Is a reference voltage slightly higher than V _THRESH V (V) _PIN A stable voltage. Slope V _PIN Is expected to be exponentially stable, which will be about 5V _THRESH 。

The circuit 101 implements a voltage-to-current (V-I) converter 112 to convert V _PIN Converted into proportional current I _SS The proportional current I _SS Used as reference current in SS operation, where G _M Representing the transconductance of V-I converter 112. During SS operation, V _PIN Ramp up, and when it ramps up, comparator 114 will V _PIN And V is equal to _THRESH A comparison is made. When V is _PIN Exceeding V _THRESH When the comparator 114 outputs a signal (TO), which is also shown in fig. 1C. TO signal indicationThe end of SS operation and the beginning of OCL sensing operation, and may also be used to turn off current source 102.SS operation is performed by program time (T _PRG ) Definition wherein

Once the SS operation is complete (marked by TO assertion), the circuit 100 is configured for OCL sensing operations. Referring to FIG. 1B, in the OCL sensing mode configured circuit 151, V is determined using a source follower transistor configuration _REF Is transferred to pin 106 to generate reference current I for OCL sensing operations _{REF_OCL} The OCL sensing operation includes sensing R _EXT Is a resistor of (a). The current (V) provided by the internal current source 152 that is turned on at the beginning of the OCL sensing operation (e.g., in response TO assertion of the TO signal _REF /R _INT1 ) Flow to R _INT1 In the formula, R is _INT1 Is an internal resistor coupled between the source terminal of transistor 154 and ground 110. Transistor 154 is configured with source follower and I _{REF_OCL} The pass transistor 156 is coupled. Current V _REF /R _INT1 Generates a reference voltage V at the source of transistor 154 _REF And V will be the source follower of transistor 154 using transistor 156 _REF To V _PIN . In an example, each of transistors 154 and 156 is an n-type metal oxide semiconductor (NMOS) field effect transistor. Pin 106 is coupled to or is part of the source terminal of transistor 156. RC network 108 is coupled between pin 106 and ground 110.

By means of the action of the source follower,thus being capable of sensing R _EXT Is a resistance value of (a). Furthermore, as shown more clearly in the FET current limiting circuit of fig. 6, the current limit (I _{FET_LIM} ) By the ratio of the resistances of the two internal resistors to I _{REF_OCL} Correlation: r is R _INT2 R is R _SNS Wherein R is _INT2 For connecting I _{REF_OCL} Is converted into a voltage, and R _SNS For connecting I _FET Converted to voltage, then comparedTwo voltages. I.e.)>R _INT2 R is R _SNS The ratio of the resistances of (2) is process independent; thus, the process variation is about zero. Thus, due to R _EXT R is R _INT1 The DC accuracy of circuit 100 may be only subject to V of transistors 154 and 156 in the source follower configuration _REF V (V) _GS -V _T And (3) limitation of mismatch.

FIGS. 2A and 2B (collectively FIG. 2) show an example circuit 200 that may be configured to perform both SS operations and OCL sensing operations. Similar to circuit 100 of FIGS. 1A and 1B, circuit 200 includes current sources 102 and 152, pins 106, R, respectively _INT1 Comprising R _EXT C (C) _EXT And power supply voltage and ground terminals 104 and 110. Source follower transistor configurations are also included. In fig. 2A and 2B, this configuration includes an NMOS transistor M _N1 M and M _N2 Switch S ₁ S and S ₂ . The example circuit 200 is configured as follows.

During SS operation, current source 102 is actively coupled between supply voltage terminal 104 and M _N1 Between the drains of M _N1 Is coupled to pin 106. During OCL sensing operation, current source 152 is actively coupled between supply voltage terminals 104 and M _N2 Between the drains of M _N2 Is coupled to R _INT1 。M _N1 M and M _N2 Is commonly coupled to the gates of (c). Switch S1 is configured to couple M when closed _N1 And switch S2 is configured to couple M when closed _N2 Drain and gate of (a) are provided. In an example, during SS operation, S1 is closed and S2 is open, and during OCL sensing operation, S2 is closed and S1 is open.

In SS operation, M with S1 closed, S2 open, current source 102 enabled, and current source 152 disabled _N1 Drain electrode of M _N1 Gate and M of (2) _N2 Is coupled together, as shown in fig. 2A, essentially providing the functionality of a voltage-to-current (V-I) converter. In response to generation of I by current source 102 _INT Is C _EXT Charging up to V _PIN Reach V _THRESH ，V _THRESH Slightly lower than V _REF ，V _REF Is V _PIN A stable approximate voltage. Slope V _PIN Is converted into SS reference current I _SS . During SS operation, M _N2 (V _{S_N2} ) Voltage at the source of (V) _PIN . Thus, the first and second substrates are bonded together,with this arrangement, C can be sensed _EXT Is a capacitor of (a).

When V is _PIN Reach V _THRESH When S1 is open, S2 is closed, current source 102 is deactivated, and current source 152 is activated, providing the configuration of fig. 2B. S1 and S2 may be initially set (e.g., for SS operation) and then controlled by the output of the comparator (e.g., TO signal of fig. 1). The current sources 102 and 152 may likewise be initially set and then controlled by the TO signal.

In fig. 2B, current source 152 delivers a current (V when circuit 200 is configured as shown in fig. 2B _REF /R _INT1 ) And is present at M _N2 (V _{S_N2} ) Reference voltage V at the source of (2) _REF By M _N1 M and M _N2 Is passed to pin 106. Thus, the first and second substrates are bonded together,this generates a reference current (I _{OCL_REF} ) The reference current is approximately equal to V _REF /R _EXT This achieves R _EXT Is a sensing of the resistance of (a).

Fig. 3 is a circuit diagram of an example circuit 300 configured to perform both SS and OCL functions using a single pin. The circuit 300 includes current sources 102 and 152, pins 106, R _INT Comprising R _EXT C (C) _EXT And power supply voltage and ground terminals 104 and 110. Also included is an NMOS transistor M in a source follower configuration _N1 M and M _N2 And a switch S ₁ S and S ₂ . The comparator function and V-I conversion function are included with minor modifications.

The circuit 300 includes a first current mirror 304 used during SS operation and a second current mirror 302 used during OCL sensing operation. In general, the first and second current mirrors may be considered current mirror circuitry.

The first current mirror 304 comprises a p-type metal oxide semiconductor (PMOS) field effect transistor M _P1 、M _P2 、M _P3 、M _P4 M and M _P5 。M _P1 、M _P3 M and M _P4 Are commonly coupled through their corresponding gates and each of their sources is coupled to a supply voltage terminal 104.M is M _P1 、M _P3 M and M _P4 Is also coupled to M _P3 During SS operation, current flows through M _P3 Through the current source 102.M is M _P4 Is coupled to M _P5 When the switch 306 is closed during OCL sensing operation, M _P5 Forms a current path via switch 306. Switch 306 is open during SS operation. M is M _P1 Is coupled to M _P2 Source of M _P2 Is coupled to M _P5 Is formed on the substrate. M is M _P2 Is configured to be coupled to ground terminal 110 via switch 308 during SS operation or to its own drain via switch 312 during OCL sensing operation. The circuit 300 is configured such that when the switch 308 is open, the switch 312 is closed, and vice versa.

M _N1 Drain coupling M of (2) _P2 Is formed on the drain electrode of the transistor. Pin 106 is coupled to M _N1 Or a part thereof, and comprises R coupled in parallel _EXT C (C) _EXT Is coupled between pin 106 and ground terminal 110. In this example, when the enable signal (EN) is low (and its complement signal ENZ is high), switch 314 is provided to short pin 106 to ground; otherwise, switch 314 is open and does not affect RC network 108.

The second current mirror 302 includes a PMOS transistor M _P6 、M _P7 M and M _P8 Their respective gates are commonly coupled and also coupled to M _P6 Is formed on the drain electrode of the transistor. M is M _P6 、M _P7 M and M _P8 The source of each of which is coupled to a supply voltage terminal 104.M is M _P6 Drain of (and M) _P6 、M _P7 M and M _P8 Is coupled TO current source 152 via switch 316 when comparator output signal TO is high during OCL sensing operations and TO M via switch 318 when TO is low (and its complement signal TOZ is high) during SS operations _N2 Is formed on the drain electrode of the transistor. When TO is high, M _P7 Is coupled to M via switch 322 _N2 And when TO is low, a reference current I is formed for SS operation via switch 324 _SS Is provided.

M _N2 Is coupled to M _N1 And S1 and S2 selectively couple the common gate connection to M, respectively _N1 Drain electrode of (d) and M _N2 Is formed on the drain electrode of the transistor. R is R _INT Coupled at M _N2 Between the source of (c) and ground terminal 110.

NAND gate 332 has a gate coupled to M _P8 And another input configured to receive an enable signal (EN). The output of NAND gate 332 is coupled TO the input of inverter 334, which inverter 334 has an output for the TO signal. NAND gate 332 and inverter 334 are combined with M _P8 Operates to form a comparator for stopping SS operation and starting the next OCL sensing operation. EN may be supplied by any suitable source and its supplemental signal ENZ may be generated by inverter 336 or other suitable circuitry.

When EN is low, TO is also low. Thus, all TOZ actuated switches (i.e., switches S1, 308, 318, and 324) are closed, and C _EXT In a discharge state. The SS operation begins when EN is asserted (e.g., EN high). M is M _N1 Is C _EXT Charged and M _N2 Used as a source follower and a V-I converter. M is M _N2 Generating a ramp current as V _PIN /R _INT1 。M _P8 In conjunction with NAND gate 332 and inverter 334, act as comparators. When V is _PIN ＝V _THRESH When M is _P8 The current of (2) is V _THRESH /R _INT1 . Once the comparator output switches, all TO-actuated switches (i.e., switches S2, 306, 312, 316, and 322) are closed, and all TOZ-actuated switches are open, marking the end of SS operation and the sense of OCLThe start of the test operation. During OCL sensing operation, M _N1 Acting as a source follower to divide V _REF To pin 106 and at M _P5 Output of mirror image I _{REF_OCL} . Current through MP8 becomes V _REF /R _INT1 By design greater than V _THRESH /R _INT1 Because of V _REF >V _THRESH . Thus, the comparator output remains high and stable. When EN goes low, the state of circuit 300 is reset low.

Fig. 4 is a flow diagram of an example method 400 of performing SS operations on a circuit (e.g., circuits 100, 200, and/or 300). In describing the method 400, the circuit 200 is used by way of example.

In operation 402, a circuit is configured in an SS mode for SS operation. For example, switch S1 is closed and switch S2 is open; in addition, current source 102 is on and current source 152 is off. In operation 404, a constant current (I via the current source 102 _INT ) A pin (or node) on circuit 200 for both SS operation and OCL sensing operation, i.e., pin 106. In the example, I _INT Greater than threshold voltage (V) _THRESH ) Divided by capacitor C _EXT R together forming part of RC network 108 _EXT Five times the resistance of (c). In operation 406, C _EXT Charge to charge the voltage (V) at pin 106 _PIN ) Ramp up to a set voltage (e.g., V _THRESH ). In operation 408, a first reference current I is generated for SS operation _SS As V _PIN /R _INT1 . In so doing, via transistor M in the source follower configuration _N1 M and M _N2 Will V _PIN Delivery to M _N2 Is provided. Thus, I _SS And V is equal to _PIN Proportional to the ratio. From these relationships, C can be sensed _EXT Is a capacitor of (a).

Once V is _PIN Reach V _THRESH (this may be determined via comparator 114 or other suitable circuitry) circuit 200 is reconfigured for OCL sensing operations. Such reconfiguration (operation 412) may involve opening switch S1, closing switch S2, turning off current source 102, and turning on current source 152. In the case where the circuit 200 is in OCL sensing mode, inIn operation 414, the internal current source 152 is activated to generate a reference voltage (V _REF ) Wherein V is _REF Slightly higher than V _THRESH . Via a transistor M in a source follower configuration _N1 M and M _N2 Will V _REF To pin 106 such that V _PIN Follow V _REF And thus, the resistance of the external resistor is sensed in operation 416 and a reference current I for current limiting is generated in operation 418 _{REF_OCL} . Thus, I _{REF_OCL} About equal to V _REF /R _EXT 。

FIG. 4 depicts one possible operational sequence for performing an OCL sensing operation after performing an SS operation. Not all operations need be performed in the order described. Some operations may be combined into a single operation. One or more operations may be performed substantially simultaneously or in an overlapping manner. Additional and/or alternative operations may be performed.

For example, consistent with the above description, the method 400 may include outputting a comparison signal indicating an end of an SS operation and a start of an OCL sensing operation. The comparison signal may be based on V _PIN And V is equal to _THRESH Is a comparison of (c).

Fig. 5 is a diagram of an example system 500 (e.g., a DC-DC voltage converter) with circuitry for performing both SS and OCL sensing using a single pin. The DC-DC voltage converter 500 may include: conversion circuitry 502, which may be embodied on a semiconductor chip having external connections (or pins) including an input voltage (V) configured to be coupled to a supply voltage terminal 504 _IN ) Pins; a ground terminal 510; and pins 506 for both SS operation and OCL sensing operation. Comprising R _EXT C (C) _EXT Is coupled between pin 506 and ground terminal 510. When the conversion circuitry 502 is embodied on a semiconductor chip, the RC network 508 may be external to the chip. The conversion circuitry 502 includes two output terminals, denoted SWA and SWB, configured to be coupled to output circuitry 520, the output circuitry 520 also having an input coupled to a supply voltage terminal 504. During operation, a supply Voltage (VDD) is coupled to supply voltage terminal 504. Output circuitry 520 may be configured as known in the artIncluding suitable transformer couplings and other components such as inductor(s) and capacitors.

FIG. 6 shows a circuit for limiting current I _FET Is described. The drain of the FET is coupled to the output (e.g., SWA or SWB) of the DC-DC converter 500. The source of the FET is coupled to a sensor resistor R _SNS Is provided with a sensor resistor R _SNS The other end of which is coupled to ground. Reference current I _{REF OCL} Is fed to an internal node (REF_OCL node) coupled to an internal resistor R _INT2 Is provided with an internal resistor R _INT2 The other end of which is coupled to ground. One input (e.g., negative input) of the comparator is coupled to the source of the FET, where a voltage V is generated _SNS And the other input of the comparator is coupled to the ref_ocl node, where an internal voltage is generated. The output of the comparator is coupled to one input of an AND gate, the other input of which is configured to receive a Pulse Width Modulation (PWM) signal. The FET limit circuit may also include a latch downstream of the AND gate to keep the FET in an off state for the remainder of the PWM period after the comparator is triggered, as is known in the art. When the comparator is triggered to assert a logic low signal, the AND gate is caused to assert a logic low signal, which turns off the FET, thereby stopping I _FET Is provided. Will be represented by I _FET R is R _SNS V produced _SNS Compared with the voltage at the REF_OCL node, the voltage is represented by I _{REF_OCL} R is R _INT2 And (3) generating. I _FET (I _{FET_LIM} ) The restriction of (c) may be based on I _{FET_LIM} And I _{REF_OCL} The relationship between them is set. That is to say,

SS and OCL operations may be performed on the DC-DC converter 500 using pins 106 for both operations, as described above.

Various examples of circuitry, systems, and methods are provided in which a single pin or node is used for both SS and OCL sensing operations, thus relaxing the design constraints of the chip to be able to include pins for other functionality. In RC networks, which may be located outside the chip, capacitance and resistance are sensed independently. A large amount of current is delivered during SS to charge the capacitor of the RC network such that the period of time during which SS is performed is independent of the resistance of the resistor of the RC network. The use of a source follower transistor configuration enables a reference voltage to be transmitted to the pin, enabling the resistance of the resistor of the RC network to be sensed during OCL sensing based on the reference voltage and reference current values. The reference current may be compared to the main FET current for current limiting. The internal resistance can be matched to simplify the process and minimize or eliminate process variations. Advantageously, the source follower transistor configuration is very stable and does not depend on the capacitance of the capacitor of the RC network. The DC accuracy of the system (e.g., DC-DC converter) may be improved.

The term "coupled" is used throughout the specification. The terms or derivatives thereof may encompass a connection, communication, or signal path that achieves a functional relationship consistent with the description. For example, if device a provides a signal to control device B to perform an action, then in a first example, device a is coupled to device B, or in a second example, device a is coupled to device B through intermediary component C, provided that intermediary component C does not substantially alter the functional relationship between device a and device B, such that device B is controlled by device a via the control signal provided by device a.

A device "configured to" perform a task or function may be configured (e.g., programmed and/or hardwired) by the manufacturer at the time of manufacture to perform the function and/or may be configured (or reconfigurable) by a user after manufacture to perform the function and/or other additional or alternative functions. The configuration may be programmed by firmware and/or software of the device, by construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

As used herein, the term "pin" means "terminal," node, "" interconnect, "and/or" lead. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components, or ends thereof.

Circuits or devices described herein as including certain components may alternatively be adapted to be coupled to those components to form the described circuitry or devices. For example, structures described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors and/or capacitors), and/or one or more sources (e.g., current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and/or Integrated Circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and/or sources to form the described structures at or after manufacture, such as by an end user and/or a third party.

Although the use of CMOS fabrication techniques is described herein, other fabrication techniques using other types of transistors (or equivalent devices) may be used instead. For example, instead of using p-type and n-type Metal Oxide Silicon Field Effect Transistors (MOSFETs), other types of transistors, such as Bipolar Junction Transistors (BJTs) or switching elements, may be used instead.

The circuitry described herein is reconfigurable to include components that are replaced to provide functionality at least partially similar to functionality available prior to replacement of the components. Unless otherwise indicated, components shown as delays generally represent one or more delay elements coupled in series and/or parallel to provide a particular amount of delay.

The use of the phrase "ground" in the foregoing description includes chassis ground, ground, floating ground, virtual ground, digital ground, common ground, and/or any other form of ground connection suitable or adapted for the teachings of the present application. Unless otherwise indicated, "about," "about," or "substantially" preceding a value means +/-10% of the stated value.

Modifications to the described examples are possible and other examples are possible within the scope of the claims. Furthermore, the features described herein may be applied to other environments and applications consistent with the provided teachings.

Claims (23)

1. A circuit, comprising:

a first resistor and a capacitor each having one end coupled to a pin of the circuit and each having another end coupled to a common node to form a parallel resistor-capacitor RC network;

first and second transistors each having a first current terminal, a second current terminal, and a control terminal, the control terminals of the first and second transistors coupled together to form a common control terminal, the second terminal of the first transistor coupled to the pin;

a first switch configured to couple the first current terminal of the first transistor to the common control terminal during soft start SS of the circuit and decouple the first current terminal of the first transistor from the common control terminal during over-current limit OCL sensing of the circuit;

a second switch configured to couple the first current terminal of the second transistor to the common control terminal during OCL sensing and decouple the first current terminal of the second transistor from the common control terminal during SS;

a first current source coupled to the first transistor and configured to deliver a constant current to the pin when enabled during SS;

a second current source coupled to the second transistor and configured to generate a reference voltage at the second current terminal of the second transistor when enabled during OCL sensing; a kind of electronic device with high-pressure air-conditioning system

A comparator configured to control the first and second switches to switch from SS to OCL sensing, a comparator output signal being based on a comparison of a voltage at the pin to a threshold voltage.

2. The circuit of claim 1, further comprising:

a second resistor is coupled to the second current terminal of the second transistor.

3. The circuit of claim 1, wherein the first terminal of each of the first and second transistors is a drain terminal and the second terminal of each of the first and second transistors is a source terminal.

4. The circuit of claim 1, wherein the constant current is at least five times the division of the threshold voltage by a minimum resistance of the resistor.

5. The circuit of claim 2, wherein the reference voltage generated by the second current source is used to sense a resistance of the first resistor during OCL sensing.

6. The circuit of claim 3, wherein during SS, the voltage at the source terminal of the second transistor follows the voltage at the pin.

7. The circuit of claim 3, wherein during OCL sensing, the voltage at the pin follows the voltage at the source terminal of the second transistor.

8. The circuit of claim 6, wherein during SS the second transistor acts as a source follower to generate a reference current for SS, the reference current being based on the voltage at the pin and a resistance value of a second resistor coupled to the source terminal of the second transistor.

9. The circuit of claim 7, wherein during OCL sensing, the first transistor acts as a source follower to generate a reference current for OCL sensing, the reference current being based on the voltage at the source terminal of the second transistor and a resistance value of the first resistor.

10. A circuit, comprising:

a parallel resistor-capacitor RC network coupled between a pin of the circuit and ground;

first and second transistors each having a drain terminal, a source terminal, and a gate terminal, the gate terminals of the first and second transistors coupled together to form a common gate terminal, the source terminal of the first transistor coupled to the pin;

current mirror circuitry configured to determine a threshold voltage (V _THRESH ) A constant current at least five times divided by a minimum resistance of a resistor of the RC network to generate a first reference current (I _SS ) And generates a second reference current (I _{REF_OCL} ) The method comprises the steps of carrying out a first treatment on the surface of the A kind of electronic device with high-pressure air-conditioning system

A switch to configure the circuit for the SS operation for a first period of time and to configure the circuit for an over-current limited OCL sensing operation for a second period of time.

11. The circuit of claim 10, further comprising:

a resistor coupled between the drain terminal of the second transistor and ground.

12. The circuit of claim 10, further comprising:

comparison circuitry coupled to the current mirror circuitry, the comparison circuitry configured to detect a transition from the SS operation to the OCL sensing operation.

13. A method, comprising:

a soft start SS operation is performed on a circuit, comprising:

delivering a constant current to a pin of the circuit;

charging a capacitor of a resistor-capacitor, RC, network of the circuit to increase the voltage at the pin to a set voltage; a kind of electronic device with high-pressure air-conditioning system

Generating a first reference current for the SS operation; a kind of electronic device with high-pressure air-conditioning system

After performing the SS operation, performing an over-current limited OCL sensing operation on the circuit, the OCL sensing operation comprising:

activating an internal current source to generate a reference voltage; a kind of electronic device with high-pressure air-conditioning system

A second reference current for the OCL operation is generated by sensing a resistance of a resistor of the RC network.

14. The method of claim 13, wherein the constant current delivered to the pin of the circuit during the SS operation is at least five times a quotient of a threshold voltage and a resistance of a resistor of the RC network.

15. The method as recited in claim 14, further comprising:

a comparison signal is output indicating an end of the SS operation and a start of the OCL sensing operation, the comparison signal being based on a comparison of the voltage at the pin to a threshold voltage.

16. The method of claim 15, wherein the comparison signal is output at the end of a program period of time that is a function of the capacitance of the capacitor of the RC network, the threshold voltage, and the constant current delivered during the SS operation.

17. The method of claim 13, wherein the generating the first reference current for the SS operation includes transferring the voltage at the pin to a node in a current path of the first reference current.

18. The method of claim 13, wherein the activating the internal current source to generate the reference voltage for the OCL operation includes communicating the reference voltage to the pin.

19. A system, comprising:

a semiconductor chip having circuitry thereon and a pin coupled to the circuitry and configured for external access, the circuitry configured to perform both soft start SS operation and over-current limited OCL sensing operation on the system using the pin;

an external resistor and an external capacitor coupled in parallel between the pin and ground;

wherein the circuit comprises:

current mirror circuitry configured to generate a first reference current for the SS operation and to generate a second reference current for the OCL sensing operation based on a constant current of at least five times a division of a threshold voltage and a minimum resistance of the external resistor; a kind of electronic device with high-pressure air-conditioning system

A plurality of switches to configure the circuit for the SS operation in a first period of time and to configure the circuit for the OCL sensing operation in a second period of time.

20. The system of claim 19, wherein the circuit further comprises:

first and second transistors each having a drain terminal, a source terminal, and a gate terminal, the gate terminals of the first and second transistors coupled together to form a common gate terminal, the source terminal of the first transistor coupled to the pin.

21. The system of claim 20, wherein a first switch of the plurality of switches is configured to couple the drain and gate terminals of the first transistor during the SS operation and a second switch of the plurality of switches is configured to couple the drain and gate terminals of the second transistor during the OCL sensing operation.

22. The system of claim 19, wherein the first period of time is based on a capacitance of the external capacitance and is substantially independent of a resistance of the external resistor.

23. The system of claim 19, wherein the system comprises a DC-DC converter.