CN116742743A - Charging abnormality alarm circuit, method, device, electronic apparatus, and storage medium - Google Patents
Charging abnormality alarm circuit, method, device, electronic apparatus, and storage medium Download PDFInfo
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- CN116742743A CN116742743A CN202310589477.7A CN202310589477A CN116742743A CN 116742743 A CN116742743 A CN 116742743A CN 202310589477 A CN202310589477 A CN 202310589477A CN 116742743 A CN116742743 A CN 116742743A
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- 230000005856 abnormality Effects 0.000 title claims description 22
- 238000005070 sampling Methods 0.000 claims abstract description 31
- 230000002159 abnormal effect Effects 0.000 claims description 29
- 239000004973 liquid crystal related substance Substances 0.000 claims description 13
- 238000001514 detection method Methods 0.000 claims description 12
- 238000004590 computer program Methods 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 description 28
- 238000010586 diagram Methods 0.000 description 18
- RZKYEQDPDZUERB-UHFFFAOYSA-N Pindone Chemical compound C1=CC=C2C(=O)C(C(=O)C(C)(C)C)C(=O)C2=C1 RZKYEQDPDZUERB-UHFFFAOYSA-N 0.000 description 11
- 238000004891 communication Methods 0.000 description 8
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- 238000012544 monitoring process Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Abstract
The embodiment of the disclosure discloses a charging abnormity alarm circuit, a method, a device, electronic equipment and a storage medium, wherein the method comprises the following steps: the device comprises a battery charging management circuit, a power supply switching circuit, a power supply circuit, an ADC sampling circuit, a USB interface circuit and a CPU processor; the USB interface circuit is used for connecting an external charger power supply; the battery charging control circuit realizes battery charging management; the power supply switching circuit switches the system power supply between an external battery and an external charger power supply; the power supply circuit provides a stable 3.3v working power supply for the CPU processor; the ADC sampling circuit detects the input voltage of an external charger power supply port and transmits the input voltage to the CPU processor; and the CPU processor judges whether the current charging state is normal or not through the detected charging state signal, the detected charging completion signal and the detected input voltage of the ADC sampling circuit.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of electronic circuits, in particular to a charging abnormity alarm circuit, a charging abnormity alarm method, a charging abnormity alarm device, electronic equipment and a storage medium.
Background
At present, the POS machine is charged by adopting a charger with 5V voltage mostly, a charging interface is consistent with a mobile phone charger, and the mobile phone charger on the default market can be used for charging the POS machine, so that no monitoring or early warning prompt is generated when the voltage of the charger is higher than the abnormal voltage.
In recent years, the mobile phone charging technology enters a quick charging age, a mobile phone charger can simultaneously support three charging voltage modes of 5V, 9V and 10V, and when the mobile phone charger charges a POS, and once the charger works abnormally, the mobile phone charger enters the 9V or 10V mode by default, the POS machine is abnormally charged or damaged; at present, a large number of 5V chargers or mobile phone chargers exist in the market, and many of the chargers have the condition of high voltage, and the chargers charge the POS machine, so that the POS machine is also abnormal or damaged in charging.
Therefore, a solution is needed to detect if the charging voltage of the electronic device exceeds a set value and give an early warning when it exceeds.
Disclosure of Invention
The embodiment of the disclosure provides a charging abnormity alarm circuit, a charging abnormity alarm method, a charging abnormity alarm device, electronic equipment and a storage medium.
In a first aspect, in an embodiment of the present disclosure, there is provided a charging anomaly alarm circuit, including: the device comprises a battery charging management circuit, a power supply switching circuit, a 3.3v power supply circuit, an ADC sampling circuit, a USB interface circuit and a CPU processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the USB interface circuit is used for being accessed by an external charger power supply VBUS;
the battery charging control circuit is used for realizing battery charging management, starting charging after detecting that an external charger power supply VBUS is inserted, and outputting a charging state signal and a charging completion signal to the CPU processor;
the power supply switching circuit is used for switching the power supply of the system between an external battery and an external charger power supply VBUS;
the 3.3v power supply circuit is used for providing a stable 3.3v working power supply for the CPU processor;
the ADC sampling circuit is used for detecting the input voltage of an external charger power port and transmitting the input voltage to the CPU;
and the CPU processor judges whether the current charging state is normal or not through the detected charging state signal and the detected charging completion signal output by the battery charging control circuit and the detected input voltage output by the ADC sampling circuit, and outputs alarm information under the condition that the current charging state is abnormal.
Further, in the power-on state, when the external charger power supply VBUS is not connected to the USB interface circuit, the CPU processor outputs a high-level signal to the power supply circuit, so as to keep the power supply circuit to provide a stable system power supply through a battery; in a starting state, after an external charger power supply VBUS is connected to the USB interface circuit, the CPU processor detects the connection of the external charger power supply VBUS through the USB interface circuit, and the power supply switching circuit switches a system power supply from an external battery to the external charger power supply VBUS; the external charger power supply VBUS outputs a high-level enable signal to the battery charge control circuit, thereby starting the battery charge control circuit.
Further, in the device shutdown state, after the external charger power VBUS is connected to the USB interface circuit, the power supply source switching circuit switches the power supply source of the system power VSYS from the external battery to the external charger power VBUS, and the external charger power VBUS is connected to the power supply circuit, so that the power supply circuit is started to output a stable 3.3V power to the CPU processor.
Further, the CPU processor receives a charging state signal and a charging completion signal which are output by the battery charging control circuit, and when the CPU processor detects that the charging state signal is at a low level and the charging completion signal is at a high level, the battery charging control circuit is determined to be in a normal charging state; and when the CPU processor detects that the charging state signal is high level and the charging completion signal is high level, the battery charging control circuit is determined to be in an abnormal charging state, and when the CPU processor detects that the voltage of the external charger power supply exceeds a preset threshold value through the ADC sampling circuit, warning information is displayed through the equipment display module.
Further, the battery charge control circuit includes: the first chip U1, the first resistor R5, the second resistor R6, the third resistor R7, the fourth resistor R128, the fifth resistor R129, the sixth resistor R130 and the first capacitor C1, wherein:
one end of the first resistor R1 is connected with an external charger power supply VBUS, and the other end of the first resistor R1 is connected with an enabling pin CE of the first chip U1;
one end of the second resistor R2 is connected with a current control pin PROG of the first chip U1, and the other end of the second resistor R is grounded;
one end of the third resistor R3 is connected with the charge state output pin CHRG of the first chip U1, and the other end of the third resistor R3 is simultaneously connected with the charge state pin interface GPIO2 of the CPU processor and one end of the sixth resistor R6; the charging state output pin GPIO2 of the first chip U1 outputs the charging state signal; the charging state output pin GPIO2 of the first chip U1 outputs a low level to indicate that charging is performed, and outputs a high level to indicate that charging is not performed;
one end of the fourth resistor R4 is connected with the charging completion output pin DONE of the first chip U1, and the other end of the fourth resistor R4 is simultaneously connected with the charging completion pin interface GPIO3 of the CPU processor and one end of the fifth resistor R5; the charging completion output pin DONE of the first chip U1 outputs the charging completion signal; the charging completion output pin DONE of the first chip U1 outputs a low level to indicate that charging is normal, and outputs a high level to indicate that charging is not completed;
one end of the first capacitor C1 is connected with an external charger power supply VBUS and a power supply input pin VCC of the first chip U1, and the other end of the first capacitor C is grounded;
the battery pin BAT of the first chip U1 is connected with an external battery end VBAT;
the battery charging control circuit pulls up the enable pin CE of the first chip U1 through the insertion of the external charger power supply VBUS, so that the first chip U1 starts charging.
Further, the power supply switching circuit includes: the first diode D1, the first MOS transistor Q1, the seventh resistor R7 and the eighth resistor R8; wherein, the liquid crystal display device comprises a liquid crystal display device,
the positive electrode of the first diode D1 is connected with an external charger power supply VBUS, and the negative electrode of the first diode D1 is connected with the source electrode of the first MOS transistor Q1 and the 4.2V voltage end VYSY;
the drain electrode of the first MOS tube Q1 is connected with an external battery end VBAT, and the grid electrode of the first MOS tube Q1 is connected with one end of a seventh resistor R7;
the other end of the seventh resistor R7 is connected with an external charger power supply VBUS;
one end of the eighth resistor R8 is connected with an external charger power supply VBUS, and the other end of the eighth resistor R8 is grounded.
Further, the power supply circuit includes: the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the ninth resistor R9, the tenth resistor R10, the second diode D2 and the second chip U2, wherein:
one end of the second capacitor C2 is grounded, and the other end of the second capacitor C2 is connected with the 4.2V voltage end VSYS and the input end Vin of the second chip U2;
one end of the ninth resistor R9 is connected with an external charger power supply VBUS, and the other end of the ninth resistor R9 is connected with the A1 end of the second diode D2;
the end A2 of the second diode D2 is connected with a control enabling signal VDD33OUT of the CPU processor, and the other end of the second diode D2 is connected with an enabling pin CE of the second chip U2, one end of a tenth resistor R10 and one end of a fifth capacitor C5;
the other ends of the tenth resistor R10 and the fifth capacitor C5 are grounded;
one end of the third capacitor C3 and one end of the fourth capacitor C4 are connected with the output end Vout of the second chip U2 and the 3.3 volt voltage end V3.3, and the other end of the third capacitor C4 is grounded;
the power supply circuit pulls up the enable pin CE of the second chip U2 through the insertion of the external charger power supply VBUS, so that the second chip U2 can output a 3.3V power supply for the CPU processor to work.
Further, the USB interface circuit includes: an eleventh resistor R11 and a USB interface seat J1; wherein:
one end of the eleventh resistor R11 is connected with a pin of the USB interface seat J1 connected with an external charger power supply VBUS, and the other end of the eleventh resistor R is connected with an external USB power supply detection pin VUSB of the CPU processor; when the external charger power supply VBUS is inserted into the USB interface socket J1, the external USB power supply detection pin VUSB of the CPU processor is pulled high by the connection action of the eleventh resistor R11, and the CPU processor detects that the external charger power supply VBUS has been inserted.
Further, the ADC sampling circuit includes: a twelfth resistor R12 and a thirteenth resistor R13, wherein:
one end of the twelfth resistor R12 is connected with an external charger power supply VBUS, the other end of the twelfth resistor R12 is connected with one end of the thirteenth resistor R13, and an ADC detection signal input pin VBUS_ADC of the CPU processor;
one end of the thirteenth resistor R13 is connected with one end of the twelfth resistor R12, and the other end of the thirteenth resistor R13 is grounded.
In a second aspect, in an embodiment of the disclosure, a POS machine is provided, including a charging anomaly alarm circuit according to the first aspect.
In a third aspect, an embodiment of the present disclosure provides a method for alarming charge abnormality, including:
detecting an input signal; the input signals include a charge state signal and a charge completion signal received from a battery charge control circuit;
when the charging completion signal is detected to be at a high level, if the charging state signal is detected to be at a low level, determining that the battery charging control circuit is in a normal charging state;
when the charging completion signal is detected to be at a low level, if the charging state signal is detected to be at a high level, determining that the battery charging control circuit is in a charging end state;
when the charging completion signal is detected to be at a high level, if the charging state signal is detected to be at a high level, determining that the battery charging control circuit is in an abnormal charging state;
detecting the output voltage of the ADC sampling circuit after determining that the battery charge control circuit is in an abnormal charge state;
and when the output voltage of the ADC sampling circuit is larger than a preset threshold value, outputting alarm information of abnormal charging.
In a fourth aspect, in an embodiment of the present disclosure, there is provided a charging abnormality alarm device including:
a first detection module configured to detect an input signal; the input signals include a charge state signal and a charge completion signal received from a battery charge control circuit;
a first determination module configured to determine that the battery charge control circuit is in a normal charge state if the charge state signal is detected to be a low level when the charge completion signal is detected to be a high level;
a second determination module configured to determine that the battery charge control circuit is in a charge end state if the charge state signal is detected to be high level when the charge completion signal is detected to be low level;
a third determination module configured to determine that the battery charge control circuit is in an abnormal charge state if the charge state signal is detected to be high level when the charge completion signal is detected to be high level;
a second detection module configured to detect an output voltage of the ADC sampling circuit after determining that the battery charge control circuit is in an abnormal charge state;
and the alarm module is configured to output alarm information of abnormal charging when the output voltage of the ADC sampling circuit is greater than a preset threshold value.
The functions may be implemented by hardware, or may be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the functions described above.
In one possible design, the structure of the above apparatus includes a memory for storing one or more computer instructions for supporting the above apparatus to perform the corresponding method, and a processor configured to execute the computer instructions stored in the memory. The apparatus may further comprise a communication interface for the apparatus to communicate with other devices or a communication network.
In a fifth aspect, embodiments of the present disclosure provide an electronic device comprising a memory for storing one or more computer instructions supporting any of the apparatus for performing the corresponding method described above, and a processor configured to execute the computer instructions stored in the memory. Any of the above-described apparatuses may further include a communication interface for communicating with other devices or a communication network.
In a sixth aspect, embodiments of the present disclosure provide a computer-readable storage medium storing computer instructions for use by any one of the above-described apparatuses, comprising computer instructions for performing any one of the above-described methods.
In a seventh aspect, embodiments of the present disclosure provide a computer program product comprising computer instructions for implementing the steps of the method of any one of the above aspects when executed by a processor.
The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects:
according to the embodiment of the disclosure, the monitoring of the high abnormality of the charging voltage of the POS machine is realized by combining a hardware circuit with software logic; the POS machine equipment can be prevented from being abnormally damaged, friendly prompts are provided for users, and the users can replace chargers in time, so that normal business development is guaranteed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of embodiments of the disclosure.
Drawings
Other features, objects and advantages of the embodiments of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:
fig. 1 illustrates a schematic configuration diagram of a charge abnormality alarm circuit according to an embodiment of the present disclosure;
fig. 2 shows a circuit configuration diagram of a battery charge control circuit according to an embodiment of the present disclosure;
fig. 3 shows a circuit configuration diagram of a power supply switching circuit according to an embodiment of the present disclosure;
FIG. 4 shows a circuit block diagram of a 3.3V power supply circuit according to an embodiment of the present disclosure;
FIG. 5 shows a circuit block diagram of a USB interface circuit according to an embodiment of the present disclosure;
FIG. 6 shows a circuit configuration diagram of an ADC sampling circuit according to an embodiment of the present disclosure;
FIG. 7 illustrates a flow chart of a charge anomaly alarm method according to an embodiment of the present disclosure;
fig. 8 shows a block diagram of a charging abnormality warning apparatus according to an embodiment of the present disclosure;
fig. 9 is a schematic structural view of an electronic device suitable for use in implementing a charge abnormality warning method according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, exemplary implementations of the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, portions irrelevant to description of the exemplary embodiments are omitted in the drawings.
In the presently disclosed embodiments, it is to be understood that the terms such as "comprises" or "comprising" and the like are intended to indicate the presence of features, numbers, steps, acts, components, portions, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility of one or more other features, numbers, steps, acts, components, portions, or combinations thereof being present or added.
In addition, it should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other. Embodiments of the present disclosure will be described in detail below with reference to the attached drawings in conjunction with the embodiments.
Fig. 1 shows a schematic diagram of a charging anomaly alarm circuit according to an embodiment of the present disclosure, where the charging anomaly alarm circuit is located within an electronic device, which may be a handheld electronic device, such as a POS machine, or the like. As shown in fig. 1, the abnormal charging alarm circuit comprises a battery charging management circuit, a power supply switching circuit, a 3.3v power supply circuit, an ADC sampling circuit, a USB interface circuit and a CPU processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the USB interface circuit is used for being accessed by an external charger power supply VBUS;
the battery charging control circuit is used for realizing battery charging management, starting charging after detecting that an external charger power supply VBUS is inserted, and outputting a charging state signal and a charging completion signal to the CPU processor;
the power supply switching circuit is used for switching the power supply of the system between an external battery and an external charger power supply VBUS;
the 3.3v power supply circuit is used for providing a stable 3.3v working power supply for the CPU processor;
the ADC sampling circuit is used for detecting the input voltage of an external charger power port and transmitting the input voltage to the CPU;
and the CPU processor judges whether the current charging state is normal or not through the detected charging state signal and the detected charging completion signal output by the battery charging control circuit and the detected input voltage output by the ADC sampling circuit, and outputs alarm information under the condition that the current charging state is abnormal.
Fig. 2 shows a circuit configuration diagram of a battery charge control circuit according to an embodiment of the present disclosure, as shown in fig. 2, in an embodiment of the present invention, the battery charge control circuit includes: the first chip U1, the first resistor R5, the second resistor R6, the third resistor R7, the fourth resistor R128, the fifth resistor R129, the sixth resistor R130 and the first capacitor C1, wherein:
one end of the first resistor R1 is connected with an external charger power supply VBUS, and the other end of the first resistor R1 is connected with an enabling pin CE of the first chip U1;
one end of the second resistor R2 is connected with a current control pin PROG of the first chip U1, and the other end of the second resistor R is grounded;
one end of the third resistor R3 is connected with the charge state output pin CHRG of the first chip U1, and the other end of the third resistor R3 is simultaneously connected with the charge state pin interface GPIO2 of the CPU processor and one end of the sixth resistor R6; the charging state output pin GPIO2 of the first chip U1 outputs the charging state signal; the charging state output pin GPIO2 of the first chip U1 outputs a low level to indicate that charging is performed, and outputs a high level to indicate that charging is not performed;
one end of the fourth resistor R4 is connected with the charging completion output pin DONE of the first chip U1, and the other end of the fourth resistor R4 is simultaneously connected with the charging completion pin interface GPIO3 of the CPU processor and one end of the fifth resistor R5; the charging completion output pin DONE of the first chip U1 outputs the charging completion signal; the charging completion output pin DONE of the first chip U1 outputs a low level to indicate that charging is normal, and outputs a high level to indicate that charging is not completed;
one end of the first capacitor C1 is connected with an external charger power supply VBUS and a power supply input pin VCC of the first chip U1, and the other end of the first capacitor C is grounded;
the battery pin BAT of the first chip U1 is connected with an external battery end VBAT;
the battery charging control circuit pulls up the enable pin CE of the first chip U1 through the insertion of the external charger power supply VBUS, so that the first chip U1 starts charging.
Fig. 3 shows a circuit configuration diagram of a power supply switching circuit according to an embodiment of the present disclosure, and as shown in fig. 3, in an embodiment of the present invention, the power supply switching circuit includes: the first diode D1, the first MOS transistor Q1, the seventh resistor R7 and the eighth resistor R8; wherein, the liquid crystal display device comprises a liquid crystal display device,
the positive electrode of the first diode D1 is connected with an external charger power supply VBUS, and the negative electrode of the first diode D1 is connected with the source electrode of the first MOS transistor Q1 and the 4.2V voltage end VSYS;
the drain electrode of the first MOS tube Q1 is connected with an external battery end VBAT, and the grid electrode of the first MOS tube Q1 is connected with one end of a seventh resistor R7;
the other end of the seventh resistor R7 is connected with an external charger power supply VBUS;
one end of the eighth resistor R8 is connected with an external charger power supply VBUS, and the other end of the eighth resistor R8 is grounded.
Fig. 4 shows a circuit configuration diagram of a 3.3V power supply circuit according to an embodiment of the present disclosure, as shown in fig. 4, in an embodiment of the present invention, the 3.3V power supply circuit includes: the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the ninth resistor R9, the tenth resistor R10, the second diode D2 and the second chip U2, wherein:
one end of the second capacitor C2 is grounded, and the other end of the second capacitor C2 is connected with the 4.2V voltage end VSYS and the input end Vin of the second chip U2;
one end of the ninth resistor R9 is connected with an external charger power supply VBUS, and the other end of the ninth resistor R9 is connected with the A1 end of the second diode D2;
the end A2 of the second diode D2 is connected with a control enabling signal VDD33OUT of the CPU processor, and the other end of the second diode D2 is connected with an enabling pin CE of the second chip U2, one end of a tenth resistor R10 and one end of a fifth capacitor C5;
the other ends of the tenth resistor R10 and the fifth capacitor C5 are grounded;
one end of the third capacitor C3 and one end of the fourth capacitor C4 are connected with the output end Vout of the second chip U2 and the 3.3 volt voltage end V3.3, and the other end of the third capacitor C4 is grounded;
the power supply circuit pulls up the enable pin CE of the second chip U2 through the insertion of the external charger power supply VBUS, so that the second chip U2 can output a 3.3V power supply for the CPU processor to work.
Fig. 5 shows a circuit configuration diagram of a USB interface circuit according to an embodiment of the present disclosure, and as shown in fig. 5, in an embodiment of the present invention, the USB interface circuit includes: an eleventh resistor R11 and a USB interface seat J1;
one end of the eleventh resistor R11 is connected with a pin of the USB interface seat J1 connected with an external charger power supply VBUS, and the other end of the eleventh resistor R is connected with an external USB power supply detection pin VUSB of the CPU processor; when the external charger power supply VBUS is inserted into the USB interface socket J1, the external USB power supply detection pin VUSB of the CPU processor is pulled high by the connection action of the eleventh resistor R11, and the CPU processor detects that the external charger power supply VBUS has been inserted.
Fig. 6 shows a circuit configuration diagram of an ADC sampling circuit according to an embodiment of the disclosure, as shown in fig. 6, in an embodiment of the invention, the ADC sampling circuit includes: a twelfth resistor R12 and a thirteenth resistor R13, wherein:
one end of the twelfth resistor R12 is connected with an external charger power supply VBUS, the other end of the twelfth resistor R12 is connected with one end of the thirteenth resistor R13, and an ADC detection signal input pin VBUS_ADC of the CPU processor;
one end of the thirteenth resistor R13 is connected with one end of the twelfth resistor R12, and the other end of the thirteenth resistor R13 is grounded.
In some embodiments, in a power-on state, when the external charger power VBUS is not connected to the USB interface circuit, the CPU processor outputs a high level signal to the power supply circuit, so as to keep the power supply circuit to provide a stable system power through a battery; in a starting state, after an external charger power supply VBUS is connected to the USB interface circuit, the CPU processor detects the connection of the external charger power supply VBUS through the USB interface circuit, and the power supply switching circuit switches a system power supply from an external battery to the external charger power supply VBUS; the external charger power supply VBUS outputs a high-level enable signal to the battery charge control circuit, thereby starting the battery charge control circuit.
In other embodiments, after the external charger power VBUS is connected to the USB interface circuit in the device shutdown state, the power supply source switching circuit switches the power supply source of the system power VSYS from the external battery to the external charger power VBUS, and the external charger power VBUS is connected to the power supply circuit, so that the power supply circuit is started to output a stable 3.3V power to the CPU processor.
The CPU processor receives a charging state signal and a charging completion signal which are output by the battery charging control circuit, and when the CPU processor detects that the charging state signal is in a low level and the charging completion signal is in a high level, the battery charging control circuit is determined to be in a normal charging state; and when the CPU processor detects that the charging state signal is high level and the charging completion signal is high level, the battery charging control circuit is determined to be in an abnormal charging state, and when the CPU processor detects that the voltage of the external charger power supply exceeds a preset threshold value through the ADC sampling circuit, warning information is displayed through the equipment display module.
In this alternative implementation, VDD33OUT output by the CPU is high in the device on state for maintaining 3.3V system power. If the external charger power supply VBUS is plugged in at the moment, the CPU acquires that the USB is in the plugged-in state through a VUSB pin of the CPU, and the VUSB pin is connected with the USB interface circuit.
The system power VSYS will also be switched from the external battery to the external charger power VBUS by the power supply switching circuit. VBUS pulls up the enabling of the charging integrated circuit chip U1 in the battery charging control circuit, namely the first chip, through the connection of R5, and the working state of U1 is started. The CPU is respectively connected with a charging state output pin CHRG of U1 and a charging completion output pin DONE of U1 through two pins of GPIO2 and GPIO3, receives the output levels of the charging state output pins CHRG and the charging completion output pin DONE of U1, and when the CPU detects that the charging state output pin CHRG of U1 outputs a low level through GPIO2 and the charging completion output pin DONE of U1 outputs a high level through GPIO3, the CPU indicates that the charging management circuit is in a normal charging state at the moment, and software running on the CPU normally prompts the charging process through the display module. If GPIO2 detects a high level and GPIO3 detects a high level at this time, this indicates that the charge is abnormal at this time (VBUS is in place at this time). The CPU collects VBUS voltage through the ADC collecting circuit to exceed 6.0V, and at the moment, warning information can be prompted through a display module on the electronic equipment.
In the equipment shutdown state, the external charger power supply is directly inserted, at the moment, the power supply source of the system power supply VSYS is switched into the external charger power supply VBUS from an external battery by the power supply switching circuit, the external charger power supply VBUS is connected with the diode D2 through the resistor R12, the enabling pin CE of the second chip U2 in the power supply circuit is pulled up, and the U2 outputs stable 3.3V power to the CPU processor. After the CPU processor is normally started, the output level of the charging completion output pin DONE of the charging state output pin CHRG of the first chip U1 and the charging completion output pin DONE of the first chip U1 are detected respectively, and when the GPIO2 detects low and the GPIO3 detects high, the state is indicated to be in a normal charging state at the moment. When GPIO2 detects high and GPIO3 detects high, the charging is abnormal, the VBUS voltage is detected through the ADC acquisition circuit, and the voltage exceeds more than 6.0V, so that the input voltage of the USB interface is excessively high. At this time, the warning message is prompted by the display module.
FIG. 7 illustrates a flow chart of a charge anomaly alarm method performed on the charge anomaly alarm circuit shown in FIG. 1, according to an embodiment of the present disclosure; as shown in fig. 7, the charge abnormality warning method includes the steps of:
in step S701, an input signal is detected; the input signals include a charge state signal and a charge completion signal received from a battery charge control circuit;
in step S702, when the charging completion signal is detected to be at a high level, if the charging state signal is detected to be at a low level, it is determined that the battery charging control circuit is in a normal charging state;
in step S703, when the charge completion signal is detected to be low level, if the charge state signal is detected to be high level, it is determined that the battery charge control circuit is in a charge end state;
in step S704, when the charging completion signal is detected to be at a high level, if the charging state signal is detected to be at a high level, it is determined that the battery charging control circuit is in an abnormal charging state;
in step S705, after determining that the battery charge control circuit is in an abnormal charge state, detecting an output voltage of an ADC sampling circuit;
in step S706, when the output voltage of the ADC sampling circuit is greater than a preset threshold, alarm information of abnormal charging is output.
In some embodiments, the alert information may include, but is not limited to: equipment risk, too high charging voltage, charger replacement and other information.
For specific details of the charge abnormality warning circuit, reference may be made to the description of the embodiments shown in fig. 1 to 6 above, and no further description is given here.
In some embodiments, the charge anomaly alarm circuit and method are implemented in POS devices.
According to the embodiment of the disclosure, the monitoring of the high abnormality of the charging voltage of the POS machine is realized by combining a hardware circuit with software logic; the POS machine equipment can be prevented from being abnormally damaged, friendly prompts are provided for users, and the users can replace chargers in time, so that normal business development is guaranteed.
The following are device embodiments of the present disclosure that may be used to perform method embodiments of the present disclosure.
Fig. 8 shows a block diagram of a charging abnormality alarm device according to an embodiment of the present disclosure, which may be implemented as part or all of an electronic device by software, hardware, or a combination of both. The charge abnormality warning device is located in the charge abnormality warning circuit shown in fig. 1. As shown in fig. 8, the charge abnormality warning apparatus includes:
a first detection module 801 configured to detect an input signal; the input signals include a charge state signal and a charge completion signal received from a battery charge control circuit;
a first determining module 802 configured to determine that the battery charge control circuit is in a normal charge state if the charge state signal is detected to be low level when the charge completion signal is detected to be high level;
a second determining module 803 configured to determine that the battery charge control circuit is in a charge end state if the charge state signal is detected to be high level when the charge completion signal is detected to be low level;
a third determining module 804 configured to determine that the battery charge control circuit is in an abnormal charge state if the charge state signal is detected to be high level when the charge completion signal is detected to be high level;
a second detection module 805 configured to detect an output voltage of the ADC sampling circuit after determining that the battery charge control circuit is in an abnormal charge state;
and an alarm module 806 configured to output alarm information of abnormal charging when the output voltage of the ADC sampling circuit is greater than a preset threshold.
The charging abnormality alarm device in this embodiment corresponds to the charging abnormality alarm method described above, and specific details may be found in the description of the charging abnormality alarm device described above, which is not repeated here.
Fig. 9 is a schematic structural view of an electronic device suitable for use in implementing a charge abnormality warning method according to an embodiment of the present disclosure.
As shown in fig. 9, the electronic apparatus 900 includes a processing unit 901 that can execute various processes in the above-described embodiments in accordance with a program stored in a Read Only Memory (ROM) 902 or a program loaded from a storage portion 908 into a Random Access Memory (RAM) 903. In the RAM903, various programs and data necessary for the operation of the electronic device 900 are also stored. The processing unit 901, the ROM902, and the RAM903 are connected to each other by a bus 904. An input/output (I/O) interface 905 is also connected to the bus 904.
The following components are connected to the I/O interface 905: an input section 906 including a keyboard, a mouse, and the like; an output portion 907 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and a speaker; a storage portion 908 including a hard disk or the like; and a communication section 909 including a network interface card such as a LAN card, a modem, or the like. The communication section 909 performs communication processing via a network such as the internet. The drive 910 is also connected to the I/O interface 905 as needed. A removable medium 911 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is installed as needed on the drive 910 so that a computer program read out therefrom is installed into the storage section 908 as needed. The processing unit 901 may be implemented as a processing unit such as CPU, GPU, TPU, FPGA, NPU.
In particular, according to embodiments of the present disclosure, the methods described above may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program tangibly embodied on a medium readable thereby, the computer program comprising program code for performing the data transmission method. In such an embodiment, the computer program may be downloaded and installed from the network through the communication section 909, and/or installed from the removable medium 911.
The disclosed embodiments also disclose a computer program product comprising a computer program/instructions which, when executed by a processor, implement any of the method steps described above.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units or modules described in the embodiments of the present disclosure may be implemented by software, or may be implemented by hardware. The units or modules described may also be provided in a processor, the names of which in some cases do not constitute a limitation of the unit or module itself.
As another aspect, the embodiments of the present disclosure also provide a computer-readable storage medium, which may be a computer-readable storage medium included in the apparatus described in the above-described embodiment; or may be a computer-readable storage medium, alone, that is not assembled into a device. The computer-readable storage medium stores one or more programs for use by one or more processors in performing the methods described in the embodiments of the present disclosure.
The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by those skilled in the art that the scope of the invention in the embodiments of the present disclosure is not limited to the specific combination of the above technical features, but encompasses other technical features formed by any combination of the above technical features or their equivalents without departing from the inventive concept. Such as the technical solution formed by mutually replacing the above-mentioned features and the technical features with similar functions (but not limited to) disclosed in the embodiments of the present disclosure.
Claims (10)
1. A charging abnormality alarm circuit comprising: the device comprises a battery charging management circuit, a power supply switching circuit, a 3.3v power supply circuit, an ADC sampling circuit, a USB interface circuit and a CPU processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the USB interface circuit is used for being accessed by an external charger power supply VBUS;
the battery charging control circuit is used for realizing battery charging management, starting charging after detecting that an external charger power supply VBUS is inserted, and outputting a charging state signal and a charging completion signal to the CPU processor;
the power supply switching circuit is used for switching the power supply of the system between an external battery and an external charger power supply VBUS;
the 3.3v power supply circuit is used for providing a stable 3.3v working power supply for the CPU processor;
the ADC sampling circuit is used for detecting the input voltage of an external charger power port and transmitting the input voltage to the CPU;
and the CPU processor judges whether the current charging state is normal or not through the detected charging state signal and the detected charging completion signal output by the battery charging control circuit and the detected input voltage output by the ADC sampling circuit, and outputs alarm information under the condition that the current charging state is abnormal.
2. The circuit of claim 1, wherein in a power-on state, when an external charger supply VBUS is not connected to the USB interface circuit, the CPU processor outputs a high level signal to the power supply circuit to keep the power supply circuit to provide a stable system power supply through a battery; in a starting state, after an external charger power supply VBUS is connected to the USB interface circuit, the CPU processor detects the connection of the external charger power supply VBUS through the USB interface circuit, and the power supply switching circuit switches a system power supply from an external battery to the external charger power supply VBUS; the external charger power supply VBUS outputs a high-level enable signal to the battery charge control circuit, thereby starting the battery charge control circuit.
3. The circuit of claim 1, wherein the power supply switching circuit switches a power supply source of the system power supply VSYS from an external battery to the external charger power supply VBUS after the external charger power supply VBUS is connected to the USB interface circuit in a device shutdown state, and the external charger power supply VBUS is connected to the power supply circuit, and the power supply circuit is started so that the power supply circuit outputs a stable 3.3V power supply to the CPU processor.
4. A circuit according to any one of claims 1 to 3, wherein the CPU processor receives a charge state signal and a charge completion signal output by the battery charge control circuit, and determines that the battery charge control circuit is in a normal charge state when the CPU processor detects that the charge state signal is low and the charge completion signal is high; and when the CPU processor detects that the charging state signal is high level and the charging completion signal is high level, the battery charging control circuit is determined to be in an abnormal charging state, and when the CPU processor detects that the voltage of the external charger power supply exceeds a preset threshold value through the ADC sampling circuit, warning information is displayed through the equipment display module.
5. A POS machine comprising the charge anomaly alarm circuit of any one of claims 1-4.
6. A charging abnormality alarm method, comprising:
detecting an input signal; the input signals include a charge state signal and a charge completion signal received from a battery charge control circuit;
when the charging completion signal is detected to be at a high level, if the charging state signal is detected to be at a low level, determining that the battery charging control circuit is in a normal charging state;
when the charging completion signal is detected to be at a low level, if the charging state signal is detected to be at a high level, determining that the battery charging control circuit is in a charging end state;
when the charging completion signal is detected to be at a high level, if the charging state signal is detected to be at a high level, determining that the battery charging control circuit is in an abnormal charging state;
detecting the output voltage of the ADC sampling circuit after determining that the battery charge control circuit is in an abnormal charge state;
and when the output voltage of the ADC sampling circuit is larger than a preset threshold value, outputting alarm information of abnormal charging.
7. A charging abnormality warning device, comprising:
a first detection module configured to detect an input signal; the input signals include a charge state signal and a charge completion signal received from a battery charge control circuit;
a first determination module configured to determine that the battery charge control circuit is in a normal charge state if the charge state signal is detected to be a low level when the charge completion signal is detected to be a high level;
a second determination module configured to determine that the battery charge control circuit is in a charge end state if the charge state signal is detected to be high level when the charge completion signal is detected to be low level;
a third determination module configured to determine that the battery charge control circuit is in an abnormal charge state if the charge state signal is detected to be high level when the charge completion signal is detected to be high level;
a second detection module configured to detect an output voltage of the ADC sampling circuit after determining that the battery charge control circuit is in an abnormal charge state;
and the alarm module is configured to output alarm information of abnormal charging when the output voltage of the ADC sampling circuit is greater than a preset threshold value.
8. An electronic device includes a memory and a processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory is configured to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the steps of the method of claim 6.
9. A computer readable storage medium having stored thereon computer instructions, wherein the computer instructions, when executed by a processor, implement the steps of the method of claim 6.
10. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method of claim 6.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310589477.7A CN116742743A (en) | 2023-05-24 | 2023-05-24 | Charging abnormality alarm circuit, method, device, electronic apparatus, and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310589477.7A CN116742743A (en) | 2023-05-24 | 2023-05-24 | Charging abnormality alarm circuit, method, device, electronic apparatus, and storage medium |
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| CN116742743A true CN116742743A (en) | 2023-09-12 |
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| CN202310589477.7A Pending CN116742743A (en) | 2023-05-24 | 2023-05-24 | Charging abnormality alarm circuit, method, device, electronic apparatus, and storage medium |
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| Country | Link |
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| CN (1) | CN116742743A (en) |
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