CN116722844A

CN116722844A - Miller platform determining method and system, power tube driving method and integrated chip

Info

Publication number: CN116722844A
Application number: CN202310529635.XA
Authority: CN
Inventors: 闵闰; 张凯; 童乔凌; 张德生; 彭晗; 周傲松; 张文佳
Original assignee: Huazhong University of Science and Technology
Current assignee: Huazhong University of Science and Technology
Priority date: 2023-05-11
Filing date: 2023-05-11
Publication date: 2023-09-08

Abstract

The invention provides a miller platform determining method and system, a power tube driving method and an integrated chip; the sampling and analog-to-digital conversion of the gate source voltage in the power tube conduction stage are controlled through M groups of phase-shifting pulse groups and a second clock signal; each phase-shifting pulse group corresponds to one on-off period of the power tube; each phase-shifting pulse group comprises n phase-shifting pulses which are adjacent in sequence, and the serial numbers of the phase-shifting pulses of the adjacent phase-shifting pulse groups are continuous; sequentially performing back-to-front comparison on digital level signals obtained by sampling and digital-to-analog conversion, judging whether the time sequence of a first group of phase-shifting pulse groups is matched with the waveform of the gate source voltage according to comparison results, and acquiring digital level signals corresponding to a Miller platform stage in a conduction stage of the power tube, namely first voltage signals; repeating the sampling and the analog-to-digital conversion, and comparing the digital level signals obtained by the sampling and the digital-to-analog conversion with the first voltage signals in sequence to determine the starting point position of the miller platform and the end point position of the miller platform.

Description

Miller platform determining method and system, power tube driving method and integrated chip

Technical Field

The field relates to the field of integrated circuits, in particular to a method and a system for determining a Miller platform, a power tube driving method and an integrated chip

Background

With the development of wide bandgap devices, gaN HEMTs have been developed and applied very rapidly in recent years because of their faster switching speed and switching frequency than Si MOSFETs, which can effectively increase the efficiency of power supply systems. However, the EMI problem and the switching loss problem of the GaN HEMT are more prominent due to the application in the faster switching speed and switching frequency scenarios. The conventional driving circuit is difficult to optimize the EMI problem and the switching loss problem of the GaN HEMT at the same time, so that the driving current of different stages in the driving process of the Si MOSFET needs to be controlled by adopting the multi-stage driving circuit, the driving current is reduced in the stage where the EMI problem occurs, and the driving current is increased in other stages, so that the voltage and current peak problem and the switching loss problem can be simultaneously optimized in the driving process of the GaN HEMT.

The EMI problem of a typical GaN HEMT during the on-phase typically occurs during the miller plateau, using high current conduction before and after the miller plateau occurs, and using low current conduction during the miller plateau can optimize both the voltage-current spike problem and the switching loss problem. Therefore, it is important to accurately find the starting point position and the end point position of the miller stage.

The prior art typically employs off-chip programming drive or on-chip drive control. The off-chip programming drive can realize dynamic and flexible drive control by manually programming the drive sequence, but a large amount of debugging is needed to obtain a proper drive sequence, so that the use is complex; existing on-chip drive control includes feed-forward drive and feedback drive; the feedforward driving is to monitor the gate-source voltage of the GaN HEMT to find the starting point position and the end point position of the Miller platform, and segment the GaN HEMT; however, the mode is sensitive to parasitic capacitance of the grid electrode, and the voltage oscillation of the grid electrode often causes a false triggering problem; the feedback driving is to monitor the drain-source voltage or drain-source current of the GaN HEMT to find out the starting position and the end position of the Miller platform, and to segment the GaN HEMT; however, due to the delay in the control loop, the driving state cannot be responded in time.

There is an urgent need for a method for precisely determining the start position and the end position of the miller platform and a corresponding GaN HEMT driving method.

Disclosure of Invention

The invention provides a miller platform determining method and system, a power tube driving method and an integrated chip, which are used for accurately positioning the starting point position and the end point position of the miller platform and conducting the power tube in stages with low delay according to the starting point position and the end point position of the miller platform.

According to a first aspect of the present invention, there is provided a miller stage determining method for determining a start position and an end position of a miller stage in a conducting stage of a power tube, the method comprising:

under the control of a driving enabling signal, periodically controlling the gate-source voltage loaded on the gate of the power tube so as to enable the power tube to be periodically turned on and turned off;

performing multipath phase shifting processing on a first clock signal between each rising edge interval of a phase shifting enabling signal to obtain M groups of phase shifting pulse groups; each group of phase-shifting pulses corresponds to one on-off period of the power tube; each phase-shifting pulse group comprises n phase-shifting pulses which are adjacent in sequence, and the serial numbers of the phase-shifting pulses of the adjacent phase-shifting pulse groups are continuous; wherein M, n is a positive integer, and M is greater than or equal to 16;

sampling the gate-source voltage of the power tube in the conduction stage, and performing analog-to-digital conversion on the sampling voltage corresponding to each phase-shifting pulse under the control of a second clock signal and all phase-shifting pulses of the M groups of phase-shifting pulse groups so as to obtain corresponding digital level signals;

selecting each digital level signal corresponding to each phase-shifting pulse in a first group of phase-shifting pulse groups, comparing the digital level signal corresponding to each phase-shifting pulse in the first group of phase-shifting pulse groups with the digital level signal corresponding to the previous adjacent phase-shifting pulse, and judging whether the time sequence of the first group of phase-shifting pulse groups is matched with the waveform of the gate source voltage; if the first group of phase-shifting pulse groups are not matched, adjusting the time sequence of the first group of phase-shifting pulse groups or the waveform of the gate-source voltage so that the time sequence of the first group of phase-shifting pulse groups is matched with the waveform of the gate-source voltage; the time sequence of the first group of phase-shifting pulse groups is matched with the waveform of the gate-source voltage, and the gate-source voltage corresponding to the first group of phase-shifting pulse groups is characterized as the gate-source voltage before the transistor enters the Miller platform;

Comparing the digital level signal corresponding to each phase-shifting pulse with the digital level signal corresponding to the previous adjacent phase-shifting pulse in the second group phase-shifting pulse group to the M group phase-shifting pulse group to acquire the digital level signal corresponding to the Miller stage of the power tube in the conduction stage; and taking the digital level signal as a first voltage signal;

and resampling and analog-to-digital converting the gate-source voltage of the power tube in the conducting stage according to the second clock signal and the M groups of phase-shifting pulse groups, and comparing the digital level signal corresponding to each gate-source voltage with the first voltage signal to determine the starting point position of the Miller platform and the end point position of the Miller platform.

Optionally, comparing the digital level signal corresponding to each phase-shift pulse in the first group of phase-shift pulse groups with the digital level signal corresponding to the previous adjacent phase-shift pulse specifically includes:

comparing the digital level signal corresponding to each phase-shift pulse in the first group of phase-shift pulse groups with the digital level signal corresponding to the previous adjacent phase-shift pulse; if the digital level signal corresponding to the current phase-shifting pulse is greater than the digital level signal corresponding to the previous adjacent phase-shifting pulse and the difference value between the two signals is greater than the second threshold signal, outputting a high level signal; if the digital level signal corresponding to the current phase-shifting pulse is smaller than or equal to the digital level signal corresponding to the previous adjacent phase-shifting pulse or the digital level signal corresponding to the current phase-shifting pulse is larger than the digital level signal corresponding to the previous adjacent phase-shifting pulse, but the difference value between the two signals is smaller than the second threshold value signal, outputting a low level signal;

And obtaining a first level signal group corresponding to the first group of phase-shifting pulse groups according to the comparison rule.

Optionally, determining whether the timing sequence of the first group of phase-shifting pulse groups matches the waveform of the gate-source voltage specifically includes:

if the first level signal in the first level signal group is low level and two continuous low levels exist, judging that the time sequence of the first group of phase-shifting pulse groups is not matched with the waveform of the gate-source voltage;

if a first level signal in the first level signal group is high level or two continuous high levels exist, judging that the time sequence of the first group of phase-shifting pulse groups is matched with the waveform of the gate-source voltage;

and if the continuous jump level signals appear in the first level signal group, discarding the digital level signals corresponding to the first group of phase-shifting pulse groups.

Optionally, after determining that the timing sequence of the first group of phase-shifting pulse groups does not match the waveform of the gate-source voltage, the method further includes:

comparing the digital level signal corresponding to the first phase-shift pulse in the first group of phase-shift pulses with a zero value; if the digital level signal is between zero and zero, judging that the time sequence of the first group of phase shifting pulse groups is advanced relative to the waveform of the grid source voltage; if the digital level signal is greater than the zero value, determining that the timing of the first set of phase-shifted pulse groups lags the waveform of the gate-source voltage.

Optionally, the acquiring of the driving enable signal and the phase shift enable signal specifically includes:

synchronizing a control signal input from the outside with the first clock signal to obtain a first enabling signal;

and obtaining the driving enabling signal and the phase shifting enabling signal according to the first enabling signal.

Optionally, adjusting the timing sequence of the first group of phase-shifting pulse groups or the waveform of the gate-source voltage specifically includes:

if the time sequence of the first group of phase-shifting pulse groups is judged to be advanced relative to the waveform of the gate-source voltage, the phase-shifting enabling signals are obtained after hysteresis processing is carried out on the first enabling signals, and the driving enabling signals are identical to the first enabling signals;

and if the time sequence of the first group of phase-shifting pulse groups is judged to be lagging relative to the waveform of the gate-source voltage, obtaining the driving enabling signal after carrying out lagging treatment on the first enabling signal, wherein the phase-shifting enabling signal is identical with the first enabling signal.

Optionally, comparing the digital level signal corresponding to each phase-shift pulse with the digital level signal corresponding to the previous adjacent phase-shift pulse in the second group phase-shift pulse group to the mth group phase-shift pulse group to obtain the first voltage signal, which specifically includes:

Each phase-shifting pulse group from the second group phase-shifting pulse group to the M group phase-shifting pulse group sequentially compares a digital level signal corresponding to the phase-shifting pulse in the group with a digital level signal corresponding to the previous adjacent phase-shifting pulse; the digital level signal corresponding to the first phase-shifting pulse in one phase-shifting pulse group is compared with the digital level signal corresponding to the last phase-shifting pulse in the previous adjacent phase-shifting pulse group; if the digital level signal corresponding to the current phase-shifting pulse is greater than the digital level signal corresponding to the previous adjacent phase-shifting pulse and the difference value between the digital level signal and the digital level signal is greater than a first threshold signal, outputting a high level signal; if the digital level signal corresponding to the current phase-shifting pulse is smaller than or equal to the digital level signal corresponding to the previous adjacent phase-shifting pulse or the digital level signal corresponding to the current phase-shifting pulse is larger than the digital level signal corresponding to the previous adjacent phase-shifting pulse, but the difference value between the two signals is smaller than the first threshold value signal, outputting a low level signal;

and stopping subsequent comparison after the first high-level signal is output, and selecting the intermediate value of the digital level signal corresponding to the phase-shifting pulse as the first voltage signal when the low-level signal is output before.

Optionally, comparing each of the digital level signals with the first voltage signal to determine a start position of the miller stage and an end position of the miller stage, specifically including:

and comparing each of said digital level signals with said first voltage signal:

will satisfy V first _s >V _pl -V _ths The phase-shifting pulse corresponding to the digital level signal is used as the starting point position of the miller platform; wherein: v (V) _s Is used for representing the digital level signal; v (V) _pl For characterizing the first voltage signal; v (V) _ths For characterizing the first threshold signal;

will satisfy V first _s >V _pl +V _ths The phase-shifted pulse corresponding to the digital level signal is used as the end position of the miller stage.

According to a second aspect of the present invention, there is provided a driving method of a power tube, the method comprising:

determining a starting point position and an end point position of a miller platform in a conducting stage of a power tube by using the miller platform determining method according to the first aspect and the optional embodiment of the invention;

aiming at a first conduction stage of the power tube, conducting control is carried out on the power tube by adopting a first conduction current; the first conduction stage is used for representing a stage of the power tube before a miller platform in a conduction process;

Aiming at a second conduction stage of the power tube, conducting control is carried out on the power tube by utilizing a second conduction current; the second conduction stage is used for representing a stage that the power tube goes through a starting point position to an end point position of the miller platform in a conduction process;

aiming at a third conduction stage of the power tube, conducting control is carried out on the power tube by utilizing a third conduction current; the third conduction stage is used for representing a stage of the power tube after the power tube passes through a miller platform in a conduction process;

wherein the third conduction current is greater than the first conduction current, and the first conduction current is greater than the second conduction current.

According to a third aspect of the present invention, there is provided a miller stage determination system for implementing the miller stage determination method according to the first aspect and the optional embodiment of the present invention, the system comprising:

the on-off control module is used for periodically controlling the gate source voltage loaded on the grid of the power tube under the control of a driving enabling signal so as to periodically turn on and off the power tube;

the phase-shifting pulse generation module is used for carrying out multipath phase-shifting processing on a first clock signal between each rising edge interval of a phase-shifting enabling signal so as to obtain M groups of phase-shifting pulse groups; each group of phase-shifting pulses corresponds to one on-off period of the power tube; each phase-shifting pulse group comprises n phase-shifting pulses which are adjacent in sequence, and the phase-shifting pulse groups of adjacent on-off periods are continuous in the same on-off period; wherein M, n is a positive integer, and M is greater than or equal to 16;

The digital-to-analog conversion module is coupled to the output end of the phase-shift pulse generation module; the digital-to-analog conversion module samples the gate-source voltage of the power tube in the conducting stage, and under the control of a second clock signal and all phase-shifting pulses of the M groups of phase-shifting pulse groups, the digital-to-analog conversion module carries out analog-to-digital conversion on the sampling voltage corresponding to each phase-shifting pulse to obtain a corresponding digital level signal;

the logic control module is coupled to the output end of the digital-to-analog conversion module; the logic control module is used for:

selecting each digital level signal corresponding to each phase-shifting pulse in a first group of phase-shifting pulse groups, comparing the digital level signal corresponding to each phase-shifting pulse in the first group of phase-shifting pulse groups with the digital level signal corresponding to the previous adjacent phase-shifting pulse, and judging whether the time sequence of the first group of phase-shifting pulse groups is matched with the waveform of the gate source voltage; if the first group of phase-shifting pulse groups are not matched, adjusting the time sequence of the first group of phase-shifting pulse groups or the waveform of the gate-source voltage so that the time sequence of the first group of phase-shifting pulse groups is matched with the waveform of the gate-source voltage; the time sequence of the first group of phase-shifting pulse groups is matched with the waveform of the gate-source voltage, wherein the gate-source voltage corresponding to the first group of phase-shifting pulse groups is characterized in that the gate-source voltage before the transistor enters the Miller platform;

Comparing the digital level signal corresponding to each phase-shifting pulse with the digital level signal corresponding to the previous adjacent phase-shifting pulse in the second group phase-shifting pulse group to the M group phase-shifting pulse group to acquire the digital level signal corresponding to the Miller stage of the power tube in the conduction stage; and taking the digital level signal as a first voltage signal, and;

and controlling the digital-to-analog conversion module to resample and analog-to-digital convert the gate-source voltage of the power tube in the conduction stage, and comparing the digital level signal corresponding to each gate-source voltage with the first voltage signal to determine the starting point of the miller platform and the ending point of the miller platform.

Optionally, after determining that the timing sequence of the first group of phase-shifting pulse groups does not match the waveform of the gate-source voltage, the logic control module is further configured to:

comparing the digital level signal corresponding to the first phase-shift pulse in the first phase-shift pulse group with a zero value; if the digital level signal is smaller than or equal to a zero value, judging that the first group of phase shifting pulse groups advance relative to the actual digital level signal; if the digital level signal is greater than the zero value, determining that the first set of phase-shifted pulse sets lags relative to the actual digital level signal.

Optionally, the miller stage determination system further comprises:

the control unit is used for outputting a control signal according to an input level;

a clock module for generating the first clock signal and the second clock signal;

the pulse self-adaptive module comprises a synchronous unit, a first pulse self-adaptive unit and a second pulse self-adaptive unit;

the synchronization unit is coupled to the output end of the control unit and the output end of the clock module respectively, and is used for performing synchronization processing on the control signal and the first clock signal and outputting a first enabling signal;

the first pulse self-adaptive unit is respectively coupled to the output end of the synchronous unit and the output end of the clock module; the first pulse self-adaptive unit is used for carrying out first processing on the first clock signal, the first enabling signal and a first self-adaptive signal group and outputting the phase-shifting enabling signal; wherein the first adaptive signal set is used for representing whether the time sequence of the first phase-shifting pulse set is advanced relative to the time sequence of the grid voltage; if so, the phase-shifting enable signal is lagged relative to the first enable signal; if so, matching; the phase-shifted enable signal is the same as the first enable signal;

The second pulse self-adaptive unit is respectively coupled to the output end of the synchronous unit and the output end of the clock module; the second pulse self-adaptive unit is used for performing first processing on the first clock signal, the first enabling signal and a second self-adaptive signal group and outputting the driving enabling signal; wherein the second adaptive signal set is used to characterize whether the timing of the first set of phase-shifted pulse sets lags with respect to the timing of the gate voltage; if so, the drive enable signal is lagged with respect to the first enable signal; if so, matching; the driving enable signal is the same as the first enable signal.

Optionally, the logic control module is configured to compare the digital level signal corresponding to each phase-shifting pulse with the digital level signal corresponding to the previous adjacent phase-shifting pulse in the second group of phase-shifting pulse groups to the mth group of phase-shifting pulse groups, so as to obtain the first voltage signal, which specifically is:

each phase-shifting pulse group from the second group phase-shifting pulse group to the M group phase-shifting pulse group, and the logic control module sequentially compares a digital level signal corresponding to the phase-shifting pulse in the group with a digital level signal corresponding to the previous adjacent phase-shifting pulse; the digital level signal corresponding to the first phase-shifting pulse in one phase-shifting pulse group is compared with the digital level signal corresponding to the last phase-shifting pulse in the previous adjacent phase-shifting pulse group; if the digital level signal corresponding to the current phase-shifting pulse is greater than the digital level signal corresponding to the previous adjacent phase-shifting pulse and the difference value between the digital level signal and the digital level signal is greater than a first threshold signal, outputting a high level signal; if the digital level signal corresponding to the current phase-shifting pulse is smaller than or equal to the digital level signal corresponding to the previous adjacent phase-shifting pulse or the digital level signal corresponding to the current phase-shifting pulse is larger than the digital level signal corresponding to the previous adjacent phase-shifting pulse, but the difference value between the two signals is smaller than the first threshold value signal, outputting a low level signal;

Optionally, the logic control module is configured to compare each of the digital level signals with the first voltage signal to determine a start point of the miller stage and an end point of the miller stage, specifically:

the logic control module compares each of the digital level signals with the first voltage signal:

will satisfy V first _s >V _pl -V _ths The phase-shifting pulse corresponding to the digital level signal is used as the starting point position of the miller platform; wherein: v (V) _s Is used for representing the digital level signal; v (V) _pl For characterizing the first voltage signal; v (V) _ths For characterizing the first threshold signal；

Optionally, the digital-to-analog conversion module includes n digital-to-analog converters independent of each other; wherein, the digital-to-analog converters respectively correspond to the phase-shifting pulses in the single phase-shifting pulse group in sequence.

According to a fourth aspect of the present invention, there is provided an integrated driving chip of a power tube for implementing the driving method of the second aspect of the present invention, wherein a first end of the power tube is coupled to ground, and a second end of the power tube is connected to a switching power supply end through a load, the chip comprising:

A miller stage determination system according to a third aspect and an alternative embodiment of the invention;

the driving output module is respectively coupled to the output end of the second pulse self-adaptive unit and the output end of the logic control module; the driving output module is used for sequentially outputting a first conduction current, a second conduction current and a third conduction current according to the driving enabling signal, the starting point position of the miller platform, the driving enabling signal and the ending point position of the miller platform so as to control the staged conduction of the power tube; wherein the third conduction current is greater than the first conduction current, and the first conduction current is greater than the second conduction current; the power tube is also used for outputting a first turn-off current according to the drive enabling signal so as to turn off the power tube;

and the power supply end is used for providing working voltage for each module in the miller platform determination system and the driving output module.

Optionally, the integrated driving chip of the power tube further comprises a protection module; the protection module is coupled between the output end of the control unit and the input end of the synchronization unit;

The protection module is used for filtering the control signal in a narrow pulse mode and outputting the control signal to the synchronization unit; the temperature sensor is also used for detecting whether the working temperature of each module in the chip exceeds a third threshold temperature; if the temperature of the power supply end exceeds the preset temperature, the protection module cuts off the power supply of the power supply end and forms temperature hysteresis; the power supply terminal is also used for detecting whether the voltage of the power supply terminal is lower than a fourth threshold voltage; if the voltage is lower than the preset voltage, the protection module cuts off the power supply of the power supply end and forms voltage hysteresis.

According to a fifth aspect of the present invention, there is provided an electronic device comprising an integrated driving chip of a power transistor according to the fourth aspect of the present invention and an alternative embodiment.

According to the Miller platform determining method and system, the power tube driving method and the integrated chip, the grid source voltage of the power tube in the conducting stage is sampled and corresponding analog-to-digital conversion is carried out through each phase-shifting pulse in the M phase-shifting pulse groups in different on-off periods of the power tube; comparing the digital level signals corresponding to each phase-shifting pulse in the first group of phase-shifting pulse groups to the M group of phase-shifting pulse groups with the digital level signals corresponding to the previous adjacent phase-shifting pulse; the comparison in the first group of phase-shifting pulse groups is used for matching the time sequence of the first group of phase-shifting pulse groups with the waveform of the gate-source voltage; the comparison between the second group of phase-shifting pulse groups and the Mth group of phase-shifting pulse groups is used for obtaining digital level signals corresponding to the Miller platform stage of the power tube in the conduction stage; and then sampling and corresponding analog-to-digital conversion are carried out on the gate source voltage of the power tube in the conducting stage through each phase-shifting pulse in the M phase-shifting pulse groups in different on-off periods of the power tube, and each obtained digital level signal is compared with the digital level signal corresponding to the Miller stage of the power tube in the conducting stage, so that the starting point position and the end point position of the Miller stage are accurately obtained respectively.

And conducting the power tube with large current at a stage before the starting point of the miller platform, conducting the power tube with small current at a stage from the starting point of the miller platform to the end point of the miller platform, conducting the power tube with large current again at a stage after the end point of the miller platform, and conducting the power tube with low-delay subsection by the accurate starting point and the accurate end point of the miller platform.

Drawings

The invention will be described in further detail with reference to the drawings and the detailed description.

FIG. 1 is a flowchart of a method for determining a Miller platform according to an embodiment of the present invention;

fig. 2 is a waveform diagram of a gate-source voltage and a drain-source voltage in a power tube conduction stage according to an embodiment of the present invention;

FIG. 3 is an exemplary diagram of a first set of phase-shifted pulse sets having a timing mismatch with respect to a gate-source voltage waveform according to an embodiment of the present invention;

FIG. 4 is a block diagram I of a Miller platform determination system according to an embodiment of the invention;

FIG. 5 is a second block diagram of a Miller platform determination system according to an embodiment of the present invention;

FIG. 6 is a circuit diagram of a pulse adaptive module according to an embodiment of the present invention;

FIG. 7 is a circuit diagram of a phase-shifting pulse generating module according to an embodiment of the present invention;

Fig. 8 is a conceptual diagram of a digital-to-analog conversion module according to an embodiment of the present invention;

FIG. 9 is a block diagram of an integrated driving chip of a power tube according to an embodiment of the present invention;

fig. 10 is a circuit configuration diagram of a driving output module according to an embodiment of the present invention;

FIG. 11 is a circuit diagram illustrating a first conductive device to a third conductive device according to an embodiment of the present invention;

fig. 12 is a circuit configuration diagram of a first shutdown component according to an embodiment of the present disclosure;

fig. 13 is a circuit configuration diagram of an over-temperature protection circuit according to an embodiment of the present invention;

FIG. 14 is a circuit diagram of an undervoltage protection circuit according to an embodiment of the present invention;

fig. 15 is a circuit configuration diagram of a narrow pulse filtering circuit according to an embodiment of the present invention.

Description of the drawings:

10-miller stage determination system; 11-an on-off control module; 12-a phase-shifting pulse generating module; 121-a phase-shift pulse group first pulse generation unit; 1211-a first group phase-shifted pulse group first pulse generation subunit; 12111-a first generation subunit; 12112-a second generation subunit; 1212-a second set of phase-shifted pulse set first pulse generation subunits; 122-each phase-shift pulse generating unit of the phase-shift pulse group; 1222-a second phase-shifted pulse generating subunit; 1223-said third phase-shifted pulse generating subunit; 122 n-nth phase-shifted pulse generation subunit; 123-counting module; 13-a digital-to-analog conversion module; 14-a logic control module; 15-a control unit; a 16-clock module; 17-a pulse adaptation module; 171-a synchronization unit; 172-a first pulse adaptation unit; 173-a second pulse adaptation unit; 20 a drive output module; a 21-drive signal generation unit; 22-a drive output unit; 221-a first pass component; 222-a second pass-through component; 223-a third pass-through component; 224-a first shutdown component; a1-a first AND gate; a2-a second AND gate; a3-a third AND gate; a4-fourth and gate; a5-fifth AND gate; a6-sixth AND gates; a7-seventh AND gate; a8-eighth AND gate; adv 1-first adaptive signal; adv 2-second adaptive signal; c1-a first phase signal; c2-second phase signal; CM-mth phase signal; COMP-comparator; c1-a first capacitor; clk-a first clock signal; clk' -a first clock inversion signal; en_pulse-phase shift enable signal; an en_drive-DRIVE enable signal; EN-first enable signal; en_d-a second enable signal; i1-a first conduction sub-current; i2-a second conduction sub-current; i3-a third conduction sub-current; IN-first off current; lag 1-a third adaptive signal; lag 2-fourth adaptive signal; m1-a first MOS tube; m2-a second MOS tube; m3-a third MOS tube; m4-a fourth MOS tube; m5-a fifth MOS tube; m6-a sixth MOS tube; m7-seventh MOS tube; m8-eighth MOS tube; m9-ninth MOS tube; m10-tenth MOS tube; m11-eleventh MOS tube; m12-twelfth MOS tube; m13-thirteenth MOS tube; o1-a first OR gate; o2-a second OR gate; o3-a third OR gate; o4-fourth OR gate; o5-a fifth OR gate; o6-sixth or gate; o7-seventh or gate; o8-eighth OR gate; o9-ninth or gate; an OTP-second level signal; op-amp; pwm_im-control signal; p 1-a first drive signal; p 2-a second drive signal; pls 1-first pulse; pls 2-second pulse; q 1-a first transistor; q 2-a second transistor; q1-a first D flip-flop; q2-a second D flip-flop; q3-a third D flip-flop; q4-fourth D flip-flop; q5-fifth D flip-flop; q6-sixth D flip-flop; q8-eighth D flip-flop; q9-ninth D flip-flop; q10-tenth D flip-flop; q11-eleventh D flip-flop; q12-twelfth D flip-flop; q13-thirteenth D flip-flop; q14-fourteenth D flip-flop; QN 1-a second signal; QN 2-fourth signal; RSTN-reset signal; r1-a first resistor; r2-a second resistor; r3-a third resistor; r4-fourth resistor; r5-fifth resistor; r6-sixth resistance; r7-seventh resistor; t1-a first inverter; t2-a second inverter; a T3-third inverter; t4-fourth inverter; t5-fifth inverter; VS-high signal; VCC-power supply terminal; vds-switching power supply terminal; VREF-reference voltage.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Before the embodiments of the present invention are described, the design idea of the present invention will now be briefly described:

the excessive switching speed and the excessive switching frequency of the GaN HEMT can cause serious EMI problems in the switching-on process, which can certainly increase the voltage stress and the current stress of the GaN HEMT in operation, reduce the reliability of the GaN HEMT in long-term operation, and lead the parasitic inductance of the GaN HEMT to be smaller than the parasitic inductance of a loop due to the adoption of DFN patch package by most GaN HEMTs according to a peak voltage formula:

V _os for characterizing spike voltages; l (L) _DS The drain-source parasitic inductance is used for representing the GaN HEMT; i.e _D For characterizing the drain current of GaN HEM.

The voltage spike, i.e., EMI, problem of the GaN HEMT during turn-off is not a major goal of optimization; if the working stress problem of the GaN HEMT is considered too conservatively, the power class of the GaN HEMT during working is obviously limited, and the opening loss is increased. Therefore, it is necessary to optimize both the EMI problem and the turn-on loss problem of the GaN HEMT during the turn-on process. Referring to fig. 1, because the GaN HEMT is usually subjected to EMI problems during the miller stage during each stage of turn-on, it is necessary to differentiate the turn-on of the GaN HEMT during different stages, and to use slow turn-on during the stage when the miller stage is present and to maintain fast turn-on during other stages. Because the opening speed of the GaN HEMT and the driving current are positively correlated, small driving current is adopted at the stage of the GaN HEMT where a miller platform appears, and large driving current is kept at other stages, so that the peak current level in the opening process can be restrained, and smaller switching loss can be kept. In order to improve the conducting effect of the GaN HEMT and reduce whether the detection response to the starting point position and the end point position of the Miller platform is timely and crucial, compared with the problem that the detection response to the starting point position and the end point position of the Miller platform is not timely in the prior art in the common on-chip drive control, the invention samples and carries out digital-to-analog conversion on the gate-source voltage of the GaN HEMT in the conducting stage through phase shifting pulse so as to obtain corresponding digital level signals; and comparing the obtained digital level signals to match the time sequence of the phase-shifting pulse with the time sequence of the actual gate-source voltage waveform, and obtaining a digital level signal corresponding to the gate-source voltage, namely a first level signal, when the power tube is in a miller stage in the conduction stage. And sampling and digital-to-analog converting the gate-source voltage of the GaN HEMT in the conduction stage through the phase-shifting pulse, comparing the obtained digital level signal with the first level signal to obtain the starting point position and the end point position of the Miller platform, and conducting the segmented current on the GaN HEMT according to the phase-shifting pulse corresponding to the starting point position and the end point position of the Miller platform. In addition, as long as the load of the GaN HEMT is not changed, the phase shifting pulse corresponding to the starting point position and the end point position of the Miller platform can be always applied to the conduction of the GaN HEMT, so that the detection response time of the starting point position and the end point position of the Miller platform can be omitted, and the response delay of the segmented driving of the GaN HEMT is reduced.

Referring to fig. 1, the embodiment of the invention provides a miller stage determining method for determining a start position and an end position of a miller stage in a conducting stage of a power tube, which includes:

s10: under the control of a DRIVE enable signal en_drive, the gate-source voltage applied to the gate of the power transistor is periodically controlled so that the power transistor is periodically turned on and off.

S20: performing multipath phase shifting processing on a first clock signal clk between each rising edge interval of a phase shifting enable signal EN_PULSE to obtain M groups of phase shifting PULSE groups; each group of phase-shifting pulses corresponds to one on-off period of the power tube; each phase-shifting pulse group comprises n phase-shifting pulses which are adjacent in sequence, and the serial numbers of the phase-shifting pulses of the adjacent phase-shifting pulse groups are continuous; wherein M, n is a positive integer, and M is greater than or equal to 16.

S30: sampling the gate-source voltage of the power tube in the conduction stage, and performing analog-to-digital conversion on the sampling voltage corresponding to each phase-shifting pulse under the control of a second clock signal and all phase-shifting pulses of the M groups of phase-shifting pulse groups so as to obtain corresponding digital level signals; the second clock signal is specifically an intermediate frequency clock signal.

S40: and selecting each digital level signal corresponding to each phase-shifting pulse in the first group of phase-shifting pulse groups, and comparing the digital level signal corresponding to each phase-shifting pulse in the first group of phase-shifting pulse groups with the digital level signal corresponding to the previous adjacent phase-shifting pulse.

S50: judging whether the time sequence of the first group of phase-shifting pulse groups is matched with the waveform of the gate source voltage or not; if yes, jumping to S80; if not, go to S60.

S60: and judging whether the time sequence of the first group of phase-shifting pulse groups is lagging or leading relative to the waveform of the gate-source voltage.

S70: adjusting the time sequence of the first group of phase-shifting pulse groups or the waveform of the gate-source voltage according to the judging result so that the time sequence of the first group of phase-shifting pulse groups is matched with the waveform of the gate-source voltage; the waveform matching of the time sequence of the first group of phase-shifting pulse groups and the waveform of the gate-source voltage is characterized in that the gate-source voltage corresponding to the first group of phase-shifting pulse groups is the gate-source voltage before the transistor enters the miller stage.

S80: comparing the digital level signal corresponding to each phase-shifting pulse with the digital level signal corresponding to the previous adjacent phase-shifting pulse in the second group phase-shifting pulse group to the M group phase-shifting pulse group to acquire the digital level signal corresponding to the Miller stage of the power tube in the conduction stage; and takes the digital level signal as a first voltage signal.

S90: and S30, repeating the step of comparing the digital level signal corresponding to each gate-source voltage with the first voltage signal to determine the starting point position of the miller stage and the ending point position of the miller stage.

The power transistor is specifically a GaN HEMT, however, the power transistor may be any other type of transistor, such as a SiC MOSFET, a D-MOS, an IGBT, a superjunction MOSFET, and the like, which is not limited herein.

As a specific embodiment, the acquiring of the driving enable signal en_drive and the phase shift enable signal en_pulse specifically includes:

synchronizing the rising edge of an externally input control signal PWM_IM and the rising edge of the first clock signal clk to obtain a first enable signal EN; the control signal pwm_im is specifically an externally input PWM signal, and the first clock signal clk is specifically a high-frequency clock signal; because the externally input PWM signal and the first clock signal clk are not synchronous signals, using the rising edge of the externally input PWM signal as a time reference for generating each set of phase-shifted pulses may cause each set of phase-shifted pulses to be discontinuous with respect to a complete gate-source voltage waveform of the power transistor during the on-phase. Therefore, the control signal pwm_im and the first clock signal clk are first subjected to rising edge synchronization to generate the first enable signal EN, rising edges of the first enable signal EN are used as time references for generating respective phase-shifting pulse groups, and the first enable signal EN is used as a driving signal to periodically control the gate-source voltage applied to the gate of the power tube so that the power tube is periodically turned on and off. However, the problem that delay exists in the generation process of each phase-shifting pulse group is also considered, so that the time sequence of each phase-shifting pulse group is not matched with the waveform of the actual gate-source voltage of the power tube in the conducting stage, and the mismatch is specifically that the time sequence of each phase-shifting pulse group is advanced or delayed relative to the waveform of the gate-source voltage. It is therefore necessary to delay compensate the first enable signal EN in different usage scenarios depending on the specific cause of the mismatch, to obtain the DRIVE enable signal en_drive and the phase shift enable signal en_pulse. Of course, if the timing sequence of each phase-shifting PULSE group is matched with the waveform of the actual gate-source voltage of the power tube in the on phase, the driving enable signal en_drive and the phase-shifting enable signal en_pulse are equal to the first enable signal EN. How the timing sequence of each phase-shifting pulse group is matched with the waveform of the actual gate-source voltage of the power tube in the conducting stage, and the delay compensation of the first enable signal EN in different use situations under the different situations of mismatch is described below.

In one embodiment, in S20, the first clock signal clk is subjected to a multi-path phase shift process between each rising edge interval of a phase shift enable signal en_pulse to obtain M groups of phase shift PULSE groups, which specifically includes:

generating n phase-shifting PULSEs which are adjacent in sequence according to the rising edge and the falling edge of the first clock signal clk when the first rising edge of the phase-shifting enabling signal EN_PULSE arrives, namely the first group of phase-shifting PULSE groups; when the second rising edge of the enable signal en_pulse arrives, delay of n phase-shifting PULSEs which are adjacent in sequence is performed compared with that of the first phase-shifting PULSE group, and n phase-shifting PULSEs which are adjacent in sequence are generated according to the rising edge and the falling edge of the first clock signal clk, namely the second phase-shifting PULSE group; similarly, M phase-shifted pulse sets are generated. The rising edges of the driving enable signal EN_DRIVE and the phase-shifting enable signal EN_PULSE which control the on-off of the power tube are both obtained by the first enable signal EN, so that the rising edges of the driving enable signal EN_DRIVE and the phase-shifting enable signal EN_PULSE are synchronous, and the driving enable signal EN_DRIVE is in a high level and corresponds to the conduction of the power tube; when the driving enabling signal EN_DRIVE is at a low level, the power tube is correspondingly turned off; the M phase-shifting pulse groups generated in the mode correspond to one on-off period of the power tube respectively, and the serial numbers of the phase-shifting pulses of the adjacent phase-shifting pulse groups are continuous; wherein, the serial numbers here are specifically: for example, 16 phase-shifting pulses which are adjacent in sequence are needed for sampling the gate-source voltage of the power tube in the conducting stage completely; however, considering that the circuit cost of arranging 16 ADCs is too high, 4 ADCs are used for sampling the gate-source voltage of the power tube in the conducting stage in a segmented manner. In a first on-off period, 4 ADCs are controlled to be sampled sequentially through the first phase-shifting pulse to the fourth phase-shifting pulse; in the second on-off period, firstly delaying the first phase-shifting pulse to the fourth phase-shifting pulse, and then controlling 4 ADCs to sample sequentially through the fifth phase-shifting pulse to the eighth phase-shifting pulse; and analogizing is performed sequentially until the sampling of the grid source voltage of the power tube in the conducting stage is completed; wherein the first phase-shifting pulse to the fourth phase-shifting pulse correspond to the first group of phase-shifting pulse groups, and the fifth phase-shifting pulse to the eighth phase-shifting pulse correspond to the second group of phase-shifting pulse groups; and so on. Of course, the complete sampling of the gate-source voltage of the power tube in the conduction stage is not limited to only use 16 phase-shifting pulses which are adjacent in sequence, because the more the set phase-shifting pulses are, the more complete the gate-source voltage waveform is obtained by sampling; meanwhile, the number of ADCs is not limited to 4. If circuit cost is not considered, the sampling can be directly completed in one on-off period. However, considering the circuit cost, a compromise between the circuit cost and the operating efficiency is required, which can be set according to practical requirements.

As a specific implementation manner, in S30, under the control of a second clock signal and all phase-shifting pulses of the M groups of phase-shifting pulse groups, analog-to-digital conversion is performed on sampling voltages corresponding to each phase-shifting pulse to obtain corresponding digital level signals, which specifically includes:

and n sequentially adjacent phase-shifting pulses in the phase-shifting pulse group respectively correspond to n parallel samples, the sampling of the gate-source voltage of the power tube is stopped under the control of the falling edges of the n sequentially adjacent phase-shifting pulses, and the gate-source voltage corresponding to the falling edge time of the phase-shifting pulse is converted into a digital level signal under the control of the second clock signal.

In one specific embodiment, in S40, comparing the digital level signal corresponding to each phase-shifted pulse in the first group of phase-shifted pulses with the digital level signal corresponding to the previous adjacent phase-shifted pulse specifically includes:

comparing the digital level signal corresponding to each phase-shift pulse in the first group of phase-shift pulse groups with the digital level signal corresponding to the previous adjacent phase-shift pulse; if the digital level signal corresponding to the current phase-shifting pulse is greater than the digital level signal corresponding to the previous adjacent phase-shifting pulse and the difference value between the two signals is greater than the second threshold signal, outputting a high level signal; and if the digital level signal corresponding to the current phase-shifting pulse is smaller than or equal to the digital level signal corresponding to the previous adjacent phase-shifting pulse or the digital level signal corresponding to the current phase-shifting pulse is larger than the digital level signal corresponding to the previous adjacent phase-shifting pulse, but the difference value between the two signals is smaller than the second threshold value signal, outputting a low level signal.

The second threshold signal is set to be beneficial to alleviating misjudgment caused by grid voltage fluctuation; regarding the setting of the second threshold signal and the magnitude of the gate-source voltage of the power tube in the miller stage at the conducting stage, for example, the magnitude of the gate-source voltage in the miller stage is 2.38V, the second threshold signal may be set to 1V or 1.2V, which are all experimental data, but not limited thereto.

Wherein, because a group of phase-shifting pulse groups contains n phase-shifting pulses which are adjacent in sequence, the first level signal group is specifically n-1 bit binary code.

As one specific embodiment, in S50, determining whether the timing sequence of the first phase-shifting pulse group matches the waveform of the gate-source voltage specifically includes:

Illustrated with n being 4: if the first level signal group is 001 or 000, determining that the time sequence of the first phase-shifting pulse group is not matched with the waveform of the gate-source voltage; if the first level signal group is 111 or 110 or 100 or 011, determining that the time sequence of the first phase-shifting pulse group is matched with the waveform of the gate-source voltage; if the first level signal group is 010 or 101, the digital level signal corresponding to the first phase-shifting pulse group is judged to be abnormal and is discarded.

The principle is as follows: referring to fig. 2, the first set of phase-shifted pulse groups mainly corresponds to the T0 phase: if the first level signal of the first level signal group is low level and two continuous low levels exist, the time sequence of the first phase shifting pulse group is indicated to be before the T0 phase or in the T1 phase, and the time sequence is not matched with the waveform of the gate source voltage; if the first level signal in the first level signal group is high or there are two continuous high levels, it indicates that the timing of the first set of phase-shifting pulse groups is in the T0 stage, perhaps not completely corresponding to the waveform of the gate-source voltage, but the starting position of the miller stage may be included in the first set of phase-shifting pulse groups. If the continuous jump level signals appear in the first level signal group, the existence of the gate source voltage fluctuation is indicated, and the digital level signals corresponding to the first phase shift pulse group are needed to be discarded.

In one specific embodiment, in S60, determining whether the timing of the first set of phase-shifting pulses is lagging or leading with respect to the waveform of the gate-source voltage further includes:

The principle is as follows: referring to fig. 3, if the timing of the first set of phase-shifted pulses is advanced with respect to the waveform of the gate-source voltage, the digital level signal corresponding to the first phase-shifted pulse in the first set of phase-shifted pulses should be approximately equal to 0; if the timing sequence of the first group of phase-shifting pulse groups lags relative to the waveform of the gate-source voltage, the digital level signal corresponding to the first phase-shifting pulse in the first group of phase-shifting pulse groups should be greater than 0.

As a specific embodiment, in S70, adjusting the timing of the first phase-shifting pulse group or the waveform of the gate-source voltage according to the determination result specifically includes:

If the timing sequence of the first group of phase-shifting PULSE groups is judged to be advanced relative to the waveform of the gate-source voltage, the phase-shifting enable signal EN_PULSE is obtained after the first enable signal EN is subjected to hysteresis processing, and the driving enable signal EN_DRIVE is identical with the first enable signal EN; the hysteresis process here is specifically; lagging the first enable signal EN by one period to obtain a first phase-shifting enable signal EN_PULSE; if the time sequence of the first group of phase-shifting pulse groups is judged to be advanced relative to the waveform of the gate-source voltage after the hysteresis processing, the first enabling signal EN is continued to be delayed for one period until the time sequence of the first group of phase-shifting pulse groups is matched with the waveform of the gate-source voltage.

If the time sequence of the first group of phase-shifting PULSE groups is judged to be lagging relative to the waveform of the gate-source voltage, the driving enable signal EN_DRIVE is obtained after the first enable signal EN is subjected to lagging treatment, and the phase-shifting enable signal EN_PULSE is identical with the first enable signal EN. The hysteresis processing is identical to the hysteresis processing described above, and will not be described in detail.

As a specific embodiment, in S80, comparing the digital level signal corresponding to each phase-shift pulse with the digital level signal corresponding to the previous adjacent phase-shift pulse in the second group of phase-shift pulses to the mth group of phase-shift pulses to obtain the first voltage signal, which specifically includes:

Each phase-shifting pulse group from the second group phase-shifting pulse group to the M group phase-shifting pulse group sequentially compares a digital level signal corresponding to the phase-shifting pulse in the group with a digital level signal corresponding to the previous adjacent phase-shifting pulse; the digital level signal corresponding to the first phase-shifting pulse in one phase-shifting pulse group is compared with the digital level signal corresponding to the last phase-shifting pulse in the previous adjacent phase-shifting pulse group; if the digital level signal corresponding to the current phase-shifting pulse is greater than the digital level signal corresponding to the previous adjacent phase-shifting pulse and the difference value between the digital level signal and the digital level signal is greater than the first threshold signal, outputting a high level signal; if the digital level signal corresponding to the current phase-shifting pulse is smaller than or equal to the digital level signal corresponding to the previous adjacent phase-shifting pulse or the digital level signal corresponding to the current phase-shifting pulse is larger than the digital level signal corresponding to the previous adjacent phase-shifting pulse, but the difference value between the two signals is smaller than the first threshold value signal, outputting a low level signal;

The principle is as follows: referring to fig. 2, starting from the second set of phase-shifting pulse groups, the power tube in the on-state performs a miller stage, i.e., a T1 stage. While in the T1 phase the digital level signals corresponding to the phase-shifted pulses in each phase-shifted pulse group should be similar to each other compared to the digital level signal corresponding to the preceding adjacent phase-shifted pulse, of course, this does not exclude slight fluctuations, which are already contained in the first threshold signal. Therefore, in the comparison process, when a high-level signal is output for the first time, the miller platform is finished, and when a low-level signal is output before selection, the intermediate value of the digital level signal corresponding to the phase-shifting pulse is used as the digital level signal corresponding to the gate-source voltage of the power tube in the miller platform period in the conduction stage, namely the first voltage signal.

As a complementary implementation manner, the miller voltage of the power tube, that is, the gate-source voltage corresponding to the miller stage of the power tube in the conducting stage, is not limited to be obtained by sampling and comparing, but may be obtained by other modes, not limited thereto. For example: (1) setting and storing manually. (2) The slope of the grid source voltage of the power tube in the conducting stage relative to time, namely dV, is obtained by utilizing a capacitor _GS Conversion of/dt into current information orVoltage information from which the miller voltage is obtained.

As a specific embodiment, in S90, each of the digital level signals and the first voltage signal are compared to determine a start position of the miller stage and an end position of the miller stage, which specifically includes:

will satisfy V first _s >V _pl +V _th The phase-shifted pulse corresponding to the digital level signal is used as the end position of the miller stage.

In the conducting stage of the power tube, the gate-source voltage can reach the corresponding magnitude of the first voltage signal very quickly, so the starting point position of the miller stage is set to be the first one to meet V _s >V _pl -V _ths The phase-shifted pulses corresponding to the digital level signals help to reduce the error between the miller plateau start position and the actual miller plateau start position obtained by the sample comparison. Meanwhile, the end position of the Miller platform is set to be the first position meeting V _s >V _pl +V _ths The phase-shifted pulses corresponding to the digital level signals of (a) help to avoid erroneous decisions due to gate voltage fluctuations.

The embodiment of the invention also provides a driving method of the power tube, which comprises the following steps:

the starting point position and the end point position of the miller platform in the conducting stage of the power tube are determined by using the miller platform determining method provided by the embodiment of the invention;

aiming at a third conduction stage of the power tube, conducting control is carried out on the power tube by utilizing a third conduction current; the third conduction stage is used for representing a stage of the power tube after the power tube passes through the miller stage in the conduction process.

The specific conduction process is as follows: taking phase-shifting pulses corresponding to the starting point positions of the Miller platforms and phase-shifting pulses corresponding to the end point positions of the Miller platforms as driving sequences;

in a first conduction stage in a conduction process, conducting the power tube through the first conduction current;

in a second conduction stage in a conduction process, reducing the first conduction current into the second conduction current according to a phase-shifting pulse corresponding to the starting point position of the miller platform so as to increase the conduction time of the second conduction stage and relieve the EMI problem of the power tube in the conduction stage;

and in a third conduction stage in a conduction process, the second conduction current is increased to the third conduction current according to the phase-shifting pulse corresponding to the end position of the miller platform, so that the conduction time of the third conduction stage is reduced, and the conduction loss of the power tube is reduced.

Referring to fig. 4, the embodiment of the present invention further provides a miller platform determining system 10, configured to implement the miller platform determining method provided by the embodiment of the present invention, where the system includes:

the on-off control module 11 is used for periodically controlling the gate-source voltage loaded on the gate of the power tube under the control of a DRIVE enable signal EN_DRIVE so as to periodically turn on and off the power tube;

The phase-shift PULSE generation module 12, the phase-shift PULSE generation module 12 is configured to perform a multi-path phase-shift processing on a first clock signal clk between each rising edge interval of a phase-shift enable signal en_pulse to obtain M groups of phase-shift PULSE groups; each group of phase-shifting pulses corresponds to one on-off period of the power tube; each phase-shifting pulse group comprises n phase-shifting pulses which are adjacent in sequence, and the phase-shifting pulse groups of adjacent on-off periods are continuous in the same on-off period; wherein M, n is a positive integer, and M is greater than or equal to 16;

a digital-to-analog conversion module 13 coupled to the output end of the phase-shift pulse generation module 12; the digital-to-analog conversion module 13 samples the gate-source voltage of the power tube in the conducting stage, and performs analog-to-digital conversion on the sampled voltage corresponding to each phase-shift pulse under the control of a second clock signal and all phase-shift pulses of the M groups of phase-shift pulse groups so as to obtain a corresponding digital level signal;

a logic control module 14 coupled to an output of the digital-to-analog conversion module 13; the logic control module 14 is configured to:

and controlling the digital-to-analog conversion module 13 to resample and analog-to-digital convert the gate-source voltage of the power tube in the conduction stage, and comparing the digital level signal corresponding to each gate-source voltage with the first voltage signal to determine the starting point of the miller stage and the ending point of the miller stage.

In one embodiment, the logic control module 14 is further configured to, after determining that the timing of the first set of phase-shifted pulse groups does not match the waveform of the gate-source voltage:

Referring to fig. 5, as a specific embodiment, the miller stage determination system 10 further includes:

a control unit 15 for outputting a control signal pwm_im according to an input level; wherein the control signal PWM_IM is specifically a PWM signal

A clock module 16 for generating the first clock signal clk and the second clock signal; wherein the first clock signal clk is specifically a high-frequency clock signal; the second clock signal is specifically an intermediate frequency clock signal.

A pulse adaptation module 17, the pulse adaptation module 17 comprising a synchronization unit 171, a first pulse adaptation unit 172, a second pulse adaptation unit 173;

referring to fig. 6, the synchronization unit 171 is coupled to the output terminal of the control unit 15 and the output terminal of the clock module 16, respectively, and the synchronization unit 171 is configured to perform synchronization processing on the control signal pwm_im and the first clock signal clk, and output a first enable signal EN; wherein the synchronization unit 171 is embodied as a D flip-flop

The first pulse adaptive unit 172 is coupled to the output terminal of the synchronization unit 171 and the output terminal of the clock module 16, respectively; the first PULSE adaptive unit 172 is configured to perform a first process on the first clock signal clk, the first enable signal EN, and a first adaptive signal adv1 set, and output the phase-shift enable signal en_pulse; the first adaptive signal adv1 set is used for representing whether the time sequence of the first phase-shifting pulse set is advanced relative to the time sequence of the grid voltage; if advanced, the phase shift enable signal en_pulse is retarded with respect to the first enable signal EN; if so, matching; the phase shift enable signal en_pulse is the same as the first enable signal EN;

The second pulse adaptive unit 173 is coupled to the output terminal of the synchronization unit 171 and the output terminal of the clock module 16, respectively; the second pulse adaptive unit 173 is configured to perform a first process on the first clock signal clk, the first enable signal EN, and a second adaptive signal adv2, and output the driving enable signal en_drive; wherein the second adaptive signal adv2 set is used for representing whether the time sequence of the first phase-shifting pulse set lags relative to the time sequence of the gate voltage; if so, the driving enable signal en_drive is delayed with respect to the first enable signal EN; if so, matching; the driving enable signal EN _ DRIVE is identical to the first enable signal EN.

Referring to fig. 6, the first pulse adaptive unit 172 includes a first D flip-flop Q1, a second D flip-flop Q2, a third D flip-flop Q3, a first or gate O1, a second or gate O2, and a first and gate A1;

the first D flip-flop Q1 is coupled to the output terminal of the synchronization unit 171 and the output terminal of the clock module 16, respectively; the second D flip-flop Q2 is coupled to the output terminal of the first D flip-flop Q1 and the output terminal of the clock module 16, respectively; the first or gate O1 is coupled to the output terminal of the second D flip-flop Q2, and receives the first adaptive signal adv1 of the first adaptive signal adv1 group; the third D flip-flop Q3 is coupled to the output terminal of the synchronization unit 171 and the output terminal of the clock module 16, respectively; the second or gate O2 is coupled to the output terminal of the third D flip-flop Q3, and receives the second adaptive signal adv2 of the first adaptive signal adv1 set; the first and gate A1 is coupled to the output of the first or gate O1, the output of the second or gate O2, and the output of the synchronization unit 171, respectively; the first and gate A1 is configured to phase-shift the first enable signal EN and the signal output by the first or gate O1 and the signal output by the second or gate O2, and output the phase-shift enable signal en_pulse. Wherein; when judging that the time sequence of the first group of phase-shifting PULSE groups advances relative to the waveform of the gate-source voltage, controlling the first adaptive signal adv1 and the second adaptive signal adv2 to be respectively high level and low level so as to enable the phase-shifting enabling signal EN_PULSE to delay the time sequence of the first clock signal clk for one period relative to the first enabling signal EN; and if the timing sequence of the first group of phase-shifting PULSE groups is judged to be advanced relative to the waveform of the gate-source voltage again, the first adaptive signal adv1 and the second adaptive signal adv2 of the first adaptive signal group are controlled to be respectively low level and high level, so that the timing sequence of the first clock signal clk is delayed relative to the first enable signal EN for one cycle on the basis of the delay.

Referring to fig. 6, the second pulse adaptive unit 173 includes a fourth D flip-flop Q4, a fifth D flip-flop Q5, a sixth D flip-flop Q6, a third or gate O3, a fourth or gate O4, and a second and gate A2; the structure is the same as the first pulse adaptation unit 172; when judging that the time sequence of the first group of phase shifting pulse groups lags behind the waveform of the gate source voltage, controlling the third adaptive signal lag1 and the fourth adaptive signal lag2 of the second adaptive signal group to be respectively high level and low level so as to enable the driving enabling signal EN_DRIVE to delay the time sequence of the first clock signal clk for one period relative to the first enabling signal EN; if it is determined again that the timing of the first phase-shifting pulse group is advanced with respect to the waveform of the gate-source voltage, the third adaptive signal lag1 and the fourth adaptive signal lag2 are controlled to be low level and high level, respectively, so that the driving enable signal en_drive is re-delayed with respect to the first enable signal EN by one cycle of the timing of the first clock signal clk on the basis of the above delay.

Wherein the enable signals neg of all D flip-flops in the first pulse adaptive unit 172 and the second pulse adaptive unit 173 are in an inactive state after the falling edge of the first enable signal EN; the enable signal is active only after the rising edge of the first enable signal EN to ensure that the adaptive adjustment of the phase-shifting pulse is only active at the rising edge of the first enable signal EN,

Referring to fig. 7, as an embodiment, the phase-shift pulse generating module 12 specifically includes: a phase-shift pulse group first pulse generating unit 121, phase-shift pulse group each phase-shift pulse generating unit 122, and a counting module 123;

the phase-shift pulse group first pulse generation unit 121 includes a first group phase-shift pulse group first pulse generation subunit 1211 to an mth group phase-shift pulse group first pulse generation subunit, a fifth or gate O5, a third and gate A3, a fourth and gate A4, a tenth D flip-flop Q10, and a first inverter T1; wherein:

the first group of phase-shifted pulse group first pulse generation subunit 1211 includes a first generation subunit 12111 and a second generation subunit 12112; the first generating subunit 12111 includes a fifth and gate A5, an eighth D flip-flop Q8; the second generation subunit 12112 includes a ninth D flip-flop Q9; the fifth and gate A5 is configured to receive a first phase signal C1 and a reset signal RSTN, and phase-output the two signals to the data terminal of the eighth D flip-flop Q8; the clock end of the eighth D trigger Q8 is connected with the first clock signal clk, the enabling end of the eighth D trigger Q8 is connected with the reset signal RSTN, and the output end of the eighth D trigger Q8 is connected with the enabling end of the eighth D trigger; the data terminal of the ninth D flip-flop Q9 is connected to a second enable signal en_d, which is a first clock inversion signal clk' Zhong Duanjie; wherein the first clock inversion signal clk' is an inversion signal of the first clock signal clk; the output end of the ninth D trigger Q9 is connected with the input end of the fifth OR gate O5;

The second group phase-shifting pulse group first pulse generation subunit 1212 to the mth group phase-shifting pulse group first pulse generation subunit also include a first generation subunit and a second generation subunit; wherein the first generating subunit 12111 included in the second group phase-shifting pulse group first pulse generating subunit 1212 to the mth group phase-shifting pulse group first pulse generating subunit and the first generating subunit 12111 included in the first group phase-shifting pulse group first pulse generating subunit 1211 have the same structure; wherein the second generation subunit included in the second group phase-shift pulse group first pulse generation subunit 1212 to the mth group phase-shift pulse group first pulse generation subunit sequentially increases two D flip-flops relative to the second generation subunit included in the first group phase-shift pulse group first pulse generation subunit 1211; wherein the signals received by the and gates of the first generating subunit 12111 included in the second group phase-shift pulse group first pulse generating subunit 1212 to the mth group phase-shift pulse group first pulse generating subunit are sequentially the second phase signal C2 to the mth phase signal CM;

the output end of the fifth or gate O5 is connected with the input end of the third and gate A3; the fifth or gate O5 is configured to phase or the input signal and output a first signal;

The other input ends of the third and gate A3 also receive the first clock signal clk and a second signal QN1, and the output end of the third and gate A3 is connected with the clock end of the tenth D flip-flop Q10 and the input end of the first inverter T1; the third AND gate A3 is used for ANDing the input signal phase and outputting a third signal;

the data terminal of the tenth D flip-flop Q10 is connected with a high level signal VS, the enabling terminal of the tenth D flip-flop Q10 is connected with the reset signal RSTN, and the output terminal of the tenth D flip-flop Q10 is connected with the input terminal of the fourth AND gate A4; the tenth D flip-flop Q10 is configured to output the second signal QN1 to the fourth and gate A4 according to the third signal, the high level signal VS, and the reset signal RSTN that are input;

the other input end of the fourth AND gate A4 also receives the phase shift enable signal EN_PULSE; the fourth and gate A4 is configured to phase an input signal and output the second enable signal en_d;

the first inverter T1 is configured to invert the third signal to output a first pulse pls1 of each phase-shifted pulse group.

The counting module 123 is configured to detect a rising edge of the first enable signal EN; when the first enable signal EN is at a first rising edge, the first phase signal C1 is at a high level, and the second phase signal C2 to the mth phase signal CM are all at a low level; when the first enable signal EN is at the second rising edge, the second phase signal C2 is at a high level, and the other phase signals are all at a low level; when the first enable signal EN is at the ith rising edge, the ith phase signal is at a high level, and other phase signals are all at low levels; wherein i is a positive integer, and i is less than or equal to M.

Each phase-shift pulse generating unit 122 of the phase-shift pulse group includes a second phase-shift pulse generating subunit 1222 to an nth phase-shift pulse generating subunit 122n; wherein:

the second phase-shift pulse generating subunit 1222 includes an eleventh D flip-flop Q11, a twelfth D flip-flop Q12, a sixth and gate A6, a second inverter T2; the data terminal of the eleventh D flip-flop Q11 is connected to the high level signal VS, while the third signal Zhong Duanjie is connected to the reset signal RSTN, the output terminal thereof is connected to the input terminal of the sixth and gate A6, and the eleventh D flip-flop Q11 is configured to output the second signal QN1 according to the third signal, the high level signal VS, and the reset signal RSTN. The other input terminals of the sixth and gate A6 also receive a fourth signal QN2 and the first clock inversion signal clk', the output terminal of the sixth and gate A6 is respectively connected to the clock terminal of the twelfth D flip-flop Q12, the input terminal of the second inverter T2, and the input terminal of the third phase-shift pulse generating subunit, and the sixth and gate A6 is configured to phase the input signal and output a fifth signal. The twelfth D flip-flop Q12 has a data terminal connected to the high level signal VS and an enable terminal connected to the reset signal RSTN, and the twelfth D flip-flop Q12 is configured to output the fourth signal QN2 according to the high level, the reset signal RSTN, and the fifth signal. The second inverter T2 is configured to invert the fifth signal and output a second pulse pls2 of each phase-shifted pulse group;

The specific structure and function of the third phase-shifted pulse generation subunit 1223 to the nth phase-shifted pulse generation subunit 122n are the same as those of the second phase-shifted pulse generation subunit 1222; each phase-shifting pulse generating subunit is connected in sequence through the output end of the AND gate and the clock end of the D trigger. The reset signal RSTN is used for resetting phase-shifting pulse information of a previous phase-shifting pulse group.

Referring to fig. 8, as a specific embodiment, the digital-to-analog conversion module 13 is specifically n parallel ADCs; and n phase-shifting pulses which are adjacent in sequence in the phase-shifting pulse group sequentially correspond to n parallel ADCs, sampling is stopped by controlling the ADCs through the falling edges of the n phase-shifting pulses which are adjacent in sequence, and the gate-source voltage corresponding to the falling edge time of the phase-shifting pulse is converted into a digital level signal. Wherein, the ADC specifically comprises: the type of the successive approximation register type ADC is not limited to the successive approximation register type, as long as the ADC capable of converting an analog voltage into a corresponding digital signal falls within the scope of the present invention, such as an integrating ADC, a parallel comparison a/D converter, and the like.

Referring to fig. 9, an embodiment of the present invention further provides an integrated driving chip of a power tube, for implementing the driving method of the power tube provided by the embodiment of the present invention, where a first end of the power tube is coupled to ground, and a second end of the power tube is connected to a switching power supply terminal Vds through a load, the chip includes:

The embodiment of the invention provides a miller platform determination system 10;

a driving output module 20 coupled to an output of the second pulse adaptive unit 173 and an output of the logic control module 14, respectively; the driving output module 20 is configured to sequentially output a first conduction current, a second conduction current, and a third conduction current according to the driving enable signal en_drive, the starting position of the miller stage, and the ending position of the driving enable signal en_drive and the miller stage, so as to control staged conduction of the power tube; wherein the third conduction current is greater than the first conduction current, and the first conduction current is greater than the second conduction current; the power tube is also used for outputting a first turn-off current according to the driving enabling signal EN_DRIVE so as to turn off the power tube;

and a power supply terminal VCC for providing an operating voltage for each module in the miller stage determination system 10 and the driving output module 20.

Referring to fig. 10, as a specific embodiment, the driving output module 20 specifically includes a driving signal generating unit 21 and a driving output unit 22;

The driving signal generating unit 21 includes a thirteenth D flip-flop Q13, a fourteenth D flip-flop Q14, a seventh and gate A7, a sixth or gate O6; the data end of the thirteenth D flip-flop Q13 is connected to a high level signal VS, while the enabling end of the phase-shifting pulse corresponding to the starting point position of the miller stage Zhong Duanjie receives the driving enabling signal en_drive, and the reverse output end of the phase-shifting pulse is connected to the input end of the seventh and gate A7; the other input end of the seventh and gate A7 is also connected to the driving enable signal en_drive, and the output end thereof is connected to the input end of the sixth or gate O6; the data terminal of the fourteenth D flip-flop Q14 is connected to a high level signal VS, and at the moment Zhong Duanjie, a phase-shifting pulse corresponding to the end position of the miller stage, the enable terminal thereof receives the driving enable signal en_drive, and the positive output terminal thereof is connected to the input terminal of the sixth or gate O6;

the driving signal generating unit 21 operates according to the following principle:

when the driving enabling signal EN_DRIVE is at a high level, namely a conducting stage of the power tube; before the rising edge of the phase-shift pulse corresponding to the starting point position of the miller stage comes, the reverse output end of the thirteenth D flip-flop Q13 outputs a high level, the seventh and gate A7 outputs a high level, and the first driving signal p1 output by the sixth or gate O6 is a high level; meanwhile, the second driving signal p2 output from the positive output terminal of the fourteenth D flip-flop Q14 is at a low level; when the rising edge of the phase-shift pulse corresponding to the starting point position of the miller stage arrives, the reverse output end of the thirteenth D flip-flop Q13 outputs a low level, the seventh and gate A7 outputs a low level, and the first driving signal p1 output by the sixth or gate O6 is changed from a high level to a low level because the second driving signal p2 output by the forward output end of the fourteenth D flip-flop Q14 is still at a low level; when the rising edge of the phase-shift pulse corresponding to the end position of the miller stage arrives, the second driving signal p2 output by the positive output end of the fourteenth D flip-flop Q14 is changed from low level to high level, so that the first driving signal p1 output by the sixth or gate O6 is changed from low level to high level.

When the driving enable signal EN_DRIVE is at a low level, namely the power tube is turned off; the first driving signal p1 output by the sixth or gate O6 and the second driving signal p2 output by the positive output terminal of the fourteenth D flip-flop Q14 are both at low level.

The driving output unit 22 includes a third inverter T3, a fourth inverter T4, a fifth inverter T5, a seventh or gate O7, an eighth or gate O8, a ninth or gate O9, an eighth and gate A8, a first turn-on component 221, a second turn-on component 222, a third turn-on component 223, and a first turn-off component 224; the input end of the third inverter T3 is connected to the first driving signal p1, and the output end thereof is connected to the input end of the seventh or gate O7; the input end of the fourth inverter T4 is connected to the second driving signal p2, and the output end thereof is connected to the input end of the eighth or gate O8; the input end of the fifth inverter T5 is connected with a conducting signal; wherein the on signal is obtained by the DRIVE enable signal en_drive through DRIVE boosting; the output end of the first logic circuit is respectively connected with the input end of the ninth or gate O9 and the input end of the eighth and gate A8; the output end of the eighth and gate A8 is connected to the control end of the first shut-off component 224, the input end of the ninth or gate O9, the input end of the eighth or gate O8, and the input end of the seventh or gate O7, respectively; the output end of the ninth or gate O9 is connected to the input end of the eighth and gate A8 and the control end of the third conducting component 223, respectively; the output end of the eighth or gate O8 is connected to the control end of the second conducting component 222; the output end of the seventh or gate O7 is connected to the control end of the first conducting component 221; the output ends of the first conduction component 221 to the third conduction component 223 are all connected to the gate of the power tube, the input ends of the first conduction component 221 to the third conduction component 223 are all connected to the power supply end VCC, the output end of the first turn-off component 224 is grounded, and the input end thereof is connected to the gate of the power tube.

The driving output unit 22 operates according to the following principle:

when the driving enable signal en_drive is at a high level, the fifth inverter T5 outputs a low level to the eighth and gate A8, and the eighth and gate A8 outputs a low level to the first turn-off component 224, so that the first turn-off component 224 does not output a current;

when the rising edge of the phase-shift pulse corresponding to the starting point of the miller stage comes before, the third inverter T3 outputs a low level to the seventh or gate O7 because the first driving signal p1 is at a high level, and the eighth and gate A8 outputs a low level to the seventh or gate O7, the eighth or gate O8, and the ninth or gate O9 respectively, so that the seventh or gate O7 outputs a low level to the first conducting component 221, and the first conducting component 221 outputs a first conducting sub-current I1; since the second driving signal p2 is at a low level at this time, the fourth inverter T4 outputs a high level to the eighth or gate O8, and the eighth or gate O8 outputs a high level to the second pass device 222, so that the second pass device 222 does not output a current; since the fifth inverter T5 and the eighth and gate A8 output low levels at this time, the ninth or gate O9 outputs low levels to the third conducting component 223, so that the third conducting component 223 outputs a third conducting sub-current I3; wherein the first conduction current=the first conduction sub-current i1+the third conduction sub-current I3.

When the rising edge of the phase-shift pulse corresponding to the starting point of the miller stage arrives, the third inverter T3 outputs a high level to the seventh or gate O7 because the first driving signal p1 is at a low level, and the seventh or gate O7 outputs a high level to the first conductive component 221, so that the first conductive component 221 does not output a current; because the second driving signal p2 is still low at this time, the second pass device 222 still outputs no current; since the fifth inverter T5 and the eighth and gate A8 still output low level at this time, the third turn-on component 223 still outputs the third turn-on sub-current I3; wherein the second conduction current=the third conduction sub-current I3.

When the rising edge of the phase-shift pulse corresponding to the end position of the miller stage arrives, the first conduction component 221 outputs the first conduction sub-current I1, and the second conduction component 222 outputs a second conduction sub-current I2 because the first driving signal p1 and the second driving signal p2 become high at this time; since the fifth inverter T5 and the eighth and gate A8 still output low level at this time, the third turn-on component 223 still outputs the third turn-on sub-current I3; wherein the third conduction current=the first conduction sub-current i1+the third conduction sub-current i3+the second conduction sub-current I2.

When the driving enable signal en_drive is at a low level, the fifth inverter T5 outputs a high level to the eighth and gate A8, and the eighth and gate A8 outputs a high level to the first turn-off component 224, so that the first turn-off component 224 outputs the first turn-off current IN; since the eighth and gate A8 outputs a high level at this time, the ninth or gate O9, the eighth or gate O8, and the seventh or gate O7 all output a high level, and none of the first through third pass components 221 through 223 outputs a current.

Referring to fig. 11 and 12, as an embodiment, the internal structures of the first conductive element 221 to the third conductive element 223 are: the output end of the inverter chain is connected with the grid electrode of a PLDMOS, and the drain electrode of the PLDMOS is used as an output end; wherein the inverter chain is composed of an even number of inverters connected in series, and the aspect ratio of the inverters connected in series is continuously increased to increase the driving capability of a signal input to the inverter chain. The internal structure of the first shut-off component 224 is specifically: the output end of the inverter chain is connected with the grid electrode of an NLDMOS, and the drain electrode of the NLDMOS is used as an output end; wherein the inverter chain is composed of an even number of inverters connected in series, and the aspect ratio of the inverters connected in series is continuously increased to increase the driving capability of a signal input to the inverter chain. Of course, the number of inverters connected in series in the inverter chain may be adjusted according to specific requirements, and is not limited herein.

As a preferred embodiment, the integrated driving chip of the power tube further comprises a protection module; the protection module is coupled between the output of the control unit 15 and the input of the synchronization unit 171; the protection module is configured to perform narrow pulse filtering on the control signal pwm_im, and output the control signal pwm_im to the synchronization unit 171; the temperature sensor is also used for detecting whether the working temperature of each module in the chip exceeds a third threshold temperature; if the power supply voltage exceeds the preset voltage, the protection module cuts off the power supply of the power supply end VCC and forms temperature hysteresis; it is also used for detecting whether the voltage of the power supply end VCC is lower than a fourth threshold voltage; if the voltage is lower than the preset voltage, the protection module cuts off the power supply of the power supply end VCC and forms voltage hysteresis.

As a specific implementation manner, the protection module specifically comprises an over-temperature protection circuit, an under-voltage protection circuit and a narrow pulse filtering circuit; wherein:

excessive operating temperatures of the chip may damage the internal circuitry of the chip and the corresponding power transistors, affecting system functionality. For this reason, a corresponding over-temperature protection circuit needs to be designed to ensure that the chip is within a reasonable temperature range during operation.

Referring to fig. 13, the over-temperature protection circuit specifically includes a first transistor q1, a second transistor q2, a first MOS transistor M1 to a twelfth MOS transistor M12, a first resistor R1 to a third resistor R3; the second MOS transistor M2 to the fifth MOS transistor M5 together form a current mirror structure, and source stages of the second MOS transistor M2 to the fifth MOS transistor M5 are connected to the power supply terminal VCC; the drain electrode of the first MOS tube M1 is connected with the grid electrode of the second MOS tube M2; the grid electrode of the first MOS tube M1 is connected with the base electrode of the first transistor q1 and is connected with a reference voltage VREF; the collector of the first transistor q1 is connected with the power supply end VCC, and the emitter of the first transistor q1 is connected with the first end of the third resistor R3; the second end of the third resistor R3 is respectively connected with the first end of the second resistor R2 and the base electrode of the second transistor q 2; the second end of the second resistor R2 is respectively connected with the first end of the first resistor R1 and the source stage of the sixth MOS tube M6; the drain electrode of the sixth MOS tube M6 is connected with the drain electrode of the third MOS tube M3; the collector electrode of the second transistor q2 is respectively connected with the drain electrode of the fourth MOS transistor M4 and the grid electrode of the seventh MOS transistor M7; the seventh MOS transistor M7 and the eighth MOS transistor M8, the ninth MOS transistor M9 and the tenth MOS transistor M10, the eleventh MOS transistor M11 and the twelfth MOS transistor M12 together form an inverter chain; the source of the first MOS transistor M1, the first end of the first resistor R1, the emitter of the second transistor q2, the source of the eighth MOS transistor M8, the source of the tenth MOS transistor M10, and the source of the twelfth MOS transistor M12 are all grounded.

The working principle of the over-temperature protection circuit is as follows: after the integrated driving chip is powered on, when the working temperature of the chip is in a normal range, the sixth MOS transistor M6 is kept closed. As the operating temperature of the integrated driving chip increases, the base-emitter voltage of the first transistor q1 decreases, so that the base voltage of the second transistor q2 increases; wherein, at this time, the base voltage of the second transistor q2 is:

V _A ＝V _REF -V _BE1 ≈I _E,Q1 (R ₁ +R ₂ )

wherein V is _A For characterizing the base voltage of the second transistor q2 at this time; v (V) _BE1 For characterizing the base-emitter voltage; i _E,Q1 For characterizing the current flowing through the first transistor q 1.

When the working temperature of the chip rises to exceed the third threshold temperature, the base voltage of the second transistor q2 is conducted to the second transistor q2, the conduction of the second transistor q2 pulls down the collector voltage of the second transistor q2, the collector voltage of the second transistor q2 is transmitted through the inverter chain, the second level signal OTP output by the over-temperature protection circuit is enabled to be turned from the original low level to the high level, and the integrated driving chip is turned off according to the high level, namely the over-temperature of the integrated driving chip is indicated. Meanwhile, since the collector voltage of the second transistor q2 is at a low level at this time, the seventh MOS transistor M7 and the eighth MOS transistor M8 form an inversion structure to output a high level; because the drain electrode of the eighth MOS transistor M8 is connected to the gate electrode of the sixth MOS transistor M6, the sixth MOS transistor M6 is turned on, so as to further increase the base voltage of the second transistor q 2; wherein, at this time, the base voltage of the second transistor q2 is:

V _A '≈(I ₃ +I _E,Q1 )R ₁ +R ₂ I _E,Q1

Wherein V is _A ' for characterizing the base voltage of the second transistor q2 at this time; i ₃ And the current used for representing the current flowing through the sixth MOS transistor M6.

This also means I _E,Q1 More drops are needed to turn back off the second transistor q2 again to flip the second level signal OTP to achieve temperature hysteresis. Of course, the over-temperature protection circuit may also have an existing structure, and is not limited herein.

When the power supply of the chip fails or the operating voltage drops below the normal range due to other reasons, this state is referred to as an under-voltage state. The chip in the under-voltage state often deviates from the pre-design index of each internal module due to the fact that the power supply voltage is too low, and even the normal operation of the chip is affected. This need to be avoided during circuit operation, and therefore undervoltage protection circuits are necessary in chip design.

Referring to fig. 14, referring to the drawings, the under-voltage protection circuit specifically includes: fourth resistor R4 to sixth resistor R6, thirteenth MOS tube M13, comparator COMP; the first end of the fourth resistor R4 is connected with the power supply end VCC, and the second end of the fourth resistor R4 is respectively connected with the first end of the fifth resistor R5 and the inverting input end of the comparator COMP; the second end of the fifth resistor R5 is respectively connected with the first end of the sixth resistor R6 and the drain electrode of the thirteenth MOS tube M13; the non-inverting input end of the comparator COMP is connected with the reference voltage VREF, and the output end of the comparator COMP is connected with the grid electrode of the thirteenth MOS transistor M13; the source of the thirteenth MOS transistor M13 and the second end of the sixth resistor R6 are both grounded.

The working principle of the undervoltage protection circuit is as follows: when the voltage provided by the power supply end VCC is in a reasonable range, the comparator COMP outputs a low level, and the subsequent logic control judges that the integrated driving chip is in a normal state according to the low level; when the voltage provided by the power supply terminal VCC is lower than the fourth threshold voltage, the comparator COMP outputs a high level, and the subsequent logic control determines that the integrated driving chip is in an abnormal state according to the high level, and turns off the integrated driving chip, and meanwhile, the thirteenth MOS transistor M13 is turned on due to the high level output by the comparator COMP, so as to reduce the voltage division ratio of the power supply terminal VCC input to the negative terminal of the comparator COMP, thereby forming a hysteresis effect. In order to improve the driving capability of the thirteenth MOS transistor M13, an even number of inverters may be added between the comparator COMP and the gate of the thirteenth MOS transistor M13, and the specific number may be adjusted according to the actual situation, which is not limited herein. Of course, the undervoltage protection circuit may also be an existing structure, which is not limited herein.

The embodiment of the invention considers that the integrated driving chip possibly has circuit parasitics and other reasons, and can cause the control signal PWM_IM input from the outside to generate wrong narrow pulses. In order to prevent such invalid signals from interfering with the chip circuitry, it is necessary to provide a narrow pulse filtering circuit in the chip to clean it.

Referring to fig. 15, the narrow pulse filtering circuit specifically includes a driving enhancer, a seventh resistor R7, a first capacitor c1, an operational amplifier Op, and an inverter chain; the input end of the input buffer is connected with the control signal PWM_IM input from the outside, and the output end of the input buffer is connected with the first end of the seventh resistor R7; the second end of the seventh resistor R7 is respectively connected with the first end of the first capacitor c1 and the non-inverting input end of the operational amplifier Op; the second end of the first capacitor c1 is grounded; the inverting input end of the operational amplifier Op is connected with the output end of the operational amplifier Op, and the output end of the operational amplifier Op is connected with the inverter chain.

The working principle of the narrow pulse filtering circuit is as follows: the parameters of the RC filter network formed by the seventh resistor R7 and the first capacitor c1 are adjusted to filter out unwanted narrow pulses, and the specific parameters can be set according to actual requirements without limitation.

As a specific implementation manner, the integrated driving chip of the power tube further comprises a band gap reference circuit. The over-voltage protection circuit and the under-voltage protection circuit are provided with the reference voltage VREF, wherein the reference voltage VREF is independent of temperature. The specific structure of the bandgap reference circuit is common knowledge in the art, and will not be described herein.

The embodiment of the invention also provides electronic equipment, which comprises the integrated driving chip of the power tube.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. The utility model provides a miller platform determination method for determining starting point position and terminal point position of miller platform in the switching-on stage of power tube, characterized in that, this method includes:

2. The miller stage determination method of claim 1, wherein comparing the digital level signal corresponding to each phase-shifted pulse in the first set of phase-shifted pulses with the digital level signal corresponding to the previous adjacent phase-shifted pulse, comprises:

3. The miller stage determination method of claim 1, wherein determining whether the timing of the first set of phase-shifted pulse groups matches the waveform of the gate-source voltage comprises:

4. The miller stage determination method of claim 1, further comprising, after determining that the timing of the first set of phase-shifted pulse groups does not match the waveform of the gate-source voltage:

5. The miller stage determination method of claim 4, wherein the acquisition of the drive enable signal and the phase shift enable signal comprises:

6. The miller stage determination method of claim 5, wherein adjusting the timing of the first set of phase-shifted pulse groups or the waveform of the gate-source voltage comprises:

7. The miller stage determination method according to claim 1, wherein comparing the digital level signal corresponding to each phase-shifted pulse with the digital level signal corresponding to the previous adjacent phase-shifted pulse in the second group of phase-shifted pulses to the mth group of phase-shifted pulses to obtain the first voltage signal, specifically comprising:

8. The miller stage determination method of claim 7, wherein comparing each of the digital level signals with the first voltage signal to determine a starting point location of the miller stage and an ending point location of the miller stage comprises:

9. A method of driving a power tube, the method comprising:

determining a starting point position and an end point position of a miller stage in a conducting stage of a power tube by using the miller stage determination method according to any one of claims 1 to 8;

10. A miller stage determination system for implementing the miller stage determination method of any of claims 1 to 8, the system comprising:

11. The miller stage determination system of claim 10, wherein the logic control module, upon determining that the timing of the first set of phase-shifted pulse groups does not match the waveform of the gate-source voltage, is further configured to:

12. The miller stage determination system of claim 11, wherein the miller stage determination system further comprises:

13. The miller stage determination system according to claim 12, wherein the logic control module is configured to compare the digital level signal corresponding to each phase-shifted pulse with the digital level signal corresponding to the previous adjacent phase-shifted pulse in the second group of phase-shifted pulses to the mth group of phase-shifted pulses to obtain the first voltage signal, specifically:

14. The miller stage determination system of claim 13, wherein the logic control module is configured to compare each of the digital level signals with the first voltage signal to determine a start point of the miller stage and an end point of the miller stage, in particular:

will satisfy V first _s >V _pl +V _ths Digital level signal correspondence of (2)As an end position of the miller stage.

15. The miller stage determination system of claim 10, wherein the digital-to-analog conversion module comprises n digital-to-analog converters independent of each other; wherein, the digital-to-analog converters respectively correspond to the phase-shifting pulses in the single phase-shifting pulse group in sequence.

16. An integrated driving chip of a power tube for implementing the driving method of a power tube as claimed in claim 9, wherein a first end of the power tube is coupled to ground, and a second end of the power tube is connected to a switching power supply end through a load, the chip comprising:

the miller stage determination system of any of claims 10 to 15;

17. The integrated driver chip of claim 16, wherein the integrated driver chip of the power tube further comprises a protection module; the protection module is coupled between the output end of the control unit and the input end of the synchronization unit;

18. An electronic device comprising the integrated driver chip of claim 16 or 17.