CN116722028A - 一种碳化硅mosfet器件结构及制备方法 - Google Patents
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Abstract
一种碳化硅MOSFET器件结构及制备方法,包括:SiCN++衬底、N型SiC外延层、自适应P+屏蔽区、自适应连接P区、自适应P+注入区、P型基区、P+注入区、源极欧姆接触、N+源区、栅氧化层、自适应连接源极欧姆接触、栅源隔离介质、栅极、源极加厚金属。本发明具有更低的比导通电阻、更低的峰值氧化层电场强度;本发明能够降低器件导通损耗、提升器件栅氧长期可靠性;本发明公开的屏蔽区电压自适应调整的SiC MOSFET结构,既拥有浮空P+屏蔽区MOSFET的低导通电阻,又具有接地P+屏蔽区SiC MOSFET的低氧化层峰值电场强度,在低损耗、高可靠性等方面具有明显的优势。
Description
技术领域
本发明涉及半导体技术领域,具体涉及一种碳化硅MOSFET器件结构及制备方法。
背景技术
SiC是一种宽禁带半导体材料,其拥有比硅材料更宽的禁带宽度、更高的临界击穿电场强度和更高的热导率。采用碳化硅材料制备功率器件,既可显著提升器件本身的性能,如导通电阻和开关速度等,还可以提升整个系统的性能,如提升工作频率、降低无源器件体积和提升系统转换效率等。
当前,功率器件仍然主要基于硅材料。但是,随着硅材料、加工工艺的不断进步以及硅功率器件结构的不断演变,硅功率器件的性能已经逐渐逼近材料的理论极限。为了提升硅功率器件的性能,需要付出更大的成本和代价。硅IGBT是应用极为广泛的硅功率器件。但是,硅IGBT是一种双极型器件,在关断过程中存在长时间的拖尾电流,一方面增加了关断损耗,另一方面还限制了上限开关速度。而基于SiC材料的制造的MOSFET属于单极型器件,可以从原理上避免硅IGBT器件的拖尾电流现象,有望在未来替代同等电压等级的硅IGBT,极大的提升系统的性能和工作频率。而碳化硅沟槽型MOSFET可以比平面MOSFET实现更低的导通电阻,可进一步降低器件导通损耗。碳化硅沟槽MOSFET是当前研究的热点和重点。
但是,在SiC沟槽MOSFET的栅沟槽底部和拐角位置容易出现电场集中,造成栅氧化层击穿和可靠性等问题。为了降低栅氧化层的峰值电场强度,在沟槽底部引入P+屏蔽区是被证实非常有效的手段。通常,为了发挥P+屏蔽区的屏蔽作用且避免P+屏蔽区浮空可能出现的动态退化问题,该注入区需和源极地电位连接。但是,在器件导通时P+屏蔽区和N型外延层会形成耗尽区,极大的缩小了电子电流的流通路径,增加了SiC MOSFE的导通电阻。
为了实现栅氧化层电场强度和导通电阻之间的更好折衷,目前主要有两种解决方案。一种是采用Infineon公司提出的非对称沟槽MOSFET,栅沟槽一侧用于导电,另一侧用于制作P+屏蔽区,但是该结构仍然会引入较大的JFET电阻。另一种方法是Rohm公司的双沟槽MOSFET,引入栅沟槽和源沟槽,但是该结构在栅极沟槽中心仍然具有较大的栅氧化层电场强度。
发明内容
为克服现有技术的不足,本发明提供了一种碳化硅MOSFET器件结构及制备方法,具体的,是一种屏蔽区电压自适应调整的碳化硅MOSFET器件结构及其制备方法。
本发明采用了如下的技术方案:
本发明的第一方面提供了一种碳化硅MOSFET器件结构,包括:SiC N++衬底、N型SiC外延层、自适应P+屏蔽区、自适应连接P区、自适应P+注入区、P型基区、P+注入区、源极欧姆接触、N+源区、栅氧化层、自适应连接源极欧姆接触、栅源隔离介质、栅极、源极加厚金属;
N型外延层位于SiC N++衬底上方,P+注入区和N+源区位于P型基区的上方,自适应P+屏蔽区位于栅氧化层的下方,自适应连接P区位于栅氧化层的侧方,自适应P+注入区位于自适应连接P区的上方,自适应连接源极欧姆接触和源极欧姆接触位于N型外延层的上方,栅氧化层和N型外延层的表面接触,源极加厚金属位于最表面;
所述结构是建立在N++ SiC衬底的N型外延层上,自适应连接P区位于栅沟槽的侧方,P型基区和自适应连接P区分列栅沟槽两侧,自适应P+注入区和自适应P+屏蔽区通过自适应连接P区相连。
进一步的,所述的自适应连接P区的掺杂浓度低于自适应P+屏蔽区和自适应P+注入区的掺杂浓度。
进一步的,栅极沟槽内包括栅氧化层和栅极,栅氧化层采用热氧化工艺或化学气相淀积工艺生成。
进一步的,所述的自适应连接P区与自适应P+注入区和自适应P+屏蔽区有交集,当器件处于阻断状态时,从自适应P+注入区到自适应P+屏蔽区应有连续的掺杂类型分布;
所述的自适应连接P区的掺杂区域和自适应P+注入区和自适应P+屏蔽区相交叠,自适应连接P区的掺杂区域的下方边缘可以超过自适应P+屏蔽区的下方边缘。
进一步的,所述自适应连接P区在垂直方向上分为多段,每段区域的间距保证在器件处于导通状态时至少有两段区域的耗尽区不能相连接;
所述的自适应P+屏蔽区可以同时位于栅极沟槽的侧方和下方,器件处于正向导通状态时自适应P+屏蔽区处于浮空状态;
所述的自适应P+屏蔽区最右侧边缘超过自适应连接P区的最右侧边缘。
本发明还涉及一种碳化硅MOSFET器件的制备方法,包括如下步骤:
步骤S701,在碳化硅N++衬底上外延生长一层N型外延层;
步骤S702,采用局部离子注入形成P型基区;
步骤S703,采用局部离子注入形成N+源区;
步骤S704,采用局部离子注入形成P+注入区和自适应P+注入区;
步骤S705,采用干法刻蚀形成穿过P型基区的栅极沟槽;
步骤S706,采用垂直和侧向离子注入组合形成自适应连接P区和自适应P+屏蔽区;
步骤S707,采用碳膜保护进行杂质离子注入激活;采用高温离子注入激活工艺完成注入杂质的激活;
步骤S708,采用热氧化或介质层淀积工艺形成栅氧化层,采用金属或掺杂多晶硅形成栅极;
步骤S709,采用欧姆接触工艺,形成正面欧姆接触、自适应源极欧姆接触和背面欧姆接触;
步骤S710,在器件上方淀积层间隔离介质并进行图形化,采用化学气相淀积CVD工艺生长一层层间隔离介质;
步骤S711,在器件的上方淀积源极加厚金属,实现源极互连;
步骤S712,在正面金属上方涂保护层并进行图形化;
步骤S713,背面金属化工艺。
进一步的,在表面淀积一定厚度的注入掩膜,通过光刻工艺确定离子注入窗口,调整离子注入参数、采用不同离子注入剂量和能量调整自适应P+屏蔽区和自适应连接P区的掺杂浓度和注入深度,采用垂直方向注入形成自适应P+屏蔽区,采用侧向即偏离垂直方向一定角度形成自适应连接P区。
进一步的,步骤S709中,对于背面欧姆接触,通过溅射方法生长一层欧姆接触金属,对于正面欧姆接触,先通过光刻工艺确定欧姆接触工艺窗口,然后通过金属溅射工艺生长一层特定厚度的欧姆接触金属,之后,通过金属剥离工艺以保证需要制备欧姆接触的区域保留欧姆接触金属,去除表面的光刻胶后,最后再进行欧姆退火工艺以形成良好的欧姆接触。
进一步的,步骤S711中,在器件正面,首先通过金属溅射工艺生长一定厚度的互连金属,然后通过光刻工艺确定工艺窗口,采用湿法腐蚀或干法刻蚀工艺以保证需要保留互连金属的区域有剩余的互连金属,最后去除表面的光刻胶。
进一步的,步骤S712中,在互连金属的上方涂抹一层保护层,通过光刻工艺确定工艺窗口,采用刻蚀工艺以保证需要保留保护层的区域有剩余的保护层,最后去除表面的光刻胶。
本发明的技术方案能够实现如下有益的技术效果:
本发明比接地屏蔽层沟槽MOSFET具有更低的比导通电阻;本发明比浮空屏蔽层沟槽MOSFET具有更低的峰值氧化层电场强度;本发明能够降低器件导通损耗、提升器件栅氧长期可靠性;
本发明公开的屏蔽区电压自适应调整的SiC MOSFET结构,既拥有浮空P+屏蔽区MOSFET的低导通电阻,又具有接地P+屏蔽区SiC MOSFET的低氧化层峰值电场强度,在低损耗、高可靠性等方面具有明显的优势。
附图说明
图1为本发明一个实施例中的屏蔽区电压自适应调整的SiC MOSFET结构示意图;
图2为本发明一个实施例中的传统浮空屏蔽区的SiC沟槽MOSFET结构;
图3为本发明一个实施例中的传统接地屏蔽区的SiC沟槽MOSFET结构;
图4为本发明一个实施例中的仿真模拟得到的图1至图3三种SiC沟槽MOSFET结构的静态导通特性比较图;
图5为本发明一个实施例中的仿真模拟得到的图1至图3三种SiC沟槽MOSFET结构的静态阻断电场分布拓扑图;
图6为本发明一个实施例中的仿真模拟得到的图1至图3三种SiC沟槽MOSFET结构的栅电荷特性比较图;
图7为本发明一个实施例中的屏蔽区电压自适应调整的SiC MOSFET制备方法流程图;
图8为本发明一个具体实施例中的屏蔽区电压自适应调整的SiC MOSFET制备方法流程图;
其中,100-屏蔽区电压自适应调整的SiC MOSFET结构:1-SiC N++衬底;2-N型SiC外延层;3-自适应P+屏蔽区;4-自适应连接P区;5-自适应P+注入区;6-P型基区;7-P+注入区;8-源极欧姆接触;9-N+源区;10-栅氧化层;11-自适应源极欧姆接触;12-栅源隔离介质;13一栅极;14-源极加厚金属。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明了,下面结合具体实施方式并参照附图,对本发明进一步详细说明。应该理解,这些描述只是示例性的,而并非要限制本发明的范围。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本发明的概念。
下面结合附图及实施例对本发明进行详细说明。
本发明是一种屏蔽区电压自适应调整的碳化硅MOSFET器件结构及其制备方法。本发明中,SiC MOSFET结构制备在N++SiC衬底上的N型外延层上,包括:栅极、源极、栅氧化层、N+源区、P型基区、N型外延层、自适应连接P区、自适应P+屏蔽区、自适应P+注入区,其中自适应P+屏蔽区位于栅沟槽的下方,自适应连接P区位于栅沟槽的侧方,P型基区和自适应连接P区分列栅沟槽两侧,自适应P+注入区和自适应P+屏蔽区通过自适应连接P区相连。通过调整自适应连接P区的掺杂浓度等参数,自适应P+屏蔽区的电位会随着SiC MOSFET的工作状态而自适应调整,在导通时,自适应P+屏蔽区电位浮空,有利于降低器件通态压降,在阻断时,自适应P+屏蔽区连接到地电位,从而自适应P+屏蔽区可以有效抑制栅氧化层峰值电场强度。
图1给出了本发明一个示例中的屏蔽区电压自适应调整的SiC MOSFET结构示意图,本发明的碳化硅MOSFET器件结构100包括:SiCN++衬底1、N型SiC外延层2、自适应P+屏蔽区3、自适应连接P区4、自适应P+注入区5、P型基区6、P+注入区7、源极欧姆接触8、N+源区9、栅氧化层10、自适应连接源极欧姆接触11、栅源隔离介质12、栅极13、源极加厚金属14。
N型外延层2位于SiCN++衬底上1上方,P+注入区7和N+源区9位于P型基区6的上方,自适应P+屏蔽区3位于栅氧化层10的下方,自适应连接P区4位于栅氧化层10的侧方,而自适应P+注入区5位于自适应连接P区4的上方,自适应连接源极欧姆接触11和源极欧姆接触8位于N型外延层2的上方,栅氧化层10和N型外延层2的表面应接触,源极加厚金属14位于最表面。
所述SiC MOSFET结构是建立在N++SiC衬底的N型外延层上,自适应连接P区4位于栅沟槽的侧方,P型基区6和自适应连接P区4分列栅沟槽两侧,自适应P+注入区5和自适应P+屏蔽区3通过自适应连接P区4相连。
具体的,自适应P+注入区5和P+注入区7可采用两步注入工艺也可采用一步工艺同时形成;两者的注入浓度和注入深度等参数可以相同也可以不相同,但是其浓度必须足够高(典型值大于1e19cm-3)以保证源极欧姆接触和自适应源极欧姆接触的质量。
具体的,所述的自适应连接P区的掺杂浓度应低于自适应P+屏蔽区和自适应P+注入区的掺杂浓度,其中,所述自适应连接P区的掺杂浓度典型范围为1e15cm-3~1e19cm-3。
具体的,栅极沟槽内包括栅氧化层10和栅极13。栅氧化层可以采用热氧化工艺生成,也可采用化学气相淀积CVD工艺生成。但必须指出,栅氧化层并不仅是指SiO2,其他MOSFET器件可用的介质,如Si3N4和高K介质,都适用于本发明所提出的器件结构。
具体的,自适应连接P区4的掺杂浓度和宽度(横向长度)需要通过优化以实现本发明器件性能提升的目的。自适应连接P区4必须保证:在SiC MOSFET导通时,其处于耗尽状态以使得栅沟槽底部的自适应P+屏蔽区3处于浮空状态,而在SiC MOSFET关断时,其能够连接自适应P+注入区5和自适应P+屏蔽区3,以使得从自适应P+注入区5到自适应P+屏蔽区3形成连续的相同掺杂类型分布。
所述的自适应连接P区应在器件处于导通状态时处于耗尽状态或部分耗尽状态,至少保证与栅氧化层接触的特定宽度范围内的区域耗尽,所述的特定宽度典型值为0.01μrn~1μm。
所述的自适应连接P区与自适应P+注入区和自适应P+屏蔽区要有交集,特别的,当器件处于阻断状态时,从自适应P+注入区到自适应P+屏蔽区应有连续的掺杂类型分布。
所述的N型和P型掺杂可以互换,即所有的N型掺杂均可以为P型掺杂且所有的P型掺杂均可以为N型掺杂,所提出的工作机理仍然适用。
所述的P+注入区和自适应P+注入区既可分两步工艺制作,也可采用一步工艺制作。特别的,P+注入区和自适应P+注入的掺杂浓度、注入深度等参数可保持一致也可按照特定的规律变化。
所述的自适应连接P区的掺杂区域可以和自适应P+注入区和自适应P+屏蔽区相交叠,特别的,自适应连接P区的掺杂区域的下方边缘可以超过自适应P+屏蔽区的下方边缘。
所述自适应连接P区在垂直方向上可以分为多段,每段区域的间距需保证在器件处于导通状态时至少有两段区域的耗尽区不能相连接,即该两段区域之间的N型区域不能够被完全耗尽。而且,各段自连接P区的横向长度和纵向长度既可以保持一致也可以按照特定的规律变化。
所述的自适应P+屏蔽区可以同时位于栅极沟槽的侧方和下方,但必须保证在器件处于正向导通状态时自适应P+屏蔽区处于浮空状态。
所述的自适应连接P区和自适应P+屏蔽区在横向和纵向上的掺杂浓度和宽度既可以保持一致也可以按照特定的规律变化。
所述的自适应P+屏蔽区最右侧边缘可以超过自适应连接P区的最右侧边缘。
本发明实施例基于TCAD软件,对图1~图3所示的三种典型器件结构进行了仿真对比。仿真对比前,均对三种典型器件的结构参数进行了变化。
图4给出了利用仿真获得的三种器件结构的静态导通特性对比。从仿真结果可以看出,相比于接地屏蔽区的SiC MOSFET结构,本发明实施例中的SiC MOSFET结构的比导通电阻显著降低,这有利于降低器件导通过程中的损耗和提高系统的电能转换效率。
图5给出了利用仿真获得的三种器件结构的静态阻断电场分布拓扑图。从仿真结果可以看出,相比于传统浮空屏蔽区的SiC MOSFET结构,本发明示例中的SiC MOSFET结构的峰值栅氧化层电场强度显著降低,这有利于避免栅氧化层击穿和提升器件的长期可靠性。
图6给出了利用仿真获得的三种器件结构的栅电荷特性对比结果。栅电荷特性的米勒平台时间越短,则意味着米勒电容越小,开关速度越快。对于SiC MOSFET结构,米勒电容主要取决于栅电极和漏电极的重叠面积大小。由于本发明实例提出的SiC MOSFET器件结构可能需要采用侧向离子注入工艺来形成自适应连接P区和自适应P+屏蔽区,因此其元胞宽度要大于浮空屏蔽区和接地屏蔽区的SiC MOSFET结构,这意味着更小的栅极和漏极重叠面积。所以,本发明实例中的SiC MOSFET结构米勒平台时间最短,具有比其他两种结构更快的开关速度,更适合于高频工作。
本发明还提供了一种碳化硅MOSFET器件的制备方法,具体的,图7给出了本发明实施例的一种具体的工艺流程图。
所述碳化硅MOSFET器件的制备方法包括:
步骤S701,在碳化硅N++衬底上外延生长一层N型外延层;
步骤S702,采用局部离子注入方法形成P型基区;
步骤S703,采用局部离子注入方法形成N+源区(N+源区);
步骤S704,采用局部离子注入方法形成P+注入区和自适应P+注入区;
步骤S705,采用干法刻蚀方法形成穿过P型基区的栅极沟槽;
步骤S706,采用垂直和侧向离子注入组合方法形成自适应连接P区和自适应P+屏蔽区;
步骤S707,采用碳膜保护进行杂质离子注入激活;采用高温离子注入激活工艺完成注入杂质的激活;
步骤S708,采用热氧化或介质层淀积工艺形成栅氧化层,采用金属或掺杂多晶硅形成栅极;
步骤S709,采用欧姆接触工艺,形成正面欧姆接触、自适应源极欧姆接触和背面欧姆接触;
步骤S710,采用化学气相淀积CVD工艺生长一层层间隔离介质;在器件上方淀积层间隔离介质并进行图形化;
步骤S711,采用溅射工艺生长源极互连金属;在器件的上方淀积源极加厚金属,实现源极互连;
步骤S712,在正面金属上方涂保护层并进行图形化;
步骤S713,背面金属化工艺。
下面结合图8对工艺流程作更具体的说明,
步骤S701,如图8(a)所示,在碳化硅N++衬底上外延生长一层掺杂浓度为1e13~1e18cm-3的N型外延层,
以穿通型器件为例,阻断电压和外延层厚度及掺杂浓度之间的关系可表述为:
其中,BV为器件的阻断电压,Ec为碳化硅材料的临界击穿电场强度,Wn为所需的外延层厚度,Nd为外延层的掺杂浓度,q为单电子电荷,εs为碳化硅材料的介电常数。
步骤S702,如图8(b)所示,采用局部注入方法形成P型基区,掺杂浓度范围在1e14~5e18cm-3之间。
步骤S703,如图8(c)所示,利用局部离子注入方法形成N+源区,注入掺杂杂质通常为氮。
步骤S704,如图8(d)所示,利用局部离子注入方法形成P+注入区和自适应P+注入区,注入掺杂杂质通常为铝,可采用多种不同剂量和能量组合的方法来形成预期的掺杂浓度分布。必须指出,P+注入区和自适应P+注入区可采用两个工艺步骤进行制备,其浓度和深度保证高质量欧姆接触即可。在本发明实例提供的工艺流程中,P+注入区和自适应P+注入区采用一步完成,是为了简化工艺实现步骤,有利于降低实际制造中的成本。
步骤S705,如图8(e)所示,采用干法刻蚀等工艺形成栅极沟槽。栅极沟槽刻蚀深度应该足够大(刻蚀深度典型值应大于0.6μm)以保证穿透P型基区,用来提供电子导通路径。
步骤S706,如图8(f)所示,采用垂直和侧向离子注入组合的方式形成自适应连接P区和自适应P+屏蔽区。自适应连接P区的掺杂浓度和宽度等参数可以通过改变侧向注入角度、能量和剂量来实现。
具体的,在表面淀积一定厚度的注入掩膜,通过光刻工艺确定离子注入窗口,调整离子注入参数、采用不同离子注入剂量和能量调整自适应P+屏蔽区和自适应连接P区的掺杂浓度和注入深度,注入杂质通常采用铝(A1),采用垂直方向注入形成自适应P+屏蔽区,采用侧向即偏离垂直方向一定角度形成自适应连接P区。
步骤S707,采用碳膜保护进行杂质的离子注入激活。
步骤S708,如图8(g)所示,采用热氧化工艺形成栅氧化层,采用掺杂多晶硅形成栅极。栅氧化层的形成既可以采用热氧化工艺,也可采用化学气相淀积CVD工艺。栅极既可采用重掺杂的多晶硅,也可采用金属。
步骤S709,如图8(h)所示,采用欧姆接触工艺,形成正面源极欧姆、自适应源极欧姆接触和背面的欧姆接触(图中未给出)。
具体的,碳化硅材料欧姆接触常用金属有镍(Ni)、钛(Ti)。对于背面欧姆接触,可通过溅射方法生长一层欧姆接触金属,对于正面欧姆接触,先通过光刻工艺确定欧姆接触工艺窗口,然后通过金属溅射工艺生长一层特定厚度的欧姆接触金属,之后,通过金属剥离工艺以保证需要制备欧姆接触的区域保留欧姆接触金属,去除表面的光刻胶后,最后再进行欧姆退火工艺以形成良好的欧姆接触。
步骤S710,如图8(i)所示,采用化学气相淀积CVD工艺生长一层层间隔离介质。典型的隔离介质包括SiO2和Si3N4等。
步骤S711,如图8(j)所示,采用溅射工艺在正面淀积一定厚度的金属作为源极互连金属。典型的互连金属为铝。
具体的,在器件正面,首先通过金属溅射工艺生长一定厚度的互连金属,厚度典型值为2~5μm,然后通过光刻工艺确定工艺窗口,采用湿法腐蚀或干法刻蚀工艺以保证需要保留互连金属的区域有剩余的互连金属,最后去除表面的光刻胶。
步骤S712,在正面金属上方涂一层保护层,如聚酰亚胺等,并进行图形化以提供封装用键合窗口。
具体的,在互连金属的上方涂抹一层保护层,如聚酰亚胺等,通过光刻工艺确定工艺窗口,采用刻蚀工艺以保证需要保留保护层的区域有剩余的保护层,最后去除表面的光刻胶。
步骤S713,背面金属化工艺,为后续封装做准备。
至此,本实例所提出的屏蔽区电压自适应调整的SiC MOSFET结构可采用S701~S713步骤实现。
综上所述,本发明提供了一种碳化硅MOSFET器件结构及制备方法,包括:SiCN++衬底、N型SiC外延层、自适应P+屏蔽区、自适应连接P区、自适应P+注入区、P型基区、P+注入区、源极欧姆接触、N+源区、栅氧化层、自适应连接源极欧姆接触、栅源隔离介质、栅极、源极加厚金属。本发明具有更低的比导通电阻、更低的峰值氧化层电场强度;本发明能够降低器件导通损耗、提升器件栅氧长期可靠性;本发明公开的屏蔽区电压自适应调整的SiC MOSFET结构,既拥有浮空P+屏蔽区MOSFET的低导通电阻,又具有接地P+屏蔽区SiC MOSFET的低氧化层峰值电场强度,在低损耗、高可靠性等方面具有明显的优势。
应当理解的是,本发明的上述具体实施方式仅仅用于示例性说明或解释本发明的原理,而不构成对本发明的限制。因此,在不偏离本发明的精神和范围的情况下所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。此外,本发明所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。
Claims (10)
1.一种碳化硅MOSFET器件结构,其特征在于,包括:SiCN++衬底、N型SiC外延层、自适应P+屏蔽区、自适应连接P区、自适应P+注入区、P型基区、P+注入区、源极欧姆接触、N+源区、栅氧化层、自适应连接源极欧姆接触、栅源隔离介质、栅极、源极加厚金属;
N型外延层位于SiCN++衬底上方,P+注入区和N+源区位于P型基区的上方,自适应P+屏蔽区位于栅氧化层的下方,自适应连接P区位于栅氧化层的侧方,自适应P+注入区位于自适应连接P区的上方,自适应连接源极欧姆接触和源极欧姆接触位于N型外延层的上方,栅氧化层和N型外延层的表面接触,源极加厚金属位于最表面;
所述结构是建立在N++SiC衬底的N型外延层上,自适应连接P区位于栅沟槽的侧方,P型基区和自适应连接P区分列栅沟槽两侧,自适应P+注入区和自适应P+屏蔽区通过自适应连接P区相连。
2.根据权利要求1所述的碳化硅MOSFET器件结构,其特征在于,所述的自适应连接P区的掺杂浓度低于自适应P+屏蔽区和自适应P+注入区的掺杂浓度。
3.根据权利要求1所述的碳化硅MOSFET器件结构,其特征在于,栅极沟槽内包括栅氧化层和栅极,栅氧化层采用热氧化工艺或化学气相淀积工艺生成。
4.根据权利要求1所述的碳化硅MOSFET器件结构,其特征在于,所述的自适应连接P区与自适应P+注入区和自适应P+屏蔽区有交集,当器件处于阻断状态时,从自适应P+注入区到自适应P+屏蔽区应有连续的掺杂类型分布;
所述的自适应连接P区的掺杂区域和自适应P+注入区和自适应P+屏蔽区相交叠,自适应连接P区的掺杂区域的下方边缘可以超过自适应P+屏蔽区的下方边缘。
5.根据权利要求1所述的碳化硅MOSFET器件结构,其特征在于,所述自适应连接P区在垂直方向上分为多段,每段区域的间距保证在器件处于导通状态时至少有两段区域的耗尽区不能相连接;
所述的自适应P+屏蔽区可以同时位于栅极沟槽的侧方和下方,器件处于正向导通状态时自适应P+屏蔽区处于浮空状态;
所述的自适应P+屏蔽区最右侧边缘可以超过自适应连接P区的最右侧边缘。
6.一种碳化硅MOSFET器件的制备方法,其特征在于,包括如下步骤:
步骤S701,在碳化硅N++衬底上外延生长一层N型外延层;
步骤S702,采用局部离子注入形成P型基区;
步骤S703,采用局部离子注入形成N+源区;
步骤S704,采用局部离子注入形成P+注入区和自适应P+注入区;
步骤S705,采用干法刻蚀形成穿过P型基区的栅极沟槽;
步骤S706,采用垂直和侧向离子注入组合形成自适应连接P区和自适应P+屏蔽区;
步骤S707,采用碳膜保护进行杂质离子注入激活;采用高温离子注入激活工艺完成注入杂质的激活;
步骤S708,采用热氧化或介质层淀积工艺形成栅氧化层,采用金属或掺杂多晶硅形成栅极;
步骤S709,采用欧姆接触工艺,形成正面欧姆接触、自适应源极欧姆接触和背面欧姆接触;
步骤S710,在器件上方淀积层间隔离介质并进行图形化,采用化学气相淀积CVD工艺生长一层层间隔离介质;
步骤S711,在器件的上方淀积源极加厚金属,实现源极互连;
步骤S712,在正面金属上方涂保护层并进行图形化;
步骤S713,背面金属化工艺。
7.根据权利要求6所述的碳化硅MOSFET器件的制备方法,其特征在于,步骤S706中,在表面淀积一定厚度的注入掩膜,通过光刻工艺确定离子注入窗口,调整离子注入参数、采用不同离子注入剂量和能量调整自适应P+屏蔽区和自适应连接P区的掺杂浓度和注入深度,采用垂直方向注入形成自适应P+屏蔽区,采用侧向即偏离垂直方向一定角度形成自适应连接P区。
8.根据权利要求6所述的碳化硅MOSFET器件的制备方法,其特征在于,步骤S709中,对于背面欧姆接触,通过溅射方法生长一层欧姆接触金属,对于正面欧姆接触,先通过光刻工艺确定欧姆接触工艺窗口,然后通过金属溅射工艺生长一层特定厚度的欧姆接触金属,之后,通过金属剥离工艺以保证需要制备欧姆接触的区域保留欧姆接触金属,去除表面的光刻胶后,最后再进行欧姆退火工艺以形成良好的欧姆接触。
9.根据权利要求6所述的碳化硅MOSFET器件的制备方法,其特征在于,步骤S711中,在器件正面,首先通过金属溅射工艺生长一定厚度的互连金属,然后通过光刻工艺确定工艺窗口,采用湿法腐蚀或干法刻蚀工艺以保证需要保留互连金属的区域有剩余的互连金属,最后去除表面的光刻胶。
10.根据权利要求6所述的碳化硅MOSFET器件的制备方法,其特征在于,步骤S712中,在互连金属的上方涂抹一层保护层,通过光刻工艺确定工艺窗口,采用刻蚀工艺以保证需要保留保护层的区域有剩余的保护层,最后去除表面的光刻胶。
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