CN116721689A - Storage device with post-package repair function and repair method thereof - Google Patents
Storage device with post-package repair function and repair method thereof Download PDFInfo
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- CN116721689A CN116721689A CN202211562810.7A CN202211562810A CN116721689A CN 116721689 A CN116721689 A CN 116721689A CN 202211562810 A CN202211562810 A CN 202211562810A CN 116721689 A CN116721689 A CN 116721689A
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- 230000008439 repair process Effects 0.000 title claims abstract description 89
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004806 packaging method and process Methods 0.000 claims abstract description 6
- 230000006870 function Effects 0.000 claims description 23
- 238000005538 encapsulation Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 8
- 102100023882 Endoribonuclease ZC3H12A Human genes 0.000 description 2
- 101710112715 Endoribonuclease ZC3H12A Proteins 0.000 description 2
- QGVYYLZOAMMKAH-UHFFFAOYSA-N pegnivacogin Chemical compound COCCOC(=O)NCCCCC(NC(=O)OCCOC)C(=O)NCCCCCCOP(=O)(O)O QGVYYLZOAMMKAH-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000013475 authorization Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a storage device with a post-package repair function and a repair method thereof, wherein the storage device with the post-package repair function comprises a storage unit, and the storage device further comprises: a FAM register set disposed in the storage device, each FAM register in the FAM register set being configured to record an address of a failed storage unit according to an external command; an embedded processor, comprising: the FAM register group comprises a programming controller and a FAM counter, wherein the FAM counter is used for sequentially selecting the FAM registers in the FAM register group when program execution starts, and the programming controller is used for repairing corresponding invalid storage units after packaging according to address bit information of the FAM registers selected by the FAM counter until all address bit information of the FAM registers are output. According to the technical scheme, the storage device can repair a plurality of storage units after executing one external command, so that the repair efficiency is greatly improved.
Description
Technical Field
The present application relates to the field of semiconductor manufacturing, and in particular, to a memory device having a post-package repair function and a repair method thereof.
Background
Based on JEDEC protocol, for a storage device supporting post-package repair (PPR: post Package Repair), the address of 1 storage unit corresponding thereto can be repaired only by 1 command/repair address. However, when multiple memory units need to be repaired, a separate FAM (Fast Access Memory ) register needs to be configured for the application processor (Application Processor) to store the addresses of the failed units, and at the same time, the same number of commands/address information as the number of memory units needing to be repaired need to be externally authorized, which is complicated in execution steps.
Therefore, it is a problem to be solved to provide a storage device and a repair method thereof that are easy to execute and enable post-package repair of a plurality of storage units based on JEDEC protocol.
Disclosure of Invention
The application aims to solve the technical problem of providing a storage device with a post-packaging repair function and a repair method thereof, which can repair a plurality of storage units after packaging.
In order to solve the above-mentioned problem, the present application provides a storage device with post-package repair function, including a storage unit, the storage device further including: a FAM register set disposed in the storage device, each FAM register in the FAM register set being configured to record an address of a failed storage unit according to an external command; an embedded processor, comprising: the FAM register group comprises a programming controller and a FAM counter, wherein the FAM counter is used for sequentially selecting the FAM registers in the FAM register group when program execution starts, and the programming controller is used for repairing corresponding invalid storage units after packaging according to address bit information of the FAM registers selected by the FAM counter until all address bit information of the FAM registers are output.
In some embodiments, the programming controller has a built-in programming sequence to program address information of the failed memory cell according to the address bit information and output address command information.
In some embodiments, the embedded processor reads the address bit information from the FAM register according to a post-encapsulation repair protocol and sequentially repairs all of the failed memory cells according to the address bit information.
In some embodiments, the storage device further comprises: and the MRW protocol and the MRW register set are arranged in the storage device so as to define an access method for writing fault addresses into the FAM register set according to the JEDEC protocol.
In some embodiments, the embedded processor further controls the FAM register to record address bit information of failed memory locations according to external commands and the MRW protocol.
In some embodiments, the memory cell is further an array of antifuse cells.
The application also provides a repairing method of the storage device with the post-packaging repairing function, the storage device comprises a storage unit, and the repairing method is characterized by comprising the following steps: configuring a FAM register set in the storage device, wherein each FAM register in the FAM register set is used for recording address bit information of a failed storage unit according to an external command; configuring an embedded processor in the storage device, the embedded processor comprising: programming a controller and a FAM counter; and when program execution starts, the FAM counter sequentially selects the FAM registers in the FAM register group, and the programming controller packages and restores the corresponding invalid storage units according to the address bit information of the FAM registers selected by the FAM counter until the address bit information of all the FAM registers is output, so that program execution is completed.
In some embodiments, the programming controller employs a built-in programming sequence to program address information of the failed memory cell according to the address bit information and output address command information.
In some embodiments, the method further comprises: and the embedded processor is adopted to read the address bit information from the FAM register according to a post-encapsulation repair protocol, and repair all the failed memory cells in sequence according to the address bit information.
According to the technical scheme, the FAM register is arranged in the storage device, and the address of the failed storage unit is recorded through the FAM register; sequentially selecting FAM registers through the FAM counter; the storage device is packaged and repaired according to the address bit information of the selected FAM register, so that the storage device can repair a plurality of storage units after executing an external command, the situation that when the storage device executes multi-unit repair according to JEDEC protocol, a single FAM register is required to be prepared for storing the address information of the failed storage unit and as many external commands as the failed storage unit are required is avoided, and the repairing efficiency is greatly improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory device with post-package repair function in accordance with an embodiment of the present application;
FIG. 2 is a flow chart of a repair method for a storage device with post-package repair function in one embodiment of the application;
FIG. 3 is a flow chart of a repair method for a memory device with post-package repair function in another embodiment of the application;
FIG. 4 is a timing diagram illustrating operation of a memory device according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a prior art memory device with post-package repair function;
FIG. 6 is a timing diagram illustrating operation of the memory device of FIG. 5.
Detailed Description
The following describes in detail a specific embodiment of a storage device with a post-package repair function and a repair method thereof according to the present application with reference to the accompanying drawings. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the application, its application, or uses. That is, those skilled in the art will appreciate that they are merely illustrative of the manner in which they may be used in real time and not exhaustive. Furthermore, the relative arrangement of the components and steps set forth in these embodiments does not limit the scope of the present application unless specifically stated otherwise.
The following first describes a storage device with post-package repair function according to an embodiment of the present application. FIG. 1 is a schematic diagram of a memory device with post-package repair function in an embodiment of the application. Referring to fig. 1, the storage device with post-package repair function includes a register module 1 and a control repair module 2, wherein the register module 1 complies with a mode register write protocol (Mode Register Write protocol) D1 in the JEDEC protocol, and the control repair module 2 complies with a post-package repair protocol (Post Package Repair protocol) D2 in the JEDEC protocol.
The register module 1 includes a FAM (Fast Access Memory ) register set 3 disposed within the storage device, and the control repair module 2 includes: a memory unit 4 and an embedded processor (build-In processor) 5. The FAM register set 3 includes a plurality of FAM registers REG 0-REGn-1, each of which complies with JEDEC protocol and records an address of a failed memory cell according to an external command (not shown). The embedded processor 5 includes: a program controller (PGM Control) 6 and a FAM counter (FAM counter) 7; the FAM counter 7 is configured to sequentially select FAM registers in the FAM register set 3 when program execution begins, and the programming controller 6 is configured to encapsulate and repair corresponding failed memory cells according to Address bit information (Address bit) D3 of the FAM registers selected by the FAM counter 7 until the Address bit information D3 of all FAM registers in the FAM register set 3 is sequentially output, and the program execution is completed.
The storage device with the post-encapsulation repair function provided by the embodiment avoids the situation that when the storage device complies with JEDEC protocol, because the storage device can only perform one-time address repair on the storage unit by executing one external command, when multi-unit repair is required to be performed, a single FAM register is required to be prepared for storing address information of a failed storage unit and as many external commands as the failed storage unit are required, the storage device can perform post-encapsulation repair on a plurality of storage units by executing one external command.
With continued reference to fig. 1, in this embodiment, the storage device further includes: the MRW protocol and MRW (Mode Register Write ) register set 8 disposed in the storage device is used to define an access method for writing to the FAM register set 3 according to JEDEC protocol.
In this embodiment, the embedded processor 5 further controls the FAM register to record address bit information of the failed memory cell according to an external command. For example, the embedded processor 5 controls the FAM register according to an access method of the FAM register, and records address bit information of a failed memory cell according to an external command and the MRW protocol.
In some embodiments, the register module 1 further comprises: and a decoder 12, where the decoder 12 is configured to decode the external command, and output the decoded external command to enable the embedded processor 5 to control the FAM register to record address bit information of a failed memory location according to the external command.
With continued reference to fig. 1, the embedded processor 5 further reads the address bit information D3 from the FAM register according to the post-package repair Protocol (PPR Protocol) D2, and repairs all the failed memory cells in sequence according to the address bit information D3.
In some embodiments, the programming controller 6 has a built-in programming sequence to program the address information of the failed memory cell according to the address bit information D3 and output address command information (Program Command Address) D4 to repair the memory cell in sequence according to the address command information D4. Of course, the embedded processor 5 may also execute applications providing internet browsers, games, video, etc. In other embodiments, the embedded processor 5 may further include a cache memory disposed in the embedded processor 5 or disposed external to the embedded processor 5.
In the present embodiment, the FAM register set 3 includes n FAM registers REG0 to REGn-1, and the FAM register set 3 can record the number of addresses of failed memory cells as n according to an external command (not shown). The MRW register set 8 includes n MRW registers REG 0-REGn-1 for adhering to a mode register write protocol (Mode Register Write protocol) D1 in the JEDEC protocol, and defines access methods for writing to the FAM registers REG 0-REGn-1, respectively.
Assuming that the initial value of the FAM counter 7 is 0, when the embedded processor 5 reads the address bit information D3 from the FAM register REG0, the programming controller 6 programs the address information of the failed memory cell according to the address bit information D3 and outputs address command information D4 to cause the memory device to repair the memory cell corresponding to the address bit information D3 stored in the FAM register REG0, and at this time, the count value of the FAM counter 7 is updated to 1; when the embedded processor 5 reads the address bit information D3 from the FAM register REG1, the programming controller 6 programs the address information of the failed memory cell according to the address bit information D3, and outputs address command information D4 to cause the memory device to repair the memory cell corresponding to the address bit information D3 stored in the FAM register REG1, at this time, the count value of the FAM counter 7 is updated to 2, & gtuntil the count value of the FAM counter 7 is n-1, and the memory cells corresponding to the address bit information D3 stored in all FAM registers in the FAM register group 3 are repaired, and at this time, the program execution is ended.
With continued reference to fig. 1, in this embodiment, the storage device further includes: a row decoder 9, a column decoder 10, and a current source 11. The row decoder 9 and the column decoder 10 receive the address command information D4 and address the memory cell 4 according to the address command information D4. The current source 11 is connected to the memory cell 4 for providing a current for programming the memory cell 4.
In some embodiments, the memory Cell 4 is further an array of antifuse cells (Anti-Fuse cells), and after the row decoder 9 and the column decoder 10 address target antifuse cells according to the address command information D4, a path is formed between the current source 11 and the target antifuse cells by the embedded processor 5 to program the target antifuse cells.
According to the technical scheme, the FAM register set is arranged in the storage device, and addresses of invalid storage units are recorded through the FAM register set; sequentially selecting FAM registers in a FAM register group through the FAM counter 7; the storage device is packaged and repaired according to the address bit information D3 of the selected FAM register, so that the storage device can be packaged and repaired for a plurality of storage units after executing an external command, the situation that a single FAM register is required to store the address information of the failed storage unit and as many external commands as the failed storage unit are required when the storage device complies with JEDEC protocol to execute multi-unit repair is avoided, and the repairing efficiency is greatly improved.
Corresponding to the specific implementation manner of the storage device with the post-package repair function, the specific implementation manner of the application further provides a repair method of the storage device with the post-package repair function, which can be realized through the storage device with the post-package repair function.
FIG. 2 is a flow chart of a repair method for a memory device with post-package repair function in an embodiment of the application. Referring to fig. 2, the method for repairing a storage device with post-package repair function includes: step S201, a FAM register set is configured in the storage device, and each FAM register in the FAM register set is used for recording address bit information of a failed storage unit according to an external command; step S202, an embedded processor is configured in the storage device, where the embedded processor includes: programming a controller and a FAM counter; step S203, when program execution starts, the FAM counter sequentially selects the FAM registers in the FAM register set, and the programming controller encapsulates the corresponding failed memory cells according to the address bit information of the FAM registers selected by the FAM counter, and then repairs the memory cells until all the address bit information of the FAM registers is output, and the program execution is completed.
In some embodiments, the programming controller employs a built-in programming sequence to program address information of the failed memory cell according to the address bit information and output address command information (Program Command Address).
In some embodiments, the method further comprises: and adopting the embedded processor to read the address bit information from the FAM register according to the post-encapsulation repair Protocol (PPR Protocol), and repairing all the failed storage units in sequence by using the address bit information. Reference is made to the aforementioned embedded processor in the storage device with post-package repair function, and details are not repeated here.
FIG. 3 is a flow chart of a repair method for a memory device with post-package repair function in another embodiment of the application. Referring to fig. 3, the FAM counter 7 has an initial value of 0, the FAM register set 3 includes n FAM registers REG 0-REGn-1, and the FAM register set 3 can record n addresses of failed memory cells according to an external command (not shown) and the MRW protocol. Reading the FAM register group 3 after the post-encapsulation repair (PPR) procedure starts to be executed; when the number of addresses of the failed memory cells read by the FAM register group 3 is 1, executing a recording command program, and judging whether the number of addresses of the failed memory cells is equal to n or not; when the number of addresses of the failed memory cells read by the FAM register group 3 is greater than 1, directly judging whether the number of addresses of the failed memory cells is equal to n. If the number of addresses of the failed storage units is smaller than n, the FAM register group 3 continues to read the addresses of the failed storage units; if the number of addresses of the failed memory cells is equal to n, the embedded processor 5 sequentially reads the address bit information D3 in the registers REG0 to REGn-1 based on a post-package repair Protocol (PPR Protocol), and outputs address command information D4 to enable the memory device to repair the memory cells corresponding to the address bit information D3 stored in the FAM registers REG0 to REGn-1. And when the embedded processor 5 reads the address bit information D3 in a FAM register, the count value +1 of the FAM counter 7 is equal to n, and all the memory cells corresponding to the address bit information D3 stored in the FAM register group 3 are repaired, so that the program execution is finished. FIG. 4 is a timing diagram illustrating the operation of a memory device according to an embodiment of the present application, wherein the memory device may be packaged for repair by executing an external command.
Fig. 5 is a schematic diagram of a prior art memory device with post-package repair function. The memory device shown in fig. 5 reads the address bit information D3 from an external FAM register according to the post-package repair Protocol (PPR Protocol) D2 and programs the address information of the failed memory cell through the program controller 6. The programming controller 6 outputs the address command information D4 to repair the memory cell corresponding to the address bit information D3 stored in the external FAM register, and when the next failed memory cell needs to be repaired, the above steps need to be repeated. As shown in FIG. 6, comparing the timing diagrams shown in FIG. 4 and FIG. 6, the prior art can only repair the addresses of 1 memory cell corresponding to the same through 1 command/repair address, when the repair of a plurality of failed memory cells is required, the command/address information with the same number of memory cells to be repaired is required to be externally authorized, so that the activation command ATC is required to be executed for multiple times, and the repair of a plurality of failed memory cells can be performed only by one external authorization, thereby greatly improving the repair efficiency.
According to the technical scheme, the FAM register set is configured in the storage device, so that the FAM register complies with JEDEC protocol and records address bit information of a failed storage unit according to an external command; and when program execution starts, the internal FAM counter sequentially selects the FAM register, and the programming controller packages and repairs the failed storage unit according to the address bit information of the selected FAM register until all the address bit information of the FAM register is sequentially output, and the program execution is completed. The storage device can repair a plurality of storage units after executing one external command, so that the situation that a single FAM register is required to be prepared for storing address information of a failed storage unit and as many external commands as the failed storage unit are required when the storage device executes multi-unit repair according to JEDEC protocol is avoided, and the repair efficiency is greatly improved.
It should be noted that the terms "comprising" and "having" and their variants are referred to in the document of the present application and are intended to cover non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. In addition, the embodiments of the present application and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present application.
The foregoing is merely a preferred embodiment of the present application and is not intended to limit the scope of the present application. It should be noted that modifications and adaptations to the present application may occur to one skilled in the art without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.
Claims (9)
1. A memory device having post-package repair functionality, comprising a memory cell, the memory device further comprising:
a FAM register set disposed in the storage device, each FAM register in the FAM register set being configured to record an address of a failed storage unit according to an external command;
an embedded processor, comprising: the FAM register group comprises a programming controller and a FAM counter, wherein the FAM counter is used for sequentially selecting the FAM registers in the FAM register group when program execution starts, and the programming controller is used for repairing corresponding invalid storage units after packaging according to address bit information of the FAM registers selected by the FAM counter until all address bit information of the FAM registers are output.
2. The memory device of claim 1, wherein the programming controller has a built-in programming sequence to program address information of the failed memory cell according to the address bit information and output address command information.
3. The memory device of claim 1, wherein the embedded processor reads the address bit information from the FAM register according to a post-package repair protocol and sequentially repairs all of the failed memory cells according to the address bit information.
4. The storage device of claim 1, wherein the storage device further comprises: and the MRW protocol and the MRW register set are arranged in the storage device so as to define an access method for writing fault addresses into the FAM register set according to the JEDEC protocol.
5. The memory device of claim 4, wherein the embedded processor further controls the FAM register to record address bit information of a failed memory location according to an external command and the MRW protocol.
6. The memory device of claim 1, wherein the memory cell is further an array of antifuse cells.
7. A repair method of a storage device having a post-package repair function, the storage device including a storage unit, the repair method comprising:
configuring a FAM register set in the storage device, wherein each FAM register in the FAM register set is used for recording address bit information of a failed storage unit according to an external command;
configuring an embedded processor in the storage device, the embedded processor comprising: programming a controller and a FAM counter;
and when program execution starts, the FAM counter sequentially selects the FAM registers in the FAM register group, and the programming controller packages and restores the corresponding invalid storage units according to the address bit information of the FAM registers selected by the FAM counter until the address bit information of all the FAM registers is output, so that program execution is completed.
8. The method of claim 7, wherein the programming controller employs a built-in programming sequence to program address information of the failed memory cell according to the address bit information and output address command information.
9. The method of claim 7, wherein the method further comprises: and the embedded processor is adopted to read the address bit information from the FAM register according to a post-encapsulation repair protocol, and repair all the failed memory cells in sequence according to the address bit information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211562810.7A CN116721689A (en) | 2022-12-07 | 2022-12-07 | Storage device with post-package repair function and repair method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211562810.7A CN116721689A (en) | 2022-12-07 | 2022-12-07 | Storage device with post-package repair function and repair method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN116721689A true CN116721689A (en) | 2023-09-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202211562810.7A Withdrawn CN116721689A (en) | 2022-12-07 | 2022-12-07 | Storage device with post-package repair function and repair method thereof |
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| CN (1) | CN116721689A (en) |
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2022
- 2022-12-07 CN CN202211562810.7A patent/CN116721689A/en not_active Withdrawn
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