CN116720553A - T-type and P-type memristor neuron circuit designed based on HH model - Google Patents
T-type and P-type memristor neuron circuit designed based on HH model Download PDFInfo
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- 210000002569 neuron Anatomy 0.000 title claims abstract description 89
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- 230000001256 tonic effect Effects 0.000 description 4
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 3
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Abstract
The invention discloses a T-type and P-type memristor neuron circuit designed based on an HH model, and relates to the technical field of nerve morphology engineering. The T-type memristive neuron circuit includes: the P-type memristor comprises a potassium ion channel memristor circuit, a sodium ion channel memristor circuit, a resistor R1, a first capacitor, a second capacitor and a direct-current voltage source, wherein the P-type memristor neuron circuit is added with a capacitor and a resistor on the basis of a T-type memristor neuron circuit. The T-type and P-type memristor neuron circuits are constructed by imitating biological neuron structures and HH models, and after input currents are respectively injected into the two memristor neuron circuits, two types of outputs similar to biological neurons can be obtained, and the two memristor neuron circuits can realize most biological neuron dynamics behaviors including absolute refractory periods. The invention can eliminate complex integrated devices and can realize the construction of a memristor circuit with high-speed resistance switching by using a simple semiconductor device.
Description
Technical Field
The invention relates to the technical field of neuromorphic engineering, in particular to a T-type and P-type memristor neuron circuit designed based on an HH model.
Background
The neuromorphic network constructed with artificial neurons is a key to solve the difficulty of energy efficiency computation that cannot be achieved by von neumann architecture. For deep learning, and in particular image processing, neuromorphic processors are far superior to graphics processors (Graphic Processing Unit, GPU) in terms of energy efficiency, but neuromorphic processors can provide lower data throughput. Memristors are often used as the first choice for simulating biological neuron ion channels due to the nonlinear characteristics, but most memristors are difficult to maintain single nonlinear characteristics even if some memristors still stay in a theoretical model stage due to the fact that the existing memristor preparation technology is not mature, so that memristor circuits capable of realizing the memristor nonlinear characteristics are often used for replacing memristors to build related nonlinear circuits. At present, a very large variety of memristor circuits are proposed in the field of nonlinear circuits, but the circuit structures are relatively complex, and complex integrated devices such as an operational amplifier, a multiplier and the like are often included in the circuit, so that the switching time of high and low resistance states of the memristor circuits is greatly increased. Such memristive circuits are not suitable for simulating the opening and closing behavior of biological neuron ion channels due to the high and low resistance state switching speeds.
Disclosure of Invention
The invention aims to provide a T-type and P-type memristor neuron circuit designed based on an HH model, which can abandon complex integrated devices and can realize the construction of a memristor circuit with high-speed resistance switching by using a simple semiconductor device.
In order to achieve the above object, the present invention provides the following solutions:
a HH model design-based T-type memristor neuron circuit, comprising: the device comprises a potassium ion channel memristor circuit, a sodium ion channel memristor circuit, a resistor R1, a first capacitor, a second capacitor and a direct-current voltage source;
the negative electrode of the direct-current voltage source is connected with one end of the resistor R1; the positive electrode of the direct-current voltage source is grounded; the other end of the resistor R1 is connected with a node a; the node a is connected with the circuit input end through a first branch line; the node a is connected with the node b through a second branch line;
the input end of the sodium ion channel memristor circuit is connected with one end of the first capacitor; the output end of the sodium ion channel memristor circuit is connected with the other end of the first capacitor; the input end of the sodium ion channel memristor circuit is also connected with the node b; the output end of the sodium ion channel memristor circuit is also grounded; the node b is connected with the node c through a third branch line;
the input end of the potassium channel memristor circuit is connected with one end of the second capacitor; the output end of the potassium channel memristor circuit is connected with the other end of the second capacitor; the input end of the potassium channel memristor circuit is also connected with the node c; the output end of the potassium channel memristor circuit is also grounded; the node c is connected with the circuit output end through a fourth branch line.
Optionally, the sodium ion channel memristor circuit specifically includes: the first bidirectional thyristor switch, the first P-type mos transistor, the second P-type mos transistor, the third P-type mos transistor, the P-type triode, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor, the first direct current voltage source, the second direct current voltage source, the third direct current voltage source and the fourth direct current voltage source;
one end of the fourth resistor is connected with the circuit input end; the other end of the fourth resistor is connected with a first interface of the first bidirectional thyristor switch; the second interface of the first bidirectional thyristor switch is connected with the positive electrode of the third direct-current voltage source; the negative electrode of the third direct-current voltage source is connected with the drain electrode of the second P-type mos tube; the source electrode of the second P-type mos tube is connected with the output end of the circuit;
the grid electrode of the second P-type mos tube is respectively connected with one ends of the fifth resistor and the sixth resistor; the other end of the fifth resistor is connected with the negative electrode of the fourth direct-current voltage source; the positive electrode of the fourth direct-current voltage source is grounded; the other end of the sixth resistor is connected with the drain electrode of the third P-type mos tube; the source electrode of the third P-type mos tube is grounded; the grid electrode of the third P-type mos tube is respectively connected with one end of the seventh resistor and one end of the eighth resistor; the other end of the eighth resistor is grounded; the other end of the seventh resistor is connected with one end of the first resistor; the other end of the seventh resistor and one end of the first resistor are also connected with the input end of the circuit;
the third interface end of the first bidirectional thyristor switch is connected with the source electrode of the first P-type mos tube; the drain electrode of the first P-type mos tube is grounded; the grid electrode of the first P-type mos tube is respectively connected with one ends of the second resistor and the third resistor; the other end of the third resistor is connected with the positive electrode of the second direct-current voltage source; the negative electrode of the second direct-current voltage source is grounded;
the other end of the second resistor is connected with the collector electrode of the P-type triode; the emitter of the P-type triode is grounded; the base electrode of the P-type triode is connected with the positive electrode of the first direct-current voltage source; and the negative electrode of the first direct current voltage source is connected with the other end of the first resistor.
Optionally, the potassium channel memristor circuit specifically includes: the second bidirectional thyristor switch, the first N-type mos tube, the second N-type mos tube, the ninth resistor, the tenth resistor, the fifth direct current voltage source, the sixth direct current voltage source and the seventh direct current voltage source;
one end of the ninth resistor is connected with the circuit input end; the other end of the ninth resistor is connected with a first interface of the second bidirectional thyristor switch; the second interface of the second bidirectional thyristor switch is connected with the negative electrode of the seventh direct-current voltage source; the anode of the seventh direct-current voltage source is connected with the drain electrode of the second N-type mos tube; the source electrode of the N-type mos tube is connected with the output end of the circuit; the grid electrode of the N-type mos tube is connected with the positive electrode of the sixth direct-current voltage source; the negative electrode of the sixth direct-current voltage source is respectively connected with the positive electrode of the fifth direct-current voltage source and one end of the tenth resistor; the negative electrode of the fifth direct current voltage source and the grid electrode of the first N-type mos tube; the drain electrode of the first N-type mos tube is grounded; the source electrode of the first N-type mos tube is connected with a third interface of the second bidirectional thyristor switch; the other end of the tenth resistor is connected with the input end of the circuit.
The invention also provides a P-type memristor neuron circuit designed based on the HH model, which comprises the following components: the device comprises a potassium ion channel memristor circuit, a sodium ion channel memristor circuit, a resistor R1, a resistor R2, a first capacitor, a second capacitor, a third capacitor and a direct-current voltage source;
the negative electrode of the direct-current voltage source is connected with one end of the resistor R1; the positive electrode of the direct-current voltage source is grounded; the other end of the resistor R1 is connected with a node a; the node a is connected with one end of the third capacitor through a first branch line; the other end of the third capacitor is connected with a node d; the node d is connected with the circuit input end through a fifth branch line; the node d is also connected with one end of a resistor R2 through a sixth branch line; the other end of the resistor R2 is grounded; the node a is connected with the node b through a second branch line;
the input end of the sodium ion channel memristor circuit is connected with one end of the first capacitor; the output end of the sodium ion channel memristor circuit is connected with the other end of the first capacitor; the input end of the sodium ion channel memristor circuit is also connected with the node b; the output end of the sodium ion channel memristor circuit is also grounded; the node b is connected with the node c through a third branch line;
the input end of the potassium channel memristor circuit is connected with one end of the second capacitor; the output end of the potassium channel memristor circuit is connected with the other end of the second capacitor; the input end of the potassium channel memristor circuit is also connected with the node c; the output end of the potassium channel memristor circuit is also grounded; the node c is connected with the circuit output end through a fourth branch line.
Optionally, the sodium ion channel memristor circuit specifically includes: the first bidirectional thyristor switch, the first P-type mos transistor, the second P-type mos transistor, the third P-type mos transistor, the P-type triode, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor, the first direct current voltage source, the second direct current voltage source, the third direct current voltage source and the fourth direct current voltage source;
one end of the fourth resistor is connected with the circuit input end; the other end of the fourth resistor is connected with a first interface of the first bidirectional thyristor switch; the second interface of the first bidirectional thyristor switch is connected with the positive electrode of the third direct-current voltage source; the negative electrode of the third direct-current voltage source is connected with the drain electrode of the second P-type mos tube; the source electrode of the second P-type mos tube is connected with the output end of the circuit;
the grid electrode of the second P-type mos tube is respectively connected with one ends of the fifth resistor and the sixth resistor; the other end of the fifth resistor is connected with the negative electrode of the fourth direct-current voltage source; the positive electrode of the fourth direct-current voltage source is grounded; the other end of the sixth resistor is connected with the drain electrode of the third P-type mos tube; the source electrode of the third P-type mos tube is grounded; the grid electrode of the third P-type mos tube is respectively connected with one end of the seventh resistor and one end of the eighth resistor; the other end of the eighth resistor is grounded; the other end of the seventh resistor is connected with one end of the first resistor; the other end of the seventh resistor and one end of the first resistor are also connected with the input end of the circuit;
the third interface end of the first bidirectional thyristor switch is connected with the source electrode of the first P-type mos tube; the drain electrode of the first P-type mos tube is grounded; the grid electrode of the first P-type mos tube is respectively connected with one ends of the second resistor and the third resistor; the other end of the third resistor is connected with the positive electrode of the second direct-current voltage source; the negative electrode of the second direct-current voltage source is grounded;
the other end of the second resistor is connected with the collector electrode of the P-type triode; the emitter of the P-type triode is grounded; the base electrode of the P-type triode is connected with the positive electrode of the first direct-current voltage source; and the negative electrode of the first direct current voltage source is connected with the other end of the first resistor.
Optionally, the potassium channel memristor circuit specifically includes: the second bidirectional thyristor switch, the first N-type mos tube, the second N-type mos tube, the ninth resistor, the tenth resistor, the fifth direct current voltage source, the sixth direct current voltage source and the seventh direct current voltage source;
one end of the ninth resistor is connected with the circuit input end; the other end of the ninth resistor is connected with a first interface of the second bidirectional thyristor switch; the second interface of the second bidirectional thyristor switch is connected with the negative electrode of the seventh direct-current voltage source; the anode of the seventh direct-current voltage source is connected with the drain electrode of the second N-type mos tube; the source electrode of the N-type mos tube is connected with the output end of the circuit; the grid electrode of the N-type mos tube is connected with the positive electrode of the sixth direct-current voltage source; the negative electrode of the sixth direct-current voltage source is respectively connected with the positive electrode of the fifth direct-current voltage source and one end of the tenth resistor; the negative electrode of the fifth direct current voltage source and the grid electrode of the first N-type mos tube; the drain electrode of the first N-type mos tube is grounded; the source electrode of the first N-type mos tube is connected with a third interface of the second bidirectional thyristor switch; the other end of the tenth resistor is connected with the input end of the circuit.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a T-type memristor neuron circuit and a P-type memristor neuron circuit designed based on an HH model, wherein the T-type memristor neuron circuit comprises a potassium ion channel memristor circuit, a sodium ion channel memristor circuit, a resistor R1, a first capacitor, a second capacitor and a direct-current voltage source, and the P-type memristor neuron circuit is added with a capacitor and a resistor on the basis of the T-type memristor neuron circuit. The T-type and P-type memristor neuron circuits are constructed by imitating biological neuron structures and HH models, two types of outputs similar to biological neurons can be obtained after input currents are respectively injected into the two types of memristor neuron circuits, and the two types of memristor neuron circuits can realize most biological neuron dynamics behaviors including absolute refractory periods, can abandon complex integrated devices, and can realize the construction of the memristor circuit with high-speed resistance switching by using simple semiconductor devices, unlike the existing fire collecting-emitting artificial neurons (such as LIF circuits).
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a T-type memristive neuron circuit of the present disclosure;
FIG. 2 is a schematic diagram of a P-type memristive neuron circuit in accordance with the present disclosure;
FIG. 3 is a diagram of a sodium channel memristor circuit in this embodiment;
FIG. 4 is a diagram of a potassium channel memristor circuit in this embodiment;
FIG. 5 is a diagram showing the experimental results of simulation of the T-type neuron circuit according to the present embodiment;
fig. 6 is a diagram showing the simulation experiment result of the P-type neuron circuit in this embodiment.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a T-type and P-type memristor neuron circuit designed based on an HH model, which can abandon complex integrated devices and can realize the construction of a memristor circuit with high-speed resistance switching by using a simple semiconductor device.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
As shown in FIG. 1, the present invention provides a T-shaped memristor neuron circuit designed based on an HH model, comprising: the device comprises a potassium ion channel memristor circuit, a sodium ion channel memristor circuit, a resistor R1, a first capacitor, a second capacitor and a direct current voltage source.
Specifically, the negative electrode of the direct-current voltage source is connected with one end of the resistor R1; the positive electrode of the direct-current voltage source is grounded; the other end of the resistor R1 is connected with a node a; the node a is connected with the circuit input end through a first branch line; the node a is connected with the node b through a second branch line; the input end of the sodium ion channel memristor circuit is connected with one end of the first capacitor; the output end of the sodium ion channel memristor circuit is connected with the other end of the first capacitor; the input end of the sodium ion channel memristor circuit is also connected with the node b; the output end of the sodium ion channel memristor circuit is also grounded; the node b is connected with the node c through a third branch line; the input end of the potassium channel memristor circuit is connected with one end of the second capacitor; the output end of the potassium channel memristor circuit is connected with the other end of the second capacitor; the input end of the potassium channel memristor circuit is also connected with the node c; the output end of the potassium channel memristor circuit is also grounded; the node c is connected with the circuit output end through a fourth branch line.
As shown in fig. 2, the present invention further provides a P-type memristor neuron circuit designed based on HH model, including: the device comprises a potassium ion channel memristor circuit, a sodium ion channel memristor circuit, a resistor R1, a resistor R2, a first capacitor, a second capacitor, a third capacitor and a direct current voltage source.
Specifically, the negative electrode of the direct-current voltage source is connected with one end of the resistor R1; the positive electrode of the direct-current voltage source is grounded; the other end of the resistor R1 is connected with a node a; the node a is connected with one end of the third capacitor through a first branch line; the other end of the third capacitor is connected with a node d; the node d is connected with the circuit input end through a fifth branch line; the node d is also connected with one end of a resistor R2 through a sixth branch line; the other end of the resistor R2 is grounded; the node a is connected with the node b through a second branch line; the input end of the sodium ion channel memristor circuit is connected with one end of the first capacitor; the output end of the sodium ion channel memristor circuit is connected with the other end of the first capacitor; the input end of the sodium ion channel memristor circuit is also connected with the node b; the output end of the sodium ion channel memristor circuit is also grounded; the node b is connected with the node c through a third branch line; the input end of the potassium channel memristor circuit is connected with one end of the second capacitor; the output end of the potassium channel memristor circuit is connected with the other end of the second capacitor; the input end of the potassium channel memristor circuit is also connected with the node c; the output end of the potassium channel memristor circuit is also grounded; the node c is connected with the circuit output end through a fourth branch line.
Based on the structures of the T-type memristor neuron circuit and the P-type memristor neuron circuit, a specific implementation mode of the sodium ion channel memristor circuit and the potassium ion channel memristor circuit is provided.
The sodium ion channel memristor circuit mainly realizes the function of improving the voltage of an output end, and specifically comprises the following components: the device comprises a first bidirectional thyristor switch, a first P-type mos transistor, a second P-type mos transistor, a third P-type mos transistor, a P-type triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first direct current voltage source, a second direct current voltage source, a third direct current voltage source and a fourth direct current voltage source.
Specifically, one end of the fourth resistor is connected with the circuit input end; the other end of the fourth resistor is connected with a first interface of the first bidirectional thyristor switch; the second interface of the first bidirectional thyristor switch is connected with the positive electrode of the third direct-current voltage source; the negative electrode of the third direct-current voltage source is connected with the drain electrode of the second P-type mos tube; the source electrode of the second P-type mos tube is connected with the output end of the circuit; the grid electrode of the second P-type mos tube is respectively connected with one ends of the fifth resistor and the sixth resistor; the other end of the fifth resistor is connected with the negative electrode of the fourth direct-current voltage source; the positive electrode of the fourth direct-current voltage source is grounded; the other end of the sixth resistor is connected with the drain electrode of the third P-type mos tube; the source electrode of the third P-type mos tube is grounded; the grid electrode of the third P-type mos tube is respectively connected with one end of the seventh resistor and one end of the eighth resistor; the other end of the eighth resistor is grounded; the other end of the seventh resistor is connected with one end of the first resistor; the other end of the seventh resistor and one end of the first resistor are also connected with the input end of the circuit; the third interface end of the first bidirectional thyristor switch is connected with the source electrode of the first P-type mos tube; the drain electrode of the first P-type mos tube is grounded; the grid electrode of the first P-type mos tube is respectively connected with one ends of the second resistor and the third resistor; the other end of the third resistor is connected with the positive electrode of the second direct-current voltage source; the negative electrode of the second direct-current voltage source is grounded; the other end of the second resistor is connected with the collector electrode of the P-type triode; the emitter of the P-type triode is grounded; the base electrode of the P-type triode is connected with the positive electrode of the first direct-current voltage source; and the negative electrode of the first direct current voltage source is connected with the other end of the first resistor.
The potassium ion channel memristor circuit mainly realizes the reduction of the voltage of an output end, and specifically comprises the following components: the second bidirectional thyristor switch, the first N-type mos transistor, the second N-type mos transistor, the ninth resistor, the tenth resistor, the fifth direct current voltage source, the sixth direct current voltage source and the seventh direct current voltage source.
Specifically, one end of the ninth resistor is connected with the circuit input end; the other end of the ninth resistor is connected with a first interface of the second bidirectional thyristor switch; the second interface of the second bidirectional thyristor switch is connected with the negative electrode of the seventh direct-current voltage source; the anode of the seventh direct-current voltage source is connected with the drain electrode of the second N-type mos tube; the source electrode of the N-type mos tube is connected with the output end of the circuit; the grid electrode of the N-type mos tube is connected with the positive electrode of the sixth direct-current voltage source; the negative electrode of the sixth direct-current voltage source is respectively connected with the positive electrode of the fifth direct-current voltage source and one end of the tenth resistor; the negative electrode of the fifth direct current voltage source and the grid electrode of the first N-type mos tube; the drain electrode of the first N-type mos tube is grounded; the source electrode of the first N-type mos tube is connected with a third interface of the second bidirectional thyristor switch; the other end of the tenth resistor is connected with the input end of the circuit.
Based on the above technical solution, an embodiment as shown in fig. 3-6 is provided, the T-type and P-type memristor circuits imitate biological neuron structures and Hodgkin-Huxley model (HH), two memristor circuits simulate the opening and closing behaviors of potassium and sodium ion channels involved in the action potential generation of biological neurons, a capacitor is used for simulating the function of isolating intracellular and extracellular ions, a direct current voltage source is used for realizing the potential difference between the inside and the outside of the nerve cells, and the specific implementation functions comprise:
the toni type neuron circuit generates an action potential, i.e., a pulse signal, by directly inputting a current to an input terminal to break the internal balance of the neuron circuit. When the input end of the memristor neuron circuit continuously inputs current, a capacitor connected in parallel with the sodium ion channel memristor circuit continuously charges, when the voltage values at two ends of the capacitor reach a trigger threshold value, the sodium ion channel memristor circuit is switched from a high-resistance state to a low-resistance state in an extremely short time (microsecond level) and keeps the low-resistance state before the potassium ion channel memristor circuit is started, at the moment, the voltage at the output end of the memristor neuron circuit is also increased and temporarily kept due to the fact that the transient resistance value of the sodium ion channel memristor circuit changes and keeps changing the voltage distribution of the memristor neuron circuit, and the rising speed of the voltage at the output end of the memristor circuit is related to the capacity of the parallel capacitor and the resistance value of the sodium ion channel memristor circuit. The output end voltage of the memristor circuit is instantaneously raised to simulate the action of biological neuron transmitting pulse, and the high-resistance state and low-resistance state of the sodium ion channel memristor circuit are instantaneously switched and kept to simulate the biological dynamics action of biological neuron sodium ion channel.
When the sodium ion channel memristor circuit is switched to a low-resistance state and kept, the voltage of the output end of the memristor neuron circuit is increased, the capacitor connected in parallel with the potassium ion channel memristor circuit is continuously charged, and when the voltage of the two ends of the capacitor reaches the trigger threshold value of the potassium ion channel memristor circuit, the resistance value of the potassium ion channel memristor circuit is switched from a high-resistance state to a low-resistance state instantly (microsecond level) and kept. In the process that the resistance value of the potassium ion channel memristor circuit is reduced to a low resistance state and kept, a capacitor connected in parallel with the potassium ion channel memristor circuit continuously discharges, the voltage of the output end of the memristor circuit continuously reduces, when the voltage is lower than the recovery threshold value of the sodium ion channel memristor circuit, the voltage of the sodium ion channel memristor circuit is instantaneously switched from the low resistance state to a high resistance state, at the moment, the parallel capacitor still continuously discharges, when the voltage of the output end of the potassium ion channel memristor circuit is lower than the recovery threshold value of the potassium ion channel memristor circuit, the voltage of the output end of the potassium ion channel memristor circuit is switched from the low resistance state to the high resistance state, the voltage of the output end of the potassium ion channel memristor circuit is recovered to the initial state, and the memristor circuit finishes one-time pulse emission. If the input end of the memristor neuron circuit still has enough current input, the circuit can repeat the process again to emit a pulse again, and if no continuous current input or input current intensity is too low, the circuit maintains an initial state or the voltage value of the output end is slightly higher than the initial state.
The biggest difference between the Phacic type neuron circuit and the Tonic type neuron circuit is that an input capacitor and an input resistor are added on the basis of the Phacic type neuron circuit, and the input end does not directly inject current, but the balance of the neuron circuit is destroyed by changing the voltage values of the two ends of the input capacitor, so that action potential is generated. When the input end of the memristor neuron circuit continuously inputs current, the input resistor is connected with the input capacitor in parallel, so that the voltage at two ends of the input capacitor is equal to the voltage at two ends of the input resistor finally. When the input capacitor is continuously charged, a capacitor connected with the sodium ion channel memristor circuit in parallel is continuously charged, when the voltage values at two ends of the capacitor reach a trigger threshold, the sodium ion channel memristor circuit is switched from a high resistance state to a low resistance state in a very short time (microsecond level) and keeps the low resistance state before the potassium ion channel memristor circuit is started, at the moment, the voltage distribution of the memristor neuron circuit is changed due to the transient resistance value change and the keeping of the sodium ion channel memristor circuit, and therefore the voltage at the output end of the memristor neuron circuit is also increased and kept temporarily, and the rising speed of the voltage is related to the capacity of the parallel capacitor and the resistance value of the sodium ion channel memristor circuit.
When the sodium ion channel memristor circuit is switched to a low-resistance state and kept, the voltage of the output end of the memristor neuron circuit is increased, the capacitor connected in parallel with the potassium ion channel memristor circuit is continuously charged, and when the voltage of the two ends of the capacitor reaches the trigger threshold value of the potassium ion channel memristor circuit, the resistance value of the potassium ion channel memristor circuit is switched from a high-resistance state to a low-resistance state instantly (microsecond level) and kept. In the process that the resistance value of the potassium ion channel memristor circuit is reduced to a low resistance state and kept, a capacitor connected in parallel with the potassium ion channel memristor circuit continuously discharges, the voltage of the output end of the memristor circuit continuously reduces, when the voltage is lower than the recovery threshold value of the sodium ion channel memristor circuit, the voltage of the sodium ion channel memristor circuit is instantaneously switched from the low resistance state to a high resistance state, at the moment, the parallel capacitor still continuously discharges, when the voltage of the output end of the potassium ion channel memristor circuit is lower than the recovery threshold value of the potassium ion channel memristor circuit, the voltage of the output end of the potassium ion channel memristor circuit is switched from the low resistance state to the high resistance state, the voltage of the output end of the potassium ion channel memristor circuit is recovered to the initial state, and the memristor circuit finishes one-time pulse emission. If the input capacitor is not fully charged at this time and the charging period is enough to allow the output voltage to reach the trigger threshold of the neuron circuit, the circuit will repeat the process again and transmit a pulse again, otherwise if the charging period is insufficient to allow the output voltage to reach the trigger threshold of the neuron circuit, the circuit will eventually maintain the initial state. If the input capacitor is already fully charged and the input current is not changed or reduced in magnitude, the circuit eventually remains in an initial state.
The T-shaped memristor neuron circuit comprises two memristor circuits respectively realizing the change rule of potassium and sodium ion channel resistance values, an output resistor, two capacitors for realizing the cell membrane function and a direct current voltage source required by simulating the difference between the voltages inside and outside the biological neuron cell.
The specific operation flow is as follows:
step S11: using a direct current source to input a current with the intensity of 5mA to the input end of the Tonic type neuron circuit;
step S12: the voltage at the output end of the circuit continuously rises, the capacitor in fig. 1 continuously charges, and when the trigger threshold of the sodium ion channel memristor circuit is reached, the triode Q 1 Conducting, then P-type mos tube M 1 Conduction further results in a triac T 1 The switch is conducted, at this time, according to the property of the bidirectional thyristor, even if the voltage of the bidirectional thyristor gate is removed, the bidirectional thyristor switch is always kept in a conducting state before the current passing through the bidirectional thyristor is infinitely close to 0 or the current direction is changed, and the structure of the sodium ion channel memristor circuit is shown in the figure 3;
step S13: when the bidirectional thyristor switch in the sodium ion channel memristor circuit is turned on, the resistance value between the input end and the output end of the sodium ion channel memristor circuit is rapidly reduced, and the low-resistance state is maintained before the bidirectional thyristor switch is turned off.At the moment, the voltage of the output end of the neuron circuit is instantaneously increased, and when the voltage value reaches the trigger threshold value of the potassium ion channel memristor circuit, an N-type mos tube M in the potassium ion channel memristor circuit 1 Conducting, thereby causing a bidirectional controllable switch T 1 Conduction, the resistance values of the input end and the output end of the potassium ion channel circuit are rapidly reduced, so that the voltage of the output end of the neuron circuit is instantaneously reduced, and the structure of the potassium ion channel memristor circuit is shown in figure 4;
step S14: when the output voltage of the neuron circuit is lower than the closing threshold value of the sodium ion channel memristor circuit, a P-type mos tube M in the sodium ion channel memristor circuit 3 Conducting, which will result in a P-type mos tube M 2 The power supply voltage of the grid electrode is insufficient to maintain the operation of the P-type mos transistor M 2 The high resistance state is temporarily restored, so that the current flows through the bidirectional thyristor switch T 1 The current of the (2) is infinitely zero-forcing, so that the resistance value between the input end and the output end of the sodium ion channel memristor circuit is recovered to a high resistance state, and the voltage of the output end of the neuron circuit is further reduced.
Step S15: when the voltage of the output end of the neuron circuit is lower than the closing threshold value of the potassium ion channel memristor circuit, a P-type mos tube M in the potassium ion channel memristor circuit 2 The high resistance state is temporarily restored, so that the current flows through the bidirectional thyristor switch T 1 The current of the (2) is infinitely forced to zero, so that the resistance value between the input end and the output end of the potassium channel memristor circuit is recovered to a high resistance state, the voltage of the output end of the neuron circuit is recovered to an initial state, and one action potential emission is completed. If the input current is still unchanged at this time, the whole process of steps S11-S15 is repeated until the input current intensity is insufficient to reach the neuron circuit triggering threshold. The input and output of the Tonic type neuron circuit are shown in figure 5.
For a P-type memristive neuron circuit, comprising: two memristor circuits for respectively realizing the resistance change rule of potassium and sodium ion channels, two resistors, three capacitors and a direct current voltage source.
The principle of circuit structure and action potential generation of a Phacic type neuron circuit is the same as that of a Tonic type neuron circuitThe input structure is identical, the process is not repeated, and only the influence caused by different input structures is briefly described. The pharmaceutical type neuron circuit breaks the internal balance of the neuron circuit by charging the capacitor, thereby generating an action potential, in other words, when the voltage across the capacitor is substantially stabilized, the internal balance of the neuron circuit is not broken, that is, the action potential is not emitted. As can be seen from a comparison of the inputs and outputs of the Phasic neuron circuits, as shown in FIG. 6, when the capacitor C is inputted, it is clear from an examination of FIG. 6 that even if the same current is continuously inputted to the input terminal of the neuron circuit 3 After full charge, the neuron circuit will not emit action potential, which is consistent with the discharge characteristics of partial biological neurons.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the core concept of the invention; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (6)
1. A T-memristor neuron circuit designed based on HH model, comprising: the device comprises a potassium ion channel memristor circuit, a sodium ion channel memristor circuit, a resistor R1, a first capacitor, a second capacitor and a direct-current voltage source;
the negative electrode of the direct-current voltage source is connected with one end of the resistor R1; the positive electrode of the direct-current voltage source is grounded; the other end of the resistor R1 is connected with a node a; the node a is connected with the circuit input end through a first branch line; the node a is connected with the node b through a second branch line;
the input end of the sodium ion channel memristor circuit is connected with one end of the first capacitor; the output end of the sodium ion channel memristor circuit is connected with the other end of the first capacitor; the input end of the sodium ion channel memristor circuit is also connected with the node b; the output end of the sodium ion channel memristor circuit is also grounded; the node b is connected with the node c through a third branch line;
the input end of the potassium channel memristor circuit is connected with one end of the second capacitor; the output end of the potassium channel memristor circuit is connected with the other end of the second capacitor; the input end of the potassium channel memristor circuit is also connected with the node c; the output end of the potassium channel memristor circuit is also grounded; the node c is connected with the circuit output end through a fourth branch line.
2. The HH model design-based T-type memristor neuron circuit according to claim 1, wherein the sodium-channel memristor circuit specifically comprises: the first bidirectional thyristor switch, the first P-type mos transistor, the second P-type mos transistor, the third P-type mos transistor, the P-type triode, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor, the first direct current voltage source, the second direct current voltage source, the third direct current voltage source and the fourth direct current voltage source;
one end of the fourth resistor is connected with the circuit input end; the other end of the fourth resistor is connected with a first interface of the first bidirectional thyristor switch; the second interface of the first bidirectional thyristor switch is connected with the positive electrode of the third direct-current voltage source; the negative electrode of the third direct-current voltage source is connected with the drain electrode of the second P-type mos tube; the source electrode of the second P-type mos tube is connected with the output end of the circuit;
the grid electrode of the second P-type mos tube is respectively connected with one ends of the fifth resistor and the sixth resistor; the other end of the fifth resistor is connected with the negative electrode of the fourth direct-current voltage source; the positive electrode of the fourth direct-current voltage source is grounded; the other end of the sixth resistor is connected with the drain electrode of the third P-type mos tube; the source electrode of the third P-type mos tube is grounded; the grid electrode of the third P-type mos tube is respectively connected with one end of the seventh resistor and one end of the eighth resistor; the other end of the eighth resistor is grounded; the other end of the seventh resistor is connected with one end of the first resistor; the other end of the seventh resistor and one end of the first resistor are also connected with the input end of the circuit;
the third interface end of the first bidirectional thyristor switch is connected with the source electrode of the first P-type mos tube; the drain electrode of the first P-type mos tube is grounded; the grid electrode of the first P-type mos tube is respectively connected with one ends of the second resistor and the third resistor; the other end of the third resistor is connected with the positive electrode of the second direct-current voltage source; the negative electrode of the second direct-current voltage source is grounded;
the other end of the second resistor is connected with the collector electrode of the P-type triode; the emitter of the P-type triode is grounded; the base electrode of the P-type triode is connected with the positive electrode of the first direct-current voltage source; and the negative electrode of the first direct current voltage source is connected with the other end of the first resistor.
3. The HH model design-based T-type memristor neuron circuit according to claim 1, wherein the potassium-ion channel memristor circuit specifically comprises: the second bidirectional thyristor switch, the first N-type mos tube, the second N-type mos tube, the ninth resistor, the tenth resistor, the fifth direct current voltage source, the sixth direct current voltage source and the seventh direct current voltage source;
one end of the ninth resistor is connected with the circuit input end; the other end of the ninth resistor is connected with a first interface of the second bidirectional thyristor switch; the second interface of the second bidirectional thyristor switch is connected with the negative electrode of the seventh direct-current voltage source; the anode of the seventh direct-current voltage source is connected with the drain electrode of the second N-type mos tube; the source electrode of the N-type mos tube is connected with the output end of the circuit; the grid electrode of the N-type mos tube is connected with the positive electrode of the sixth direct-current voltage source; the negative electrode of the sixth direct-current voltage source is respectively connected with the positive electrode of the fifth direct-current voltage source and one end of the tenth resistor; the negative electrode of the fifth direct current voltage source and the grid electrode of the first N-type mos tube; the drain electrode of the first N-type mos tube is grounded; the source electrode of the first N-type mos tube is connected with a third interface of the second bidirectional thyristor switch; the other end of the tenth resistor is connected with the input end of the circuit.
4. A P-type memristor neuron circuit designed based on HH model, characterized by comprising: the device comprises a potassium ion channel memristor circuit, a sodium ion channel memristor circuit, a resistor R1, a resistor R2, a first capacitor, a second capacitor, a third capacitor and a direct-current voltage source;
the negative electrode of the direct-current voltage source is connected with one end of the resistor R1; the positive electrode of the direct-current voltage source is grounded; the other end of the resistor R1 is connected with a node a; the node a is connected with one end of the third capacitor through a first branch line; the other end of the third capacitor is connected with a node d; the node d is connected with the circuit input end through a fifth branch line; the node d is also connected with one end of a resistor R2 through a sixth branch line; the other end of the resistor R2 is grounded; the node a is connected with the node b through a second branch line;
the input end of the sodium ion channel memristor circuit is connected with one end of the first capacitor; the output end of the sodium ion channel memristor circuit is connected with the other end of the first capacitor; the input end of the sodium ion channel memristor circuit is also connected with the node b; the output end of the sodium ion channel memristor circuit is also grounded; the node b is connected with the node c through a third branch line;
the input end of the potassium channel memristor circuit is connected with one end of the second capacitor; the output end of the potassium channel memristor circuit is connected with the other end of the second capacitor; the input end of the potassium channel memristor circuit is also connected with the node c; the output end of the potassium channel memristor circuit is also grounded; the node c is connected with the circuit output end through a fourth branch line.
5. The HH model design-based P-type memristor neuron circuit according to claim 4, wherein the sodium-channel memristor circuit specifically comprises: the first bidirectional thyristor switch, the first P-type mos transistor, the second P-type mos transistor, the third P-type mos transistor, the P-type triode, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor, the first direct current voltage source, the second direct current voltage source, the third direct current voltage source and the fourth direct current voltage source;
one end of the fourth resistor is connected with the circuit input end; the other end of the fourth resistor is connected with a first interface of the first bidirectional thyristor switch; the second interface of the first bidirectional thyristor switch is connected with the positive electrode of the third direct-current voltage source; the negative electrode of the third direct-current voltage source is connected with the drain electrode of the second P-type mos tube; the source electrode of the second P-type mos tube is connected with the output end of the circuit;
the grid electrode of the second P-type mos tube is respectively connected with one ends of the fifth resistor and the sixth resistor; the other end of the fifth resistor is connected with the negative electrode of the fourth direct-current voltage source; the positive electrode of the fourth direct-current voltage source is grounded; the other end of the sixth resistor is connected with the drain electrode of the third P-type mos tube; the source electrode of the third P-type mos tube is grounded; the grid electrode of the third P-type mos tube is respectively connected with one end of the seventh resistor and one end of the eighth resistor; the other end of the eighth resistor is grounded; the other end of the seventh resistor is connected with one end of the first resistor; the other end of the seventh resistor and one end of the first resistor are also connected with the input end of the circuit;
the third interface end of the first bidirectional thyristor switch is connected with the source electrode of the first P-type mos tube; the drain electrode of the first P-type mos tube is grounded; the grid electrode of the first P-type mos tube is respectively connected with one ends of the second resistor and the third resistor; the other end of the third resistor is connected with the positive electrode of the second direct-current voltage source; the negative electrode of the second direct-current voltage source is grounded;
the other end of the second resistor is connected with the collector electrode of the P-type triode; the emitter of the P-type triode is grounded; the base electrode of the P-type triode is connected with the positive electrode of the first direct-current voltage source; and the negative electrode of the first direct current voltage source is connected with the other end of the first resistor.
6. The HH model design-based P-type memristor neuron circuit according to claim 4, wherein the potassium-ion channel memristor circuit specifically comprises: the second bidirectional thyristor switch, the first N-type mos tube, the second N-type mos tube, the ninth resistor, the tenth resistor, the fifth direct current voltage source, the sixth direct current voltage source and the seventh direct current voltage source;
one end of the ninth resistor is connected with the circuit input end; the other end of the ninth resistor is connected with a first interface of the second bidirectional thyristor switch; the second interface of the second bidirectional thyristor switch is connected with the negative electrode of the seventh direct-current voltage source; the anode of the seventh direct-current voltage source is connected with the drain electrode of the second N-type mos tube; the source electrode of the N-type mos tube is connected with the output end of the circuit; the grid electrode of the N-type mos tube is connected with the positive electrode of the sixth direct-current voltage source; the negative electrode of the sixth direct-current voltage source is respectively connected with the positive electrode of the fifth direct-current voltage source and one end of the tenth resistor; the negative electrode of the fifth direct current voltage source and the grid electrode of the first N-type mos tube; the drain electrode of the first N-type mos tube is grounded; the source electrode of the first N-type mos tube is connected with a third interface of the second bidirectional thyristor switch; the other end of the tenth resistor is connected with the input end of the circuit.
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