CN116709770A - Semiconductor structure and forming method thereof - Google Patents

Abstract

The present disclosure relates to the field of semiconductor technology, and relates to a semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, wherein the substrate comprises an active region, and the active region comprises a source region, a channel region and a channel region connected with the source region and the drain region; a word line groove is arranged in the substrate and penetrates through the channel region; forming a doped layer covering the inner wall of the word line groove along with the shape, wherein the doping type of doping ions in the doped layer is the same as the doping type of the source electrode area and the drain electrode area and is different from the doping type of the channel area; processing the doped layer to convert the doped layer into a first gate dielectric layer and diffuse doped ions in the doped layer into the source region, the channel region and the drain region; forming a second gate dielectric layer covering the first gate dielectric layer along with the shape; a word line structure is formed within the word line trench. The forming method can improve the stability of the device and the channel control capability.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method of forming the same.

Background

The dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used in mobile devices such as mobile phones and tablet computers due to its small size, high integration level, and high transmission speed. However, during the process of manufacturing the transistor of the DRAM, structural defects are liable to occur due to the limitation of the manufacturing process, and the product yield is low.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

In view of the above, the present disclosure provides a semiconductor structure and a method for forming the same, which can improve device stability and channel control capability.

According to one aspect of the present disclosure, there is provided a method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises an active region, and the active region comprises a source region, a drain region and a channel region connected with the source region and the drain region; a word line groove is arranged in the substrate and penetrates through the channel region;

forming a doped layer covering the inner wall of the word line groove in a conformal manner, wherein the doping type of doping ions in the doped layer is the same as the doping type of the source region and the drain region and different from the doping type of the channel region;

processing the doped layer to convert the doped layer into a first gate dielectric layer and diffuse the doped ions in the doped layer into the source region, the channel region and the drain region;

Forming a second gate dielectric layer covering the first gate dielectric layer along with the shape;

and forming a word line structure in the word line groove.

In an exemplary embodiment of the present disclosure, the material of the doped layer is polysilicon, and the processing the doped layer to convert the doped layer into a first gate dielectric layer includes:

and oxidizing the doped layer by adopting an in-situ water vapor oxidation process at a preset temperature to convert the doped layer into a first gate dielectric layer, wherein the preset temperature comprises 900-1100 ℃.

In one exemplary embodiment of the present disclosure, the forming a word line structure within the word line trench includes:

forming a diffusion barrier material layer covering the second gate dielectric layer in a conformal manner;

forming a first conductive material layer on the surface of the diffusion barrier material layer, wherein the first conductive material layer fills the word line groove;

etching back the diffusion barrier material layer and the first conductive material layer, taking the rest of the diffusion barrier material layer as a diffusion barrier layer, taking the rest of the first conductive material layer as a first conductive layer, covering the bottom and the side wall of the word line groove along with the diffusion barrier layer, wherein the top end of the diffusion barrier layer positioned on the side wall is lower than the top surface of the substrate, the surface of the first conductive layer, which is far away from the bottom of the word line groove, is higher than the top end of the diffusion barrier layer and lower than the top surface of the substrate, and the surface of the first conductive layer, which is far away from the bottom of the word line groove, is convex;

And forming a second conductive layer covering the first conductive layer in a conformal manner, wherein the work function of the second conductive layer is smaller than that of the diffusion barrier layer.

In an exemplary embodiment of the present disclosure, the forming method further includes:

and forming a third gate dielectric layer on the surface of the side wall, which is not covered by the word line structure, of the side wall of the word line groove, wherein the material of the third gate dielectric layer is a high dielectric constant material.

In an exemplary embodiment of the present disclosure, the forming method further includes:

and forming a passivation layer on the surface of the second conductive layer, wherein the passivation layer fills the residual gaps in the word line grooves.

According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:

a substrate comprising an active region comprising a source region, a drain region, and a channel region connecting the source region and the drain region; a word line groove is arranged in the substrate and penetrates through the channel region;

the first gate dielectric layer covers the inner wall of the word line groove along with the shape, and comprises doping ions, wherein the doping type of the doping ions is the same as that of the source electrode region and the drain electrode region;

The second gate dielectric layer covers the surface of the first gate dielectric layer along with the shape;

and the word line structure is positioned in the word line groove.

In an exemplary embodiment of the present disclosure, the thickness of the second gate dielectric layer is 2nm to 3nm.

In one exemplary embodiment of the present disclosure, the word line structure includes:

the diffusion barrier layer covers the bottom and the side wall of the word line groove in a conformal manner, and the top end of the diffusion barrier layer positioned on the side wall is lower than the top surface of the substrate;

the first conductive layer is arranged on the surface of the diffusion barrier layer, in the depth direction of the word line groove, the surface of the first conductive layer, which is far away from the bottom of the word line groove, is higher than the top end of the diffusion barrier layer and lower than the top surface of the substrate, and the surface of the first conductive layer, which is far away from the bottom of the word line groove, is convex;

and the second conductive layer covers the first conductive layer in a conformal manner, and the work function of the second conductive layer is smaller than that of the diffusion barrier layer.

In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:

and the third gate dielectric layer is positioned on the surface of the side wall, which is not covered by the word line structure, of the side wall of the word line groove, and the third gate dielectric layer is made of a high dielectric constant material.

In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:

and the passivation layer is positioned on the surface of the second conductive layer and fills the residual gaps in the word line grooves.

The semiconductor structure and the forming method thereof can jointly form a transistor by a source region, a drain region, a channel region, a first gate dielectric layer, a second gate dielectric layer and a word line structure. In the process of forming the transistor, a doped layer with doped ions can be formed on the inner wall of the word line groove, ions in the doped layer are diffused into the source region, the channel region and the drain region through treatment, in the process, as the doped type of the doped ions in the doped layer is the same as the doped type of the source region and the doped type of the drain region, the doped ions lost in the process of etching the source region and the drain region to form the word line groove can be compensated through the doped ions, the current amplifying capability of the transistor can be improved, the stability of the transistor can be improved, and the risks of signal distortion, noise increase and the like of the transistor can be further reduced. Meanwhile, as the doping type of the doping ions in the doping layer is different from that of the channel region, after the doping ions in the doping layer enter the channel region, the effective doping concentration of the channel region can be reduced, and effective regulation and control of a channel at the bottom of the word line structure can be realized.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a flow chart of a method of forming a semiconductor structure in an embodiment of the disclosure.

Fig. 2 is a top view of a substrate in an embodiment of the present disclosure.

Fig. 3 is a cross-sectional view taken along the x-direction in fig. 2 in an embodiment of the present disclosure.

Fig. 4 is a schematic diagram of a doped layer and a first gate dielectric layer in an embodiment of the disclosure.

Fig. 5 is a schematic diagram of a second gate dielectric layer in an embodiment of the disclosure.

FIG. 6 is a schematic diagram of a word line structure in an embodiment of the disclosure.

Fig. 7 is a schematic view of a diffusion barrier material layer and a first conductive material layer in an embodiment of the present disclosure.

Fig. 8 is a schematic diagram of a second conductive material layer in an embodiment of the disclosure.

Fig. 9 is a schematic diagram of a third dielectric material layer in an embodiment of the disclosure.

Fig. 10 is a schematic diagram of a third gate dielectric layer in an embodiment of the disclosure.

Fig. 11 is a schematic view of a passivation layer in an embodiment of the disclosure.

Reference numerals illustrate:

1. a substrate; 11. an active region; 111. a source region; 112. a channel region; 113. a drain region; 101. word line trenches; 12. shallow trench isolation structures; 2. a doped layer; 3. a first gate dielectric layer; 4. a second gate dielectric layer; 5. a word line structure; 51. a diffusion barrier layer; 52. a first conductive layer; 521. a convex surface; 53. a second conductive layer; 530. a second conductive material layer; 6. a third gate dielectric layer; 7. a passivation layer; x, a first direction; y, second direction.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.

An embodiment of the present disclosure provides a method for forming a semiconductor structure, fig. 1 shows a flowchart of the method for forming a semiconductor structure of the present disclosure, and please refer to fig. 1, the method includes steps S110-S150, wherein:

step S110, providing a substrate, wherein the substrate comprises an active region, and the active region comprises a source region, a drain region and a channel region connected with the source region and the drain region; a word line groove is arranged in the substrate and penetrates through the channel region;

step S120, forming a doped layer covering the inner wall of the word line groove in a conformal manner, wherein the doping type of doping ions in the doped layer is the same as the doping type of the source electrode region and the drain electrode region and is different from the doping type of the channel region;

step S130, processing the doped layer to convert the doped layer into a first gate dielectric layer, and diffusing the doped ions in the doped layer into the source region, the channel region and the drain region;

step S140, forming a second gate dielectric layer covering the first gate dielectric layer in a conformal manner;

step S150, forming a word line structure in the word line groove.

The source region, the drain region, the channel region, the first gate dielectric layer, the second gate dielectric layer and the word line structure can jointly form a transistor. In the process of forming the transistor, a doped layer with doped ions can be formed on the inner wall of the word line groove, ions in the doped layer are diffused into the source region, the channel region and the drain region through treatment, in the process, as the doped type of the doped ions in the doped layer is the same as the doped type of the source region and the doped type of the drain region, the doped ions lost in the process of etching the source region and the drain region to form the word line groove can be compensated through the doped ions, the current amplifying capability of the transistor can be improved, the stability of the transistor can be improved, and the risks of signal distortion, noise increase and the like of the transistor can be further reduced. Meanwhile, as the doping type of the doping ions in the doping layer is different from that of the channel region, after the doping ions in the doping layer enter the channel region, the effective doping concentration of the channel region can be reduced, and effective regulation and control of a channel at the bottom of the word line structure can be realized.

The steps of the method for forming a semiconductor structure of the present disclosure and their specific details are described in detail below:

The steps of the method for forming a semiconductor structure of the present disclosure and their specific details are described in detail below:

as shown in fig. 1, in step S110, a substrate 1 is provided, the substrate 1 including an active region 11, the active region 11 including a source region 111, a drain region 113, and a channel region 112 connecting the source region 111 and the drain region 113; a word line trench 101 is provided in the substrate 1, the word line trench 101 passing through the channel region 112.

As shown in fig. 2 and 3, the substrate 1 may have a flat structure, which may be rectangular, circular, elliptical, polygonal, or irregular, and the material may be a semiconductor material, for example, silicon, etc., and the shape and material of the substrate 1 are not particularly limited.

In some embodiments of the present disclosure, the substrate 1 may be a P-type substrate, which includes P-type doping ions therein, and may be n-doped, thereby forming an n-type source-drain doped layer within the P-type substrate; subsequently, the p-type substrate including the n-type source/drain doped layer may be etched to form isolation trenches, and the isolation trenches may be filled with an insulating material to form shallow trench isolation structures 12, where the shallow trench isolation structures 12 may separate the p-type substrate including the n-type source/drain doped layer into a plurality of active regions 11 on the substrate 1.

In other embodiments of the present disclosure, the shallow trench isolation structure 12 may be formed in the p-type substrate before the n-type source/drain doped layer is formed, and the n-type substrate is doped after the shallow trench isolation structure 12 is formed, so as to form a plurality of n-type doped active regions 11, where each active region 11 may together form the n-type source/drain doped layer.

With continued reference to fig. 2 and 3, the word line trench 101 may be formed in the substrate 1 by dry etching, the word line trench 101 may be stripe-shaped and may extend along the second direction y, and the word line trench 101 may pass through the plurality of active regions 11 and the shallow trench isolation structure 12 between the active regions 11 along the second direction y. The source/drain doped layer of the active region 11 remaining on one side of the word line trench 101 may be used as the source region 111, the source/drain doped layer of the active region 11 remaining on the other side of the word line trench 101 may be used as the drain region 113, a portion of the remaining active region 11 connected between the source region 111 and the drain region 113 and adjacent to the word line trench 101 may be used as the channel region 112, and an arrangement direction of the source region 111, the channel region 112, and the drain region 113 may be used as the first direction. The second direction y and the first direction x may be directions parallel to the substrate 1, and the second direction y may intersect the first direction x, and an included angle between the second direction y and the first direction x may be greater than or equal to 30 ° and less than 90 °, for example, an included angle between the second direction y and the first direction x may be 30 °, 40 °, 45 °, 50 °, 60 °, 70 ° or 80 °, or the like, which may be other angles, and are not specifically mentioned herein.

In some embodiments of the present disclosure, the number of word line trenches 101 may be plural, the plurality of word line trenches 101 may be spaced apart in a direction perpendicular to the second direction y, and different word line trenches 101 may pass through different channel regions 112.

As shown in fig. 1, in step S120, a doped layer 2 is formed to cover the inner wall of the word line trench 101, and the doping type of the doping ions in the doped layer 2 is the same as the doping type of the source region 111 and the drain region 113 and is different from the doping type of the channel region 112.

As shown in fig. 4, the doped layer 2 may be formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like, and the doped layer 2 may cover the sidewall and the bottom of the word line trench 101 in a conformal manner, however, the doped layer 2 may be formed by other methods, and the forming manner of the doped layer 2 is not particularly limited. The in-situ doping may be performed during the formation of the doped layer 2 such that the doped layer 2 contains dopant ions. The doping type of the doping ions is the same as the doping type of the source region 111 and the drain region 113 and is different from the doping type of the channel region 112, for example, when the doping type of the source region 111 and the drain region 113 is n-type and the doping type of the channel region 112 is p-type, the doping ions in the doping layer 2 are n-type doping ions. For example, the doping ions in the doping layer 2 may be phosphorus ions or arsenic ions.

In some embodiments of the present disclosure, the material of the doped layer 2 may be polysilicon, and the thickness of the doped layer 2 may be 2nm to 3nm, for example, the thickness may be 2nm, 2.2nm, 2.4nm, 2.6nm, 2.8nm or 3nm, and of course, other thicknesses may be also used, which are not listed here.

As shown in fig. 1, in step S130, the doped layer 2 is processed to convert the doped layer 2 into the first gate dielectric layer 3, and diffuse the dopant ions in the doped layer 2 into the source region 111, the channel region 112, and the drain region 113.

In some embodiments of the present disclosure, please continue to refer to fig. 4, an in-situ water vapor oxidation process may be used to oxidize the doped layer 2 at a preset temperature, so as to convert the doped layer 2 into the first gate dielectric layer 3; when the material of the doped layer 2 is polysilicon, the material of the first gate dielectric layer 3 is silicon oxide. In some embodiments, the predetermined temperature may include 900-1100 ℃, e.g., 900 ℃, 950 ℃, 1000 ℃, 1050 ℃, or 1100 ℃, although other temperatures are also possible and are not listed here. Due to the fact that the preset temperature is high, in the in-situ steam oxidation process, under the action of high temperature, doped ions in the doped layer 2 diffuse into the source region 111, the drain region 113 and the channel region 112 adjacent to the doped ions, in the process, the doped type of the doped ions in the doped layer 2 is the same as the doped type of the source region 111 and the drain region 113, the doped ions lost in the process of etching the source region 111 and the drain region 113 to form the word line groove 101 can be compensated after the doped ions enter the source region and the drain region 113, current amplifying capability of a transistor formed later can be improved, stability of the transistor is improved, and risks such as signal distortion and noise increase of the transistor are reduced. Meanwhile, since the doping type of the doping ions in the doping layer 2 is different from the doping type of the channel region 112, the effective doping concentration of the channel region 112 can be reduced after the doping ions in the doping layer 2 enter the channel region 112, and effective regulation of the bottom channel of the word line structure 5 can be realized.

It will be appreciated that a small amount of dopant ions may remain in the first gate dielectric layer 3 after the in-situ steam oxidation process is completed.

As shown in fig. 1, in step S140, a second gate dielectric layer 4 is formed to cover the first gate dielectric layer 3 in a conformal manner.

As shown in fig. 5, the second gate dielectric layer 4 covering the surface of the first gate dielectric layer 3 in a conformal manner may be formed by atomic layer deposition or the like, and the second gate dielectric layer 4 and the first gate dielectric layer 3 may together form a gate dielectric layer of a transistor to be formed subsequently. The material of the second gate dielectric layer 4 may be silicon oxide, and the second gate dielectric layer 4 may block the first gate dielectric layer 3 and the word line structure 5 formed in the word line trench 101, so as to reduce the risk of leakage between the first gate dielectric layer 3 and the word line structure 5.

In some embodiments of the present disclosure, the thickness of the second gate dielectric layer 4 may be 2nm to 3nm, for example, the thickness may be 2nm, 2.2nm, 2.4nm, 2.6nm, 2.8nm or 3nm, and of course, other thicknesses may be also used, which are not listed here.

As shown in fig. 1, in step S150, a word line structure 5 is formed in the word line trench 101.

As shown in fig. 6, after the second gate dielectric layer 4 is formed, a word line structure 5 may be formed within the word line trench 101 to form a buried word line structure 5. The word line structure 5 may be stripe-shaped and may extend along the extending direction of the word line trench 101, for example, the word line structure 5 may extend along the second direction y. Note that, when the number of the word line trenches 101 is plural, the number of the word line structures 5 may be plural, and each word line trench 101 may have one word line structure 5 formed therein.

In some embodiments of the present disclosure, the word line structure 5 may include a diffusion barrier layer 51, a first conductive layer 52, and a second conductive layer 53, wherein:

with continued reference to fig. 6, the diffusion barrier layer 51 may cover the bottom and sidewalls of the word line trench 101, and the top of the diffusion barrier layer 51 on the sidewalls of the word line trench 101 may be lower than the surface of the substrate 1, i.e., the diffusion barrier layer 51 does not completely cover the inner walls of the word line trench 101. The material of the diffusion barrier layer 51 may be a material having an ion blocking function and a higher work function in order to raise the threshold voltage of a transistor to be formed later. For example, the material of the diffusion barrier layer 51 may be titanium nitride, etc., and its thickness may be 1nm to 2nm, for example, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, or 2nm.

With continued reference to fig. 6, the first conductive layer 52 may be disposed on the surface of the diffusion barrier layer 51, and in the depth direction of the word line trench 101, the surface of the first conductive layer 52 away from the bottom of the word line trench 101 may be higher than the top of the diffusion barrier layer 51 and lower than the top of the substrate 1, i.e., the surface of the first conductive layer 52 protrudes from the top of the diffusion barrier layer 51. In some embodiments of the present disclosure, the surface of the first conductive layer 52 away from the bottom of the word line trench 101 may be convex 521, where the convex 521 is relatively smooth, and no corner exists, which is beneficial to better fit with other film structures formed on the surface of the first conductive layer 52, and may reduce the risk of peeling between the films, which is beneficial to improving the product yield.

The material of the first conductive layer 52 may be a material having good conductivity so as to reduce the resistance. For example, the material of the first conductive layer 52 may be tungsten, but other materials with better conductive properties may be used, which are not listed here. Since the first conductive layer 52 is located on the surface of the diffusion barrier layer 51, the diffusion barrier layer 51 can isolate the first conductive layer 52 from the second gate dielectric layer 4, and the diffusion barrier layer 51 can prevent the metal ions in the first conductive layer 52 from diffusing into the second gate dielectric layer 4, which is helpful for improving the stability of the device.

With continued reference to fig. 6, the second conductive layer 53 may cover the surface of the first conductive layer 52 in a conformal manner, for example, the second conductive layer 53 may cover the convex surface 521 in a conformal manner, and in this process, the second conductive layer 53 may also be convex, which is beneficial to better adhering other film structures formed on the surface of the second conductive layer 53 to the second conductive layer 53, so as to further reduce the risk of peeling between the film layers and further improve the product yield. It should be noted that the second conductive layer 53, the first conductive layer 52, and the diffusion barrier layer 51 may together form the word line structure 5 of the present disclosure.

In some embodiments of the present disclosure, the material of the second conductive layer 53 may be a material with a lower work function in order to reduce the risk of shorting or coupling between the word line structure 5 and other surrounding structures. For example, the material of the second conductive layer 53 may be polysilicon, and the second conductive layer 53 may be ion doped, thereby improving the conductivity of the second conductive layer 53 and adjusting the work function of the second conductive layer 53.

In one exemplary embodiment of the present disclosure, forming the wordline structure 5 within the wordline trench 101 (i.e. step S150) may include steps S210-S240, wherein:

in step S210, a diffusion barrier material layer 510 is formed to cover the second gate dielectric layer 4 in a conformal manner.

As shown in fig. 7, the diffusion barrier material layer 510 may be formed on the inner wall of the word line trench 101 having the first gate dielectric layer 3 and the second gate dielectric layer 4 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like, however, the diffusion barrier material layer 510 may be formed by other methods, and the forming method of the diffusion barrier material layer 510 is not particularly limited. The material of the diffusion barrier material layer 510 may be titanium nitride, and its thickness may be 1nm to 2nm.

In step S220, a first conductive material layer 520 is formed on the surface of the diffusion barrier material layer 510, and the first conductive material layer 520 fills the word line trench 101.

With continued reference to fig. 7, the first conductive material layer 520 may be formed on the surface of the diffusion barrier material layer 510 by atomic layer deposition, chemical vapor deposition or physical vapor deposition, so that the first conductive material layer 520 may fill the word line trench 101 for facilitating the subsequent control of the height of the first conductive layer 52 to be formed.

In step S230, the diffusion barrier material layer 510 and the first conductive material layer 520 are etched back, the remaining diffusion barrier material layer 510 is used as a diffusion barrier layer 51, the remaining first conductive material layer 520 is used as a first conductive layer 52, the diffusion barrier layer 51 covers the bottom and the side wall of the word line trench 101 in a conformal manner, the top end of the diffusion barrier layer 51 on the side wall is lower than the top surface of the substrate 1, the surface of the first conductive layer 52 away from the bottom of the word line trench 101 is higher than the top end of the diffusion barrier layer 51 and lower than the top surface of the substrate 1, and the surface of the first conductive layer 52 away from the bottom of the word line trench 101 is convex 521.

The diffusion barrier material layer 510 and the first conductive material layer 520 may be etched back by dry etching or wet etching, so that the top ends of the diffusion barrier material layer 510 and the first conductive material layer 520 are lower than the surface of the substrate 1, and in the etching back process, the surface of the finally remaining first conductive material layer 520 may be convex 521 by controlling the injection angle of the etching gas, so that the remaining first conductive material layer 520 of the word line trench 101 may be used as the first conductive layer 52, and the remaining diffusion barrier material layer 510 in the word line trench 101 may be used as the diffusion barrier layer 51.

In step S240, a second conductive layer 53 is formed to cover the first conductive layer 52 in a conformal manner, and the work function of the second conductive layer 53 is smaller than the work function of the diffusion barrier layer 51.

As shown in fig. 8, the second conductive material layer 530 may be formed on the surface of the first conductive layer 52 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like, and of course, the second conductive material layer 530 may be formed by other methods, and the material of the second conductive material layer 530 is not limited specifically. Then, the second conductive material layer 530 may be etched back, and the remaining second conductive material layer 530 after etching back covers the surface of the first conductive layer 52 in a conformal manner, that is, the upper surface and the lower surface of the remaining second conductive material layer 530 are convex, and the remaining second conductive material layer 530 may be used as the second conductive layer 53.

In some embodiments of the present disclosure, the work function of the second conductive material layer 530 may be less than the work function of the diffusion barrier layer 51, for example, the material of the second conductive material layer 530 may be polysilicon with ion doping, and the material of the diffusion barrier layer 51 may be titanium nitride.

In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include:

In step S160, a third gate dielectric layer 6 is formed on the sidewall surface of the sidewall of the word line trench 101, which is not covered by the word line structure 5, and the material of the third gate dielectric layer 6 is a high dielectric constant material.

After the formation of the word line structure 5, the third gate dielectric layer 6 may be formed on the sidewall of the word line trench 101 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like, and of course, the third gate dielectric layer 6 may be formed by other methods, and the formation method of the third gate dielectric layer 6 is not particularly limited. For example, as shown in fig. 9, a third dielectric material layer 610 may be formed on the surface of the structure formed by the word line structure 5, the substrate 1 and the second gate dielectric layer 4, and then the third dielectric material layer 610 on the top of the substrate 1 and the top of the word line structure 5 may be removed by etching back, so as to expose the top of the word line structure 5, for example, the surface of the second conductive layer 53 may be exposed. The remaining third dielectric material layer 610 may be used as the third gate dielectric layer 6, i.e., one end of the third gate dielectric layer 6 may be in contact with an end of the diffusion barrier layer 51 away from the bottom of the word line trench 101, and the other end may be flush with the surface of the substrate 1. In the embodiment of the present disclosure, the structure after step S160 is completed is shown in fig. 10.

In some embodiments of the present disclosure, the material of the third Gate dielectric layer 6 may be a material with a higher dielectric constant, so that the Gate induced drain leakage (GIDL, gate-Induced Drain Leakage) between the word line structure 5 and the source region 111 and/or the drain region 113 can be reduced by the arrangement of the third Gate dielectric layer 6, thereby reducing the risk of leakage. For example, the material of the third gate dielectric layer 6 may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide or a mixture thereof, but may also be other materials, which are not listed here. The thickness of the third gate dielectric layer 6 may be 1nm to 2nm, for example, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm or 2nm, but of course, other thicknesses are also possible and are not specifically mentioned here.

In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include:

in step S170, a passivation layer 7 is formed on the surface of the second conductive layer 53, and the passivation layer 7 fills the remaining space in the word line trench 101.

As shown in fig. 11, after the third gate dielectric layer 6 is formed, a passivation layer 7 may be formed on the surface of the second conductive layer 53 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like, and the passivation layer 7 may fill the space remaining in the word line trench 101 and may have a surface flush with the surface of the substrate 1. That is, the passivation layer 7 may be in contact with both the second conductive layer 53 and the third gate dielectric layer 6. For example, in the process of forming the passivation layer 7, for convenience of the process, a passivation material layer may be formed on top of the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like, until the passivation material layer fills each word line trench 101; subsequently, the passivation material layer located on top of the substrate 1 may be removed by etching back or grinding, etc., and the top of the passivation material layer located in the word line trench 101 may be made flush with the surface of the substrate 1, and the remaining passivation material layer in the word line trench 101 may be used as the passivation layer 7. In the process of etching back or polishing the passivation layer, if other film structures (for example, the doped layer 2 or the first gate dielectric layer 3) remain on top of the substrate 1 in the other process, the other film structures remaining on the surface of the substrate 1 may be removed at the same time, so that the surfaces of the source region 111 and the drain region 113 are exposed.

In some embodiments of the present disclosure, the material of the passivation layer 7 may be an insulating material, and the passivation layer 7 may insulate and protect the surface of the word line structure 5, so that damage to the surface of the word line structure 5 caused by subsequent processes may be avoided, and the probability of coupling or short circuit between the word line structure 5 and other surrounding structures may be reduced, which is helpful for improving the product yield. For example, the material of the passivation layer 7 may be silicon oxynitride or silicon nitride.

It should be noted that although the steps of the method of forming a semiconductor structure in the present disclosure are depicted in a particular order in the figures, this does not require or imply that the steps must be performed in that particular order or that all of the illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.

The present disclosure also provides a semiconductor structure, as shown in fig. 11, which includes a substrate 1, a doped layer 2, a second gate dielectric layer 4, and a word line structure 5, wherein:

the substrate 1 comprises an active region 11, wherein the active region 11 comprises a source region 111, a channel region 112 and a drain region 113 which are adjacently distributed in sequence; a word line trench 101 is arranged in the substrate 1, and the word line trench 101 passes through the channel region 112;

The first gate dielectric layer 3 covers the inner wall of the word line groove 101 along with the shape, and the first gate dielectric layer 3 comprises doping ions, wherein the doping type of the doping ions is the same as that of the source electrode region 111 and the drain electrode region 113;

the second gate dielectric layer 4 covers the surface of the first gate dielectric layer 3 along with the shape;

the word line structure 5 is located within the word line trench 101.

The semiconductor structure of the present disclosure, the source region 111, the drain region 113, the channel region 112, the first gate dielectric layer 3, the second gate dielectric layer 4, and the word line structure 5 may collectively constitute a transistor. In the transistor, the first gate dielectric layer 3 is converted from a doped layer, and ions in the doped layer can diffuse into the source region 111, the channel region 112 and the drain region 113, in this process, since the doping type of the doped ions in the doped layer is the same as the doping type of the source region 111 and the drain region 113, the doped ions lost in the process of etching the source region 111 and the drain region 113 to form the word line trench 101 can be compensated by the doped ions, which is helpful for improving the current amplifying capability of the transistor, improving the stability of the transistor, and further reducing risks such as signal distortion and noise increase of the transistor. Meanwhile, since the doping type of the doping ions in the doping layer is different from the doping type of the channel region 112, after the doping ions in the doping layer enter the channel region 112, the effective doping concentration of the channel region 112 can be reduced, and effective regulation and control of the bottom channel of the word line structure 5 can be realized.

The following is a detailed description of portions and details of the semiconductor structures of the present disclosure:

as shown in fig. 2 and 3, the substrate 1 may have a flat structure, which may be rectangular, circular, elliptical, polygonal, or irregular, and the material may be a semiconductor material, for example, silicon, etc., and the shape and material of the substrate 1 are not particularly limited.

In some embodiments of the present disclosure, the substrate 1 may be a P-type substrate, which includes P-type doping ions therein, and may be n-doped, thereby forming an n-type source-drain doped layer within the P-type substrate; subsequently, the p-type substrate including the n-type source/drain doped layer may be etched to form isolation trenches, and the isolation trenches may be filled with an insulating material to form shallow trench isolation structures 12, where the shallow trench isolation structures 12 may separate the p-type substrate including the n-type source/drain doped layer into a plurality of active regions 11 on the substrate 1.

In other embodiments of the present disclosure, the shallow trench isolation structure 12 may be formed in the p-type substrate before the n-type source/drain doped layer is formed, and the n-type substrate is doped after the shallow trench isolation structure 12 is formed, so as to form a plurality of n-type doped active regions 11, where each active region 11 may together form the n-type source/drain doped layer.

With continued reference to fig. 2 and 3, the word line trench 101 may be formed in the substrate 1 by dry etching, the word line trench 101 may be stripe-shaped and may extend along the second direction y, and the word line trench 101 may pass through the plurality of active regions 11 and the shallow trench isolation structure 12 between the active regions 11 along the second direction y. The source/drain doped layer of the active region 11 remaining on one side of the word line trench 101 may be used as the source region 111, the source/drain doped layer of the active region 11 remaining on the other side of the word line trench 101 may be used as the drain region 113, a portion of the remaining active region 11 connected between the source region 111 and the drain region 113 and adjacent to the word line trench 101 may be used as the channel region 112, and an arrangement direction of the source region 111, the channel region 112, and the drain region 113 may be used as the first direction. The second direction y and the first direction x may be directions parallel to the substrate 1, and the second direction y may intersect the first direction x, and an included angle between the second direction y and the first direction x may be greater than or equal to 30 ° and less than 90 °, for example, an included angle between the second direction y and the first direction x may be 30 °, 40 °, 45 °, 50 °, 60 °, 70 ° or 80 °, or the like, which may be other angles, and are not specifically mentioned herein.

In some embodiments of the present disclosure, the number of word line trenches 101 may be plural, the plurality of word line trenches 101 may be spaced apart in a direction perpendicular to the second direction y, and different word line trenches 101 may pass through different channel regions 112.

The first gate dielectric layer 3 may cover the sidewalls and bottom of the word line trench 101 in a conformal manner, and the first gate dielectric layer 3 may include dopant ions. The doping type of the doping ions is the same as the doping type of the source region 111 and the drain region 113 and is different from the doping type of the channel region 112, for example, when the doping type of the source region 111 and the drain region 113 is n-type and the doping type of the channel region 112 is p-type, the doping ions in the first gate dielectric layer 3 are n-type doping ions. For example, the doping ions in the first gate dielectric layer 3 may be phosphorus ions or arsenic ions.

In some embodiments of the present disclosure, the material of the first gate dielectric layer 3 may be silicon oxide.

As shown in fig. 5, the second gate dielectric layer 4 may be formed on the surface of the first gate dielectric layer 3, and the concentration of the dopant ions in the second gate dielectric layer 4 is smaller than the concentration of the dopant ions in the first gate dielectric layer 3. For example, the second gate dielectric layer 4 does not include doping ions therein; alternatively, the dopant ions in the first gate dielectric layer 3 may diffuse into the second gate dielectric layer 4, so that the second gate dielectric layer 4 includes a small amount of dopant ions. The second gate dielectric layer 4 and the first gate dielectric layer 3 may together form a gate dielectric layer of a transistor to be formed later. The material of the second gate dielectric layer 4 may be silicon oxide, and the second gate dielectric layer 4 may block the first gate dielectric layer 3 and the word line structure 5 formed in the word line trench 101, so as to reduce the risk of leakage between the first gate dielectric layer 3 and the word line structure 5.

In some embodiments of the present disclosure, the thickness of the second gate dielectric layer 4 may be 2nm to 3nm, for example, the thickness may be 2nm, 2.2nm, 2.4nm, 2.6nm, 2.8nm or 3nm, and of course, other thicknesses may be also used, which are not listed here.

As shown in fig. 6, after the second gate dielectric layer 4 is formed, a word line structure 5 may be formed within the word line trench 101 to form a buried word line structure 5. The word line structure 5 may be stripe-shaped and may extend along the extending direction of the word line trench 101, for example, the word line structure 5 may extend along the second direction y. Note that, when the number of the word line trenches 101 is plural, the number of the word line structures 5 may be plural, and each word line trench 101 may have one word line structure 5 formed therein.

In some embodiments of the present disclosure, the word line structure 5 may include a diffusion barrier layer 51, a first conductive layer 52, and a second conductive layer 53, wherein:

with continued reference to fig. 6, the diffusion barrier layer 51 may cover the bottom and sidewalls of the word line trench 101, and the top of the diffusion barrier layer 51 on the sidewalls of the word line trench 101 may be lower than the surface of the substrate 1, i.e., the diffusion barrier layer 51 does not completely cover the inner walls of the word line trench 101. The material of the diffusion barrier layer 51 may be a material having an ion blocking function and a higher work function in order to raise the threshold voltage of a transistor to be formed later. For example, the material of the diffusion barrier layer 51 may be titanium nitride, etc., and its thickness may be 1nm to 2nm, for example, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, or 2nm.

With continued reference to fig. 6, the first conductive layer 52 may be disposed on the surface of the diffusion barrier layer 51, and in the depth direction of the word line trench 101, the surface of the first conductive layer 52 away from the bottom of the word line trench 101 may be higher than the top of the diffusion barrier layer 51 and lower than the top of the substrate 1, i.e., the surface of the first conductive layer 52 protrudes from the top of the diffusion barrier layer 51. In some embodiments of the present disclosure, the surface of the first conductive layer 52 away from the bottom of the word line trench 101 may be convex 521, where the convex 521 is relatively smooth, and no corner exists, which is beneficial to better fit with other film structures formed on the surface of the first conductive layer 52, and may reduce the risk of peeling between the films, which is beneficial to improving the product yield.

The material of the first conductive layer 52 may be a material having good conductivity so as to reduce the resistance. For example, the material of the first conductive layer 52 may be tungsten, but other materials with better conductive properties may be used, which are not listed here. Since the first conductive layer 52 is located on the surface of the diffusion barrier layer 51, the diffusion barrier layer 51 can isolate the first conductive layer 52 from the second gate dielectric layer 4, and the diffusion barrier layer 51 can prevent the metal ions in the first conductive layer 52 from diffusing into the second gate dielectric layer 4, which is helpful for improving the stability of the device.

With continued reference to fig. 6, the second conductive layer 53 may cover the surface of the first conductive layer 52 in a conformal manner, for example, the second conductive layer 53 may cover the convex surface 521 in a conformal manner, and in this process, the second conductive layer 53 may also be convex, which is beneficial to better adhering other film structures formed on the surface of the second conductive layer 53 to the second conductive layer 53, so as to further reduce the risk of peeling between the film layers and further improve the product yield. It should be noted that the second conductive layer 53, the first conductive layer 52, and the diffusion barrier layer 51 may together form the word line structure 5 of the present disclosure.

In some embodiments of the present disclosure, the material of the second conductive layer 53 may be a material with a lower work function in order to reduce the risk of shorting or coupling between the word line structure 5 and other surrounding structures. For example, the material of the second conductive layer 53 may be polysilicon, and the second conductive layer 53 may be ion doped, thereby improving the conductivity of the second conductive layer 53 and adjusting the work function of the second conductive layer 53.

In one exemplary embodiment of the present disclosure, as shown in fig. 10, the semiconductor structure of the present disclosure may further include a third gate dielectric layer 6, the third gate dielectric layer 6 may be located on a sidewall surface of the sidewall of the word line trench 101 that is not covered by the word line structure 5, for example, the third gate dielectric layer 6 may be located on a sidewall surface of the sidewall of the word line trench 101 that is not covered by the diffusion barrier layer 51, for example, one end of the third gate dielectric layer 6 may be in contact with an end of the diffusion barrier layer 51 away from the bottom of the word line trench 101, and the other end may be flush with the surface of the substrate 1.

In some embodiments of the present disclosure, the material of the third gate dielectric layer 6 may be a material with a higher dielectric constant, so that the Gate Induced Drain Leakage (GIDL) between the word line structure 5 and the source region 111 and/or the drain region 113 can be reduced by the arrangement of the third gate dielectric layer 6, thereby reducing the risk of leakage. For example, the material of the third gate dielectric layer 6 may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide or a mixture thereof, but may also be other materials, which are not listed here. The thickness of the third gate dielectric layer 6 may be 1nm to 2nm, for example, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm or 2nm, but of course, other thicknesses are also possible and are not specifically mentioned here.

In one exemplary embodiment of the present disclosure, as shown in fig. 11, the semiconductor structure of the present disclosure may further include a passivation layer 7, and the passivation layer 7 may be located at a surface of the second conductive layer 53 and may fill the remaining voids within the word line trench 101, and the surface thereof may be flush with the surface of the substrate 1. That is, the passivation layer 7 may be in contact with both the second conductive layer 53 and the third gate dielectric layer 6.

In some embodiments of the present disclosure, the material of the passivation layer 7 may be an insulating material, and the passivation layer 7 may insulate and protect the surface of the word line structure 5, so that damage to the surface of the word line structure 5 caused by subsequent processes may be avoided, and the probability of coupling or short circuit between the word line structure 5 and other surrounding structures may be reduced, which is helpful for improving the product yield. For example, the material of the passivation layer 7 may be silicon oxynitride or silicon nitride.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (10)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises an active region, and the active region comprises a source region, a drain region and a channel region connected with the source region and the drain region; a word line groove is arranged in the substrate and penetrates through the channel region;

forming a doped layer covering the inner wall of the word line groove in a conformal manner, wherein the doping type of doping ions in the doped layer is the same as the doping type of the source region and the drain region and different from the doping type of the channel region;

processing the doped layer to convert the doped layer into a first gate dielectric layer and diffuse the doped ions in the doped layer into the source region, the channel region and the drain region;

Forming a second gate dielectric layer covering the first gate dielectric layer along with the shape;

and forming a word line structure in the word line groove.

2. The method of claim 1, wherein the doped layer is polysilicon, and the processing the doped layer to convert the doped layer to a first gate dielectric layer comprises:

and oxidizing the doped layer by adopting an in-situ water vapor oxidation process at a preset temperature to convert the doped layer into a first gate dielectric layer, wherein the preset temperature comprises 900-1100 ℃.

3. The method of forming of claim 1, wherein the forming of the wordline structure within the wordline trench comprises:

forming a diffusion barrier material layer covering the second gate dielectric layer in a conformal manner;

forming a first conductive material layer on the surface of the diffusion barrier material layer, wherein the first conductive material layer fills the word line groove;

etching back the diffusion barrier material layer and the first conductive material layer, taking the rest of the diffusion barrier material layer as a diffusion barrier layer, taking the rest of the first conductive material layer as a first conductive layer, covering the bottom and the side wall of the word line groove along with the diffusion barrier layer, wherein the top end of the diffusion barrier layer positioned on the side wall is lower than the top surface of the substrate, the surface of the first conductive layer, which is far away from the bottom of the word line groove, is higher than the top end of the diffusion barrier layer and lower than the top surface of the substrate, and the surface of the first conductive layer, which is far away from the bottom of the word line groove, is convex;

And forming a second conductive layer covering the first conductive layer in a conformal manner, wherein the work function of the second conductive layer is smaller than that of the diffusion barrier layer.

4. The forming method according to claim 3, characterized in that the forming method further comprises:

and forming a third gate dielectric layer on the surface of the side wall, which is not covered by the word line structure, of the side wall of the word line groove, wherein the material of the third gate dielectric layer is a high dielectric constant material.

5. The forming method according to claim 4, characterized in that the forming method further comprises:

and forming a passivation layer on the surface of the second conductive layer, wherein the passivation layer fills the residual gaps in the word line grooves.

6. A semiconductor structure, comprising:

a substrate comprising an active region comprising a source region, a drain region, and a channel region connecting the source region and the drain region; a word line groove is arranged in the substrate and penetrates through the channel region;

the first gate dielectric layer covers the inner wall of the word line groove along with the shape, and comprises doping ions, wherein the doping type of the doping ions is the same as that of the source electrode region and the drain electrode region;

The second gate dielectric layer covers the surface of the first gate dielectric layer along with the shape;

and the word line structure is positioned in the word line groove.

7. The semiconductor structure of claim 6, wherein the second gate dielectric layer has a thickness of 2nm to 3nm.

8. The semiconductor structure of claim 7, wherein the word line structure comprises:

the diffusion barrier layer covers the bottom and the side wall of the word line groove in a conformal manner, and the top end of the diffusion barrier layer positioned on the side wall is lower than the top surface of the substrate;

the first conductive layer is arranged on the surface of the diffusion barrier layer, in the depth direction of the word line groove, the surface of the first conductive layer, which is far away from the bottom of the word line groove, is higher than the top end of the diffusion barrier layer and lower than the top surface of the substrate, and the surface of the first conductive layer, which is far away from the bottom of the word line groove, is convex;

and the second conductive layer covers the first conductive layer in a conformal manner, and the work function of the second conductive layer is smaller than that of the diffusion barrier layer.

9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises:

and the third gate dielectric layer is positioned on the surface of the side wall, which is not covered by the word line structure, of the side wall of the word line groove, and the third gate dielectric layer is made of a high dielectric constant material.

10. The semiconductor structure of claim 9, wherein the semiconductor structure further comprises:

and the passivation layer is positioned on the surface of the second conductive layer and fills the residual gaps in the word line grooves.