CN116707522A - Multi-octave-crossing digital delay line circuit and digital delay method thereof - Google Patents

Abstract

The application relates to a digital delay line circuit crossing multiple octaves and a digital delay method thereof, belongs to the technical field of signal processing, and solves the problems that the area power consumption is wasted and the design complexity of a DAC is increased due to the fact that a plurality of ADPLLs exist. The circuit comprises: the control circuit is used for selecting a delay path in the delay module according to the frequency information of the input clock signal to be delayed; the delay module is used for delaying the clock signal to be delayed to generate a plurality of output clock signals with different phases; the phase-locked loop circuit is used for carrying out frequency and phase discrimination on the clock signal to be delayed and the output clock signal, converting the frequency and phase discrimination information into a voltage signal and feeding the voltage signal back to the control power supply of the delay module; and a phase selector circuit for selecting a plurality of output clock signals having different phases to obtain a target delayed clock signal. The digital delay line circuit does not need a DAC and a plurality of ADPLLs, and reduces area power consumption and design complexity.

Description

Multi-octave-crossing digital delay line circuit and digital delay method thereof

Technical Field

The application relates to the technical field of signal processing, in particular to a digital delay line circuit crossing multiple octaves and a digital delay method thereof.

Background

Modern communication standards must employ high peak-to-average ratio modulation to achieve full utilization of limited bandwidth, and switched mode power amplifiers can be driven directly by digital circuitry with higher efficiency than conventional linear amplifiers. This type of transmitter, in addition to flexibility and efficiency, is more suitable for implementation of nano-scale CMOS technology on a chip, which is important for cost and size reduction. The development of switch-like power amplifiers provides a high-efficiency solution for digital radio frequency front-end technology, i.e., digital radio frequency transmitters. The advent of digital radio frequency technology has provided a practical theoretical basis and a viable solution for the goal of low power consumption. The phase modulator is used as an important component module of the digital radio frequency front end and plays a key role in modulating baseband phase information to a radio frequency carrier wave, and the quality of a transmitted signal is directly determined by the performance of the phase modulator, so that the design complexity of analog devices such as a PA, a filter and the like is influenced.

Currently, accurate relative delay accuracy is provided by the closed loop of the phase-locked loop, so that the circuit has the capability of high-performance operation under different PVT (process, voltage and temperature).

Referring to fig. 1, one type of digital phase modulation commonly used is closed loop phase modulation based on an All-digital phase locked loop (All-Digital Phase Locked Loop, ADPLL). The principle of closed-loop phase modulation based on ADPLL is as follows: the frequency division ratio of the closed-loop phase-locked loop is controlled by a data frequency control word and a carrier frequency control word together, a frequency-divided signal and a reference frequency are compared through a frequency-phase discriminator, the obtained phase difference is injected into a charge pump and converted into voltage after passing through a low-pass filter, the voltage is used as the control input of an oscillator, the frequency adjustment is realized, and the path is a low-pass path of the phase-locked loop; on the high-pass path, the data frequency control word is directly converted into a voltage signal by a (Digital-Analog Converter, DAC) and loaded at the input of the oscillator. However, the phase modulation system is very sensitive to the nonlinearity of the oscillator, limits the capability of the ADPLL to modulate the wideband signal, and requires multiple ADPLLs in a transmitter circuit with multiple phase branches, which is a waste of area power consumption and may cause injection traction problems.

Modulators based on digital delay lines (Digital Delay Line), which are essentially digital time converters (Digital to Time Converter, DTCs), have been used in various transmitter architectures for digitally controlled delay chain based phase modulators, by outputting corresponding delay waveforms from different control codes. But the circuit uses a DAC to convert the digital control word to an analog signal to be loaded at the input of the oscillator, adding complexity to the system design.

Disclosure of Invention

In view of the above analysis, the embodiments of the present application aim to provide a digital delay line circuit and a method for cross-octaves, which are used to solve the problems that the existing phase modulation system needs multiple ADPLLs in a transmitter circuit with multiple phase branches, which causes waste of area power consumption, and the DAC converts a digital control word into an analog signal to be loaded at an input end of an oscillator, thereby increasing complexity of system design.

In one aspect, an embodiment of the present application provides a digital delay line circuit across multiple octaves, including: the phase-locked loop circuit comprises a control circuit, a delay module, a phase-locked loop circuit and a phase selector circuit, wherein the control circuit is used for selecting a delay path in the delay module according to frequency information of an input clock signal to be delayed; the delay module is used for delaying the clock signal to be delayed based on the selected delay path to generate a plurality of output clock signals with different phases, wherein the plurality of output clock signals with different phases comprise output clock signals delayed by one period; the phase-locked loop circuit is used for carrying out frequency and phase discrimination on the clock signal to be delayed and the output clock signal delayed for one period, converting the frequency and phase discrimination information into a voltage signal and feeding back the voltage signal to a control power supply of the delay module; and the phase selector circuit is used for selecting the plurality of output clock signals with different phases to acquire a target delay clock signal.

The beneficial effects of the technical scheme are as follows: the digital delay line circuit of the embodiment of the application does not need DAC and a plurality of ADPLLs, and reduces the area power consumption and the design complexity. And carrying out frequency discrimination and phase discrimination on an input clock signal to be delayed of the delay module and an output clock signal passing through the whole delay module in a closed loop, converting frequency discrimination and phase discrimination information into a voltage signal, and feeding the voltage signal back to a control power supply of the delay module to form a closed loop so as to obtain accurate relative delay precision.

Based on the further improvement of the device, the control circuit comprises an amplitude-phase control algorithm module and a plurality of combination control logic units, wherein the amplitude-phase control algorithm module is used for detecting the frequency information of an input clock signal to be delayed and converting the frequency information into a corresponding digital control word; and the plurality of combination control logic units are used for converting the digital control word into control enabling signals so as to control the on-off of different delay paths in the delay module.

Based on the further improvement of the device, the delay module comprises a plurality of delay paths, and the frequency information comprises different frequency ranges, wherein the delay paths respectively correspond to delays of clock signals to be delayed in the different frequency ranges, and the clock signals to be delayed are distributed to the corresponding delay paths according to the digital control word so as to carry out time delay.

Based on a further improvement of the above device, the delay module is further configured to operate one of the plurality of delay paths in an operating state.

Based on a further improvement of the above device, the delay path comprises a plurality of delay units connected in series, wherein the delay units are used for carrying out minimum unit time delay on the input clock signal, and clock signals with corresponding phase information are generated after passing through each delay unit.

Based on the further improvement of the device, the phase-locked loop circuit comprises a frequency and phase discrimination module, a charge pump module and a current-voltage conversion module, wherein the frequency and phase discrimination module is used for comparing the frequency and phase of the clock signal to be delayed with the frequency and phase of the delayed output clock signal; the charge pump module is used for converting the compared frequency and phase information into a current signal; and the current-voltage conversion module is used for converting the current signal into a voltage signal and feeding the voltage signal back to the control power supply of the delay unit to form a closed loop.

Based on a further improvement of the above device, the closed loop is configured to adjust the delay amount of the delay module according to the voltage signal fed back to the control power supply of the delay unit, and the higher the control power supply voltage of the delay unit, the lower the delay amount.

Based on a further improvement of the above apparatus, the phase selector circuit includes a plurality of combination selection logic units, wherein the plurality of combination selection logic units are configured to select the plurality of output clock signals having different phases to obtain the target delay clock signals having corresponding phases.

In another aspect, an embodiment of the present application provides a digital delay method across multiple octaves, including: selecting a delay path in the delay module according to the frequency information of the input clock signal to be delayed; delaying the clock signal to be delayed to generate a plurality of output clock signals with different phases; performing frequency and phase discrimination on the clock signal to be delayed and the output clock signal, converting the frequency and phase discrimination information into a voltage signal, and feeding back the voltage signal to a control power supply of the delay module; and selecting the plurality of output clock signals having different phases to obtain a target delayed clock signal.

Based on a further improvement of the above method, selecting the delay path in the delay module according to the frequency information of the input clock signal to be delayed further includes: detecting frequency information of an input clock signal to be delayed, and converting the frequency information into a corresponding digital control word; and converting the digital control word into a control enabling signal to control the on-off of different delay paths in the delay module.

Compared with the prior art, the application has at least one of the following beneficial effects:

1. the digital delay line circuit of the embodiment of the application does not need DAC and a plurality of ADPLLs, and reduces the area power consumption and the design complexity. And carrying out frequency discrimination and phase discrimination on an input clock signal to be delayed of the delay module and an output clock signal passing through the whole delay module in a closed loop, converting frequency discrimination and phase discrimination information into a voltage signal, and feeding the voltage signal back to a control power supply of the delay module to form a closed loop so as to obtain accurate relative delay precision.

2. The digital delay line circuit provided by the embodiment of the application has the advantages of multi-octave frequency range coverage and accurate relative delay precision, and is suitable for phase modulation in a digital radio frequency transmitter;

3. the control circuit converts the frequency information of the clock signal to be delayed into digital control signals to select a delay path in the delay module by detecting the frequency information of the clock signal to be delayed;

4. the phase selector circuit selects a plurality of output clock signals with different phase information generated by the delay module to obtain a target output delay clock signal.

In the application, the technical schemes can be mutually combined to realize more preferable combination schemes. Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the application, like reference numerals being used to refer to like parts throughout the several views.

FIG. 1 is a schematic diagram of a prior art ADPLL-based closed loop phase modulation circuit;

FIG. 2 is a schematic diagram of a digital delay line circuit across multiple octaves according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a closed loop of a delay path according to an embodiment of the present application;

fig. 4 is a schematic time domain diagram of a delay module according to an embodiment of the present application;

FIG. 5 is a diagram of an embodiment of the present application for distributing clock signals to be delayed to corresponding delay paths according to a digital control word;

fig. 6 is a block diagram of a phase selector circuit according to an embodiment of the present application; and

FIG. 7 is a flow chart of a digital delay line circuit across multiple octaves according to an embodiment of the present application.

Detailed Description

The following detailed description of preferred embodiments of the application is made in connection with the accompanying drawings, which form a part hereof, and together with the description of the embodiments of the application, are used to explain the principles of the application and are not intended to limit the scope of the application.

In one embodiment of the application, a digital delay line circuit across multiple octaves is disclosed, comprising: control circuitry 202, delay block 204, phase-locked loop circuitry 206, and phase selector circuitry 208, as shown in fig. 2. The control circuit 202 is configured to select a delay path in the delay module according to the frequency information of the input clock signal to be delayed. The delay module 204 is configured to delay the clock signal to be delayed based on the selected delay path to generate a plurality of output clock signals with different phases, where the plurality of output clock signals with different phases includes an output clock signal delayed by one period. The phase-locked loop circuit 206 is configured to perform frequency and phase discrimination on the clock signal to be delayed and the output clock signal delayed for one period, convert the frequency and phase discrimination information into a voltage signal, and feed back the voltage signal to the control power supply of the delay module. The phase selector circuit 208 is configured to select a plurality of output clock signals having different phases to obtain a target delayed clock signal.

Compared with the prior art, the digital delay line circuit provided by the embodiment does not need a DAC and a plurality of ADPLLs, and reduces the area power consumption and the design complexity. And carrying out frequency discrimination and phase discrimination on an input clock signal to be delayed of the delay module and an output clock signal passing through the whole delay module in a closed loop, converting frequency discrimination and phase discrimination information into a voltage signal, and feeding the voltage signal back to a control power supply of the delay module to form a closed loop so as to obtain accurate relative delay precision.

Referring to fig. 2, a digital delay line circuit across multiple octaves according to an embodiment of the present application will be described in detail below. A digital delay line circuit across multiple octaves comprising: control circuitry 202, delay block 204, phase-locked loop circuitry 206, and phase selector circuitry 208.

The control circuit 202 is configured to select a delay path in the delay module according to the frequency information of the input clock signal to be delayed. The control circuit 202 comprises an amplitude-phase control algorithm module and a plurality of combination control logic units, wherein the amplitude-phase control algorithm module is used for detecting the frequency information of the input clock signal to be delayed and converting the frequency information into corresponding digital control words; and the various combination control logic units are used for converting the digital control words into control enabling signals so as to control the on-off of different delay paths in the delay module.

The delay module 204 is configured to delay the to-be-delayed clock signal based on the selected delay path to generate a plurality of output clock signals with different phases, where, referring to fig. 3, the plurality of output clock signals with different phases include clock signals with delay time MT/N, N is a total number of delay units in the selected delay path, M is a positive integer from 1 to N, where, when M is N, the output clock signal is an output clock signal delayed by one period T. The delay module 204 includes a plurality of delay paths and the frequency information includes different frequency ranges. The delay paths respectively correspond to delays of clock signals to be delayed in different frequency ranges, and the clock signals to be delayed are distributed to the corresponding delay paths according to the digital control word so as to carry out time delay. The delay module 204 is further configured to operate one of the plurality of delay paths in an operational state. Referring to fig. 3, the delay path includes a plurality of delay units 302-1, 302-2, 302-3, …, 302-N connected in series, wherein the delay units are used to delay an input clock signal by a minimum unit of time and generate a clock signal having corresponding phase information after passing through each delay unit. The corresponding time delay T/N is carried out by each time delay unit, and a clock signal delayed by one period T relative to the clock signal to be delayed is generated after the whole delay path is passed. For example, the clock signals output from the plurality of delay units 302-1, 302-2, 302-3, …, 302-N have delay times T/N, 2T/N, 3T/N, …, T, respectively, as compared to the clock signal to be delayed. The total number N of delay cells in the selected delay path is associated with the frequency of the clock signal to be delayed (f=1/T).

The phase-locked loop circuit 206 (or referring to 306 in fig. 3) is configured to perform frequency and phase discrimination on the clock signal to be delayed and the output clock signal delayed for one period, convert the information of frequency and phase discrimination into a voltage signal, and feed back the voltage signal to the control power supply of the delay module. The phase-locked loop circuit 206 includes a frequency and phase discrimination module, a charge pump module, and a current-to-voltage conversion module. Optionally, the phase-locked loop circuit 206 also includes a filter (filter), as shown in fig. 6. The frequency and phase discrimination (phase frequency detector, PDF for short) module is used for comparing the frequency and phase of the clock signal to be delayed with the frequency and phase of the output clock signal delayed for one period T; a Charge Pump (CP) module for converting the compared frequency and phase information into a current signal; and the current-voltage conversion module is used for converting the current signal into a voltage signal and feeding the voltage signal back to the control power supply of the delay units 302-1, 302-2, 302-3, … and 302-N respectively to form a closed loop. Specifically, the closed loop circuit is used for adjusting the delay amount of each delay unit in the delay module according to the voltage signal of the control power supply fed back to each delay unit, and the higher the control power supply voltage of the delay unit is, the lower the delay amount is.

The phase selector circuit 208 is configured to select a plurality of output clock signals having different phases to obtain a target delayed clock signal. The phase selector circuit includes a plurality of combination selection logic units for selecting a plurality of output clock signals having different phases to obtain a target delayed clock signal having a corresponding phase, i.e., selecting one target delayed clock signal having a corresponding phase from the plurality of output clock signals having different phases.

In another embodiment of the application, a digital delay method across multiple octaves is disclosed. Referring to fig. 7, the digital delay method across multiple octaves includes: in step S702, a delay path in the delay module is selected according to the frequency information of the input clock signal to be delayed; in step S704, delaying the clock signal to be delayed to generate a plurality of output clock signals having different phases; in step S706, the clock signal to be delayed and the output clock signal are subjected to frequency and phase discrimination, the information of frequency and phase discrimination is converted into a voltage signal, and the voltage signal is fed back to the control power supply of the delay module; and in step S708, a plurality of output clock signals having different phases are selected to obtain a target delayed clock signal. Specifically, selecting the delay path in the delay module according to the frequency information of the input clock signal to be delayed further includes: detecting frequency information of an input clock signal to be delayed, and converting the frequency information into a corresponding digital control word; and converting the digital control word into a control enabling signal to control the on-off of different delay paths in the delay module.

Hereinafter, a digital delay line circuit crossing multiple octaves according to an embodiment of the present application will be described in detail by way of specific example with reference to fig. 2 to 4.

Referring to fig. 2, the multi-octave-spanning digital delay line (i.e., digital delay path) circuit includes a control circuit 202, a delay module 204, a phase-locked loop circuit 206, and a phase selector circuit 208. The control circuit is used for determining corresponding delay paths in the delay module according to the frequency information of the input clock signal to be delayed and controlling the on and off of different delay paths; the delay module is used for delaying an input clock signal to be delayed and generating a plurality of delay signals with different phase information; the phase-locked loop circuit carries out frequency discrimination and phase discrimination on a clock signal to be delayed and an output clock signal delayed for one period (namely, the output clock signal passing through the whole delay module) which are input by the delay module, converts information of frequency discrimination and phase discrimination into a voltage signal and feeds the voltage signal back to a control power supply of the delay module to form a closed loop so as to obtain accurate relative delay precision; the phase selector circuit selects a plurality of output clock signals with different phase information generated by the delay module to obtain a target output delay clock signal.

The control circuit includes an amplitude phase control algorithm and various combinational logic. The amplitude and phase control algorithm is used for detecting the frequency information of the input clock signal to be delayed and converting the frequency information of the input clock signal to be delayed into corresponding digital control word information. The multiple combination control logic units are used for converting digital control word information into control enabling signals and controlling the on and off of different delay lines.

Specifically, because the input of the delay line circuit is local oscillation signals with different frequencies generated by the external FPGA, and the delay module is composed of a plurality of delay lines, for example, local oscillation signals with input frequencies of 1M to 3M are input, the first delay line works, local oscillation signals with input frequencies of 3M to 5M are input, the second delay line works, and so on. Assuming that the delay module includes eight delay lines, the first delay line is operated when the digital control word is 000, and the eighth delay line is operated when the digital control word is 111. The purpose of this amplitude and phase control algorithm is to generate a digital control word based on the frequency of the incoming local oscillator signal to control which delay line is operated.

The digital control word 000 is generated by the amplitude-phase control algorithm, namely, the digital control word of which the output is 000 in the control module in fig. 2, and the digital control word 000 is connected with the digital control word of which the output is 111 generated by the inverter in the case of eight delay lines, the first delay line normally works by generating high-level enabling signals for the first delay line through the AND gate, the digital control word 000 is connected with the digital control word of which the output is 110 generated by the inverter through the first and second digital control words, the second delay line is enabled by generating low-level enabling signals for the second delay line through the AND gate, the second delay line is disabled by generating 101 digital control word through the first and third digital control words, the third delay line is disabled by generating low-level enabling signals for the third delay line through the AND gate, and so on.

The digital control word 001 is generated by the amplitude-phase control algorithm assuming that the input local oscillation signal is 3M to 5M, namely, the output of the control module in fig. 2 is a digital control word of 001, and the digital control word 001 is connected with the digital control word of the inverter to generate 110 by the assumption of eight delay lines, the first delay line is abnormally operated by generating a low-level enabling signal by the AND gate, the digital control word 001 is connected with the digital control word of the inverter to generate 111 by the first and the second digital control words, the second delay line is normally operated by generating a high-level enabling signal by the AND gate, the second delay line is normally operated by the digital control word 001 by connecting the first and the third digital control words with the inverter to generate 100, the third delay line is abnormally operated by generating a low-level enabling signal by the AND gate, and so on.

The delay module includes a plurality of delay paths. The delay paths respectively correspond to the delays of the input clock signals to be delayed in different frequency ranges, and the input clock signals to be delayed are distributed to the corresponding delay paths for time delay according to the digital control word information. The delay period of each delay path is different according to the different frequency of the input signal. Specifically, the difference in frequency of the input signals causes the period of the input signals to be different, the period of the input signals corresponding to the delay period of each delay path is different, and the number of delay units in each delay path is also different.

Different digital control words are generated according to different input signal frequencies. These digital control words will be changed to high level through the enable signals of the corresponding delay paths (also called delay lines) and the other delay lines will not work through AND gates to generate low level enable signals. Referring to fig. 5, when the digital control word is a three-bit digital control word, the three-bit digital control word generates an enable signal EN <0> of the first delay path, enable signals EN <1>, … of the second delay path, and enable signal EN <7> of the eighth delay path through an inverter and an and gate combination.

For example, the inverter converts the CHIPEN <0:2> to the inverted signal CHIPENB <0:2>. For example, when the three-bit digital control word is 000, the three-bit digital control word 000 is converted to 111 by three inverters, respectively, and then an enable signal EN <0> =1 of the first delay path is generated by an and gate, specifically, CHIPEN <2> =0 is converted to CHIPENB <2> =1 by the first inverter; the CHIPEN <1> =0 is converted to CHIPENB <1> =1 by a second inverter; and converting CHIPEN <0> =0 to CHIPENB <0> =1 by a third inverter, and then generating an enable signal EN <0> =1 of the first delay path by the converted 111 through an and gate. Further, when the three-bit digital control word is 000, the three-bit digital control word 000 is converted into 110 by two inverters, respectively, and then an enable signal EN <1> =0 of the second delay path is generated by the and gate; converting the three-bit digital control word 000 into 101 through two inverters, and then generating an enable signal EN <2> =0 of a third delay path through an AND gate; converting the three-bit digital control word 000 into 100 through an inverter, and then generating an enable signal EN <3> =0 of a fourth delay path through an and gate; converting the three-bit digital control word 000 into 011 through two inverters, and then generating an enable signal EN <4> =0 of a fifth delay path through an AND gate; converting the three-bit digital control word 000 into 010 by an inverter, and then generating an enable signal EN <5> =0 of a sixth delay path by an and gate; converting the three-bit digital control word 000 to 001 through an inverter, and then generating an enable signal EN <6> =0 of a seventh delay path through an and gate; and generating an enable signal EN <7> =0 of the eighth delay path by the and gate.

Referring to fig. 3, the closed loop of the delay path includes a plurality of delay units, the clock signal to be delayed is time-delayed by the delay units, frequency discrimination and phase discrimination are performed on the clock signal to be delayed and the clock signal delayed for one period, and frequency and phase information of the clock signal to be delayed and the clock signal are converted into voltage signals by the phase-locked loop and fed back to the control power supply of the delay units to form a closed loop, so that accurate relative delay precision is provided. The closed loop circuit is particularly used for generating error voltage according to the deviation between an input clock signal to be delayed and a clock signal delayed for one period, and feeding the error voltage back to a control power supply of the delay module to change the delay amount of the delay module, so that the relative delay precision of the delay module is ensured.

For example, assuming that there are 128 Delay units (7 bits), in fig. 3, the output of each Delay module is a Delay signal of different phase information, and the output of each Delay unit needs to be led out, so there are 128 outputs, the 128 outputs select a target Delay signal through a phase selector, a signal without Delay and a Delay signal with Delay of 128 Delay units are connected to a phase frequency discriminator, in fig. 3, besides the Delay signal input through the whole Delay module is input to a PLL, and another input signal is a local oscillation signal generated without Delay external connection to an FPGA.

Referring to fig. 4, each time a delay unit passes, a corresponding time delay is performed, and a clock signal delayed by one period with respect to the clock signal to be delayed is generated after passing through the whole delay path.

The delay module is provided with a plurality of delay paths, each delay path has different delay time resolutions, and according to different frequencies of input clock signals, clock signals to be delayed are distributed to corresponding delay paths by the control circuit to carry out delay, and the whole delay module only has one delay path to operate in a working state. Although the frequencies of the input clock signals are different, the relative consistency of the input clock signals of the delay module and the clock signals passing through the whole delay path can be ensured under the action of the closed loop.

Because the delay module comprises a plurality of delay paths, each delay path can obtain accurate relative delay precision in a certain frequency range, and the whole delay module can realize time delay across multiple octaves. The control of the phase-locked loop output voltage to the delay module power supply voltage ensures the delay amount of each delay path. The phase-locked loop circuit comprises a frequency discrimination phase discrimination module, a charge pump module and a current-voltage conversion module; the frequency and phase discrimination module is used for comparing the clock signal to be delayed with the frequency and phase information of the clock signal delayed for one period; the charge pump module is used for converting the frequency and phase information compared by the frequency and phase discrimination module into a current signal; the current-voltage conversion module is used for converting a current signal output by the charge pump module into a voltage signal, and feeding the voltage signal back to the control power supply of the delay module to form a closed loop.

Phase locked loop circuits are a basic widely used circuit configuration, and are briefly described below. The frequency and phase discriminator performs frequency discrimination and phase discrimination on the local oscillation signal generated by the external FPGA without delay and the delay signal passing through the whole delay module, when the PLL (Phase Locked Loop, namely the phase-locked loop) is locked, two input signals are in the same frequency and phase (namely the local oscillation signal passing through the whole delay module is generated by delaying one period of the local oscillation signal generated by the external FPGA), if the two input signals are in different frequency and phase, the charge pump module is controlled to charge and discharge the current and voltage conversion module (the current and voltage conversion module can be a filter), and if the local oscillation signal passing through the whole delay module exceeds the delay amount of one period, the frequency and phase discriminator detects the difference, so that the charge pump charges the current and voltage conversion module, the output voltage signal is increased, and the higher the power voltage of the delay unit is, the lower the delay amount is, until the signal delay amount passing through the whole delay module is reduced to be just one period of the input local oscillation signal, and the closed loop feedback is formed, so that the relative delay precision is ensured.

The phase selector circuit includes a variety of combinational logic; the combination logic is used for selecting clock signals with different phase information generated by the delay module to obtain a target delay clock signal with corresponding phase information to be obtained.

When the delay path shown in fig. 5 is one-eighth, i.e., the delay path is eight chains in parallel, the phase selector circuit shown in fig. 6 is one-128 (or 2 ⁿ One choice) phase selection is 128 phases (7 bits) in parallel. Assuming a total of 128 phases (7 bits), the phase selector is one from the 128 phasesA target phase delay is selected. The delay whole chain is one period, and the principle of selection is to select the output signal according to the target phase. Referring to fig. 6, buffer is a buffer, enable is a control circuit of a delay path, mux is a phase selector, and the phase selector is a multi-phase selector (mux) module. Assuming 128 phases, 7bit control words are used to control the output, 0000000 outputs the first and 1111111 outputs 128 th. Assuming 256 phases, the output is controlled with an 8bit control word, SEL <0> =1, SEL <1 when the digital control word is 00000000: 255 > =0, i.e. only the first phase output signal can pass, and none of the other phase signals can pass.

For example, the phase selector selects and outputs 128 output delay signals, and selects which output is determined by a 7bit digital control word, for example 0000000 outputs a local oscillation signal passing through one delay unit, and 1111111 outputs a local oscillation signal passing through 128 delay units. When the digital control word is 0000000, seven digital control words are changed into 1111111 through an inverter, and high level is generated through an AND gate to be output enabled through a delay unit; the first six digital control words are changed into 1111110 through an inverter, and the low level is generated through an AND gate to be output and enabled through two delay units; the first five and seventh digital control words become 1111101 through an inverter, and are enabled by the output of the three delay units when low is generated by an AND gate; and so on. So when the digital control word is 0000000, only the local oscillation signal passing through one delay unit is normally output; when the digital control word is 0000001, only local oscillation signals passing through the two delay units are normally output; when the digital control word is 1111111, only local oscillation signals passing through 128 delay units are normally output.

In summary, the embodiment of the application provides a digital delay line circuit crossing multiple octaves, which has the following beneficial effects: (1) The embodiment of the application realizes a digital delay line circuit crossing multiple octaves through the control circuit, the closed-loop structure and the phase selector circuit, has the advantages of covering the frequency range of the multiple octaves and having accurate relative delay precision, and is suitable for phase modulation in a digital radio frequency transmitter; (2) The control circuit converts the frequency information of the clock signal to be delayed into digital control signals by detecting the frequency information of the clock signal to be delayed, and selects a delay path in the delay module; (3) In the closed loop, the input clock signal to be delayed of the delay module and the output clock signal passing through the whole delay module are subjected to frequency discrimination and phase discrimination, and the frequency discrimination and phase discrimination information is converted into a voltage signal and fed back to a control power supply of the delay module to form a closed loop so as to obtain accurate relative delay precision; (4) The phase selector circuit selects a plurality of output clock signals with different phase information generated by the delay module to obtain a target output delay clock signal.

Those skilled in the art will appreciate that all or part of the flow of the methods of the embodiments described above may be accomplished by way of a computer program to instruct associated hardware, where the program may be stored on a computer readable storage medium. Wherein the computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory, etc.

The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application.

Claims (10)

1. A digital delay line circuit across multiple octaves, comprising: a control circuit, a delay module, a phase-locked loop circuit and a phase selector circuit, wherein,

the control circuit is used for selecting a delay path in the delay module according to the frequency information of the input clock signal to be delayed;

the delay module is used for delaying the clock signal to be delayed based on the selected delay path to generate a plurality of output clock signals with different phases, wherein the plurality of output clock signals with different phases comprise output clock signals delayed by one period;

the phase-locked loop circuit is used for carrying out frequency and phase discrimination on the clock signal to be delayed and the output clock signal delayed for one period, converting the frequency and phase discrimination information into a voltage signal and feeding back the voltage signal to a control power supply of the delay module; and

the phase selector circuit is used for selecting the plurality of output clock signals with different phases to acquire a target delay clock signal.

2. The multi-octave-spanning digital delay line circuit of claim 1, wherein the control circuit comprises an amplitude and phase control algorithm module and a plurality of combination control logic units, wherein,

the amplitude and phase control algorithm module is used for detecting the frequency information of the input clock signal to be delayed and converting the frequency information into a corresponding digital control word; and

the combination control logic units are used for converting the digital control words into control enabling signals so as to control the on-off of different delay paths in the delay module.

3. The multi-octave digital delay line circuit of claim 2, wherein the delay module comprises a plurality of delay paths and the frequency information comprises different frequency ranges, wherein,

the delay paths respectively correspond to the delays of the clock signals to be delayed in different frequency ranges, and the clock signals to be delayed are distributed to the corresponding delay paths according to the digital control word so as to carry out time delay.

4. A digital delay line across multiple octaves as recited in claim 3, wherein said delay module is further configured to operate one of said plurality of delay paths in an operational state.

5. The multi-octave-spanning digital delay line circuit of claim 3 or 4, wherein the delay path comprises a plurality of delay cells connected in series, wherein,

the delay units are used for carrying out minimum unit time delay on the input clock signals and generating clock signals with corresponding phase information after passing through each delay unit.

6. The multi-octave-crossing digital delay line circuit of claim 5, wherein the phase-locked loop circuit comprises a frequency and phase discrimination module, a charge pump module, and a current-to-voltage conversion module, wherein,

the frequency and phase discrimination module is used for comparing the frequency and phase of the clock signal to be delayed with the frequency and phase of the delayed output clock signal;

the charge pump module is used for converting the compared frequency and phase information into a current signal; and

the current-voltage conversion module is used for converting the current signal into a voltage signal and feeding the voltage signal back to the control power supply of the delay unit to form a closed loop.

7. The digital delay line across multiple octaves of claim 6, wherein the closed loop is configured to adjust the amount of delay of the delay module based on a voltage signal fed back to the control power supply of the delay unit, and wherein the higher the control power supply voltage of the delay unit, the lower the amount of delay.

8. The multi-octave-spanning digital delay line circuit of claim 1, wherein the phase selector circuit comprises a plurality of combinational selection logic cells, wherein,

the multiple combination selection logic units are used for selecting the multiple output clock signals with different phases to obtain target delay clock signals with corresponding phases.

9. A digital delay method across multiple octaves, comprising:

selecting a delay path in the delay module according to the frequency information of the input clock signal to be delayed;

delaying the clock signal to be delayed based on the selected delay path to generate a plurality of output clock signals with different phases, wherein the plurality of output clock signals with different phases comprise an output clock signal delayed by one period;

performing frequency and phase discrimination on the clock signal to be delayed and the output clock signal delayed for one period, converting the frequency and phase discrimination information into a voltage signal, and feeding back the voltage signal to a control power supply of the delay module; and

the plurality of output clock signals having different phases are selected to obtain a target delayed clock signal.

10. The multi-octave-spanning digital delay method of claim 9, wherein selecting a delay path in the delay module according to frequency information of an input clock signal to be delayed further comprises:

detecting frequency information of an input clock signal to be delayed, and converting the frequency information into a corresponding digital control word; and

and converting the digital control word into a control enabling signal to control the on-off of different delay paths in the delay module.