CN116707471A

CN116707471A - Filter, preparation method thereof and electronic equipment

Info

Publication number: CN116707471A
Application number: CN202310609706.7A
Authority: CN
Inventors: 冯昱霖; 李月; 冯春楠; 李慧颖; 曹雪; 杨硕
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Beijing BOE Sensor Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Beijing BOE Sensor Technology Co Ltd
Priority date: 2023-05-26
Filing date: 2023-05-26
Publication date: 2023-09-05

Abstract

The disclosure provides a filter, a preparation method thereof and electronic equipment, and belongs to the technical field of electronics. Wherein the filter comprises at least one capacitor; the capacitor comprises a dielectric substrate, a first polar plate arranged on the dielectric substrate, a dielectric layer covering one side of the first polar plate away from the dielectric substrate, and a second polar plate covering one side of the dielectric layer away from the first polar plate; the thickness of the first polar plate is not larger than that of the second polar plate, and orthographic projection parts of the first polar plate and the second polar plate on a plane perpendicular to the dielectric substrate are overlapped.

Description

Filter, preparation method thereof and electronic equipment

Technical Field

The disclosure belongs to the technical field of electronics, and in particular relates to a filter, a preparation method thereof and electronic equipment.

Background

Along with the rapid progress of electronic circuit integration technology, the size of electronic devices is continuously reduced along with the improvement of technology, so that the miniaturization and rapid development of integrated circuits are promoted, the traditional macroscopic centimeter-scale is continuously evolved, the common size in the electronic equipment is reduced to millimeter and micrometer level at present, and even the prior process enters nanometer scale. Miniaturization technology of electronic devices is widely popularized in daily life, and people cannot leave portable electronic equipment with rich functions, such as mobile phones, earphones and the like. Therefore, the development of integration is a necessary trend of electronic technology.

Common integrated electronic devices are mainly passive devices, such as capacitors, inductors, resistors, etc., which are distributed throughout various types of electronic equipment, so development of integrated passive device (Integrated Passive Devices, IPD) technology is of great importance. The IPD currently forms a plurality of different process routes according to different substrate materials, and common processes include silicon-based semiconductor technology, low-temperature co-fired ceramic technology, glass-based technology and the like. Different substrate materials have great influence on subsequent process routes, but the fine preparation of each layer of process structure is a core technology because the size is basically in the micron level. However, as the size continues to shrink, more precise equipment and more excellent materials are needed to precisely control the various structures. And the uniformity, the accuracy and the like of the device can be greatly improved by the more optimized equipment.

The capacitor is widely applied to various high-frequency circuits due to the characteristic of passing high frequency and low frequency. The traditional capacitor basic structure is mainly a plate capacitor structure, namely, a capacitor with an MIM (metal-insulating layer-metal) structure is formed by two parallel metal electrodes and an intermediate insulating medium layer, and the size of the capacitor is mainly determined by factors such as the overlapping area of the metal electrodes, the metal flatness, the medium material characteristics and the like. The capacitor structure is simpler, but only the uniformity and accuracy of the integrated capacitor can be effectively ensured by finely manufacturing each layer of material.

Disclosure of Invention

The disclosure aims to at least solve one of the technical problems in the prior art, and provides a filter, a preparation method thereof and electronic equipment.

In a first aspect, a solution adopted to solve the technical problem of the present disclosure is a filter, which includes at least one capacitor; the capacitor comprises a dielectric substrate, a first polar plate arranged on the dielectric substrate, a dielectric layer covering one side of the first polar plate, which is far away from the dielectric substrate, and a second polar plate covering one side of the dielectric layer, which is far away from the first polar plate; the thickness of the first polar plate is not larger than that of the second polar plate, and orthographic projection portions of the first polar plate and the second polar plate on a plane perpendicular to the dielectric substrate are overlapped.

In some embodiments, the ratio of the thickness of the first plate to the thickness of the second plate is between 1:1 and 1:30.

In some embodiments, the filter further comprises a first interlayer insulating layer disposed on the dielectric substrate; the first interlayer insulating layer has a receiving portion in which at least a second plate of the capacitor is defined.

In some embodiments, the filter further comprises at least one inductor disposed on the dielectric substrate;

The inductor comprises a first conductive structure and a lead-out structure;

the first polar plate and the first conductive structure are arranged on the same layer, and the second polar plate and the extraction structure are arranged on the same layer.

In some embodiments, the filter further comprises a first interlayer insulating layer disposed on the dielectric substrate; the first interlayer insulating layer is provided with a containing part, and at least a second polar plate of the capacitor and a lead-out structure of the inductor are limited in the containing part;

the extraction structure is electrically connected with the first conductive structure through a first connection via hole; the first connection via penetrates the dielectric layer.

In some embodiments, a first protective layer is disposed on a side of the extraction structure facing away from the dielectric substrate; the first connecting pad is electrically connected with the extraction structure through the second connecting via hole; the second connection via penetrates through the first protection layer; the second connecting pad is electrically connected with the second electrode plate through a third connecting via hole; the third connection via penetrates through the first protection layer.

In some embodiments, the filter further comprises at least one inductor integrated on the dielectric substrate; the dielectric substrate comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the dielectric substrate;

The inductor comprises a second conductive structure, a lead-out structure and a third conductive structure, wherein the second conductive structure and the lead-out structure are sequentially arranged along the direction of the second surface away from the first surface, the third conductive structure is arranged on the first surface, and the second conductive structure, the lead-out structure and the third conductive structure are electrically connected to form a coil structure of the inductor;

the first polar plate and the second conductive structure are arranged on the same layer, and the second polar plate and the extraction structure are arranged on the same layer.

the extraction structure is electrically connected with the second conductive structure through a first connection via hole; the first connection via penetrates the dielectric layer.

In some embodiments, the dielectric substrate has a fourth connection via penetrating in a thickness direction thereof; the inductor further comprises a first connecting electrode arranged in the fourth connecting via hole, and the second conductive structure and the lead-out structure form a coil structure of the inductor through the first connecting electrode and the third conductive structure.

In some embodiments, a first protective layer is disposed on a side of the extraction structure facing away from the dielectric substrate; the third connecting pad is electrically connected with the extraction structure through a fifth connecting via hole; the fifth connection via penetrates through the first protection layer; the fourth connecting pad is electrically connected with the second electrode plate through a sixth connecting via hole; the sixth connection via penetrates through the first protection layer.

In some embodiments, a second protective layer is disposed on a side of the third conductive structure facing away from the dielectric substrate.

In a second aspect, an embodiment of the present disclosure further provides a method for preparing a filter, including: forming at least one capacitor on a dielectric substrate; the step of forming the capacitor includes:

providing a dielectric substrate, wherein the dielectric substrate comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the dielectric substrate;

forming a first polar plate on the second surface of the dielectric substrate;

forming a dielectric layer on one side of the first polar plate, which is away from the dielectric substrate, wherein the dielectric layer covers the first polar plate;

forming a second polar plate on one side of the dielectric layer away from the dielectric substrate; the thickness of the first polar plate is not larger than that of the second polar plate, and orthographic projection parts of the first polar plate and the second polar plate on a plane perpendicular to the dielectric substrate are overlapped;

A first interlayer insulating layer is formed on the second surface of the dielectric substrate, the first interlayer insulating layer having a receiving portion in which at least the second plate of the capacitor is defined.

In some embodiments, the method for manufacturing a filter further includes: forming at least one inductor on a dielectric substrate; the step of forming the inductor comprises:

forming a first conductive structure synchronously when forming a first polar plate on the second surface of the dielectric substrate;

forming a second polar plate on one side of the dielectric layer, which is away from the dielectric substrate, and synchronously forming a lead-out structure; at least a second plate of the capacitor and an extraction structure of the inductor are defined within the receptacle.

forming a second conductive structure synchronously when forming a first polar plate on the second surface of the dielectric substrate;

In some embodiments, before forming the first electrode plate on the second surface of the dielectric substrate, the method further includes:

forming a fourth connection via hole penetrating through the dielectric substrate along the thickness direction of the dielectric substrate;

forming a first connection electrode at the fourth connection via hole;

and forming a third conductive structure on the first surface of the dielectric substrate.

In a third aspect, embodiments of the present disclosure further provide an electronic device comprising a filter as in any one of the above embodiments.

Drawings

FIG. 1 is a schematic diagram of an exemplary filter;

fig. 2 is a schematic structural diagram of a filter provided in an embodiment of the disclosure;

FIG. 3 is a schematic diagram of another filter provided in an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another filter provided in an embodiment of the present disclosure;

FIGS. 5 a-5 g are process flow diagrams for preparing a 2D IPD filter according to embodiments of the present disclosure;

fig. 6a to 6k are process flow diagrams for preparing a 3D IPD filter according to an embodiment of the present disclosure.

Wherein the reference numerals are as follows: wherein the reference numerals are as follows: 1. a dielectric substrate; s1, a first surface; s2, a second surface; 21. a first plate; 22. a second polar plate; 23. a dielectric layer; 3. a first interlayer insulating layer; 41. a first conductive structure; 42. a lead-out structure; 51. a first protective layer; 43. a second conductive structure; 44. a third conductive structure; 45. a first connection electrode; 52. a second protective layer; p1, a first connection pad; p2, a second connection pad; p3, a third connection pad; and P4, a fourth connection pad.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. The components of the embodiments of the present disclosure, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the disclosure, as claimed, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of this disclosure without making any inventive effort, are intended to be within the scope of this disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

Reference in the present disclosure to "a plurality of" or "a number" means two or more than two. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

In the flat capacitor structure, the two metal electrode structures are overlapped and the part with the medium layer in the middle can form a capacitor, so that the smaller part of the metal electrode in the two metal electrode structures determines the area size of the capacitor.

In the conventional plate capacitor structure, the metal electrode closer to the dielectric substrate 1 has a larger planar area, the metal electrode farther from the dielectric substrate 1 has a smaller planar area, and an insulating dielectric layer is arranged between the two metal electrodes, wherein the metal electrode farther from the dielectric substrate 1 determines the capacitor area. Fig. 1 is a schematic structural view of an exemplary filter, and as shown in fig. 1, the filter includes a dielectric substrate 1, and a first electrode plate 21, a first interlayer insulating layer 3, a dielectric layer 23, a second electrode plate 22, a second interlayer insulating layer, and a connection structure formed on the dielectric substrate 1; wherein the first plate 21, the dielectric layer 23 and the second plate 22 form a capacitive structure.

With continued reference to fig. 1, the capacitor is a MIM structure, and is fabricated using thick film technology, and is formed of two layers of metal whose surfaces can be electroless plated, and an insulating material between the two layers of metal, which forms a capacitor. Specifically, MIM structure capacitors are typically composed of three layers: an upper metal layer, a middle insulating layer and a lower metal layer. The upper metal layer and the lower metal layer are respectively connected with the external electrode, and current is conducted through the upper metal layer and the lower metal layer; the middle insulating layer separates the upper and lower metal layers, i.e., separates their potentials, thereby creating a capacitive circuit. The first polar plate 21 of the capacitor is a lower metal layer, the second polar plate 22 is an upper metal layer, the capacitor further comprises a middle insulating layer positioned between the first polar plate 21 and the second polar plate 22, and the capacitor is connected with the outside through a connecting structure.

With continued reference to fig. 1, in this capacitor, the planar area of the second electrode plate 22 is smaller than the planar area of the first electrode plate 21, and thus the capacitor area (the overlapping area of the two metal electrodes) is mainly determined by the second electrode plate 22. Meanwhile, the capacitor second plate 22 needs to be interconnected with other structures through a connection structure, so that the overall structure is more complex.

The inventor finds that in order to ensure the accurate control of the whole capacitor, the thickness of the metal electrode which is far away from the dielectric substrate 1 is required to be smaller, but the thickness of the metal electrode is smaller, so that the electric charge transmission is not facilitated, the whole capacitor can generate larger impedance, and the thickness is more than a plurality of times lower than an ideal value, so that the performance of the device is not facilitated to be improved; the metal electrode which is closer to the dielectric substrate 1 is not only used for the capacitor electrode but also used for the line routing in the integral structure, so that the thickness is required to be larger, but the larger the thickness of the metal electrode which is closer to the dielectric substrate 1 is, the lower the integral flatness of the structure is, the flatness of the capacitor dielectric layer is difficult to ensure, and the uniformity of the capacitor is easy to influence; in the process, when the metal electrode far away from the dielectric substrate 1 is etched, certain etching conditions are generated on the unprotected metal electrode near to the dielectric substrate 1, so that the flatness of the metal surface is affected; because the thickness of the metal electrode far away from the dielectric substrate 1 is smaller, the metal electrode cannot be independently used as a metal wire, and the metal wire with larger thickness is further manufactured above the metal wire for structural interconnection, so that the whole process flow is more, wafer warpage is serious, and the process difficulty is higher.

In view of the above, the present disclosure provides a filter that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. Specifically, the capacitor in the filter according to the embodiment of the disclosure fully exerts the characteristic of high flatness of the dielectric substrate 1, reduces the area of the metal electrode close to the dielectric substrate 1 through structural design, and improves the uniformity and capacitance of the capacitor.

In a first aspect, a solution to the technical problem of the present disclosure is a filter, which includes at least one capacitor. Next, a specific description will be given of a capacitor in a filter according to an embodiment of the present disclosure, and fig. 2 is a schematic structural diagram of a filter provided in an embodiment of the present disclosure, where, as shown in fig. 2, the capacitor in the filter includes a dielectric substrate 1, a first electrode plate 21 disposed on the dielectric substrate 1, a dielectric layer 23 covering a side of the first electrode plate 21 facing away from the dielectric substrate 1, and a second electrode plate 22 covering a side of the dielectric layer 23 facing away from the first electrode plate 21; the thickness of the first polar plate 21 is not greater than that of the second polar plate 22, and orthographic projection portions of the first polar plate 21 and the second polar plate 22 on a plane perpendicular to the dielectric substrate 1 are overlapped.

Specifically, in the embodiment of the disclosure, the thickness of the first polar plate 21 of the capacitor is not greater than that of the second polar plate 22, and the orthographic projection portions of the first polar plate 21 and the second polar plate 22 on the plane perpendicular to the dielectric substrate 1 are overlapped, so that the capacitor density is increased while the uniformity of the capacitor is improved. Because the surface flatness of the dielectric substrate 1 is high, the first polar plate 21 with smaller area and smaller thickness is directly manufactured on the dielectric substrate 1, so that the flatness of the first polar plate 21 can be effectively ensured; the first polar plate 21 is directly manufactured on the medium substrate 1, so that the manufacturing precision can be effectively monitored, the manufacturing can be performed again if the deviation is large, and the loss is small; the metal electrode (i.e., the second electrode plate 22) farther from the dielectric substrate 1 can be made to a large thickness, and the requirement for uniformity of the upper surface thereof is not high, and no other processing steps are required.

It should be noted that the drawings in the embodiments of the present disclosure are only schematic, so that the present invention may be more easily understood, and specific specifications and parameters thereof may be designed and adjusted according to specific product requirements.

With continued reference to fig. 2, the filter includes a dielectric substrate 1, a first plate 21, a dielectric layer 23, a second plate 22, and a first interlayer insulating layer 3. Wherein the first plate 21, the dielectric layer 23 and the second plate 22 form a capacitive structure. The planar area of the first plate 21 is smaller than the planar area of the second plate 22, and therefore the capacitance area (the overlapping area of the two metal electrodes) is mainly determined by the first plate 21. With continued reference to fig. 1, the filter includes a dielectric substrate 1, a first plate 21, a dielectric layer 23, a first interlayer insulating layer 3, a second plate 22, a second interlayer insulating layer, and a connection structure; wherein the first plate 21, the dielectric layer 23 and the second plate 22 form a capacitive structure. The planar area of the second plate 22 is smaller than the planar area of the first plate 21, and therefore, the capacitance area (the overlapping area of the two metal electrodes) is mainly determined by the second plate 22.

With continued reference to fig. 2 and 1, the capacitors in the filter of the disclosed embodiments are structurally different and the principle of action is different compared to the capacitors in the prior art filters. As shown in fig. 2, the first electrode plate 21 and the second electrode plate 22 form a capacitance C1 in the vertical direction. The plane capacitance calculating method comprises the following steps:

Wherein ε ₀ Is vacuum dielectric constant; epsilon _s A relative dielectric constant of the dielectric layer 23; s is S _j Is the overlapping area of the first pole plate 21 and the second pole plate 22 in the vertical direction; t (T) _s Is the thickness of the dielectric layer 23.

Similar to the capacitance C1 formed by the first plate 21 and the second plate 22 in the vertical direction, the capacitance C2 in the horizontal direction is formed between the first plate 21 and the second plate 22 because the second plate 22 covers the first plate 21 and the orthographic projection portions of the first plate 21 and the second plate 22 on the plane perpendicular to the dielectric substrate 1 overlap, and the calculation formula of the capacitance C2 in the horizontal direction is similar to the capacitance C1 in the vertical direction, depending on the overlapping area and the dielectric layer material. The capacitors in the filter in the embodiment of the disclosure have a certain overlapping area in the horizontal direction and the vertical direction due to the first polar plate 21 and the second polar plate 22, so that the effective value of the capacitors is increased, and the capacitors are effective capacitors, so that the performance is not affected by other additional capacitors.

As shown in fig. 1, the capacitance in the prior art filter also includes a capacitance C1 formed by the first plate 21 and the second plate 22 in the vertical direction; however, since the planar area of the second plate 22 is smaller in the capacitor structure, the first plate 21 and the connection structure form an additional capacitor C3 in the vertical direction, and the capacitor C3 in the vertical direction is not an effective capacitor, which has a negative effect on the overall electrical performance of the capacitor, so that the electrical performance of the capacitor in the filter in the prior art is affected by the capacitor in application and is deviated.

Therefore, in the capacitance of the filter in the embodiment of the disclosure, the dielectric layer 23 is disposed to cover the first electrode plate 21, the second electrode plate 22 is disposed to cover the dielectric layer 23, and the orthographic projection portions of the first electrode plate 21 and the second electrode plate 22 on the plane perpendicular to the dielectric substrate 1 are overlapped, so that the original parasitic capacitance can be converted into the effective capacitance. In addition, in the embodiment of the disclosure, the thickness of the first polar plate 21 is not greater than that of the second polar plate 22, and the second polar plate 22 can be used as a part of the self structure of the capacitor and also as a connecting structure connected with the outside, so that the whole structure of the capacitor is simplified, the preparation process of the capacitor is reduced, and the production cost is reduced.

In some embodiments, the ratio of the thickness of the first plate 21 to the thickness of the second plate 22 is 1:1 to 1:30. Preferably, the ratio of the thicknesses of the first electrode plate 21 and the second electrode plate 22 is 1:15. By the arrangement, the overall flatness of the formed capacitor structure can be higher.

In some embodiments, as shown in fig. 2, the filter further includes a first interlayer insulating layer 3 disposed on the dielectric substrate 1; the first interlayer insulating layer 3 has a receiving portion in which at least the second plate 22 of the capacitor is defined.

Specifically, the second electrode plate 22 of the capacitor is limited in the accommodating portion of the first interlayer insulating layer 3, and meanwhile the first electrode plate 21 of the capacitor is limited in the accommodating portion of the first interlayer insulating layer 3, so that the first electrode plate 21 and the second electrode plate 22 of the capacitor can be ensured to be limited in the accommodating portion of the first interlayer insulating layer 3, and the capacitor has better electrical performance.

It should be noted that LC-type Two-Dimensional (2D) or three-Dimensional (Three Dimensional, 3D) integrated passive device (Integrated Passive Devices, IPD) filters generally involve stacking and lapping of multiple layers of metals, and the lapping condition of each layer of metal directly determines the performance and reliability of the device, so that the greater the number of metal layers, the greater the process difficulty and the greater the risk of failure. The capacitor upper electrode structures of the IPD device are now all 2-layer metal stacks, and the present disclosure will be described in detail with respect to a 2D IPD filter and a 3D IPD filter, respectively. It should be noted that, in the present disclosure, 2D and 3D refer to an inductance structure, and the capacitance in the filter is a 2D structure.

In some embodiments, fig. 3 is a schematic structural diagram of another filter provided in an embodiment of the disclosure, and as shown in fig. 3, the filter is a 2D IPD filter. The filter comprises not only at least one capacitor as in the above embodiments, but also at least one inductor arranged on the dielectric substrate 1. The inductor comprises a first conductive structure 41 and a lead-out structure 42; the first electrode plate 21 is arranged in the same layer as the first conductive structure 41, and the second electrode plate 22 is arranged in the same layer as the extraction structure 42.

The first polar plate 21 of the capacitor and the first conductive structure 41 of the inductor in the filter in the embodiment of the disclosure are arranged in the same layer, and the second polar plate 22 of the capacitor and the lead-out structure 42 of the inductor are arranged in the same layer, so that the production cost can be reduced, and the productivity can be improved.

In some embodiments, as shown in fig. 3, the filter further includes a first interlayer insulating layer 3 disposed on the dielectric substrate 1; the first interlayer insulating layer 3 has a receiving portion in which at least the second plate 22 of the capacitor and the lead-out structure 42 of the inductor are defined; the extraction structure 42 is electrically connected with the first conductive structure 41 through the first connection via; the first connection via penetrates the dielectric layer 23.

Specifically, the lead-out structure 42 of the inductor in the embodiment of the present disclosure is electrically connected to the first conductive structure 41 through the first connection via penetrating through the dielectric layer 23, so as to form a planar spiral inductor. In the embodiment of the disclosure, at least the second pole plate 22 of the capacitor and the lead-out structure 42 of the inductor are defined in the accommodating portion, the second pole plate 22 of the capacitor and the lead-out structure 42 of the inductor are defined in the accommodating portion of the first interlayer insulating layer 3, and meanwhile, the first pole plate 21 of the capacitor and the first conductive structure 41 of the inductor are defined in the accommodating portion of the first interlayer insulating layer 3, so that the arrangement can ensure that the first pole plate 21 and the second pole plate 22 of the capacitor, and the first conductive structure 41 of the inductor and the lead-out structure 42 are defined in the accommodating portion of the first interlayer insulating layer 3, so that the filter has better electrical performance as a whole.

In some embodiments, as shown in fig. 3, a first protective layer 51 is provided on the side of the lead-out structure 42 facing away from the dielectric substrate 1; the first connection pad P1 is electrically connected to the lead-out structure 42 through the second connection via; the second connection via penetrates the first protection layer 51; the second connection pad P2 is electrically connected to the second electrode plate 22 through the third connection via; the third connection via penetrates the first protection layer 51.

In some embodiments, fig. 4 is a schematic structural diagram of another filter provided in an embodiment of the disclosure, and as shown in fig. 4, the filter is a 3D IPD filter. The filter comprises not only at least one capacitor as in the above embodiments, but also at least one inductor integrated on the dielectric substrate 1; the dielectric substrate 1 includes a first surface S1 and a second surface S2 disposed opposite to each other in a thickness direction thereof; the inductor comprises a second conductive structure 43 and a lead-out structure 42 which are sequentially arranged along the second surface S2 in a direction away from the first surface S1, and a third conductive structure 44 which is arranged on the first surface S1, wherein the second conductive structure 43, the lead-out structure 42 and the third conductive structure 44 are electrically connected to form a coil structure of the inductor; the first electrode plate 21 and the second conductive structure 43 are arranged in the same layer, and the second electrode plate 22 and the extraction structure 42 are arranged in the same layer.

The first polar plate 21 of the capacitor and the second conductive structure 43 of the inductor in the filter in the embodiment of the disclosure are arranged in the same layer, and the second polar plate 22 of the capacitor and the lead-out structure 42 of the inductor are arranged in the same layer, so that the production cost can be reduced, and the productivity can be improved.

In some embodiments, as shown in fig. 4, the filter further includes a first interlayer insulating layer 3 disposed on the dielectric substrate 1; the first interlayer insulating layer 3 has a receiving portion in which at least the second plate 22 of the capacitor and the lead-out structure 42 of the inductor are defined; the extraction structure 42 is electrically connected with the second conductive structure 43 through the first connection via; the first connection via penetrates the dielectric layer 23.

Specifically, the lead-out structure 42 of the inductor in the embodiment of the present disclosure is electrically connected to the second conductive structure 43 through the first connection via penetrating through the dielectric layer 23, so as to form a 3D stereoscopic inductor. In the embodiment of the disclosure, at least the second pole plate 22 of the capacitor and the lead-out structure 42 of the inductor are defined in the accommodating portion, the second pole plate 22 of the capacitor and the lead-out structure 42 of the inductor are defined in the accommodating portion of the first interlayer insulating layer 3, and meanwhile, the first pole plate 21 of the capacitor and the second conductive structure 43 of the inductor are defined in the accommodating portion of the first interlayer insulating layer 3, so that the arrangement can ensure that the first pole plate 21 of the capacitor and the second pole plate 22, and the second conductive structure 43 of the inductor and the lead-out structure 42 are defined in the accommodating portion of the first interlayer insulating layer 3, so that the filter has better electrical performance as a whole.

In some embodiments, as shown in fig. 4, the dielectric substrate 1 has a fourth connection via penetrating in its thickness direction; the inductor further comprises a first connection electrode 45 arranged in the fourth connection via, and the second conductive structure 43 and the lead-out structure 42 form a coil structure of the inductor with the third conductive structure 44 through the first connection electrode 45.

In some embodiments, as shown in fig. 4, a first protective layer 51 is provided on the side of the lead-out structure 42 facing away from the dielectric substrate 1; the third connection pad P3 is electrically connected to the lead-out structure 42 through a fifth connection via; the fifth connection via penetrates the first protection layer 51; the fourth connection pad P4 is electrically connected to the second electrode plate 22 through a sixth connection via; the sixth connection via penetrates the first protection layer 51.

In some embodiments, as shown in fig. 4, a second protective layer 52 is provided on a side of the third conductive structure 44 facing away from the dielectric substrate 1.

In a second aspect, an embodiment of the disclosure further provides a method for manufacturing the filter. Hereinafter, a method for manufacturing the 2D IPD filter shown in fig. 3 and the 3D IPD filter shown in fig. 4 will be described in detail, respectively.

Fig. 5a to 5g are process flow diagrams for preparing a 2D IPD filter according to an embodiment of the present disclosure, where, as shown in fig. 5a to 5g, when preparing the 2D IPD filter shown in fig. 3, the preparation method may include steps S11 to S17, specifically as follows:

S11, providing a dielectric substrate 1.

Specifically, as shown in fig. 5a, the dielectric substrate 1 includes a first surface S1 and a second surface S2 that are disposed opposite to each other in the thickness direction thereof. The dielectric substrate 1 includes, but is not limited to, silicon-based, ceramic, glass, and the like.

The dielectric substrate 1 needs to be sufficiently cleaned before use. For example, the medium substrate 1 may be sequentially cleaned by a solvent such as a cleaning agent, ethanol, isopropanol, etc., and the medium substrate 1 may be ultrasonically cleaned for not less than 10 minutes each time.

Further, the thickness of the dielectric substrate 1 may be 0.2 to 1mm as required.

S12, a first electrode plate 21 of a capacitor and a first conductive structure 41 of an inductor are formed on the second surface S2 of the dielectric substrate 1.

Specifically, as shown in fig. 5b, the first plate 21 of the capacitor and the first conductive structure 41 of the inductor are formed on the second surface S2 of the dielectric substrate 1.

When the first electrode plate 21 of the capacitor and the first conductive structure 41 of the inductor are formed on the second surface S2 of the dielectric substrate 1, a high-precision patterned metal including the first electrode plate 21 and the first conductive structure 41 may be formed on the second surface S2 of the dielectric substrate 1 by spin coating, exposure, development, sputtering, electroplating, and other processes, and the thickness of the metal may be 0.05-5 um as required.

It should be noted that, since the layer where the first plate 21 of the capacitor and the first conductive structure 41 of the inductor are located is very critical in the whole device, the requirement on the flatness is high. After the plating is completed, the redundant electroplated copper on the second surface S2 is removed by Chemical Mechanical Polishing (CMP) or grinding.

And S13, forming a dielectric layer 23.

Specifically, as shown in fig. 5c, a dielectric layer 23 is formed on a side of the first electrode plate 21 and the first conductive structure 41 facing away from the dielectric substrate 1, and the dielectric layer 23 covers the first electrode plate 21 and the first conductive structure 41. Here, the dielectric layer 23, that is, the dielectric layer between the first plate 21 and the second plate 22 of the capacitor. By the coverage of the dielectric layer 23 at the first plate 21 of the capacitor in the disclosed embodiments, short circuits can be prevented.

Further, the dielectric layer 23 may be formed by depositing a dense dielectric material by sputtering or Plasma Enhanced Chemical Vapor Deposition (PECVD) or the like. The material of the dielectric layer 23 may be a common dielectric material such as silicon oxide or silicon nitride (SiNx), and the thickness of the dielectric layer 23 may be 0.05um to 0.5um as required.

Further, when preparing the dielectric layer 23, a SiNx film with high flatness of 100nm to 120nm can be deposited by adopting standard processes such as PECVD to form the dielectric layer 23, so as to ensure the uniformity of the capacitor.

S14, forming the first interlayer insulating layer 3.

Specifically, as shown in fig. 5d, a first interlayer insulating layer 3 is formed on the second surface S2 of the dielectric substrate 1, the first interlayer insulating layer 3 is located on a side of the dielectric layer 23 facing away from the dielectric substrate 1, the first interlayer insulating layer 3 has a receiving portion, and at least the second electrode plate 22 of the capacitor is defined in the receiving portion.

Further, the thickness of the first interlayer insulating layer 3 may be 3 μm to 5 μm as required.

Wherein, the first interlayer insulating layer 3 is deposited on the second pole plate 22 of the capacitor and the first conductive structure 41 of the inductor at the side facing away from the dielectric substrate 1 by adopting standard processes such as PECVD. The material of the first interlayer insulating layer 3 may be an organic material such as PI (polyimide) resin or the like.

And forming a patterned retaining wall structure by spin coating, exposure and development, and being used for metal patterning preparation.

S15, forming a second pole plate 22 of the capacitor and an extraction structure 42 of the inductor.

Specifically, as shown in fig. 5e, on the side of the dielectric layer 23 facing away from the dielectric substrate 1, the second plate 22 of the capacitor and the lead-out structure 42 of the inductor are formed by sputtering, electroplating, etching, and the like, thereby forming a filter structure.

Further, a first connection via is formed through the dielectric layer 23 by dry etching, so that the lead-out structure 42 is electrically connected to the first conductive structure 41 through the first connection via.

Wherein the thickness of the first polar plate 21 is not greater than that of the second polar plate 22, and the orthographic projection parts of the first polar plate 21 and the second polar plate 22 on the plane vertical to the dielectric substrate 1 are overlapped; at least the second plate 22 of the capacitor and the lead-out structure 42 of the inductor are defined in the housing.

Further, the side of the first interlayer insulating layer 3 facing away from the dielectric substrate 1 is formed into a conductive film including the second electrode plate 22 of the capacitor and the lead-out structure 42 of the inductor by using a magnetron sputtering method, the conductive film is used as a seed layer, thick copper is electroplated on the conductive film, and patterning treatment is performed on the electroplated conductive film to form the second electrode plate 22 of the capacitor and the lead-out structure 42 of the inductor.

The conductive film may be copper (Cu), so that the thicknesses of the layers of the second plate 22 of the capacitor and the lead-out structure 42 of the inductor formed finally are generally above 5 μm, so that the second plate 22 of the capacitor and the lead-out structure 42 of the inductor are arranged in the same layer, and the layers are formed by the same manufacturing process, thereby reducing the number of metal layers.

S16, forming a first protective layer 51.

Specifically, as shown in fig. 5f, a first protection layer 51 is formed on the second pole plate 22 of the capacitor and the side of the lead-out structure 42 of the inductor facing away from the dielectric substrate 1.

Wherein, at the side of the second pole plate 22 of the capacitor and the lead-out structure 42 of the inductor, which is far away from the dielectric substrate 1, a standard process such as PECVD is adopted to deposit and form a first protection layer 51, and then a photolithography process is used to expose, develop and bake the first protection layer 51, so as to form a second connection via hole and a third connection via hole which penetrate through the first protection layer 51.

The first protection layer 51 is used for preventing the device formed on the second surface S2 of the dielectric substrate 1 from being corroded by water and oxygen, and meanwhile, the first protection layer 51 is convenient for patterning and exposing the device after the subsequent device is completed, so as to expose the I/O port of the device. The thickness of the first protective layer 51 may be 5um to 10um as needed, and the material of the first protective layer 51 may be a photosensitive organic material, polyimide, or the like. The first protective layer 51 integrally covers the second electrode plate 22 of the capacitor and the lead-out structure 42 of the inductor, and by forming the first protective layer 51, the entire structure of the filter can be protected within the first protective layer 51.

S17, implanting the first connection pad P1 and the second connection pad P2.

Specifically, as shown in fig. 5g, the first connection pad P1 is electrically connected to the lead-out structure 42 of the inductor through a second connection via penetrating the first protection layer 51; the second connection pad P2 is electrically connected to the second plate 22 of the capacitor through a third connection via penetrating the first protection layer 51.

The first connection pad P1 and the second connection pad P2 may be solder balls, and the solder balls are transplanted at the via hole on the side of the first protection layer 51 facing away from the dielectric substrate 1, so as to form a complete device package structure.

With continued reference to fig. 5g, the finally formed 2D IPD filter comprises a dielectric substrate 1, a first plate 21 and a first conductive structure 41 arranged in a same layer, a dielectric layer 23, a second plate 22 and a lead-out structure 42 arranged in a same layer, a first interlayer insulating layer 3, a first protective layer 51 and solder balls. Wherein the first plate 21, the dielectric layer 23 and the second plate 22 form a capacitive structure, and the first conductive structure 41 and the extraction structure 42 form a planar spiral inductor.

In some embodiments, fig. 6a to 6k are process flow diagrams for preparing a 3D IPD filter according to an embodiment of the present disclosure, as shown in fig. 6a to 6k, when preparing the 3D IPD filter shown in fig. 4, the preparation method may include steps S21 to S211, which are specifically as follows:

s21, providing a dielectric substrate 1.

Specifically, as shown in fig. 6a, the dielectric substrate 1 includes a first surface S1 and a second surface S2 that are disposed opposite to each other in the thickness direction thereof. The dielectric substrate 1 includes, but is not limited to, silicon-based, ceramic, glass, and the like.

S22, a fourth connection via penetrating the dielectric substrate 1 in the thickness direction of the dielectric substrate 1 is formed.

Specifically, as shown in fig. 6b, the dielectric substrate 1 may be fabricated with a fourth connection via by using various methods. For example: sand blasting, photosensitive glass, focused discharge, plasma etching, laser ablation, electrochemical, laser induced etching, etc. Different methods have different advantages and disadvantages and application ranges. For example, the sand blasting method has the advantages of simple process, larger aperture of the fourth connecting via hole manufactured by the method, and being only applicable to manufacturing the fourth connecting via hole with the aperture larger than 200 mu m. The photosensitive glass method has the advantages of simple process and capability of manufacturing the fourth connecting via hole with high density and high depth-to-width ratio. The focusing discharge method has the advantage of high pore-forming speed. And the roughness of the side wall of the fourth connecting via hole prepared by the plasma etching method is small. The laser ablation method has the advantages that the fourth connecting via hole with high density and high depth-to-width ratio can be manufactured, but the roughness of the inner wall of the cylindrical hole is larger due to the thermal effect of laser, which can affect the deposition of a film layer in the hole and the combination with the hole wall, and is unfavorable for forming a high-density adhesive layer (Ti, ta, W, tiN, taN) and a seed layer Cu. The electrochemical method has the advantages of low cost, simple equipment, high pore forming rate and larger diameter of the fourth connecting via hole. The laser-induced etching method has the advantages of high pore forming rate, high density, high depth-to-width ratio fourth connecting via hole, no damage in the via hole and expensive laser equipment.

It should be noted that, currently, three-dimensional integration of digital circuits (such as dynamic random access memory (Dynamic Random Access Memory, DRAM), logic chip, etc.) generally adopts silicon substrate and through silicon via technology (Through Silicon Via, TSV). In recent years, as the demands of people for communication capacity and speed are continuously increased, communication frequencies are continuously increased. For high frequency applications, the materials used for the interposer or substrate must have low dielectric loss and low dielectric constant to reduce the radio frequency power dissipation of the substrate and increase the self-resonant frequency. Because silicon is a semiconductor material, carriers around TSVs can freely move under the action of an electric field or a magnetic field, influence on adjacent circuits or signals is generated, and the high-frequency performance of the chip is reduced. The glass has no free moving charges, adjustable thermal expansion coefficient and excellent dielectric property. The high frequency loss problem of TSVs can be effectively avoided by replacing the silicon substrate with a glass substrate and replacing the TSVs with glass via technology (Through Glass Via, TGV). In addition, due to the semiconductor characteristic of silicon, the TSV also needs to be manufactured with an electric isolation layer, a diffusion barrier layer, a seed layer and copper filling without gaps in the through hole, so that the process is complex, the parasitic capacitance is obvious, and the performance requirement of the three-dimensional integrated radio frequency micro system is often difficult to meet. The TGV technology can omit the manufacture of a copper filled barrier layer and an oxide covering film layer, reduce the capacitance of a via hole between a copper plating layer and a substrate, reduce electromagnetic interference between an active circuit and a passive circuit of the via hole, greatly reduce the process complexity and the processing cost, and has simpler thinning and polishing processes of glass compared with silicon. Thus, glass is a suitable material for the radio frequency domain, while TGV is also an ideal three-dimensional integration solution.

Therefore, in describing the 3D IPD filter in the embodiments of the present disclosure, a glass-based is mainly used as an example for detailed description, and in the embodiments of the present disclosure, TGV via hole fabrication is performed by using a laser induced etching method, where the diameter of the via hole may range from 50um to 80 um. Specifically, when the back through hole is formed by using a laser-induced etching method, the molecular bond at the position where the fourth connecting through hole needs to be formed is subjected to laser-induced modification by using laser, then etching is performed by using etching liquid, and the etching rate of the glass subjected to laser modification is increased to form the through hole. The inner wall of the through hole obtained by using the laser induced etching method is smooth, which is favorable for the combination of the adhesion layer and the seed layer with the side wall of the through hole and enhances the reliability. Because the rear through hole can only be manufactured by adopting a single-sided etching method, the obtained hole can only be an inverted conical hole, and for the punching method of laser-induced etching, the inverted conical hole with single-sided etching is a typical characteristic of the rear through hole at the back of the fourth connecting through hole.

Further, the adopted process technology is different, and the cross-sectional shapes of the fourth connecting via holes are also different. For example, the hole cross-sectional shape of the fourth connection via may be a cylinder, an hourglass type, or the like. And (3) carrying out metallization filling in the through hole, and completing the metallization filling in the through hole by sputtering and electroplating to ensure the effective filling of the metal in the through hole, so that the method can be used for connecting upper and lower conductive structures of the inductor.

S23, a first connection electrode 45 is formed in the fourth connection via.

Specifically, as shown in fig. 6c, the first connection electrode 45 is formed in the fourth connection via, i.e., the fourth connection via is metallized to realize the conduction between the third conductive structure 44 and the second conductive structure 43 of the inductor.

S24, forming the third conductive structure 44 of the inductor.

Specifically, as shown in fig. 6d, the third conductive structure 44 of the inductor is formed on the first surface S1 of the dielectric substrate 1. High-precision patterned metal is formed on the first surface S1 of the dielectric substrate 1 through spin coating, exposure, development, sputtering, electroplating and other processes, and the thickness of the metal can be 0.5-5 um according to requirements.

Further, since the third conductive structure 44 is a part of the 3D inductor structure and also functions as a connection to the fourth connection via, a subtractive method may be used. Wherein a Cu seed layer is sputtered, then the entire thick Cu is electroplated, and then patterned to form the third conductive structure 44.

S25, forming a second protective layer 52.

Specifically, as shown in fig. 6e, a spin coating method may be used to form the second protection layer 52 on the side of the third conductive structure 44 facing away from the dielectric substrate 1. The material of the second protection layer 52 may be an organic material, such as Polyimide (PI) resin, photoresist, etc., and the second protection layer 52 is formed by spin coating, exposure, and development to protect the third conductive structure 44 formed on the first surface S1 of the dielectric substrate 1. The material of the second protective layer 52 may also be an inorganic material, such as silicon oxide, and the like, prepared by sputtering, PECVD, and the like.

S26, a first electrode plate 21 of a capacitor and a second conductive structure 43 of an inductor are formed on the second surface S2 of the dielectric substrate 1.

Specifically, as shown in fig. 6f, the first plate 21 of the capacitor and the second conductive structure 43 of the inductor are formed on the second surface S2 of the dielectric substrate 1.

When the first electrode plate 21 of the capacitor and the second conductive structure 43 of the inductor are formed on the second surface S2 of the dielectric substrate 1, a high-precision patterned metal including the first electrode plate 21 and the second conductive structure 43 may be formed on the second surface S2 of the dielectric substrate 1 by spin coating, exposure, development, sputtering, electroplating, etc., and the thickness of the metal may be 0.05-0.5 um as required.

It should be noted that, since the layer where the first plate 21 of the capacitor and the second conductive structure 43 of the inductor are located is very critical in the whole device, the requirement on the flatness is high. After the plating is completed, the redundant electroplated copper on the second surface S2 is removed by Chemical Mechanical Polishing (CMP) or grinding.

And S27, forming a dielectric layer 23.

Specifically, as shown in fig. 6g, a dielectric layer 23 is formed on a side of the first electrode plate 21 and the second conductive structure 43 facing away from the dielectric substrate 1, and the dielectric layer 23 covers the first electrode plate 21 and the second conductive structure 43. Here, the dielectric layer 23, that is, the dielectric layer between the first plate 21 and the second plate 22 of the capacitor. By the coverage of the dielectric layer 23 at the first plate 21 of the capacitor in the disclosed embodiments, short circuits can be prevented.

Further, the dielectric layer 23 may be formed by depositing a dense dielectric material by sputtering or Plasma Enhanced Chemical Vapor Deposition (PECVD) or the like. The material of the dielectric layer 23 may be a common dielectric material such as silicon oxide or silicon nitride (SiNx), and the thickness of the dielectric layer 23 may be 0.05-0.5 um as required.

Wherein the dielectric layer 23 is patterned, and the excess SiNx is removed by dry etching to form the dielectric layer portion of the final capacitor.

S28, forming the first interlayer insulating layer 3.

Specifically, as shown in fig. 6h, a first interlayer insulating layer 3 is formed on the second surface S2 of the dielectric substrate 1, the first interlayer insulating layer 3 is located on a side of the dielectric layer 23 facing away from the dielectric substrate 1, the first interlayer insulating layer 3 has a receiving portion, and at least the second electrode plate 22 of the capacitor is defined in the receiving portion.

Wherein, the first interlayer insulating layer 3 is deposited on the second pole plate 22 of the capacitor and the second conductive structure 43 of the inductor on the side facing away from the dielectric substrate 1 by adopting standard processes such as PECVD. The material of the first interlayer insulating layer 3 may be an organic material such as PI (polyimide) resin or the like.

Further, a silicon nitride (SiNx) film layer is spin-coated on the whole surface of the capacitor dielectric layer 23 on the side facing away from the dielectric substrate 1, and then the SiNx film layer is exposed and developed, so as to finally form the first interlayer insulating layer 3. The material of the first interlayer insulating layer 3 may be an inorganic insulating material. For example: an inorganic insulating layer formed of silicon nitride (SiNx), or silicon dioxide (SiO ₂ ) An inorganic insulating layer formed of SiNx inorganic insulating layer and SiO ₂ Several laminated composite film layers of inorganic insulating layers.

S29, a second plate 22 of the capacitor and an extraction structure 42 of the inductor are formed.

Specifically, as shown in fig. 6i, on a side of the dielectric layer 23 facing away from the dielectric substrate 1, a second plate 22 of the capacitor and an inductor lead-out structure 42 are formed by sputtering, electroplating, etching, or the like, thereby forming a filter structure.

Further, a first connection via is formed through the dielectric layer 23 by dry etching, such that the extraction structure 42 is electrically connected with the second conductive structure 43 through the first connection via.

S210, forming the first protective layer 51.

Specifically, as shown in fig. 6j, a first protection layer 51 is formed on the side of the second pole plate 22 of the capacitor and the lead-out structure 42 of the inductor facing away from the dielectric substrate 1.

Wherein, a first protection layer 51 is deposited on the side of the second pole plate 22 of the capacitor and the lead-out structure 42 of the inductor, which is far away from the dielectric substrate 1, by adopting standard processes such as PECVD, and then is exposed, developed and post-baked by using a photolithography process to form a fifth connection via hole and a sixth connection via hole penetrating through the first protection layer 51.

S211, implanting the third connection pad P3 and the fourth connection pad P4.

Specifically, as shown in fig. 6k, the third connection pad P3 is electrically connected to the lead-out structure 42 of the inductor through a fifth connection via penetrating the first protection layer 51; the fourth connection pad P4 is electrically connected to the second plate 22 of the capacitor through a sixth connection via penetrating the first protection layer 51.

The third connection pad P3 and the fourth connection pad P4 may be solder balls, and the solder balls are transplanted at the via hole on the side of the first protection layer 51 facing away from the dielectric substrate 1, so as to form a complete device package structure.

With continued reference to fig. 6k, the finally formed 3D IPD filter includes the second protective layer 52, the third conductive structure 44, the first connection electrode 45, the dielectric substrate 1, the first and second electrode plates 21 and 43 arranged in a same layer, the dielectric layer 23, the second electrode plate 22 arranged in a same layer, and the lead-out structure 42, the first interlayer insulating layer 3, the first protective layer 51, and the solder balls. The first electrode plate 21, the dielectric layer 23 and the second electrode plate 22 form a capacitor structure, and the extraction structure 42, the second conductive structure 43, the first connection electrode 45 and the third conductive structure 44 form a 3D stereoscopic inductor.

In a third aspect, the disclosed embodiments also provide an electronic device comprising the filter of any of the above embodiments.

It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

Claims

1. A filter comprising at least one capacitor; the capacitor comprises a dielectric substrate, a first polar plate arranged on the dielectric substrate, a dielectric layer covering one side of the first polar plate, which is far away from the dielectric substrate, and a second polar plate covering one side of the dielectric layer, which is far away from the first polar plate; the thickness of the first polar plate is not larger than that of the second polar plate, and orthographic projection portions of the first polar plate and the second polar plate on a plane perpendicular to the dielectric substrate are overlapped.

2. The filter of claim 1, wherein a ratio of a thickness of the first plate to a thickness of the second plate is between 1:1 and 1:30.

3. The filter of claim 1, further comprising a first interlayer insulating layer disposed on the dielectric substrate; the first interlayer insulating layer has a receiving portion in which at least a second plate of the capacitor is defined.

4. The filter of claim 1 or 2, further comprising at least one inductor disposed on the dielectric substrate;

the inductor comprises a first conductive structure and a lead-out structure;

5. The filter of claim 4, further comprising a first interlayer insulating layer disposed on the dielectric substrate; the first interlayer insulating layer is provided with a containing part, and at least a second polar plate of the capacitor and a lead-out structure of the inductor are limited in the containing part;

6. The filter of claim 5, wherein a first protective layer is disposed on a side of the extraction structure facing away from the dielectric substrate; the first connecting pad is electrically connected with the extraction structure through the second connecting via hole; the second connection via penetrates through the first protection layer; the second connecting pad is electrically connected with the second electrode plate through a third connecting via hole; the third connection via penetrates through the first protection layer.

7. The filter of claim 1 or 2, further comprising at least one inductor integrated on the dielectric substrate; the dielectric substrate comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the dielectric substrate;

8. The filter of claim 7, further comprising a first interlayer insulating layer disposed on the dielectric substrate; the first interlayer insulating layer is provided with a containing part, and at least a second polar plate of the capacitor and a lead-out structure of the inductor are limited in the containing part;

9. The filter of claim 8, wherein the dielectric substrate has a fourth connection via extending therethrough in a thickness direction thereof; the inductor further comprises a first connecting electrode arranged in the fourth connecting via hole, and the second conductive structure and the lead-out structure form a coil structure of the inductor through the first connecting electrode and the third conductive structure.

10. The filter of claim 9, wherein a first protective layer is disposed on a side of the extraction structure facing away from the dielectric substrate; the third connecting pad is electrically connected with the extraction structure through a fifth connecting via hole; the fifth connection via penetrates through the first protection layer; the fourth connecting pad is electrically connected with the second electrode plate through a sixth connecting via hole; the sixth connection via penetrates through the first protection layer.

11. The filter of claim 10, wherein a second protective layer is disposed on a side of the third conductive structure facing away from the dielectric substrate.

12. A method of manufacturing a filter, comprising: forming at least one capacitor on a dielectric substrate; the step of forming the capacitor includes:

forming a first polar plate on the second surface of the dielectric substrate;

13. The method of manufacturing a filter according to claim 12, further comprising: forming at least one inductor on a dielectric substrate; the step of forming the inductor comprises:

14. The method of manufacturing a filter according to claim 12, further comprising: forming at least one inductor on a dielectric substrate; the step of forming the inductor comprises:

15. The method of manufacturing a filter according to claim 14, further comprising, before forming the second conductive structure simultaneously when the first electrode plate is formed on the second surface of the dielectric substrate:

forming a first connection electrode at the fourth connection via hole;

16. An electronic device comprising the filter of any one of claims 1-11.