CN116705733A - Three-dimensional integrated device and method of forming the same - Google Patents

Three-dimensional integrated device and method of forming the same Download PDF

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Publication number
CN116705733A
CN116705733A CN202310910112.XA CN202310910112A CN116705733A CN 116705733 A CN116705733 A CN 116705733A CN 202310910112 A CN202310910112 A CN 202310910112A CN 116705733 A CN116705733 A CN 116705733A
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China
Prior art keywords
hole
groove
stack
integrated device
dimensional integrated
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薛晓晨
盛备备
叶国梁
胡胜
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Priority to CN202310910112.XA priority Critical patent/CN116705733A/en
Publication of CN116705733A publication Critical patent/CN116705733A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention relates to a three-dimensional integrated device and a forming method thereof. The three-dimensional integrated device comprises a stacked body formed by stacking at least two layers of chips and a carrier sheet bonded on the first surface of the stacked body, wherein a heat conducting groove is formed on the first surface of the stacked body, the carrier sheet is provided with a first through hole and a second through hole, the first through hole and the second through hole expose the first end and the second end of the heat conducting groove in the length direction respectively, the first through hole is an inlet of heat dissipation liquid, and the second through hole is an outlet of heat dissipation liquid. The three-dimensional integrated device can utilize the flow of the heat dissipation liquid in the heat conduction groove to take away heat for heat dissipation, achieves the purpose of cooling the device, is higher in heat conduction efficiency and strong in heat dissipation capacity, can reduce the risk of heat accumulation in the three-dimensional integrated device, and is beneficial to improving the performance of the three-dimensional integrated device.

Description

Three-dimensional integrated device and method of forming the same
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a three-dimensional integrated device and a method for forming the same.
Background
With the increasing demand for large data processing capability of integrated circuits, moore's law approaches a limit, device size shrinking becomes more and more difficult, and three-dimensional integration technology becomes an effective scheme for continuously improving PPAC (performance, area, cost) in the latter moore age.
For three-dimensional integrated devices, as the number of layers stacked inside increases, the heat generated during operation increases dramatically. If heat cannot be conducted out in time, heat accumulation can seriously affect the operation performance of the device.
In the prior art, when manufacturing a three-dimensional integrated device, a plurality of chips are stacked and the formed stacked structure is bonded to a circuit substrate, then a heat conducting layer is manufactured on the surface of the stacked structure far away from one side of the circuit substrate, and a heat dissipation metal sheet is covered on the heat conducting layer. The metal radiating fins exchange heat with air, so that natural heat radiation can be realized, and forced air cooling can be realized in an air flow accelerating mode, but no matter the natural heat radiation or the forced air cooling is realized, the heat radiation capability is limited due to lower heat conduction efficiency, the heat accumulation in the three-dimensional integrated device can still be caused, and the normal operation of the three-dimensional integrated device is unfavorable.
Disclosure of Invention
In order to improve the heat dissipation capacity of a three-dimensional integrated device, the invention provides a three-dimensional integrated device and a method for forming the three-dimensional integrated device.
In one aspect, the invention provides a three-dimensional integrated device comprising a stack body formed by stacking at least two layers of chips and a carrier, wherein the stack body is provided with a first surface and a second surface which are opposite, the first surface is provided with a heat conduction groove, and the length direction of the heat conduction groove is parallel to the first surface; the slide is bonded to the first surface of the stacked body, the slide is provided with a first through hole and a second through hole, the first through hole exposes out of a first end of the heat conducting groove in the length direction, the second through hole exposes out of a second end of the heat conducting groove in the length direction, the first through hole is an inlet of heat dissipation liquid, and the second through hole is an outlet of heat dissipation liquid.
Optionally, an opening of the first through hole at an end facing away from the stack is not higher than the slide surface around the first through hole; an opening of the second through hole at an end facing away from the stack is not higher than the slide surface around the second through hole.
Optionally, the second surface is formed with solder bumps that are connected to circuitry inside the stack.
Optionally, the three-dimensional integrated device further comprises a circuit substrate having pads, wherein the stack is bonded to the circuit substrate by soldering the solder bumps with the respective pads.
Optionally, the stacked body includes a first chip layer, where the first chip layer includes a first substrate and an electronic component formed on a front surface of the first substrate, and the heat conduction groove is formed on a back surface of the first substrate opposite to the front surface.
Optionally, the electronic component comprises a logic device and/or a memory device.
Optionally, one or more channel paths are provided between the first and second ends of the thermally conductive channel.
Optionally, each layer of chips in the stack comprises one or more chips.
In one aspect, the present invention provides a method for forming a three-dimensional integrated device, the method comprising:
stacking at least two layers of chips to form a stack body, wherein the stack body is provided with a first surface and a second surface which are opposite;
forming a heat conducting groove on the first surface, wherein the length direction of the heat conducting groove is parallel to the first surface, and the heat conducting groove is provided with a first end and a second end in the length direction;
forming a first groove and a second groove on the surface of a slide;
bonding the stack to the carrier, wherein the first groove is opposite a first end of the thermally conductive trench and the second groove is opposite a second end of the thermally conductive trench;
removing bottoms of the first groove and the second groove, enabling the first groove to form a first through hole, enabling the second groove to form a second through hole, enabling the first through hole to expose the first end of the heat conducting groove, enabling the second through hole to expose the second end of the heat conducting groove, wherein the first through hole is an inlet of heat dissipation liquid, and the second through hole is an outlet of heat dissipation liquid.
Optionally, the bottoms of the one groove and the second groove are removed by thinning or etching the slide.
Optionally, before removing the bottoms of the first groove and the second groove, the forming method further includes: forming solder bumps on the second surface, the solder bumps being connected to circuitry inside the stack; and bonding the stack to a circuit substrate having pads, wherein the solder bumps are soldered to the respective pads.
The three-dimensional integrated device comprises a stacked body formed by stacking at least two layers of chips and a carrier sheet bonded on the first surface of the stacked body, wherein a heat conducting groove is formed on the first surface of the stacked body, the carrier sheet is provided with a first through hole and a second through hole, the first through hole is exposed out of a first end of the heat conducting groove in the length direction, the second through hole is exposed out of a second end of the heat conducting groove in the length direction, the first through hole is an inlet of heat dissipation liquid, and the second through hole is an outlet of heat dissipation liquid. Compared with the heat dissipation mode of the attached metal radiating fins adopted in the prior art, the three-dimensional integrated device can utilize the flowing of the heat dissipation liquid in the heat conduction grooves to take away heat for heat dissipation, the purpose of cooling the device is achieved, the heat conduction efficiency is higher, the heat dissipation capacity is strong, the risk of heat accumulation in the three-dimensional integrated device can be reduced, and the performance of the three-dimensional integrated device is improved.
The method for forming the three-dimensional integrated device provided by the invention and the three-dimensional integrated device provided by the invention belong to the same conception, and have the same or similar advantages.
Drawings
Fig. 1 is a flow chart of a method of forming a three-dimensional integrated device according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a stack in a method of forming a three-dimensional integrated device according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a three-dimensional integrated device after forming a heat conducting trench on a first surface of a stack according to an embodiment of the present invention.
Fig. 4 is a simulated plan view of a thermally conductive trench formed in a first surface of a stack in a method of forming a three-dimensional integrated device according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a three-dimensional integrated device according to an embodiment of the present invention after forming a first recess and a second recess on a surface of a carrier.
Fig. 6 is a simulated plan view of a second recess and a second recess formed in a surface of a carrier sheet in a method of forming a three-dimensional integrated device according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of a three-dimensional integrated device formed by bonding a stack to a carrier sheet according to an embodiment of the present invention.
Fig. 8 is a simulated cross-sectional view of a bonded stack and carrier and thermally conductive trench in a method of forming a three-dimensional integrated device according to an embodiment of the invention.
Fig. 9 is a schematic cross-sectional view of a three-dimensional integrated device after forming solder bumps on a second surface of a stack according to an embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of a three-dimensional integrated device formed by bonding a stack to a circuit substrate according to an embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view of a three-dimensional integrated device according to an embodiment of the present invention after removing bottoms of the first recess and the second recess.
Fig. 12 is a schematic cross-sectional view of a three-dimensional integrated device according to an embodiment of the present invention.
Detailed Description
The three-dimensional integrated device and the method of forming the same of the present invention are described in further detail below with reference to the accompanying drawings and specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be understood that the drawings in the specification are in a very simplified form and are all to a non-precise scale, simply to facilitate a clear and thorough description of the embodiments of the invention. It should be noted that the order of steps in the methods presented herein is not necessarily the only order in which the steps are performed, some of the described steps may be omitted and/or some other steps not described herein may be added to the method. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "above … …" may also include "below … …" and other orientations.
The method of forming the three-dimensional integrated device of the present invention will be described first by way of examples.
Referring to fig. 1 and 2, in an embodiment of the present invention, step S1 includes: at least two layers of chips are stacked to form a stack 100, the stack 100 having a first surface 100a and a second surface 100b opposite to each other.
The method for forming a three-dimensional integrated device according to the embodiment of the present invention may utilize a three-dimensional integration technique to stack at least two layers of chips to form the stack 100. In the three-dimensional integration technology, a plurality of active devices, passive devices, MEMS devices or discrete chips (such as optoelectronic chips, biochips, memory chips, logic chips, computing chips) having different functions or manufactured by different processes are assembled together in three dimensions (such as X-direction, Y-direction, Z-direction of an orthogonal coordinate system) and form a complete circuit system. Each layer of chips may be formed separately by a separate wafer level process. At least two layers of chips may be stacked by wafer-level, chip-level, or chip-to-wafer processes to form the stack 100. In the stack 100, each layer of chips (or chip layers) is, for example, a wafer, or each layer of chips (or chip layers) is a chip (or die). The number of stacked chip layers in the stack 100 may be different depending on the design, or at least one chip layer is a wafer and at least one chip layer is a chip.
Each layer of chips in the stack 100 may include a semiconductor substrate, an electronic component formed based on the semiconductor substrate fabrication, an interconnect layer, a dielectric layer, and the like. For stacking at least two chips, the chip layers may be stacked together by adhesion or bonding (e.g., hybrid bonding), for example, adhesion or bonding in such a way that the semiconductor substrates face each other, or adhesion or bonding in such a way that the semiconductor substrates face away (as shown in fig. 2), or adhesion or bonding of the semiconductor substrate of one chip layer to the dielectric layer of another chip layer.
Illustratively, as shown in fig. 2, a logic wafer W1 and a storage wafer W2 are stacked to form a stack 100, via step S1. The logic wafer W1 includes, for example, a first substrate 101 and a logic device formed on a surface of the first substrate 101, where a surface on which the logic device is formed is referred to as a front surface of the first substrate 101, and a surface opposite to the front surface is a back surface of the first substrate 101, and the logic wafer W1 may further include a first interconnect structure 102 formed on a front side of the first substrate 101. The memory wafer W2 includes, for example, a second substrate 103 and a memory device (such as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), etc.) formed on a surface of the second substrate 103, where a surface on which the memory device is formed is referred to as a front surface of the second substrate 103, and a surface opposite to the front surface is a back surface of the second substrate 103, and the memory wafer W2 may further include a second interconnect structure 104 formed on a front side of the second substrate 103. The first interconnect structure 102 and the second interconnect structure 104 may be multi-layered electrical interconnect structures, for example, including multiple patterned conductive layers and conductive plugs isolated by dielectric materials that provide a connection function between doped regions, circuits, and input/output of the logic wafer W1 or the memory wafer W2. It should be understood that the components and locations of the first interconnect structure 102 and the second interconnect structure 104 are shown only schematically in the drawings and may in fact vary depending on design requirements. For clarity, only portions of the conductive layers and conductive plugs in the first interconnect structure 102 and the second interconnect structure 104 are shown in fig. 2.
As an example, in step S1, the front sides of the first substrate 101 and the second substrate 103 are bonded, the first surface 100a of the stack 100 is the back side of the first substrate 101, and the second surface 100b is the back side of the second substrate 103. The present invention is not limited thereto, and for example, in another embodiment, a plurality of memory wafers and a logic wafer may be stacked to form a corresponding stack, or a plurality of memory chips and a logic chip may be stacked to form a corresponding stack.
Referring to fig. 1 and 3 to 5, in an embodiment of the present invention, step S2 includes: a heat transfer groove TR is formed at the first surface 100a of the stack 100, a length direction of the heat transfer groove TR being parallel to the first surface 100a, the heat transfer groove TR having a first end TR1 and a second end TR2 in the length direction.
The manufacturing of the heat conducting grooves TR includes, for example, the following processes: an patterned mask layer (e.g., photoresist or hard mask) is formed on the first surface 100a of the stack 100, exposing a region of the first surface 100a where the heat conductive trench TR is to be formed, and then the first surface 100a is etched by dry etching or wet etching, forming a trench of a predetermined depth in the stack 100 as the heat conductive trench TR.
As an example, in the present embodiment, the stacked body 100 includes a logic wafer W1 and a storage wafer W2 stacked, and the heat-conducting groove TR is used for the subsequent heat dissipation liquid flowing in the first surface 100a to remove the heat generated in the three-dimensional integrated device, and the heat-conducting groove TR may extend in the first surface 100a as required. The extending direction of the heat conducting grooves TR in the first surface 100a is the length direction thereof. The first end TR1 and the second end TR2 of the heat conducting groove TR in the length direction are located at different positions, and then the first end TR1 is used as a position where the heat dissipation liquid flows into the heat conducting groove TR, and the second end TR2 is used as a position where the heat dissipation liquid flows out of the heat conducting groove TR.
It should be noted that, the heat conduction trench TR is formed on the first surface 100a of the stack 100, i.e., the back surface of the first substrate 101 in the logic wafer W1 shown in fig. 2, but the present invention is not limited thereto, and in other embodiments, the heat conduction trench may be formed on the storage wafer side in the stack, as needed.
Fig. 4 shows an exemplary simulated planar pattern of thermally conductive grooves TR formed in the first surface 100a of the stack 100. Referring to fig. 4, the first end TR1 and the second end TR2 of the heat conducting groove TR are, for example, two ends of the heat conducting groove TR that are farther away, that is, from the first end TR1 to the second end TR2, respectively, and the heat dissipation fluid needs to flow in the heat conducting groove TR farther away. However, the planar arrangement of the heat transfer grooves TR shown in fig. 4 is merely an example, and one skilled in the art may set the planar arrangement of the heat transfer grooves TR and the first and second ends TR1 and TR2 of the heat transfer grooves TR as needed.
As shown in fig. 4, the first end TR1 and the second end TR2 of the heat conducting groove TR may have a plurality of (e.g., two, three, four, etc.) channel paths therebetween, so that the distribution of the heat conducting groove TR covers a larger range of the first surface 100a. But not limited thereto, the first and second ends TR1 and TR2 of the heat transfer groove TR may have only one channel path therebetween, and the one channel path may be a straight line or a curved line.
Referring to fig. 1 and 5, in an embodiment of the present invention, step S3 includes: a first groove U1 and a second groove U2 are formed in a surface of a slide 200.
The carrier 200 may be a semiconductor substrate, a glass substrate, a ceramic substrate, a polymer substrate, or the like. The first and second grooves U1 and U2 are opposite to the first and second ends TR1 and TR2 of the heat transfer groove TR, respectively, after the subsequent carrier 200 is bonded to the stack 100, and thus the positions of the first and second grooves U1 and U2 may be determined according to the arrangement of the heat transfer groove TR in the stack 100. The cross-sectional area of the first groove U1 may be greater than or less than the area of the first end TR1 of the heat transfer groove TR opposite thereto, and the cross-sectional area of the second groove U2 may be greater than or less than the area of the second end TR2 of the heat transfer groove TR opposite thereto.
Forming the first groove U1 and the second groove U2 on the surface of the slide 200 includes, for example, the following processes: a patterned mask layer (e.g., photoresist or hard mask) is formed on the surface of the carrier 200 to expose regions where the first and second grooves U1 and U2 are to be formed, and then the carrier 200 is etched by dry etching or wet etching to form the first and second grooves U1 and U2 in the carrier 200. Fig. 6 shows an exemplary simulated planar pattern of first and second grooves U1 and U2 formed in the surface of the carrier 200. Referring to fig. 6, the first and second grooves U1 and U2 are exemplarily rectangular in cross section, but are not limited thereto, and in other embodiments, the first and second grooves U1 and U2 may have circular, elliptical, triangular, square, pentagonal, hexagonal, or other cross-sectional shapes.
Referring to fig. 1 and 7, in an embodiment of the present invention, step S4 includes: the stack 100 is bonded to the carrier 200 with the first groove U1 opposite the first end TR1 of the thermally conductive groove TR and the second groove U2 opposite the second end TR2 of the thermally conductive groove TR. Fig. 8 shows a simulated cross-section of the bonded stack 100 and the carrier 200 and the thermally conductive trench TR.
The stack 100 and the carrier 200 are bonded, for example, using a fusion bonding (fusion bonding) method. Through bonding, the first groove U1 covers the first end TR1 of the heat conducting groove TR, so that the first groove U1 communicates with the first end TR1, and the second groove U1 covers the second end TR2 of the heat conducting groove TR, so that the second groove U1 communicates with the second end TR2.
Fig. 9 is a schematic cross-sectional view of a three-dimensional integrated device after forming solder bumps on a second surface of a stack according to an embodiment of the present invention. Referring to fig. 9, in this embodiment, in order to connect the stack 100 with the circuit substrate, solder bumps 110 are further formed on the second surface 100b of the stack 100, and the solder bumps 110 are connected with the circuit inside the stack 100.
Specifically, referring to fig. 9, after bonding the stack 100 and the carrier 200, the method of forming a three-dimensional integrated device according to an embodiment of the present invention may further include: supporting by using the carrier 200, forming a first back dielectric layer 105 on the back surface of the second substrate 103, and etching the first back dielectric layer 105 and the second substrate 103 to form a through silicon via penetrating through the second substrate 103, so that the through silicon via exposes the second interconnection structure 104; depositing a metal material (e.g., copper), forming a via (via) corresponding to the via, and forming a backside interconnect layer 106; depositing a second backside dielectric layer 107 and etching the second backside dielectric layer 107 to form a via exposing the backside interconnect layer 106; depositing a metal material (e.g., copper), forming via holes corresponding to the via holes to connect the backside interconnect layer 106, and forming pads 108; depositing a passivation layer 109 and etching the passivation layer 109 to form a via hole exposing the pad 108; solder bumps 110 are formed in the through holes that connect the pads 108. One or more solder bumps 110 may be formed on the second surface 100b, and may be specifically configured according to the integration requirement of the stack 100 and the circuit substrate.
Fig. 10 shows a cross section after the stack 100 is bonded to the circuit substrate 300. Referring to fig. 10, the stack 100 may then be bonded to a circuit substrate 300 to connect the circuits inside the stack 100 with the circuit substrate 300.
The circuit substrate 300 may include electronic components (e.g., logic elements) and interconnect structures that may provide further interconnect and support in a three-dimensional integrated device. The surface of the circuit substrate 300 is formed with pads (not shown), for example, and each solder bump 110 formed on the stack 100 is soldered to a corresponding pad on the circuit substrate 300 when the stack 100 and the circuit substrate 300 are bonded.
The circuit substrate 300 may be an interposer substrate, such as a DCB (ceramic-based copper clad laminate), an AMB (active metal solder carrier), a DPC (direct copper clad laminate), an HTCC (High-temperature co-fired multilayer ceramic) or an LTCC (Low-temperature co-fired multilayer ceramic) after the stack 100 is bonded to one side of the interposer substrate, the interposer substrate may be connected to a PCB substrate from the other side of the interposer substrate, but the circuit substrate 300 is not limited thereto.
Referring to fig. 1 and 11, in an embodiment of the present invention, step S5 includes: and removing bottoms of the first groove U1 and the second groove U2, so that the first groove U1 forms a first through hole U1a, and the second groove U2 forms a second through hole U2a. The bottoms of the first and second grooves U1 and U2 may be removed, for example, by thinning (e.g., using mechanical grinding, chemical mechanical polishing, laser grinding, or other processes) or etching (e.g., a dry etching process or a wet etching process) the carrier 200. The first through hole U1a exposes the first end TR1 of the heat conducting groove TR, and the second through hole U2a exposes the second end TR2 of the heat conducting groove TR, wherein, as indicated by the dotted arrow, the first through hole U1a is an inlet of heat dissipating liquid, and the second through hole U2a is an outlet of heat dissipating liquid.
In this embodiment, after the bottoms of the first groove U1 and the second groove U2 are removed by thinning or etching the slide 200, the opening of the first through hole U1a at the end facing away from the stack 100 (i.e., the liquid inlet of the first through hole U1 a) is not higher than the surface of the slide 200 around the first through hole U1 a; the opening of the second through-hole U2a at the end facing away from the stack 100 (i.e. at the inlet of the second through-hole U2 a) is not higher than the surface of the slide 200 around the second through-hole U2a. As shown in fig. 11, as an example, the liquid inlets of the first through hole U1a and the second through hole U2a are substantially flush with the surface of the slide 200 on the same side.
In the method for forming a three-dimensional integrated device described in the foregoing embodiment, the heat conducting groove TR is formed on the surface of the stack body 100, and the first through hole U1a communicating with the first end TR1 of the heat conducting groove TR and the second through hole U2a communicating with the second end TR2 of the heat conducting groove TR are formed in the carrier 200 bonded with the stack body 100, so that when the three-dimensional integrated device works, heat dissipation liquid (such as water, liquid nitrogen, ethanol, silicone oil, freon or special cooling liquid) can be introduced into the heat conducting groove TR from the first through hole U1a, and the heat dissipation liquid flows out from the second through hole U2a, so that heat generated during the chip work in the stack body 100 can be timely taken away, the purpose of cooling the device can be achieved, the heat conduction efficiency is higher, the heat dissipation capability is stronger, compared with the heat dissipation mode of attaching the metal heat dissipation fin adopted in the prior art, the risk of heat accumulation inside the three-dimensional integrated device can be reduced, and the performance of the three-dimensional integrated device can be improved.
The embodiment of the invention also relates to a three-dimensional integrated device. The three-dimensional integrated device can be manufactured by using the method for forming the three-dimensional integrated device described in the above embodiment.
Referring to fig. 11, according to an embodiment of the present invention, a three-dimensional integrated device includes a stack 100 formed by stacking at least two layers of chips, the stack 100 having a first surface 100a and a second surface 100b opposite to each other, wherein the first surface 100a is formed with a heat transfer groove TR, a length direction of the heat transfer groove TR is parallel to the first surface 100a, the slide 200 is bonded to the first surface 100a of the stack 100, the slide 200 has a first through hole U1a and a second through hole U2a, the first through hole U1a exposes the first end TR1 in the length direction of the heat transfer groove TR, the second through hole U2a exposes the second end TR2 in the length direction of the heat transfer groove TR, wherein the first through hole U1a is an inlet of a heat dissipation liquid, and the second through hole U2a is an outlet of the heat dissipation liquid.
The opening of the first through-hole U1a at the end facing away from the stack 100 (i.e. at the liquid inlet of the first through-hole U1 a) is for example not higher than the surface of the slide 200 around the first through-hole U1 a; the opening of the second through-hole U2a at the end facing away from the stack 100 (i.e. at the inlet of the second through-hole U2 a) is for example not higher than the surface of the slide 200 surrounding the second through-hole U2a. As shown in fig. 11, as an example, the liquid inlets of the first through hole U1a and the second through hole U2a are substantially flush with the surface of the slide 200 on the same side.
The heat conductive trench TR is formed on the first surface 100a of the stack 100, and the first surface 100a is, for example, a surface of a semiconductor substrate in the stack 100, but not limited thereto, and in other embodiments, the heat conductive trench TR may be formed on a surface of a dielectric layer in the stack 100.
Referring to fig. 2 to 11, the heat transfer grooves TR may have one or more channel paths between the first and second ends TR1 and TR2. Optionally, the second surface 100b of the stack 100 is formed with solder bumps 110, which solder bumps 110 are connected to circuitry inside the stack 100.
In some embodiments, the three-dimensional integrated device further comprises a circuit substrate 300, the circuit substrate 300 having pads, wherein the stack 100 is bonded to the circuit substrate 300 by soldering the solder bumps 110 with the respective pads.
Referring to fig. 11, in some embodiments, the stack 100 includes a first chip layer (e.g., a logic wafer W1) including a first substrate 101 and electronic components formed on a front surface of the first substrate 101, wherein the heat-conducting trench TR is formed on a back surface of the first substrate 101 opposite to the front surface. The electronic components may include logic devices and/or memory devices. Specifically, the first chip layer may be a logic wafer, a logic chip, a memory wafer, or a memory chip, or the first chip layer may be a wafer containing both a logic device and a memory device, or a chip containing both a logic device and a memory device.
In the stack 100, each layer of chips may include one or more chips. As an example, the stack 100 is formed by stacking a logic wafer W1 and a memory wafer W2. But are not limited thereto, the stack 100 may include more than two chip layers, each of which may have a wafer-level size or a chip-level size, depending on the design of the three-dimensional integrated device. Referring to fig. 12, in another embodiment, the stack 100 includes a logic wafer W1 and two or more memory wafers (e.g., a memory wafer W3 and a memory wafer W4 as examples), and the stack 100 is bonded to the circuit substrate 300 on the logic wafer W1 side, the carrier 200 is bonded to the memory wafer W3 side, and the heat transfer grooves TR are formed on the surface of the memory wafer W3 at the end.
The three-dimensional integrated device of the embodiment of the invention comprises a stacked body 100 formed by stacking at least two layers of chips and a carrier 200 bonded to a first surface 100a of the stacked body 100, wherein a heat conducting groove TR is formed on the first surface 100a of the stacked body 100, the carrier 200 is provided with a first through hole U1a and a second through hole U2a, the first through hole U1a exposes a first end TR1 in the length direction of the heat conducting groove TR, the second through hole U2a exposes a second end TR2 in the length direction of the heat conducting groove TR, the first through hole U1a is an inlet of heat dissipation liquid, and the second through hole U2a is an outlet of the heat dissipation liquid. Compared with the heat dissipation mode of the attached metal radiating fins adopted in the prior art, the three-dimensional integrated device can utilize the flowing of the heat dissipation liquid in the heat conduction groove TR to take away heat for heat dissipation, the purpose of cooling the device is achieved, the heat conduction efficiency is higher, the heat dissipation capacity is strong, the risk of heat accumulation in the three-dimensional integrated device can be reduced, and the performance of the three-dimensional integrated device is improved.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described and explained by differences from other embodiments, and relevant points can be understood by referring to the description.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims (11)

1. A three-dimensional integrated device, comprising:
a stacked body formed by stacking at least two layers of chips, wherein the stacked body is provided with a first surface and a second surface which are opposite, the first surface is provided with a heat conduction groove, and the length direction of the heat conduction groove is parallel to the first surface; and
the slide is bonded to the first surface of the stacked body, the slide is provided with a first through hole and a second through hole, the first through hole exposes out of the first end of the heat conducting groove in the length direction, the second through hole exposes out of the second end of the heat conducting groove in the length direction, the first through hole is an inlet of heat dissipation liquid, and the second through hole is an outlet of heat dissipation liquid.
2. The three-dimensional integrated device of claim 1, wherein an opening of the first through-hole at an end facing away from the stack is no higher than the slide surface surrounding the first through-hole; an opening of the second through hole at an end facing away from the stack is not higher than the slide surface around the second through hole.
3. The three-dimensional integrated device of claim 1, wherein the second surface is formed with solder bumps that connect with circuitry inside the stack.
4. The three-dimensional integrated device of claim 3, further comprising:
a circuit substrate having pads, wherein the stack is bonded to the circuit substrate by soldering the solder bumps with the respective pads.
5. The three-dimensional integrated device of claim 1, wherein the stack comprises a first chip layer comprising a first substrate and an electronic component formed on a front side of the first substrate, wherein the thermally conductive trench is formed on a back side of the first substrate opposite the front side.
6. The three-dimensional integrated device of claim 5, wherein the electronic components comprise logic devices and/or memory devices.
7. The three-dimensional integrated device of any one of claims 1-6, wherein the first end and the second end of the thermally conductive trench have one or more channel paths therebetween.
8. The three-dimensional integrated device of any one of claims 1-6, wherein each layer of chips in the stack comprises one or more chips.
9. A method of forming a three-dimensional integrated device, comprising:
stacking at least two layers of chips to form a stack body, wherein the stack body is provided with a first surface and a second surface which are opposite;
forming a heat conducting groove on the first surface, wherein the length direction of the heat conducting groove is parallel to the first surface, and the heat conducting groove is provided with a first end and a second end in the length direction;
forming a first groove and a second groove on the surface of a slide;
bonding the stack to the carrier, wherein the first groove is opposite a first end of the thermally conductive trench and the second groove is opposite a second end of the thermally conductive trench; and
removing bottoms of the first groove and the second groove, enabling the first groove to form a first through hole, enabling the second groove to form a second through hole, enabling the first through hole to expose the first end of the heat conducting groove, enabling the second through hole to expose the second end of the heat conducting groove, wherein the first through hole is an inlet of heat dissipation liquid, and the second through hole is an outlet of heat dissipation liquid.
10. The method of forming of claim 9, wherein bottoms of the one recess and the second recess are removed by thinning or etching the slide.
11. The forming method of claim 9, wherein prior to removing bottoms of the first groove and the second groove, the forming method further comprises:
forming solder bumps on the second surface, the solder bumps being connected to circuitry inside the stack; and
the stack is bonded to a circuit substrate having pads, wherein the solder bumps are soldered to the respective pads.
CN202310910112.XA 2023-07-21 2023-07-21 Three-dimensional integrated device and method of forming the same Pending CN116705733A (en)

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CN202310910112.XA CN116705733A (en) 2023-07-21 2023-07-21 Three-dimensional integrated device and method of forming the same

Applications Claiming Priority (1)

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Publications (1)

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CN116705733A true CN116705733A (en) 2023-09-05

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