CN116705622A - Manufacturing method, packaging method and structure of interconnection adapter plate - Google Patents

Manufacturing method, packaging method and structure of interconnection adapter plate Download PDF

Info

Publication number
CN116705622A
CN116705622A CN202310714212.5A CN202310714212A CN116705622A CN 116705622 A CN116705622 A CN 116705622A CN 202310714212 A CN202310714212 A CN 202310714212A CN 116705622 A CN116705622 A CN 116705622A
Authority
CN
China
Prior art keywords
interconnection
packaging
layer
adapter plate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310714212.5A
Other languages
Chinese (zh)
Inventor
陈彦亨
林正忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SJ Semiconductor Jiangyin Corp
Original Assignee
Shenghejing Micro Semiconductor Jiangyin Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenghejing Micro Semiconductor Jiangyin Co Ltd filed Critical Shenghejing Micro Semiconductor Jiangyin Co Ltd
Priority to CN202310714212.5A priority Critical patent/CN116705622A/en
Publication of CN116705622A publication Critical patent/CN116705622A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application provides a manufacturing method, a packaging method and a structure of an interconnection adapter plate. The manufacturing method of the interconnection adapter plate comprises the following steps: s11: providing a substrate, and forming a plurality of first through holes which are arranged at intervals in the substrate by adopting a photoetching process; s12: filling the first through hole with a molten glass material; s13: removing the base material between adjacent first through holes, thereby forming second through holes; s14: and filling the metal conductive layer in the second through hole to form a plurality of conductive columns which are arranged at intervals. The application can manufacture the composite TGV adapter plate structure with high-density interconnection holes through improved flow design, and can meet the high-density packaging requirement. Because the interconnection holes are insulated by the glass material, an insulating layer is not required to be electroplated inside, thereby being beneficial to reducing the process steps and reducing the production cost. Compared with the traditional TSV adapter plate, the prepared adapter plate has better electrical performance, is beneficial to improving the performance of packaging devices, and can be widely applied to advanced packaging processes such as 2.5D/3D and the like.

Description

Manufacturing method, packaging method and structure of interconnection adapter plate
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a back-end packaging, and particularly relates to a manufacturing method of an interconnection adapter plate, a packaging method and a structure.
Background
Chiplet is typically translated into "cores" or "chiplets," meaning "smaller particle size chips. In the existing Chiplet package, a through silicon via (TSV Interposer) is mainly used for die bonding, but there have been attempts by enterprises to make glass Through Glass (TGV) Interposer using glass. The advantages of The Glass Via (TGV) process over the Through Silicon Via (TSV) process are mainly manifested in:
1) Excellent high frequency electrical characteristics: the glass material is an insulator material, the dielectric constant is only about 1/3 of that of the silicon material, and the loss factor is 2-3 orders of magnitude lower than that of the silicon material, so that the substrate loss and parasitic effect are greatly reduced, and the integrity of transmission signals is ensured.
2) The process flow is simple: an insulating layer is not required to be deposited on the surface of the substrate and the inner wall of the TGV, and thinning is not required in the ultrathin adapter plate.
3) The mechanical stability is strong: even when the interposer thickness is less than 100 μm, warpage is small.
The formation process of TGV mainly comprises sand blasting, ultrasonic drilling, wet etching, deep reactive ion etching, photosensitive etching, laser induced deep etching, focusing discharge pore-forming and the like. However, these methods have different disadvantages, and TGV manufactured by these methods is difficult to be smaller than that of the existing TSV, and cannot meet the packaging requirement of high-density devices.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above drawbacks of the prior art, the present application is to provide a method for manufacturing an interconnection interposer, a method for packaging the interconnection interposer, and a structure thereof, which are used for solving the problems that the prior art has defects in methods such as sand blasting, ultrasonic drilling, wet etching, deep reactive ion etching, photosensitive etching, laser-induced deep etching, and focused discharge hole forming, and the size of a manufactured glass via hole is large, so that the packaging requirement of a high-density device is difficult to meet.
To achieve the above and other related objects, the present application provides a method for manufacturing an interconnection patch panel, including the steps of:
s11: providing a substrate, and forming a plurality of first through holes which are arranged at intervals in the substrate by adopting a photoetching process;
s12: filling the first through hole with a molten glass material;
s13: removing the base material between adjacent first through holes, thereby forming second through holes;
s14: and filling the metal conductive layer in the second through hole to form a plurality of conductive columns which are arranged at intervals.
Optionally, the step S12 includes the steps of:
bonding the glass substrate with a substrate provided with a first through hole, wherein the opening surface of the first through hole is a bonding surface;
performing high-temperature reflow on the glass substrate to enable the molten glass material to fill the first through holes;
chemical mechanical polishing is performed to level the upper surface of the substrate with the upper surface of the filled glass material.
More optionally, the temperature during high temperature reflow of the glass substrate is 700 ℃ to 900 ℃ for 30min to 1hr.
Optionally, the substrate includes a silicon wafer, and removing the corresponding material in step S11 and step S13 by using a reactive ion deep silicon etching process.
Optionally, the step S14 includes a step of electroplating to form a metal layer and then performing chemical mechanical polishing.
The application also provides a packaging method, which comprises the following steps:
s21: obtaining an interconnection patch panel by adopting the manufacturing method in any scheme;
s22: forming a wiring layer electrically connected with the conductive column of the interconnection patch panel on the interconnection patch panel;
s23: the chip is arranged on the wiring layer and is electrically connected with the wiring layer;
s24: forming a plastic packaging material layer for coating the chip;
s25: processing the surface of the interconnection patch panel, which is away from the wiring layer, to expose the conductive posts;
s26: an electrical lead-out structure is formed in electrical connection with the conductive pillars.
Optionally, the method of treating the surface of the interconnection interposer facing away from the core wiring layer to expose the conductive pillars includes etching and/or chemical mechanical polishing.
Optionally, the method of forming the electrical lead-out structure electrically connected to the conductive post includes ball mounting using a C4 standard process.
The application also provides a packaging structure which is manufactured by adopting the packaging method in any scheme, and comprises an interconnection adapter plate, a wiring layer positioned on the interconnection adapter plate, a chip electrically connected with the wiring layer, a plastic packaging material layer wrapping the chip and an electric lead-out structure positioned on the surface of the interconnection adapter plate, which is far away from the wiring layer, and electrically connected with the interconnection adapter plate.
Optionally, the packaging structure further comprises a packaging frame, the interconnection adapter plate, the wiring layer and the chip are located in the packaging frame, a heat dissipation layer is arranged between the packaging frame and the chip, and an electrical structure for electrically leading out the chip is arranged on the packaging frame.
As described above, the manufacturing method, the packaging method and the structure of the interconnection patch panel of the application have the following beneficial effects: the application can manufacture the composite TGV (glass through hole) adapter plate structure with high-density interconnection holes through improved flow design, and can meet the high-density packaging requirement. Because the interconnection holes are insulated by the glass material, an insulating layer is not required to be electroplated inside, thereby being beneficial to reducing the process steps and reducing the production cost. Compared with the traditional TSV adapter plate, the prepared adapter plate has better electrical performance, is beneficial to improving the performance of packaging devices, and can be widely applied to advanced packaging processes such as 2.5D/3D and the like.
Drawings
Fig. 1 shows a flowchart of a method for manufacturing an interconnection patch panel according to the present application.
Fig. 2 to 8 are schematic cross-sectional views showing steps of manufacturing the interconnection interposer according to the method of manufacturing the interconnection interposer of the present application.
Fig. 9 is a schematic top view of fig. 8.
Fig. 10 to 15 are schematic views showing exemplary cross-sectional structures presented in each step of packaging by the packaging method provided by the present application.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. In order to make the illustration as concise as possible, not all structures are labeled in the drawings.
Example 1
As shown in fig. 1, the present embodiment provides a method for manufacturing an interconnection patch panel. The steps will be described in detail with reference to the drawings.
Step S11 is first performed: providing a substrate 11, and forming a plurality of first through holes 111 arranged at intervals in the substrate 11 by adopting a photoetching process, wherein the obtained structure is shown in fig. 2.
The substrate 11 may be any type of substrate compatible with the manufacturing process of the semiconductor device, especially a semiconductor substrate. Such as silicon wafers, germanium wafers, silicon-on-insulator wafers, silicon carbide wafers, and the like. The substrate 11 may be a single material layer or may be a composite material layer, for example, formed by bonding a plurality of material layers. In this embodiment, the substrate 11 is a silicon wafer, and thus a reactive ion deep silicon etching (DRIE) process is used to remove the silicon material corresponding to the position of the first through hole 111 in this step. In the case where the substrate 11 is a single material layer, the etching depth in this step is smaller than the thick bottom of the substrate 11. I.e. the first through hole 111 is a blind hole, which does not penetrate the substrate 11. Parameters such as the aperture and shape of the first through hole 111 may be determined as needed, and are not particularly limited. However, in order to facilitate the subsequent filling, the first through hole 111 is preferably in a structure with a narrow top and a wide bottom, and the opening surface of the first through hole 111 may be a semicircular opening surface, so that the whole first through hole 111 is in a funnel structure, and the molten glass material in the subsequent process can flow into the through hole along the circular arc surface, thereby being beneficial to improving the filling uniformity. Because the photoetching process is adopted, the size of the first through hole 111 can reach the nanometer level, so that the density of the first through hole 111 can be quite high, and the interconnection interposer prepared by the embodiment can be used for packaging high-density devices.
In addition, in the traditional silicon etching process, a photoresist layer is generally adopted as an etching mask layer, and the residual mask layer is removed after the photoetching is completed. In a preferred example provided in this embodiment, a material layer having a melting point higher than that of glass is used as the mask layer in the photolithography process, for example, a silicon nitride layer is used as the mask layer. After the photolithography etching process is completed, a residual mask layer remains. In the subsequent process of filling the first through hole 111 with the molten glass material, the substrate 11 is protected by the residual mask layer, preventing the first through hole 111 formed due to the high temperature from being deformed.
Next, step S12 is performed, in which the first through hole 111 is filled with a molten glass material, and the glass material filled in the first through hole 111 forms the insulating structure 13.
In some examples, the molten glass material may be introduced into the first through hole 111 by means of dropping, spin coating, or the like. The filling mode is relatively simple, and accurate filling can be realized. The glass material may be USG (undoped silica) or BPSG (borophosphosilicate glass) material.
In another example, this step takes the following form:
the glass substrate 13a is bonded to the base 11 formed with the first through hole 111, wherein the opening surface of the first through hole 111 is a bonding surface. In some examples, the bonding may be performed by low-temperature anodic bonding, electrostatic bonding, or the like without using additional bonding materials (i.e., without other materials between the base 11 and the glass substrate 13 a). In other examples, bonding may be performed using a bonding paste having a melting point lower than that of the glass substrate 13a and a dielectric constant greater than that of the glass substrate 13 a. In the subsequent high-temperature reflow process, the bonding adhesive flows into the first through hole 111 by being heated and melted, so that the bottom of the first through hole 111 can be fully filled, and the dielectric constant of the filled insulating structure can be improved. The structure obtained after bonding is completed is shown in fig. 3.
The glass substrate 13a is then subjected to high-temperature reflow so that the molten glass material flows into the first through holes 111 to fill the first through holes 111. The high temperature reflow process may be performed using laser heating or by placing the bonded structure in a high temperature furnace, the latter being preferred in this embodiment.
Preferably, the temperature during the high temperature reflow of the glass substrate 13a is 700 ℃ to 900 ℃. For example 700, 800, 900 or any value in this interval. The temperature value can ensure better melting effect and prevent the molten glass material from overflowing to pollute the equipment due to overlarge fluidity. The time of the high temperature reflow may be dependent on the depth of the first via 111. But in a preferred example, this time is 30min-1hr. The structure obtained after this step is shown in fig. 4.
In some examples, an optical inspection may be performed after the filling is completed to see if the first via 111 is completely filled. If a defective filling, particularly an underfilling, occurs in the first through hole 111, rework may be performed. The reworking method is, for example, to put back into a high temperature furnace and raise the heating temperature so that the glass material flows downward to underfill the first through hole 111. In other examples, if the underfill failure of the first via 111 is found, the underfill failure may be remedied later, which will be described later.
After ensuring that the first through-holes 111 are completely filled, a surface planarization process, preferably a chemical mechanical polishing process, is performed to level the upper surface of the substrate 11 with the upper surface of the filled glass material, resulting in a structure as shown in fig. 5.
Next, step S13 is performed to remove the material of the substrate 11 between the adjacent first through holes 111, thereby forming the second through holes 112, resulting in the structure shown in fig. 6. If the substrate 11 is a silicon wafer, a reactive ion deep silicon etching (DRIE) process is preferably used in this step to remove the substrate 11 material between the first vias 111.
Then, step S14 is performed to fill the conductive metal layer 12a in the second via 112 to form a plurality of conductive pillars 12 disposed at intervals.
In a preferred embodiment, this step includes forming a metal layer that fills the second via 112 and covers the surface of the substrate 11 using processes including, but not limited to, physical vapor deposition and/or electroplating, and then performing a surface planarization process after the structure shown in fig. 7 is obtained. For example, chemical mechanical polishing is performed to expose the conductive pillars 12, resulting in the structure shown in fig. 8. For example, in one example, the conductive metal layer 12a is a copper layer formed by electroplating. In other examples, a chemical vapor deposition process may be used to form a copper seed layer on the inner surface of the second via 112 prior to electroplating. This helps to improve filling uniformity.
As can be seen from fig. 9, the interconnection interposer obtained has a plurality of conductive pillars 12 spaced apart from each other on the inner side of a substrate 11, and adjacent conductive pillars 12 are electrically isolated by an insulating structure 13 made of a glass material, and the substrate 11 material on the bottom of the conductive pillars 12 plays a role in supporting the conductive pillars 12 and preventing the conductive pillars 12 from being contaminated by oxidation.
The improved flow design of the embodiment can manufacture the composite TGV (glass through hole) adapter plate structure with high-density interconnection holes, and can meet the high-density packaging requirement. Because the interconnection holes are insulated by the glass material, an insulating layer is not required to be electroplated inside, thereby being beneficial to reducing the process steps and reducing the production cost. Compared with the traditional TSV adapter plate, the prepared adapter plate has better electrical performance, is beneficial to improving the performance of packaging devices, and can be widely applied to advanced packaging processes such as 2.5D/3D and the like.
Example two
The present embodiment provides a packaging method, which will be described in detail with reference to the accompanying drawings.
First, step S21 is performed, and the interconnection patch panel is obtained by using the manufacturing method according to any one of the embodiments. The detailed process of manufacturing the interconnection patch panel is described in the first embodiment, and is not repeated for the sake of brevity. After the interposer is manufactured, the interposer is typically cleaned. The cleaning process includes, for example, wet cleaning and drying, so that the surface of the conductive pillars 12 exposed on the surface of the interposer is free from contamination by particulate impurities, oxides, and the like.
Then, step S22 is performed to form the wiring layer 14 electrically connected to the conductive post 12 of the interconnection interposer on the interconnection interposer, resulting in the structure shown in fig. 10.
As an example, the wiring layer 14 includes a dielectric layer and a metal line layer formed within the dielectric layer and on the surface of the dielectric layer. For example, a dielectric layer is formed by a chemical vapor deposition process, and then the dielectric layer is subjected to a photolithography etching process to form a contact hole in the dielectric layer, then a physical vapor deposition process is performed to form a metal layer filling the contact hole and covering the dielectric layer, and then a planarization process such as chemical mechanical polishing is performed to expose the metal layer. The wiring layer 14 may be a single-layer or multi-layer structure. In a preferred example, the wiring layer 14 is a damascene wiring structure.
Next, step S23 is performed to dispose the chip 15 on the wiring layer 14 and electrically connect with the wiring layer 14, resulting in the structure shown in fig. 11.
The chip 15 may include a single or multiple active and/or passive devices, such as several of the devices including, but not limited to, inductors, capacitors, inverters, amplifiers, and the like. When the number of chips 15 is plural, the plural chips 15 may be disposed on the same plane at intervals or stacked one on top of the other. The chip 15 may be fixed to the surface of the wiring layer 14 by soldering and/or conductive gel or the like. To ensure electrical connection, the wiring layer 14 may be subjected to a photolithographic etching process to form openings exposing the metal layer at the corresponding electrical connection locations, prior to electrically connecting the chip 15 to the wiring layer 14.
Then, step S24 is performed to form the molding material layer 16 covering the chip 15.
As an example, the plastic package material layer 16 filled in the sides of the chips 15, between the chips 15, and on the upper surface of the chips 15 may be formed using a combination of one or more methods including, but not limited to, compression molding, transfer molding, liquid seal molding, vacuum lamination, and spin coating, etc., to obtain the structure shown in fig. 12, and then a planarization process including, but not limited to, chemical mechanical polishing may be performed to expose the upper surface of the chips 15. The material of the plastic sealing material layer 16 includes, but is not limited to, one or more of polyimide, silicone, and epoxy. In other examples, an underfill (underfill) may be applied before forming the molding material layer 16. For example, materials such as epoxy are filled using a process including, but not limited to, molding underfill, capillary underfill, etc., to encapsulate the connection points of the chip 15 and the wiring layer 14, prevent moisture penetration and oxidation contamination, and ensure device electrical performance.
Next, step S25 is performed to process the surface of the interconnection interposer facing away from the wiring layer 14 to expose the conductive pillars 12, resulting in the structure shown in fig. 13.
If the substrate 11 is a single structural layer, the back surface of the interconnection interposer may be processed by a surface planarization method including, but not limited to, etching and/or chemical mechanical polishing, where the planarization is usually performed at the bottom of the original first via 111. If it is detected that there is a defective filling in the filling process of the first through hole 111 and/or the second through hole 112, the polishing thickness in this step may be increased appropriately to remove the portion of the defective filling.
In other examples, if the substrate 11 for manufacturing the interconnection interposer is formed by bonding a plurality of material layers, for example, bonding a silicon material layer and a graphene layer, the depth of the first through hole 111 is the same as the thickness of the silicon material layer, and the graphene layer may be removed by a bonding-release process in this step. Therefore, the substrate 11 can realize recycling of part of material layers by using the structure formed by bonding different material layers, and the de-bonding process is simpler than the chemical mechanical polishing process, thereby being beneficial to reducing the production cost.
In another example, the surface planarization treatment of the plastic sealing material layer 16 may be performed after this step. I.e., the surface of the interconnection interposer facing away from the wiring layer 14 is first treated to expose the conductive pillars 12, and then the surface planarization process is performed on the molding material layer 16. This helps prevent moisture from penetrating into the chip 15 during chemical mechanical polishing. Alternatively, the step of performing the surface planarization treatment on the molding material layer 16 may be performed after the preparation of the electrical lead-out structure 17 is completed, which is not limited.
Next, step S26 is performed to form the electrical lead-out structure 17 electrically connected to the conductive pillar 12, resulting in the structure shown in fig. 14.
The electrical lead-out structure 17 may be a prefabricated, for example, a substrate with the conductive pillars 12 prefabricated, and the structure shown in fig. 13 may be electrically bonded to the substrate, or a metal layer contacting with the conductive pillars 12 may be formed on the back of the base 11 by a physical vapor deposition process, and then the electrical lead-out structure 17 may be formed by a photolithography etching process.
In a preferred example, the method of forming the electrical lead-out structure 17 electrically connected to the conductive post 12 includes ball mounting using a C4 standard process.
Specifically, the process may include: firstly, the structure exposing the conductive posts 12 is placed on a substrate with solder balls, then a layer of metal film is coated on the pins of the chip 15, then a layer of soldering paste is coated on the pins of the chip 15, and finally the chip 15 and the substrate are connected in a hot pressing mode. The packaging mode can realize high-density chip 15 connection, and meanwhile, the reliability and stability of the chip 15 can be improved.
The process of manufacturing the interconnection interposer and the process of packaging the chip may or may not be related in time and space. That is, the packaging of the chip can be continued in the same factory after the fabrication of the interconnection interposer is completed. The interconnection interposer may be manufactured in other factories and then transferred to other factories for chip packaging (i.e., the interconnection interposer may be self-made or purchased from a chip packaging manufacturer). In any event, it is desirable to ensure cleanliness of the interconnection patch panels.
The packaging method of the embodiment can be used for packaging a single device and also can be used for packaging a wafer level. When wafer level packaging is performed, there are hundreds or thousands of devices packaged at the same time, and thus the packaging method further includes a step of dicing after completing the ball mounting process to obtain a plurality of independent dies. The resulting die may be packaged according to customer requirements, such as by packaging the resulting individual die onto a package substrate as shown in fig. 14. The package substrate 181 includes, for example, a lead frame. More specifically, for example, a copper substrate having an electrical structure such as a solder ball provided on a surface thereof. The solder balls on the chip 15 are electrically connected to the electrical structures on the package substrate 181. The top and sides of the chip 15 may be covered with a metal cap 182. The metal cap layer 182 is preferably made of stainless steel or the like having good heat dissipation performance. The metal cap layer 182 may be grounded. The metal cover 182 may be attached to the package substrate 181 by an adhesive layer 184, and together with the package substrate 181, the foregoing interconnect interposer, wiring layer 14, chip 15, and molding compound layer 16 are encapsulated. The chip 15 and the metal cap layer 182 may have a pitch or no pitch therebetween. In a preferred example, a heat dissipation layer 183 may be disposed between the metal cap layer 182 and the chip 15, and the heat dissipation layer 183 may be attached to the entire inner surface of the metal cap layer 182 or a surface facing the upper surface of the chip 15. The heat dissipation layer 183 may be attached to or spaced from the chip 15. The heat dissipation layer 183 may be a single-layer or multi-layer stacked structure. The final structure obtained after this step is shown in fig. 15.
As shown in fig. 14, the present application further provides a packaging structure, which is manufactured by adopting the packaging method described in any one of the above schemes, and the packaging structure includes an interconnection interposer, a wiring layer 14 located on the interconnection interposer, a chip 15 electrically connected to the wiring layer 14, a plastic packaging material layer 16 covering the chip 15, and an electrical lead-out structure 17 located on a surface of the interconnection interposer facing away from the wiring layer 14 and electrically connected to the interconnection interposer. The package structure may be a wafer level structure, i.e., a plurality of structures as depicted in fig. 14 are formed on a single wafer.
In other examples, the package structure may also be a single stand-alone device structure as shown in fig. 15, further comprising a package frame within which the interconnection interposer, wiring layer 14, and chip 15 are located. The package frame may include a package substrate 181 and a metal cap layer 182 connected and fixed to the package substrate 181 through an adhesion layer 184. A heat dissipation layer 183 may be further disposed between the package frame and the chip 15, and an electrical structure 19, such as a solder ball, for electrically guiding out the chip 15 is disposed on the package frame.
For more description of the package structure, including the material and forming method of each structural layer, please refer to the foregoing, and details are omitted for brevity.
The packaging structure provided by the application has improved flow and structural design, and on the premise of meeting the high-density packaging requirement, the electrical performance of the packaging structure can be obviously improved, and the manufacturing cost can be relatively reduced.
In summary, the present application provides a method for manufacturing and packaging an interconnection interposer, and a structure thereof. The manufacturing method of the interconnection adapter plate comprises the following steps: s11: providing a substrate, and forming a plurality of first through holes which are arranged at intervals in the substrate by adopting a photoetching process;
s12: filling the first through hole with a molten glass material; s13: removing the base material between adjacent first through holes, thereby forming second through holes; s14: and filling the metal conductive layer in the second through hole to form a plurality of conductive columns which are arranged at intervals. The application can manufacture the composite TGV (glass through hole) adapter plate structure with high-density interconnection holes through improved flow design, and can meet the high-density packaging requirement. Because the interconnection holes are insulated by the glass material, an insulating layer is not required to be electroplated inside, thereby being beneficial to reducing the process steps and reducing the production cost. Compared with the traditional TSV adapter plate, the prepared adapter plate has better electrical performance, is beneficial to improving the performance of packaging devices, and can be widely applied to advanced packaging processes such as 2.5D/3D and the like.
Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The manufacturing method of the interconnection adapter plate is characterized by comprising the following steps:
s11: providing a substrate, and forming a plurality of first through holes which are arranged at intervals in the substrate by adopting a photoetching process;
s12: filling the first through hole with a molten glass material;
s13: removing the base material between adjacent first through holes, thereby forming second through holes;
s14: and filling the metal conductive layer in the second through hole to form a plurality of conductive columns which are arranged at intervals.
2. The method for manufacturing the interconnection patch panel according to claim 1, wherein the step S12 includes the steps of: bonding the glass substrate with a substrate provided with a first through hole, wherein the opening surface of the first through hole is a bonding surface;
performing high-temperature reflow on the glass substrate to enable the molten glass material to fill the first through holes;
chemical mechanical polishing is performed to level the upper surface of the substrate with the upper surface of the filled glass material.
3. The method of manufacturing an interconnection adapter plate according to claim 3, wherein the temperature during the high-temperature reflow of the glass substrate is 700 ℃ to 900 ℃ for 30min to 1hr.
4. The method of claim 1, wherein the substrate comprises a silicon wafer, and step S11 and step S13 each comprise removing the corresponding material using a reactive ion deep silicon etching process.
5. The method of manufacturing an interconnection interposer as claimed in claim 1, wherein the step S14 includes a step of performing electroplating to form a metal layer, and then performing chemical mechanical polishing.
6. A packaging method, characterized in that the packaging method comprises the steps of:
s21: obtaining an interconnection patch panel by adopting the manufacturing method according to any one of claims 1 to 5;
s22: forming a wiring layer electrically connected with the conductive column of the interconnection patch panel on the interconnection patch panel;
s23: the chip is arranged on the wiring layer and is electrically connected with the wiring layer;
s24: forming a plastic packaging material layer for coating the chip;
s25: processing the surface of the interconnection patch panel, which is away from the wiring layer, to expose the conductive posts;
s26: an electrical lead-out structure is formed in electrical connection with the conductive pillars.
7. The packaging method according to claim 6, wherein the method of treating the surface of the interconnection interposer facing away from the core wiring layer to reveal the conductive pillars includes an etching method and/or a chemical mechanical polishing method.
8. The method of packaging of claim 6, wherein forming the electrical lead-out structure electrically connected to the conductive post comprises ball mounting using a C4 standard process.
9. The packaging structure is characterized by being manufactured by adopting the packaging method according to any one of claims 6 to 8, and comprises an interconnection adapter plate, a wiring layer positioned on the interconnection adapter plate, a chip electrically connected with the wiring layer, a plastic packaging material layer wrapping the chip and an electric lead-out structure positioned on the surface of the interconnection adapter plate, which is away from the wiring layer, and electrically connected with the interconnection adapter plate.
10. The package structure of claim 9, further comprising a package frame, wherein the interconnection interposer, wiring layer, and chip are located in the package frame, a heat dissipation layer is disposed between the package frame and the chip, and an electrical structure for electrically guiding out the chip is disposed on the package frame.
CN202310714212.5A 2023-06-15 2023-06-15 Manufacturing method, packaging method and structure of interconnection adapter plate Pending CN116705622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310714212.5A CN116705622A (en) 2023-06-15 2023-06-15 Manufacturing method, packaging method and structure of interconnection adapter plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310714212.5A CN116705622A (en) 2023-06-15 2023-06-15 Manufacturing method, packaging method and structure of interconnection adapter plate

Publications (1)

Publication Number Publication Date
CN116705622A true CN116705622A (en) 2023-09-05

Family

ID=87842930

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310714212.5A Pending CN116705622A (en) 2023-06-15 2023-06-15 Manufacturing method, packaging method and structure of interconnection adapter plate

Country Status (1)

Country Link
CN (1) CN116705622A (en)

Similar Documents

Publication Publication Date Title
TWI701790B (en) Chip package structure and method for manufacturing the same
US10971483B2 (en) Semiconductor structure and manufacturing method thereof
CN103515362B (en) Stacked package device and the method for encapsulation semiconductor element
US6828669B2 (en) Interconnection substrate having metal columns covered by a resin film, and manufacturing method thereof
EP1775768A1 (en) Semiconductor device having three-dimensional stack structure and method for manufacturing the same
US20110217812A1 (en) Integrated circuit device and method for fabricating same with an interposer substrate
KR20130140643A (en) Semiconductor chip device with polymeric filler trench
TWI596680B (en) Low cte component with wire bond interconnects
US10580739B2 (en) Package substrate and associated fabrication method with varying depths for circuit device terminals
TW201725661A (en) Semiconductor device and manufacturing method thereof
KR102469446B1 (en) Semiconductor structure and method forming same
KR101763028B1 (en) Integrated fan-out structure and method
JP6444269B2 (en) Electronic component device and manufacturing method thereof
US20140103522A1 (en) Semiconductor substrate, semiconductor device, and method of manfacturing semiconductor substrate
KR101323925B1 (en) Stacked semiconductor package and method of manufacturing the same
CN116705622A (en) Manufacturing method, packaging method and structure of interconnection adapter plate
US8988893B2 (en) Method for electrical connection between elements of a three-dimensional integrated structure and corresponding device
TWI574597B (en) Coreless package substrate and method for manufacturing the same
TWI776678B (en) Semiconductor package and manufacturing method thereof
TWI766761B (en) Electronic package and manufacturing method thereof
KR101002041B1 (en) Chip stacked package and method for manufacturing of it
TWI611484B (en) Electronic package structure and the manufacture thereof
US7098075B1 (en) Integrated circuit and method of producing a carrier wafer for an integrated circuit
TW202131472A (en) Semiconductor device and method of fabricating the same
CN116469860A (en) Electronic package and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination