CN116705606A - HEMT device and preparation method thereof - Google Patents
HEMT device and preparation method thereof Download PDFInfo
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- CN116705606A CN116705606A CN202310786364.6A CN202310786364A CN116705606A CN 116705606 A CN116705606 A CN 116705606A CN 202310786364 A CN202310786364 A CN 202310786364A CN 116705606 A CN116705606 A CN 116705606A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 134
- 230000004888 barrier function Effects 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims description 336
- 238000000034 method Methods 0.000 claims description 79
- 238000004519 manufacturing process Methods 0.000 claims description 34
- 230000006911 nucleation Effects 0.000 claims description 14
- 238000010899 nucleation Methods 0.000 claims description 14
- 230000000149 penetrating effect Effects 0.000 claims description 8
- 239000002344 surface layer Substances 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 25
- 229910002601 GaN Inorganic materials 0.000 description 13
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 12
- 239000004020 conductor Substances 0.000 description 11
- 230000005684 electric field Effects 0.000 description 11
- 238000007740 vapor deposition Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 230000005533 two-dimensional electron gas Effects 0.000 description 7
- 229910002704 AlGaN Inorganic materials 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 229910052697 platinum Inorganic materials 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000001755 magnetron sputter deposition Methods 0.000 description 5
- 150000002736 metal compounds Chemical class 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000003321 amplification Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- FFEARJCKVFRZRR-UHFFFAOYSA-N methionine Chemical compound CSCCC(N)C(O)=O FFEARJCKVFRZRR-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention provides a HEMT device and a preparation method thereof, wherein the HEMT device comprises a substrate, a laminated structure, a first dielectric layer, a gate conducting layer, a second dielectric layer, a drain electrode contact hole, a gate electrode contact hole, a drain electrode, a gate electrode and a source electrode, wherein a groove is arranged in the substrate; the laminated structure comprises a channel layer and a barrier layer and covers the exposed surface of the groove and the upper surface of the substrate; the first dielectric layer fills the groove and covers the laminated structure, and a grid hole is formed in the first dielectric layer; the gate conducting layer fills the gate hole; the second dielectric layer covers the first dielectric layer and the gate conductive layer; the drain electrode contact hole penetrates through the second dielectric layer, the bottom surface of the drain electrode contact hole at least exposes the barrier layer above the substrate, and the grid electrode contact hole penetrates through the second dielectric layer and exposes the grid conductive layer; the drain and the grid are respectively filled with a drain and a grid contact hole; the source is electrically connected to the substrate and the channel layer. According to the invention, a laminated structure is formed in the groove with the inclined inner wall, the source electrode is formed at the bottom of the groove, the drain electrode is formed above the substrate, and the on-resistance of the unit area of the device is reduced.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a HEMT device and a preparation method thereof.
Background
Gallium nitride (GaN) has significant advantages as a third generation semiconductor material over first generation silicon, second generation gallium arsenide (GaAs). The AlGaN/GAN High Electron Mobility Transistor (HEMT) has large energy band gap, high peak saturated electron velocity, high concentration two-dimensional electron gas and higher electron mobility, so that the AlGaN/GaN HEMT is widely applied to Radio Frequency (RF), microwaves, power switching power supplies and the like.
AlGaN/GaN HEMTs belong to planar channel field effect transistors, when high voltage is applied to a drain electrode, a large electric field peak is generated on one side of the edge of a gate electrode, which is close to the drain electrode, so that a local dielectric layer is degraded, time-lapse breakdown (TDDB) is caused, and the reliability of the device is seriously affected. In order to solve the serious electric field peak problem, the prior art generally adopts to place one or more field plates at the grid position, inhibit the peak height and improve the reliability of the device.
Because of the planar channel structure of the AlGaN/GaN HEMT and the introduction of multiple field plates into the device, problems are caused, for example, in a HEMT device disclosed in the patent publication No. CN1938859a, as shown in fig. 1, the HEMT device comprises a substrate 01, a buffer layer 02, a channel layer 03, a barrier layer 04, a source 05, a first dielectric layer 06, a second dielectric layer 061, a drain 07 and a gate 08, multiple field plates are required to suppress electric field peaks in order to withstand high voltages of the device, but in order to suppress electric field peaks, the distance between the gate electrode and the field plate and the drain electrode needs to be sufficiently large, and the increase of the gate-drain spacing of the planar channel structure of the AlGaN/GaN HEMT directly results in the increase of the source-drain spacing in the horizontal direction, and the conduction internal resistance R in the unit area of the device on The method is high, in order to realize the multi-field plate, a plurality of field plates with different heights are required to be formed through a plurality of dielectric layers, and additional 2-5 steps of process steps are added, so that the process complexity and the processing cost are increased, and meanwhile, the hidden danger of introducing defects in the process is increased due to the excessive process steps, and the reliability of the device is affected; in addition, due to the planar channel structure of the AlGaN/GaN HEMT, a large number of uniformly distributed functional units are connected in parallel on the surface of the chip, and the functional units are composed of a source electrode, a drain electrode and a gate electrodeThe electrode is composed, so that a large number of source electrodes, drain electrodes and gate electrodes are densely distributed on the surface of the chip, the chip is required to be subjected to electrode redistribution for 2-4 times, the electrodes are intensively distributed and can be used for subsequent wire bonding or surface mounting, and the electrode processing cost and parasitic capacitance are increased; another HEMT device disclosed in the patent publication No. CN104332498A, as shown in fig. 2, includes a substrate 01, a buffer layer 02, a nucleation layer 021, a channel layer 03, a barrier layer 04, a source 05, a first dielectric layer 06, a drain 07, a gate 08 and a field plate 081, which simplifies the manufacturing process of the field plate by setting the field plate, but the electrode wiring process is still complex, and the distance between the source and the drain is larger, resulting in larger on-resistance of the unit area of the device.
Therefore, it is urgently needed to find a preparation method of HEMT device which reduces on-resistance of unit area of the device and simplifies field plate manufacturing process and electrode manufacturing process of the device.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an HMET device and a method for manufacturing the same, which are used for solving the problems of complex manufacturing process of a multi-field plate, complex electrode wiring process and large on-resistance per unit area in the HEMT device in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a HEMT device, including the following steps:
providing a substrate, and forming a plurality of grooves which are arranged at intervals on the upper surface layer of the substrate;
forming a laminated structure with preset thickness on the exposed surface of the groove and the upper surface of the substrate, wherein the laminated structure comprises a buffer layer, a channel layer and a barrier layer which are laminated in sequence;
forming a first dielectric layer filling the groove and covering the exposed surface of the laminated structure, forming a gate hole in the groove in the first dielectric layer, wherein the bottom surface and the inner wall of the gate hole are spaced from the laminated structure by a preset distance;
forming a gate conductive layer filling the gate hole, and forming a second dielectric layer covering the first dielectric layer and the exposed upper surface of the gate conductive layer;
Forming a drain electrode contact hole and a gate electrode contact hole penetrating through the second dielectric layer, wherein the bottom of the drain electrode contact hole at least exposes the barrier layer above the substrate between two adjacent grooves, and the bottom of the gate electrode contact hole exposes the gate conductive layer;
forming a drain electrode filling the drain electrode contact hole, and forming a gate electrode filling the gate electrode contact hole;
a source is formed in electrical connection with at least the substrate and the channel layer.
Optionally, an angle between the inner wall of the groove and the bottom surface of the groove ranges from 90 ° to 150 °.
Optionally, the stacked structure further includes a nucleation layer located at a bottom layer of the stacked structure, and the nucleation layer covers the exposed surface of the trench and the upper surface of the substrate.
Optionally, after the stacked structure is formed and before the first dielectric layer is formed, a step of forming a source contact hole located at the bottom of the trench and penetrating through the stacked structure is further included, and the source fills the source contact hole.
Optionally, after the laminated structure is formed and before the first dielectric layer is formed, a step of forming a third dielectric layer and a conductive block is further included, wherein the third dielectric layer covers the exposed upper surface of the laminated structure, the conductive block is located on the surface of the third dielectric layer above the inner wall of the trench, and the bottom surface of the gate hole exposes the conductive block.
Optionally, the gate holes in the trenches are in communication with each other.
Optionally, an included angle between the inner wall of the gate hole and the bottom surface of the gate hole is not less than 90 ° and not greater than an included angle between the bottom surface of the trench and the inner wall of the trench.
Optionally, the drain electrode further covers an upper surface of the second dielectric layer, and the gate electrode is spaced from the drain electrode by a predetermined distance.
Optionally, after forming the drain electrode and the gate electrode, the method further includes a step of thinning the substrate from a bottom surface of the substrate, and after thinning the substrate, a bottom surface of the device at least reveals the channel layer above the trench bottom surface, and the source electrode at least covers the bottom surface of the substrate and an exposed surface of the channel layer.
Optionally, after forming the gate and the drain, a step of forming a source contact hole in the bottom of the substrate, wherein the bottom of the source contact hole at least exposes the channel layer above the bottom surface of the trench, and the source at least fills the source contact hole.
The invention also provides a HEMT device, which comprises:
a substrate provided with a plurality of grooves arranged at intervals;
the laminated structure comprises a buffer layer, a channel layer and a barrier layer which are sequentially laminated, and covers the exposed surface of the groove and the upper surface of the substrate;
The first dielectric layer fills the groove and covers the exposed surface of the laminated structure, a grid hole positioned in the groove is arranged in the first dielectric layer, and the bottom surface and the inner wall of the grid hole are spaced from the laminated structure by a preset distance;
a gate conductive layer filling the gate hole;
a second dielectric layer covering the exposed upper surfaces of the first dielectric layer and the gate conductive layer;
a drain contact hole and a gate contact hole, wherein the drain contact hole penetrates through the second dielectric layer, the bottom of the drain contact hole at least exposes the barrier layer above the substrate between two adjacent trenches, and the gate contact hole penetrates through the second dielectric layer, and the bottom of the gate contact hole exposes the gate conductive layer;
the drain electrode fills the drain contact hole, and the grid electrode fills the grid contact hole;
and a source electrode electrically connected with at least the substrate and the channel layer.
The HEMT device and the preparation method thereof of the invention form the groove in the substrate by improving the manufacturing process of the device,forming a laminated structure covering the inner wall of the groove, the bottom surface of the groove and the upper surface of the substrate, forming a first dielectric layer filling the groove in the groove, forming a gate hole and a gate conducting layer filling the gate hole in the first dielectric layer of the groove, synchronously forming a drain electrode electrically connected with the laminated structure on the upper surface of the substrate and a grid electrode electrically connected with the gate conducting layer, forming a source electrode electrically connected with the laminated structure on the bottom of the groove, and further enabling the source electrode and the drain electrode to be in different planes, simplifying the wiring process of device electrodes, increasing the arrangement area of each electrode, reducing the manufacturing difficulty of the electrodes of the device, and improving the heat conduction capability of the device; because the source electrode is electrically connected with the substrate, the source drain parasitic capacitance C of the device can be effectively reduced ds The switching characteristic of the device is effectively improved, and dynamic resistance amplification of the device can be reduced by electrically connecting the substrate with the source electrode; the inner wall of the groove is inclined, so that the effective area of two-dimensional electron gas in the device is increased, the on-resistance of the unit area of the device is reduced, and meanwhile, the horizontal distance between the source electrode and the drain electrode can be shortened, and the size of the device is further reduced; forming the grid electrode hole in the groove, regulating and controlling the distance between the grid electrode conducting layer and the barrier layer by regulating the included angle between the inner wall of the grid electrode hole and the bottom surface of the grid electrode hole, reducing the electric field intensity of a conducting channel near the drain electrode end at two sides of the grid electrode conducting layer, improving the breakdown voltage of the device, inhibiting the current collapse effect of the device, and simplifying the manufacturing process of the grid field plate of the device; in addition, the third dielectric layer and the conductive block which is positioned on the third dielectric layer on the inner wall of the groove and is electrically connected with the gate conductive layer can enhance the control capability of the gate, further improve the performance of the device and have high industrial utilization value.
Drawings
Fig. 1 is a schematic cross-sectional structure of a HEMT device.
Fig. 2 is a schematic cross-sectional structure of another HEMT device.
Fig. 3 is a schematic cross-sectional structure of a substrate of the method for manufacturing a HEMT device according to the present invention.
Fig. 4 is a schematic cross-sectional structure of the HEMT device according to the present invention after forming a trench.
Fig. 5 is a schematic cross-sectional view of a HEMT device according to the present invention after forming a stacked structure.
Fig. 6 is a schematic cross-sectional structure of a HEMT device according to the present invention after forming a source at the bottom of a trench before forming a first dielectric layer.
Fig. 7 is a schematic cross-sectional structure of the HEMT device according to the present invention after forming the third dielectric layer and the conductive block.
Fig. 8 is a schematic cross-sectional structure of the HEMT device according to the present invention after forming the first dielectric layer.
Fig. 9 is a schematic cross-sectional structure of the HEMT device according to the present invention after forming a gate hole.
Fig. 10 is a schematic cross-sectional structure of the HEMT device according to the present invention after forming a gate conductive layer.
Fig. 11 is a schematic cross-sectional structure of the HEMT device according to the present invention after forming the second dielectric layer.
Fig. 12 is a schematic cross-sectional structure of the HEMT device according to the present invention after forming the drain contact hole and the gate contact hole.
Fig. 13 is a schematic cross-sectional structure of the HEMT device according to the present invention after a conductive material layer is formed.
Fig. 14 is a schematic cross-sectional structure of the HEMT device according to the present invention after forming the gate and the drain.
Fig. 15 is a schematic cross-sectional view of another method for manufacturing a HEMT device according to the present invention after forming a gate and a drain.
Fig. 16 is a schematic diagram showing the distribution of the gate and the drain in the method for manufacturing the HEMT device of the present invention.
Fig. 17 is a schematic cross-sectional structure of a HEMT device according to the present invention after forming a source electrode on the bottom of a substrate.
Fig. 18 is a schematic cross-sectional view illustrating another method for manufacturing a HEMT device according to the present invention after forming a source electrode on the bottom of a substrate.
Fig. 19 is a schematic diagram showing a third cross-sectional structure of the HEMT device according to the present invention after forming a source electrode on the bottom of the substrate.
Fig. 20 is a schematic diagram showing a fourth cross-sectional structure of the HEMT device according to the present invention after forming a source electrode on the bottom of the substrate.
Fig. 21 is a schematic perspective view of a HEMT device according to the present invention.
Description of the reference numerals
01. Substrate and method for manufacturing the same
02. Buffer layer
021. Nucleation layer
03. Channel layer
04. Barrier layer
05. Source electrode
06. A first dielectric layer
061. Second dielectric layer
07. Drain electrode
08. Grid electrode
081. Field plate
1. Substrate and method for manufacturing the same
11. Groove(s)
12. Source electrode contact hole
13. Source electrode
2. Laminated structure
20. Nucleation layer
21. Buffer layer
22. Channel layer
23. Barrier layer
3. A first dielectric layer
31. Grid electrode hole
4. Third dielectric layer
41. Conductive block
5. Gate conductive layer
6. Second dielectric layer
61. Drain electrode contact hole
62. Gate contact hole
7. Drain electrode
70. Conductive material layer
8. Grid electrode
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 3 to 21. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The embodiment provides a preparation method of an HMET device, which comprises the following steps:
s1: providing a substrate, and forming a plurality of grooves which are arranged at intervals on the upper surface layer of the substrate;
s2: forming a laminated structure with preset thickness on the exposed surface of the groove and the upper surface of the substrate, wherein the laminated structure comprises a buffer layer, a channel layer and a barrier layer which are laminated in sequence;
S3: forming a first dielectric layer filling the groove and covering the exposed surface of the laminated structure, forming a gate hole in the groove in the first dielectric layer, wherein the bottom surface and the inner wall of the gate hole are spaced from the laminated structure by a preset distance;
s4: forming a gate conductive layer filling the gate hole, and forming a second dielectric layer covering the first dielectric layer and the exposed upper surface of the gate conductive layer;
s5: forming a drain electrode contact hole and a gate electrode contact hole penetrating through the second dielectric layer, wherein the bottom of the drain electrode contact hole at least exposes the barrier layer above the substrate between two adjacent grooves, and the bottom of the gate electrode contact hole exposes the gate conductive layer;
s6: forming a drain electrode filling the drain electrode contact hole, and forming a gate electrode filling the gate electrode contact hole;
s7: a source is formed in electrical connection with at least the substrate and the channel layer.
Referring to fig. 3 to 7, the steps S1 and S2 are performed: providing a substrate 1, and forming a plurality of grooves 11 on the upper surface layer of the substrate 1 at intervals; a laminated structure 2 with a predetermined thickness is formed on the exposed surface of the trench 11 and the upper surface of the substrate 1, and the laminated structure 2 includes a buffer layer 21, a channel layer 22 and a barrier layer 23 which are sequentially laminated.
Specifically, as shown in fig. 3, a schematic cross-sectional structure of the substrate 1 is shown, where the size, thickness and shape of the substrate 1 may be selected according to practical situations under the condition of ensuring the performance of the device, and the present invention is not limited.
Specifically, as shown in fig. 4, to schematically illustrate a cross-sectional structure after forming the trench 11, the forming the trench 11 includes the following steps: forming a patterned first shielding layer (not shown) on the upper surface of the substrate 1, and patterning the first shielding layer; the substrate 1 is etched based on the patterned first masking layer to obtain the trench 11.
Specifically, the first masking layer includes photoresist or other suitable developer material. In this embodiment, a photoresist is used as the first shielding layer.
Specifically, the method for forming the first shielding layer and patterning the first shielding layer is a conventional photoresist forming and developing method, and will not be described herein.
Specifically, the method of etching the substrate 1 includes dry etching, wet etching, or other suitable methods.
Specifically, the depth of the trench 11 ranges from 5 μm to 30 μm, where the depth refers to the distance between the bottom surface of the trench 11 and the opening of the trench 11 (the upper surface of the substrate 1).
As an example, the angle between the inner wall of the groove 11 and the bottom surface of the groove 11 ranges from 90 ° to 150 °.
Specifically, under the condition of ensuring the performance of the device, the opening size of the trench 11 and the distance between two adjacent trenches 11 may be selected according to the actual situation, and are not limited herein.
As an example, as shown in fig. 5, to illustrate a cross-sectional structure of the stacked structure 2 after forming the stacked structure 2, the stacked structure 2 further includes a nucleation layer 20 located at a bottom layer of the stacked structure 2, where the nucleation layer 20 covers an exposed surface of the trench 11 and an upper surface of the substrate 1.
In particular, the buffer layer 21 is located on top of the nucleation layer 20, the buffer layer 21 being capable of blocking the diffusion of ions and also being used for bonding other layers of semiconductor material to be grown thereon.
Specifically, the channel layer 22 is located on the buffer layer 21, the barrier layer 23 is located on the channel layer 22, and the barrier layer 23 and the channel layer 22 form a heterojunction structure, thereby forming a two-dimensional electron gas (2 DEG) channel at a heterojunction interface between the barrier layer 23 and the channel layer 22.
Specifically, the nucleation layer 20, the buffer layer 21, the channel layer 22 and the barrier layer 23 are formed by a common film epitaxy process, and will not be described herein.
As an example, after the stacked structure 2 is formed and before the first dielectric layer 3 is formed, a step of forming a source contact hole 12 located at the bottom of the trench 11 and penetrating the stacked structure 2 is further included, wherein the source electrode 13 fills the source contact hole 12, that is, after the step S2 is performed and before the step S3 is performed, the step S7 is performed: a source electrode 13 is formed to be electrically connected to at least the substrate 1 and the channel layer 22.
Specifically, forming the source contact hole 12 includes the following steps: forming a patterned second shielding layer (not shown) on the exposed surface of the laminated structure 2; the stacked structure 2 at the bottom of the trench 11 is etched based on the patterned second shielding layer to form the source contact hole 12 penetrating through the stacked structure 2, and the bottom surface of the source contact hole 12 exposes the substrate 12, so as to facilitate the electrical connection between the source 13 and the substrate 1.
Specifically, the material of the second shielding layer includes photoresist or other suitable developing materials; the method for forming the second shielding layer and patterning the second shielding layer is a conventional photoresist forming and developing method, and will not be described herein.
Specifically, the depth and opening size of the source contact hole 12 may be selected according to the actual situation, while ensuring the device performance, which is not limited.
As an example, as shown in fig. 6, before forming the first dielectric layer 3, the source 13 is formed at the bottom of the trench 11, and the source 13 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.
Specifically, the method of forming the source electrode 13 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, after the source electrode 13 is formed in the source electrode contact hole 12, before the first dielectric layer 3 is formed, a step of removing the second shielding layer is further included, and a method of removing the second shielding layer is a common photoresist stripping method, which is not described herein again.
As an example, as shown in fig. 7, after forming the laminated structure 2, before forming the first dielectric layer 3, the method further includes a step of forming the third dielectric layer 4 and the conductive block 41, wherein the third dielectric layer 4 covers the exposed upper surface of the laminated structure 2, the conductive block 41 is located on the surface of the third dielectric layer 4 above the inner wall of the trench 11, and the bottom surface of the gate hole 31 exposes the conductive block 41.
Specifically, the method for forming the third dielectric layer 4 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the thickness of the third dielectric layer 4 may be selected according to practical situations, without limitation, while ensuring the device performance.
Specifically, the method of forming the conductive block 41 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, in the case where the conductive block 41 is exposed at the bottom of the gate hole (see fig. 10) formed later and the device performance is ensured, the thickness, size and shape of the conductive block 41 may be selected according to practical situations, and are not limited.
Referring to fig. 8 to 9, the step S3 is performed: forming a first dielectric layer 3 filling the trench 11 and covering the exposed surface of the laminated structure 2, forming a gate hole 31 in the trench 11 in the first dielectric layer 3, wherein the bottom surface and the inner wall of the gate hole 31 are spaced from the laminated structure 2 by a preset distance.
Specifically, as shown in fig. 8, after the stacked structure 2 is formed, the first dielectric layer 3 is directly formed to fill the trench 11 and cover the exposed surface of the stacked structure 2, and the method for forming the first dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable method.
Specifically, since the first dielectric layer 3 fills the trench 11, after the first dielectric layer 3 is formed, the upper surface of the first dielectric layer 3 may be rugged, and therefore, after the first dielectric layer 3 is formed, the upper surface of the first dielectric layer 3 needs to be planarized to planarize the upper surface of the first dielectric layer 3, and at the same time, the first dielectric layer 3 may be thinned to a predetermined thickness of the first dielectric layer 3 located on the upper surface of the substrate 1.
Specifically, the method for planarizing the first dielectric layer 3 includes chemical mechanical polishing or other suitable method.
Specifically, the thickness of the first dielectric layer 3 above the substrate 1 after planarization can be selected according to practical situations, and is not limited herein.
Specifically, as shown in fig. 9, to schematically illustrate a cross-sectional structure of the gate hole 31 after forming the gate hole 31, the step of forming the gate hole 31 includes: a patterned third shielding layer (not shown) is formed on the upper surface of the first dielectric layer 3, and the first dielectric layer 3 is etched based on the patterned third shielding layer to obtain the gate hole 31 in the trench 11.
Specifically, the material of the third shielding layer includes photoresist or other suitable developing materials; the method for forming the third shielding layer and patterning the third shielding layer is a conventional photoresist forming and developing method, and will not be described herein.
Specifically, the method of etching the first dielectric layer 3 includes dry etching, wet etching, or other suitable methods.
As an example, the angle between the inner wall of the gate hole 31 and the bottom surface of the gate hole 31 is not less than 90 ° and not more than the angle between the bottom surface of the trench 11 and the inner wall of the trench 11.
Specifically, under the condition of ensuring the performance of the device, the opening size and depth of the gate hole 31 may be selected according to the actual situation, which is not limited herein; the distance between the inner wall of the gate hole 31 and the inner wall of the trench 11 and the distance between the bottom surface of the gate hole 31 and the upper surface of the stacked structure 2 located below the gate hole 31 may be selected according to practical situations, and are not limited herein. The depth here refers to the distance between the bottom surface of the gate hole 31 and the opening of the gate hole 31.
As an example, the gate holes 31 in the trenches 11 communicate with each other to facilitate extraction of the gate of the device.
Referring to fig. 10 to 16, the steps S4, S5 and S6 are performed: forming a gate conductive layer 5 filling the gate hole 31, and forming a second dielectric layer 6 covering the first dielectric layer 3 and the exposed upper surface of the gate conductive layer 5; forming a drain contact hole 61 and a gate contact hole 62 penetrating through the second dielectric layer 6, wherein the bottom of the drain contact hole 61 at least exposes the barrier layer 23 above the substrate 1 between two adjacent trenches 11, and the bottom of the gate contact hole 62 exposes the gate conductive layer 5; a drain electrode 7 filling the drain contact hole 61 is formed, and a gate electrode 8 filling the gate contact hole 62 is formed.
Specifically, as shown in fig. 10, to schematically illustrate the cross-sectional structure of the gate conductive layer 5 after forming the gate conductive layer 5, the method for forming the gate conductive layer 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, after the gate conductive layer 5 is formed and before the second dielectric layer 6 is formed, the step of removing the third shielding layer is further included, and the method of removing the third shielding layer is a common photoresist stripping method, which is not described herein again.
Specifically, as shown in fig. 11, to schematically illustrate the cross-sectional structure of the second dielectric layer 6 after forming the second dielectric layer 6, the method for forming the second dielectric layer 6 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the thickness, size and shape of the second dielectric layer 6 may be selected according to practical situations, and are not limited herein, while ensuring the performance of the device.
Specifically, as shown in fig. 12, in order to form the drain contact hole 61 and the gate contact hole 62, the step of forming the drain contact hole 61 and the gate contact hole 62 includes the steps of: forming a patterned fourth shielding layer (not shown) on the upper surface of the second dielectric layer 6; the second dielectric layer 6 is etched based on the patterned fourth masking layer to obtain the drain contact hole 61 penetrating the second dielectric layer 6 and having a bottom surface exposing at least the barrier layer 23 and the gate contact hole 62 having a bottom surface exposing the gate conductive layer 5.
Specifically, the material of the fourth shielding layer includes photoresist or other suitable developing materials; the method for forming the fourth shielding layer and patterning the fourth shielding layer is a conventional photoresist forming and developing method, and will not be described herein.
Specifically, the drain contact hole 61 and the gate contact hole 62 may be formed in steps, that is, the drain contact hole 61 and the gate contact hole 62 may be formed separately, while ensuring the device performance.
Specifically, the method for forming the drain contact hole 61 and the gate contact hole 62 includes dry etching, wet etching, or other suitable methods.
Specifically, in the case where the formed drain electrode and the barrier layer 23 form ohmic contact and are electrically insulated from the substrate 1, the depth of the drain contact hole 61 may be selected according to practical situations, for example, the bottom surface of the drain contact hole 61 may expose the barrier layer 23 above the substrate 1, may expose the channel layer 22 above the substrate 1, may expose the buffer layer 21 above the substrate 1, or may penetrate the stacked structure 2, but when the drain contact hole 61 penetrates the stacked structure 2, since the substrate 1 is a non-insulating substrate, in order to ensure the performance of the device, an insulating material for isolating the drain electrode 7 from the substrate 1 needs to be formed on the bottom surface of the drain contact hole 61 for forming the drain electrode 7, so as to ensure the performance of the device. The depth here refers to the distance between the bottom surface of the drain contact hole 61 and the opening of the drain contact hole 61.
Specifically, when the third dielectric layer 4 is formed on the upper surface of the stacked structure 2, the drain contact hole 61 also penetrates through the third dielectric layer 4.
Specifically, after forming the drain contact hole 61 and the gate contact hole 62, before forming the gate electrode 8 and the drain electrode 7, the method further includes a step of removing the fourth shielding layer, where the method of removing the fourth shielding layer is a commonly used photoresist stripping method, and will not be described herein.
Specifically, as shown in fig. 13, 14, 15 and 16, the cross-sectional structure of the conductive material layer 70 after forming, one cross-sectional structure of the drain electrode 7 and the gate electrode 8 after forming, another cross-sectional structure of the drain electrode 7 and the gate electrode 8 after forming, and the distribution of the gate electrode 8 and the drain electrode 7 are respectively shown, and the method for forming the drain electrode 7 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the gate electrode 8 may be formed by magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. In this embodiment, the drain electrode 7 and the gate electrode 8 are formed simultaneously, that is, the conductive material layer 70 filling the drain contact hole 61 and the gate contact hole 62 is formed simultaneously, and then the conductive material layer 70 is patterned to obtain the drain electrode 7 and the gate electrode 8.
As an example, the drain electrode 7 also covers the upper surface of the second dielectric layer 6, and the gate electrode 8 is spaced apart from the drain electrode 7 by a predetermined distance.
Specifically, the distance between the gate electrode 8 and the drain electrode 7 may be selected according to the actual situation, while ensuring the device performance, and is not limited here.
Referring to fig. 17 to 20, the step S7 is performed: a source electrode 13 is formed to be electrically connected to at least the substrate 1 and the channel layer 22.
As an example, after forming the drain electrode 7 and the gate electrode 8, the method further includes a step of thinning the substrate 1 from the bottom surface of the substrate 1, and after thinning the substrate 1, the bottom surface of the device reveals at least the channel layer 22 above the bottom surface of the trench 11, and the source electrode 13 covers at least the bottom surface of the substrate 1 and the exposed surface of the channel layer 22, that is, when the step S7 is not performed before the step S3 is performed, after the step S6 is performed, before the step S7 is performed, thinning the substrate 1 so that the bottom surface of the structure after the drain electrode 7 and the gate electrode 8 is formed reveals the channel layer 22, so as to perform the step S7.
Specifically, the method of thinning the substrate 1 may be chemical mechanical polishing, dry etching, wet etching, laser lift-off, or other suitable method.
Specifically, in the case of ensuring the device performance, the barrier layer 23 or the first dielectric layer 3 may be exposed after the substrate 1 is thinned, and when the third dielectric layer 4 is formed on the upper surface of the stacked structure 2, the third dielectric layer 4 may be exposed after the substrate 1 is thinned.
Specifically, as shown in fig. 17, 18 and 19, a schematic cross-sectional structure after forming the source electrode 13 on the bottom surface of the substrate 1, and a schematic cross-sectional structure after forming the source electrode 13 on the bottom surface of the substrate 1 are respectively shown, wherein the source electrode 13 covers the exposed surface of the device structure after thinning the substrate 1, that is, after thinning the substrate 1, the source electrode 13 is directly formed on the bottom surface of the structure after thinning the substrate 1, and the source electrode 13 forms ohmic contact with the channel layer 22.
As an example, after forming the gate electrode 8 and the drain electrode 7, the method further includes a step of forming a source contact hole 12 at the bottom of the substrate 1, wherein the bottom of the source contact hole 12 at least exposes the channel layer 22 above the bottom surface of the trench 11, and the source electrode 13 at least fills the source contact hole 12, that is, when the step S7 is not performed before the step S3 is performed, after the step S6 is performed, before the step S7 is performed, the substrate 1 is etched from the bottom surface of the substrate 1, so as to obtain the source contact hole 12 with the bottom at least exposing the channel layer 22.
Specifically, when the step S7 is not performed before the step S3 is performed, after the step S6 is performed, before the step S7 is performed, the bottom surface of the source contact hole 12 formed at the bottom of the substrate 1 may expose the channel layer 22 above the bottom of the trench 11, may expose the barrier layer 23 above the bottom of the trench 11, may also expose the first dielectric layer 3 above the bottom of the trench 11, and when the third dielectric layer 4 is formed on the upper surface of the stacked structure 2, the bottom surface of the source contact hole 12 may also be the third dielectric layer 4 above the bottom of the trench 11.
Specifically, in the case of ensuring the device performance, after the drain electrode 7 and the gate electrode 8 are formed, the shape and the opening size of the source contact hole 12 formed at the bottom of the substrate 1 may be selected according to the actual situation, and are not limited.
Specifically, after forming the drain electrode 7 and the gate electrode 8, a method of forming the source contact hole 12 at the bottom of the substrate 1 includes dry etching, wet etching, or other suitable method.
Specifically, as shown in fig. 20, in order to form a schematic cross-sectional structure of the source electrode 13 filling the source contact hole 12, after forming the source contact hole 12 at the bottom of the substrate 1, the method further includes forming the source electrode 13 filling the source contact hole 12 and covering the bottom surface of the substrate 1.
Specifically, since the source electrode 13 is electrically connected to the stacked structure 2 located at the bottom of the trench 11, the drain electrode 7 is electrically connected to the stacked structure 2 located on the upper surface of the substrate 1 between two adjacent trenches 11, so that the source electrode 13 and the drain electrode 7 are located in different planes, only one gate electrode 8 and one drain electrode 7 need to be formed on the front surface of the device, and the gate electrode 8 and the drain electrode 7 can be formed synchronously, thereby avoiding multiple electrode wiring and simplifying the electrode wiring process of the device.
Specifically, the grid electrode 8, the drain electrode 7 and the source electrode 13 are formed on different planes of the device, so that the arrangement area of each electrode of the device can be increased, the manufacturing difficulty of the electrode of the device is reduced, the electrode of the device is conveniently led out, and the heat conduction capability of the device can be improved.
Specifically, by forming the stacked structure 2 including the channel layer 22 and the barrier layer 23 on the bottom surface and the inclined inner wall of the trench 11, the area of the effective two-dimensional electron gas between the source electrode 13 and the drain electrode 7 is greatly increased, and the on-resistance of the device per unit area is reduced.
Specifically, the gate holes 31 are formed to be mutually communicated and deeper by single etching, the gate holes 31 are located in the first dielectric layer 3 filling the trenches 11, the gate conductive layer 5 filling the gate holes 31 is formed, then a gate field plate perpendicular to the bottom surface of the trenches 11 is formed, the electric field strength of the conductive channels on two sides of the gate conductive layer 5 near the drain electrode 7 is reduced, then the breakdown voltage of the device is improved, meanwhile, the probability that electrons in the conductive channels of the device enter a surface state due to excitation of a strong electric field is reduced, the current collapse effect of the device is suppressed, and the process for manufacturing the gate field plate is simplified.
Specifically, when the included angle between the inner wall of the gate hole 31 and the bottom surface of the gate hole 31 is greater than 90 ° (i.e., the inner wall of the gate hole 31 is inclined), the distance between the gate field plate of the device and the barrier layer 23 may be changed, so as to control the distance between the gate field plate and the stacked structure 2.
Specifically, since the source electrode 13 is electrically connected with the substrate 1, the source drain parasitic capacitance C of the device can be effectively reduced ds In turn, device switching characteristics may be improved.
Specifically, the substrate 1 and the source electrode 13 are electrically connected, so that dynamic resistance amplification of the device can be effectively reduced, and performance of the device can be improved.
According to the preparation method of the HEMT device, the structure of the device is improved, the inner wall of the groove 11 and the exposed upper surface of the substrate 1 are formed in the substrate 1, the laminated structure 2 is formed, the gate conducting layer 5 is formed, the source electrode 13 electrically connected with the laminated structure 2 at the bottom of the groove 11 and the drain electrode 7 electrically connected with the laminated structure 2 on the upper surface of the substrate 1 are formed, the source electrode 13 and the drain electrode 7 are located on different planes, the grid electrode 8 and the drain electrode 7 are synchronously formed on the front surface of the substrate, and the source electrode 13 is formed on the back surface of the substrate 1, so that multiple wiring on the front surface of the device is avoided, the electrode wiring process of the device is simplified, the arrangement area of each electrode of the device is increased, the manufacturing difficulty of each electrode of the device is reduced, and meanwhile, the heat conduction capability of the device can be improved; since the inner wall of the trench 11 is inclined, the area of the effective electron gas between the source electrode 13 and the drain electrode 7 is increased, and the on-resistance of the unit area of the device can be reduced; because the gate hole 31 is located in the first dielectric layer 3 filling the trench 11 and is mutually communicated, the gate conductive layer 5 corresponding to the gate field plate of the device is formed in the gate hole 31, the electric field intensity of the conductive channels on two sides of the gate conductive layer 5 near the end of the drain electrode 7 is reduced, the breakdown voltage of the device can be improved, the probability that electrons in the conductive channels of the device enter a surface state under excitation of a strong electric field is reduced, the current collapse effect of the device is inhibited, the gate field plate does not need to be manufactured for many times, and the manufacturing process of the gate field plate is simplified. In addition, the source electrode 13 is electrically connected with the substrate 1, so that the source drain parasitic capacitance C of the device can be effectively reduced ds Thus, the switching characteristics of the device are effectively improved, and the dynamic resistance increase of the device can be effectively reduced by electrically connecting the substrate 1 with the source electrode 13.
Example two
The present embodiment provides a HEMT device, as shown in fig. 15, 17, 18, 19, 20 and 21, which is a schematic diagram of a cross-sectional structure of the HEMT device, a schematic diagram of another cross-sectional structure of the HEMT device, a schematic diagram of a third cross-sectional structure of the HEMT device, a schematic diagram of a fourth cross-sectional structure of the HEMT device, a schematic diagram of a fifth cross-sectional structure of the HEMT device and a schematic diagram of a three-dimensional structure of the HEMT device, including: a substrate 1, a laminated structure 2, a first dielectric layer 3, a gate conductive layer 5, a second dielectric layer 6, a drain contact hole 61, a gate contact hole 62, a drain 7, a gate 8 and a source 13, wherein a plurality of grooves 11 are arranged in the substrate 1 at intervals; the laminated structure 2 comprises a buffer layer 21, a channel layer 22 and a barrier layer 23 which are sequentially laminated, wherein the laminated structure 2 covers the exposed surface of the groove 11 and the upper surface of the substrate 1; the first dielectric layer 3 fills the trench 11 and covers the exposed surface of the laminated structure 2, and a gate hole 31 located in the trench 11 is provided in the first dielectric layer 3, and the bottom surface and the inner wall of the gate hole 31 are spaced from the laminated structure 2 by a preset distance; the gate conductive layer 5 fills the gate hole 31; the second dielectric layer 6 covers the first dielectric layer 3 and the exposed upper surface of the gate conductive layer 5; the drain contact hole 61 penetrates through the second dielectric layer 6 and the bottom of the drain contact hole at least exposes the barrier layer 23 above the substrate 1 between two adjacent trenches 11, and the gate contact hole 62 penetrates through the second dielectric layer 6 and the bottom of the drain contact hole exposes the gate conductive layer 5; the drain electrode 7 fills the drain contact hole 61, and the gate electrode 8 fills the gate contact hole 62; the source 13 is electrically connected to at least the substrate 1 and the channel layer 22.
Specifically, the material of the substrate 1 includes one or more of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire and germanium, and may be other materials capable of growing a group III nitride material.
Specifically, the included angle between the inner wall of the groove 11 and the bottom surface of the groove 11 is in the range of 90 ° to 150 °.
Specifically, the bottom layer of the laminated structure 2 is further provided with a nucleation layer 20, and the nucleation layer 20 covers the exposed surface of the trench 11 and the exposed upper surface of the substrate 1.
Specifically, the nucleation layer 20 may be made of GaN, alGaN, alN, inAlGaN, inGaN, inAlN, inN or other suitable group III nitride material.
Specifically, the material of the buffer layer 21 includes GaN, alGaN, alN, inAlGaN, inGaN, inAlN, inN or other suitable group III nitride material.
Specifically, the material of the channel layer 22 includes GaN, alGaN, alN, inAlGaN, inGaN, inAlN, inN or other suitable III-nitride semiconductor material.
Specifically, the material of the barrier layer 23 includes GaN, alGaN, alN, inAlGaN, inGaN, inAlN, inN or other suitable III-nitride semiconductor material.
Specifically, the material of the first dielectric layer 3 includes SiN and SiO 2 、SiON、Al 2 O 3 At least one of them may be a suitable dielectric material.
Specifically, the material of the gate conductive layer 5 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or a combination thereof, or other suitable conductive material.
Specifically, the material of the second dielectric layer 6 includes SiN and SiO 2 、SiON、Al 2 O 3 At least one of them may be a suitable dielectric material. In this embodiment, the first dielectric layer 3 and the second dielectric layer 6 are made of the same material.
Specifically, a third dielectric layer 4 and a conductive block 41 are further disposed in the HEMT device, the third dielectric layer 4 covers the exposed upper surface of the stacked structure 2, the conductive block 41 covers the surface of the third dielectric layer 4 above the inner wall of the trench 11, and the bottom surface of the gate hole 31 exposes the conductive block 41.
Specifically, the material of the third dielectric layer 4 includes SiN and SiO 2 、SiON、Al 2 O 3 At least one of them may be a suitable dielectric material.
Specifically, the conductive block 41 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.
Specifically, a source contact hole 12 is further provided at the bottom of the trench 11, the source 13 fills the source contact hole 12, the source contact hole 12 penetrates through the laminated structure 2 and the bottom surface of the source contact hole exposes the substrate 1, when the third dielectric layer 4 is provided in the device, the source contact hole 12 also penetrates through the third dielectric layer, the source contact hole 12 and the conductive block 41 are spaced by a preset distance, and the source 13 and the conductive block 41 are spaced by a preset distance.
Specifically, when the third dielectric layer 4 and the conductive block 41 are provided in the device, the distance between the source 13 and the conductive block 41 may be selected according to the actual situation while ensuring the device performance, and is not limited herein.
Specifically, the distance between the bottom surface of the gate hole 31 and the source electrode 13 may be selected according to the actual situation, while ensuring the device performance, and is not limited here.
Specifically, the included angle between the inner wall of the gate hole 31 and the bottom surface of the gate hole 31 is not smaller than 90 ° and not larger than the included angle between the bottom surface of the trench 11 and the inner wall of the trench 11, and the inner wall of the gate hole 31 is spaced from the inner wall of the trench 11 by a preset distance.
Specifically, when the bottom of the trench 11 is not provided with the source contact hole 12 and the trench 11 penetrates through the substrate 1, the source 13 covers at least the exposed surface of the channel layer 22 located at the bottom of the trench 11 and the bottom surface of the substrate 1, that is, the channel layer 22 located at the bottom of the trench 11 may cover the source 13 located below the trench 11, the barrier layer 23 located at the bottom of the trench 11 may cover the source 13 located below the trench 11, the first dielectric layer 3 located at the bottom of the trench 11 may also cover the source 13 located below the trench 11, and when the exposed surface of the stacked structure 2 is provided with the third dielectric layer 4, the third dielectric layer 4 located at the bottom of the trench 11 may also cover the source 13 located below the trench 11.
Specifically, when the source contact hole 12 is not disposed at the bottom of the trench 11 and the trench 11 does not penetrate through the substrate 1, the source contact hole 12 that is open from the bottom surface of the substrate 1 is disposed at the bottom of the substrate 1, and the bottom surface of the source contact hole 12 at least exposes the channel layer 22 at the bottom of the trench 11, that is, the bottom surface of the source contact hole 12 may expose the channel layer 22 at the bottom of the trench 11, may expose the barrier layer 23 at the bottom of the trench 11, may expose the first dielectric layer 3 at the bottom of the trench 11, and may also expose the third dielectric layer 4 at the bottom of the trench 11 when the third dielectric layer 4 is disposed on the upper surface of the stacked structure 2.
Specifically, when the bottom of the substrate 1 is provided with the source contact hole 12 opened from the bottom surface of the substrate 1, the source 13 fills the source contact hole 12 and covers the bottom surface of the substrate 1.
Specifically, the opening size of the gate contact hole 62 may be selected according to the actual situation, while ensuring the performance of the device, which is not limited herein; the opening size of the drain contact hole 61 may be selected according to the actual practice, and is not limited herein.
Specifically, the drain electrode 7 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the gate electrode 8 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the source electrode 13 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.
Specifically, by adjusting the angle between the inner wall of the gate hole 31 and the bottom surface of the gate hole 31, the distance between the gate conductive layer 5 and the barrier layer 23 located on the inner wall of the trench 11 can be adjusted, so that the influence of the gate conductive layer 5 on the electric field intensity in the conductive channel of the device can be adjusted, and the device performance can be adjusted.
Specifically, by the arrangement of the third dielectric layer 4 and the conductive block 41, and the bottom of the gate hole 31 exposes the conductive block 41, that is, the conductive block 41 is electrically connected with the gate conductive layer 5, the capability of the gate 8 to control the turn-off of the conductive channel in the device can be enhanced, and the performance of the device is improved.
Specifically, the stacked structure 2 is disposed on the inner wall and the bottom surface of the trench 11 and the upper surface of the substrate 1, and the inner wall of the trench 11 is inclined, so that conductive channels (the area where the two-dimensional electron gas is located) in the device are obliquely distributed, the on-resistance of the unit area of the device is reduced, the performance of the device is ensured, the horizontal distance between the source electrode 13 and the drain electrode 7 is shortened, and then the size of the device is reduced.
According to the HEMT device of the embodiment, through optimizing the structure of the device, the stacked structure 2 comprising the channel layer 22 and the barrier layer 23 is arranged on the inner wall of the groove 11, the bottom surface of the groove 11 and the upper surface of the substrate 11, the source electrode 13 is electrically connected with the stacked structure 2 at the bottom of the groove 11, the drain electrode 7 is electrically connected with the stacked structure 2 on the upper surface of the substrate 1, and due to the fact that the inner wall of the groove 11 is inclined, the effective area of two-dimensional electron gas is increased, the on resistance of a unit area in the device is reduced, meanwhile, due to the fact that the source electrode 13 and the drain electrode 7 are located on different planes, the horizontal distance between the source electrode 13 and the drain electrode 7 is shortened while the performance of the device is guaranteed, and then the size of the device is reduced. In addition, by the arrangement of the third dielectric layer 4 and the conductive block 41, the control capability of the gate 8 to turn off the device is improved, and the performance of the device is improved.
In summary, by improving the device manufacturing process, the HEMT device and the method for manufacturing the HEMT device of the present invention form a trench with an inclined inner wall in a substrate, and form a stacked structure covering the inner wall of the trench, the bottom surface of the trench, and the upper surface of the substrate, the stacked structure including a stacked channel layer and a barrier layer, filling a first dielectric layer in the trench, and forming a gate hole in the first dielectric layer filling the trench, forming a gate conductive layer filling the gate hole, a drain electrically connected to the stacked structure on the upper surface of the substrate, and a source electrically connected to the stacked structure on the bottom of the trench, the source and the drain being in different planes, and the gate and the drain The synchronous formation simplifies the wiring process of the electrodes of the device, increases the arrangement area of the electrodes, reduces the manufacturing difficulty of the electrodes of the device, and improves the heat conduction capacity of the device; the inner wall of the groove is inclined, so that the effective area of the two-dimensional electron gas is increased, the on-resistance of the unit area of the device is reduced, and the horizontal distance between the source electrode and the drain electrode is shortened, so that the size of the device is reduced; forming a grid hole in the groove, controlling the distance between the grid conducting layer and the barrier layer by adjusting the inclination angle of the inner wall of the grid hole, reducing the electric field intensity of a conducting channel near the drain electrode ends at two sides of the grid conducting layer, improving the breakdown voltage of the device, inhibiting the current collapse effect of the device, avoiding manufacturing the grid conducting layer equivalent to a grid field plate for multiple times, and simplifying the manufacturing process of the grid field plate; the third dielectric layer and the conductive block which is positioned on the third dielectric layer on the inner wall of the groove and is electrically connected with the gate conductive layer are formed, so that the control capability of the gate can be enhanced, and the performance of the device is improved. In addition, the source electrode is electrically connected with the substrate, so that the source-drain parasitic capacitance C of the device can be effectively reduced ds Therefore, the switching characteristic of the device is improved, dynamic resistance amplification of the device can be reduced through electric connection between the source electrode and the substrate, and the performance of the device is further improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (11)
1. The preparation method of the HEMT device is characterized by comprising the following steps of:
providing a substrate, and forming a plurality of grooves which are arranged at intervals on the upper surface layer of the substrate;
forming a laminated structure with preset thickness on the exposed surface of the groove and the upper surface of the substrate, wherein the laminated structure comprises a buffer layer, a channel layer and a barrier layer which are laminated in sequence;
forming a first dielectric layer filling the groove and covering the exposed surface of the laminated structure, forming a gate hole in the groove in the first dielectric layer, wherein the bottom surface and the inner wall of the gate hole are spaced from the laminated structure by a preset distance;
forming a gate conductive layer filling the gate hole, and forming a second dielectric layer covering the first dielectric layer and the exposed upper surface of the gate conductive layer;
Forming a drain electrode contact hole and a gate electrode contact hole penetrating through the second dielectric layer, wherein the bottom of the drain electrode contact hole at least exposes the barrier layer above the substrate between two adjacent grooves, and the bottom of the gate electrode contact hole exposes the gate conductive layer;
forming a drain electrode filling the drain electrode contact hole, and forming a gate electrode filling the gate electrode contact hole;
a source is formed in electrical connection with at least the substrate and the channel layer.
2. The method for manufacturing a HEMT device according to claim 1, wherein: the included angle between the inner wall of the groove and the bottom surface of the groove ranges from 90 degrees to 150 degrees.
3. The method for manufacturing a HEMT device according to claim 1, wherein: the laminated structure further comprises a nucleation layer positioned on the bottom layer of the laminated structure, and the nucleation layer covers the exposed surface of the groove and the upper surface of the substrate.
4. The method for manufacturing a HEMT device according to claim 1, wherein: after the laminated structure is formed, before the first dielectric layer is formed, a step of forming a source contact hole which is positioned at the bottom of the groove and penetrates through the laminated structure is further included, and the source electrode fills the source contact hole.
5. The method for manufacturing a HEMT device according to claim 1, wherein: after the laminated structure is formed, before the first dielectric layer is formed, a step of forming a third dielectric layer and a conductive block is further included, wherein the third dielectric layer covers the exposed upper surface of the laminated structure, the conductive block is located on the surface of the third dielectric layer above the inner wall of the groove, and the bottom surface of the gate hole is exposed out of the conductive block.
6. The method for manufacturing a HEMT device according to claim 1, wherein: the gate holes in the trenches are in communication with each other.
7. The method for manufacturing a HEMT device according to claim 1, wherein: an included angle between the inner wall of the gate hole and the bottom surface of the gate hole is not smaller than 90 degrees and not larger than an included angle between the bottom surface of the groove and the inner wall of the groove.
8. The method for manufacturing a HEMT device according to claim 1, wherein: the drain electrode also covers the upper surface of the second dielectric layer, and the grid electrode and the drain electrode are separated by a preset distance.
9. The method for manufacturing a HEMT device according to claim 1, wherein: after the drain electrode and the grid electrode are formed, the method further comprises the step of thinning the substrate from the bottom surface of the substrate, and after the substrate is thinned, the bottom surface of the device at least exposes the channel layer above the bottom surface of the groove, and the source electrode at least covers the bottom surface of the substrate and the exposed surface of the channel layer.
10. The method for manufacturing a HEMT device according to claim 1, wherein: after the grid electrode and the drain electrode are formed, a step of forming a source electrode contact hole at the bottom of the substrate is further included, the bottom of the source electrode contact hole at least exposes the channel layer above the bottom surface of the groove, and the source electrode at least fills the source electrode contact hole.
11. A HEMT device, comprising:
a substrate provided with a plurality of grooves arranged at intervals;
the laminated structure comprises a buffer layer, a channel layer and a barrier layer which are sequentially laminated, and covers the exposed surface of the groove and the upper surface of the substrate;
the first dielectric layer fills the groove and covers the exposed surface of the laminated structure, a grid hole positioned in the groove is arranged in the first dielectric layer, and the bottom surface and the inner wall of the grid hole are spaced from the laminated structure by a preset distance;
a gate conductive layer filling the gate hole;
a second dielectric layer covering the exposed upper surfaces of the first dielectric layer and the gate conductive layer;
a drain contact hole and a gate contact hole, wherein the drain contact hole penetrates through the second dielectric layer, the bottom of the drain contact hole at least exposes the barrier layer above the substrate between two adjacent trenches, and the gate contact hole penetrates through the second dielectric layer, and the bottom of the gate contact hole exposes the gate conductive layer;
The drain electrode fills the drain contact hole, and the grid electrode fills the grid contact hole;
and a source electrode electrically connected with at least the substrate and the channel layer.
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| CN202310786364.6A CN116705606A (en) | 2023-06-29 | 2023-06-29 | HEMT device and preparation method thereof |
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| CN202310786364.6A CN116705606A (en) | 2023-06-29 | 2023-06-29 | HEMT device and preparation method thereof |
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