CN1166904A - Digital data packet multiplexer, in particular for digital television - Google Patents

Abstract

A device including a plurality of packetising modules supplying packet memories (PMi) from digital input streams, and multiplexing means (14) for selecting the packet memories from which the multiplex packets are to be retrieved and transferring them sequentially to a device output. Each packet in a packet memory is combined with selection parameters calculated by its packetising module and indicating at least an earliest time, a latest time and preferably an ideal time for transmission of the packet by the multiplexing means. The multiplexing means select the memory from which each multiplex packet is to be retrieved on the basis of the packet transmission time and the respective selection parameters combined with the first packets on stand-by in each of the packet memories.

Description

Be specially adapted to the digital information packet multiplexer of Digital Television

The present invention relates to be used to produce a kind of equipment of the time division multiplexing of digital packet, comprise several packetize modules, each module receives a digital input stream; Comprise several packet memories, each memory receives the packets of information of being sent by packetize module separately: also comprise the multiplexing device of selecting packet memory, the multiplexed packets of information of extraction and described packets of information is delivered to continuously the output of this equipment from these packet memories.

The present invention relates more specifically to the field of Digital Television.Be particularly useful in the framework of MPEG2 system standard, this standard is defined among the international standard ISO/IEC 13818-1 (draft) of issue in International Standards Organization on June 10th, 1994 (general contract yard that information technology one moves image and relevant audio frequency/H.222.0 recommendation).The document ISO/IEC 13818-1 will be quoted by described all information of the structure of bag for information about of the application's book.

MPEG2 system standard defines the multiplexed digital stream of two classes: transmit stream (TS) and program flow (PS).One " program " is defined as the basic stream of one group of time correlation, that is, wherein each all have base when public with respect to certain with the information that is resumed.Program flow PS transmits single program with the form of the packets of information of the big and possible relatively elongated degree of scale.Stream PS is counted as and produces the seldom transfer channel of error.Be generally used for depositing the information on the disk.Transmit stream and form, and be used for to introduce the environment transmission information of error by the packets of information that belongs to one or more programs.Transmitting bag (TP) has the regular length of 188 bytes, and each all comprises the TP title of at least 4 bytes.

These multiplex streams are made of packetized elementary stream (PES).Directly the original basic stream (ES) that sends from video or audio coding at first becomes the form of the PES packets of information of variable-length.Then PES stream is cut apart again, will be so that constitute by multiplexed packets of information TS or PS.At present, the basic stream of some encoder output ES level, other encoder is then exported the basic stream of PES level.Basic stream also can be made up of the data of non-video or audio frequency, and for example, the detail data of specific procedure information (PSI) is to the relevant data of conditional access (ECM or EMM) of certain program ...

The effect of MPEG2 multiplexer is to receive various basic streams, forms packets of information TS or PS, carries out the time division multiplexing (switching) of these packets of information then.

An apparatus according to the invention also can be to be called as the equipment of division multiplexing device again.The division multiplexing device is for example to be used to produce multiplexed a kind of equipment of definition in this manual again, wherein, has a multiplexed upstream that has become under PS or the TS form in the inlet flow at least.The division multiplexing device can be used to extract from certain transmission stream about the packets of information of a program and as another output that transmits stream or only comprise the program flow of this program again, also can be used for from one or more transmission streams, extracting the packets of information relevant with one or more programs, transmit stream so that construct another, perhaps also can be used for certain program flow is converted to transmission stream, so that in lossy environment, transmit it.

According to MPEG2 system standard, the fill rate of the basic buffering area that multiplexer must be by the simulated target decoder is managed the time of the bag of each inlet flow and is divided, so latter's state that sky will not occur or overflow.

If there is a large amount of basic stream, that the computing capability of choosing required processor of finishing the bag that is transmitted may become is very big (suppose this election must with the speed executed in real time that bit rate was determined of output stream).

Yet, above-mentioned method forces the multiplexer piecemeal to carry out election, do not consider later bag: this makes and can only select in the getable bag of packetize module, supposes that the fixed election that some source information is postponed bag only for 4ms, then postpones more to other source information.In some cases, this method may cause the multiplexing of bag too late, and a buffering area that therefore can cause the decoder that is connected is for empty, and this is to forbid in the standard occurring.

For example the purpose of this invention is to provide that this illustrates defined a kind of equipment, this equipment can satisfy the harsh requirement that the election about bag is proposed the multiplexing module well.

In the device in accordance with the invention, each bag and one group of election relating to parameters, this group parameter of appearing in the packet memory are to be calculated by the packetize module that this bag is offered described memory, and these election parameters represent to be transmitted by the multiplexing device a minimum delivery time and maximum delivery time of described bag at least.According to the delivery time of described bag and respectively with the relevant election parameter group of in each packet memory, waiting for of first bag, the selection of multiplexing device will be from wherein extracting the packet memory of each multiplexed bag.

The packetize module is time window of each package definition, and the multiplexing module can transmit this bag in this window.The multiplexing module can also obtain other information, makes it to finish systematically and quickly its election task, and does not need to know all details about various basic streams.

Preferably further represent by the desirable delivery time of multiplexing device with the relevant election parameter of certain bag described bag.Wrap in it and transmit ideal position in window by defining this, the packetize module helps the multiplexing module to finish its task, so that enable to produce high-quality multiplexed.

By the best introducing below in conjunction with accompanying drawing but infinite embodiment, other features and advantages of the present invention will be clearly, in the accompanying drawings:

-Fig. 1 is the complete schematic of first embodiment of the invention;

-Fig. 2 is the schematic diagram that is applicable to the packetize module in the equipment of Fig. 1;

-Fig. 3 to Fig. 5 explanation is according to the operating process of the packetize module of Fig. 2;

-Fig. 6 represents can be used on the multiplexing module in Fig. 1 equipment;

-Fig. 7 and Fig. 8 illustrate the example that multiplexing module medium priority calculates;

-Fig. 9 represents the election circuit in the multiplexing module of the Fig. 6 that is used in; And

-Figure 10 is the complete schematic of the second embodiment of the present invention.

The equipment of introducing below shown in Figure 1 is used to produce the multiplexed OS of output of the transmission stream TS form that has on the MPEG2 normal meaning.Be construed as, this equipment also can be used to produce the multiplexed of another kind of type, especially the program flow PS on the MPEG2 normal meaning.

This equipment comprises several packetize module C1 ..., Cn, each module receives an inlet flow IS1 ..., ISn.These several inlet flows have m basic stream altogether.Under the situation of the multiplexer that its inlet flow all is made up of the basic stream that sends from encoder or data source respectively, we have n=m.In example shown in Figure 1, this IS2 is by multipath conversion (for example transmitting stream TS), and this equipment is considered two basic streams that are comprised in this multiplex stream in design.

Packetize module C1 ..., Cn submits to from each that is received flows substantially and transmits bag TP.These transmit bag and are had dual-port buffer memory PM1 ... among the PMm.Each packet memory PMi receives packets of information from the packetize module.Handle and can be presented to a plurality of packet memory PM2 and PM3 by the packetize module C2 of multiplex stream.Under this latter event, packet memory PM2 and PM3 can comprise two different addressed areas of same memory plane easily.

Each packet memory PMi connects a parameter storage ZMi, and it also is a kind of memory of dual-port type.Each when the packetize module is write packets of information among the packet memory PMi, the parameter set that it also will be relevant with this packets of information writes among the relevant parameters memory ZMi.In order to read, packet memory PM1 ..., PMm is connected on the public packet bus 10, and parameter storage ZM1 ..., ZMm then is connected on the public parameter bus 12.These two buses 2 are connected to multiplexing module 14, and the effect of this module is selection memory PMi, extract the packets of information of exporting multiplexed OS and the output that described packets of information is sent to continuously equipment from memory PMi.

The basic stream that packetize module Ci real-time analysis is received also will transmit bag and offer buffer memory PMi.The real-time analysis and the double-contractingization (PES and TP layer) of basic stream may need big computing capability, and especially for video flowing, video flowing may reach the bit rate of 15Mbit/s under standard resolution, and high-resolution is next may be greater than 100Mbit/s.Packetize module C1 shown in Figure 2 can satisfy these harsh requirements.

Module C1 comprises the input block 20 that receives inlet flow IS1.On the output of buffering area 20, the byte of inlet flow was passed through testing circuit 22 earlier before the storage device 23 that is sent to first in first out (FIFO) type.The output of storage device 23 is connected to the data input pin of packet memory PM1.

Testing circuit 22 is embodied as user-programmable gate array (FPGA).It comprises that having every grade is 4 other shift registers of level of 1 byte, makes byte this register of elder generation's process before arriving storage device 23 of inlet flow; Testing circuit 22 also comprises and detects logic 25, receives 4 bytes that appear among register 24 at different levels.It is the function of detected state in the inlet flow that logic 25 is programmed to.Logic 25 detects these states of inlet flow and notifies microprocessor 26.Processor 26 can pass through its address and data/ address bus 28 and 29 access parameter memory ZM1.Bus 28 and 29 also is connected to packet memory PM1 through triple gate 31.

Storage device 23 is controlled as 184 bytes that all comprise inlet flow in any moment, and therefore, each byte is left this device and all pointed out input another byte.Storage device 23 is embodied as the shift register of the level with 184 1 bytes simply.If do not have this specification and shift register, can be with several shift register cascades, perhaps use random access storage device, its read/write address adopts a kind of like this mode to produce, and makes the capacity of relative 184 bytes read to keep a constant interval between address and the write address.

According to logic 25 detected states, processor 26 offers Control Parameter and transmits sequencer 32, so that realize the transmission of byte from storage device 23 to packet memory PM1 of inlet flow.These Control Parameter comprise the initial address of the data of packets of information being write memory PM1, and the byte number that begins to be transmitted from this address.Sequencer 32 comprises address counter, and the initial address that latter's initialization provides processor, and increase 1 with the byte that each is transmitted is transmitted up to the byte number of defined.This counter is provided for byte is write the address of memory PM1.If storage device 23 adopts the form of random access storage device, sequencer 32 also provides the address of reading that is transmitted byte, and takes such mode, the agreement that makes obedience first in first out in this memory.Sequencer is submitted signal SC to, to the displacement of the transmission of storage device 23, testing circuit register 24 and read operation such as byte and carry out timing from buffering area 20.

In example shown in Figure 2, inlet flow IS1 is with by the basic stream of packetize (ES or PES).Detecting logic 25 is programmed to detect the synchronization character in the inlet flow.The state that specification logic 25 is detected, processor 26 determine to be placed in length and the content that the next one that will be deposited in memory PM1 transmits the title at the beginning of wrapping.Determine this title according to the specification of MPEG2 standard, processor 26 is carried out for example in the header format program described in the document ISO/IEC 13818-1.The length L of title can be selected between k=4 byte and K=188 byte.Therefore, before the capacity guarantee information of the K-k=184 byte of storage device 23 wraps in and begins to be sent to packet memory PM1 from storage device 23, testing circuit 22 by analysis can be introduced into whole bytes of the inlet flow that transmits bag.

Fig. 3 explanation packetize module under the situation that original basic stream ES sends from audio coder is wrapped the structure of TP to transmission.According to the MPEG2 standard, audio frequency FS stream comprises the frame of constant length, and each frame is begun by frame title 35A.Frame title 35A comprises one 12 synchronization character, and equals the FFF of 16 systems.Therefore, to detection logic 25 programmings of the packetize module of processing audio ES stream to detect this synchronization character FFF.PES stream by such ES stream structure can directly add a PES title 36 before each ES title 35A.Yet when processing audio ES flowed, packetize module of the present invention did not relate to the contingency of this PES clearly, otherwise directly structure transmits bag TP.Under situation shown in Figure 3, as long as logic 25 does not detect synchronization character FFF in the inlet flow, processor 26 calculates the title 37a of L=4 bytes, and order is sent to memory PM1 with the 188-L=184 byte from storage device 23, transmits bag TP so that set up.When logic 25 detects synchronization character during packets of information is sent to memory PM1, processor 26 calculates the length L of the title 37b of packets of information subsequently, and adopts in such a way so that with the transmission bag of filling up 188 bytes up to the byte of the basic stream of detected synchronization character.In order to produce the title of length L greater than 4 bytes, processor 26 is introduced the adaptation field of this title with flow management parameter or byte of padding, as MPEG2 system standard regulation.The packets of information of following the transmission bag of such structure will not comprise any byte of inlet flow, and only comprise a TP title 37c and a PES title 36.Can think that processor 26 determined the combination title of the L=188 of 37c-36, and carry out the operation that from storage device 23, this packets of information is transmitted K-L=0 byte.Calculate PES title 36 and the length of TP title 37c will be regulated according to the adaptation field of previous packets of information according to MPEG2 system standard.

The similar Fig. 3 of Fig. 4, but consideration is the ES stream of video type.According to the MPEG2 standard, the ES stream of video type comprises that three class titles two comprise sequence-header 35S that 16 hex value are the 4 byte of sync words of 000001 B3, comprise the figure group heading 35G that 16 hex value are the 4 byte of sync words of 000001 B8, and comprises the visual title 35P that 16 hex value are 00000100 synchronization character.The structure of video ES stream is such, even figure group heading 35G or image header 35P are always directly followed in the back of sequence-header 35S, and visual title 35P is always followed in the back of figure group heading 35G.And then the length about certain visual video data of each image 35P is variable.The PES stream of structure is before each sequence-header 35S from such video ES stream, directly do not have before each group heading 35G of sequence-header 35S in front, directly do not have to comprise PES title 36 before each visual 35P of group heading 35G in front.Yet, when flowing, this packetize resume module video ES clearly do not produce corresponding PES stream, transmit bag but directly produce TP.The insertion method of PES and TP title is identical with method under the described audio case of Fig. 3 basically, detects logic 25 and is programmed design to detect the synchronization character of title 35S, 35G and 35P.Yet processor 26 is not all to insert PES title 36 before all visual title 35P, and only be in front directly not before those visual title 35P of figure group heading 35G or sequence-header 35S bar go into PES title 36.Similarly, processor is not all to insert the PES title in all figure group heading 35G front, and does not only insert the PES title before its front directly has the figure group heading of sequence-header.According to logic 25 detected synchronization characters, can judge various such conditions easily.

The similar Fig. 3 of Fig. 5 and Fig. 4, but consideration is the inlet flow of audio or video PES type.PES title 36 in each packets of information of PES stream comprises a synchronization character of 4 bytes, and 16 hex value of preceding 3 bytes are 000001, and the 4th byte is the traffic identifier byte.This identification byte will be for being known in advance by certain given PES stream of packetize resume module, and logic 25 can be programmed design to detect 4 byte of sync words of PES stream.Processor 26 is according to PES title 36, and the employing mode identical with Fig. 3 and Fig. 4 carried out and be divided into the operation that transmits bag TP.Processor 26 is not considered ES title 35, but the data that are similar to basic stream are handled ES title 35 like that.As the situation of Fig. 3 and Fig. 4, processor 76 can Programming Design, makes the TP that comprises PES title 36 comprise the data of basic stream.Then, processor 26 need be known the length L of PES title ' be the TP title 37C of L=K-L ' byte, a packets of information of heel PES title 36 so that structure only comprises length.This length L ' can itself read from the PES title by testing circuit 22: if do not start with two " 10 " from beginning the 7th byte of PES title, then the length of PES head is L '=6 bytes; Otherwise, length L ' and from the 9th byte at the two ends of PES head, read (seeing document ISO/IEC 13818-1).

Construct this advantage that is comprising PES title 36 and only TP37a-37c and described PES title 36 are being placed on the transmission bag in the bag and be all that allow that coding comprises basic stream ES data and transmit bag, and the PES title does not need to be encoded.

Processor 26 utilizes door 31 to be write on the suitable position of packet memory PM1 by title 37a-37c and 36, and adopts the structure that makes its obedience Fig. 3, Fig. 4 and bag TP shown in Figure 5 in such a way.This write operation can occur in before the 188-L byte that transmits the inlet flow that belongs to described packets of information.Also can carry out afterwards, as long as described bag is also in memory PM1, especially under these circumstances: the parameter that the TP head of requirement bag comprises depends on the packets of information (for example image Segmentation parameter under video ES stream situation) of the packetize module of arriving soon after.

When inlet flow is a multiplexed transmission stream, detects logic 25 and be programmed design and transmit the sync byte of unwrapping end to detect indication.The input time that 16 hex value of this sync byte are 47, processor writes down this bag when detecting this sync byte.By utilizing the analysis of byte afterwards of 22 pairs of TP titles of testing circuit, processor 26 can be read 13 sign positions (PID field) of this bag and determine whether to comprise the optional tense fields of PCR or LTW type.The existence of PCR or LTW field is (the seeing document ISO/IEC 13818-1) by some bit representations of assigned address in the TP title.The position of PCR field is fixed, and the position of LTW field then can change, so that in due course, also can the position of this field be indicated to processor 26 by circuit 22.

Known the identification parameter PID (feature of the basic stream that sent of expression) of this packets of information, processor 26 just can be carried out filtering operation, only makes to be sent to packet memory being retained in the packets of information of exporting the basic stream in multiplexed.In order to eliminate certain bag, processor command transfer sequence generator 32 is write this bag on the garbage address that certain is read never again in the packet memory.

Under the situation that packetize module and a plurality of packet memory PM2 and PM3 link together, these memories are combined in the identical addressing space, and determine to transmit the word address that sequencer 32 is produced according to the identification parameter PID that offers processor 26 by testing circuit 22, and adopt a kind of like this mode so that realize the operation of first in first out in each in packet memory PM2 and PM3.

The basic stream that is retained in the multiplexed inlet flow can be introduced into each packet memory.

Packetize module shown in Figure 2 has very big flexibility.By to detecting the direct Programming Design of logic 25 and processor 26, can adapt to many different inlet flows easily.This module is particularly useful for the equipment of modular structure.Under the situation of ES class inlet flow, utilize single processor just can carry out simultaneously to form two stages of packets of information (PES and TP), the PES title is counted as the expansion of TP title.It also is applicable to the inlet flow of TS or PS type in division multiplexing is used again.

But the foundation of packets of information and the data of previous bag are sent to the operation executed in parallel of memory PMi so just can be handled sizable input bit rate.Transmission work can be entrusted to certain independently sequencer, therefore, just can allow the single processor of packetize module carry out other processing operation.

Another task that processor 26 is carried out is to calculate the parameter relevant with this bag and they are write parameter storage ZMi.These parameters comprise that the selection parameter that allows multiplexing module 14 selection packet memories is to be sent to packets of information the output of equipment.Therefore, some should be transferred to the packetize module by the task that multiplexing module is born traditionally.But the added burden of processor 26 is heavy, make under any circumstance since packetize need can not be subjected to tangible influence to the selection of this processor.

For the Best Times of seeking output distributes, need know:

-packets of information that can withdraw from immediately and the maximum delay time that can distribute to them,

-the packets of information that can withdraw from very soon with and transmission time that can be suggested.

A method that allows multiplexing module 14 understand this broadcast message is that requirement packetize module connects 3 election parameters with the packets of information that each is written to buffer memory PMi, the time of each parameter correspondence basis representation during with certain, this time base shared by packetize and multiplexing module.These 3 parameters are minimum time Tmin, maximum time Tmax and the ideal time Tideal that associated packets of information transmits.

Therefore, each processor 26 of the basic stream of management is for transmitting time window of each packet definition of setting up, and can freely regulate the character of the stream that the width of this window managed to adapt to.In addition, in order to help multiplexing module 14 to finish its task and to make it to produce high-quality stream, in its window, defined the ideal position of this packets of information.The management of parameter Tmin, Tmax and Tideal is clear and definite for the different inlet flow of every class.

At inlet flow is basic stream (ES, PES or data) time, Te input time of the input block 20 by stand-by period T1 and packet data being input to the packetize module calculates minimum delivery time Tmin in the Calais mutually, and maximum time of transmitting and the poor Tmax-Tmin between the minimum time then calculate as the function of the bit rate of the type of basic stream and this stream.If the source of basic stream has the bit rate of rule, then can adopt simple mode to release Te input time by processor 26 from the data transfer time of testing circuit 22.If the source of basic stream has the bit rate of paroxysm, then can from the bit rate clue that receives by upstream encoder or from this stream, read, retrieve input time and obtain.Stand-by period T1 is a programmable time, and purpose is to postpone the delivery time of some stream with respect to other stream.The width Tmax-Tmin of window will compare instantaneous stream (especially video flowing) does not have very accurately the stream of retransmission limit, and (for example EMM conditional access data stream) gets littler value.And the decreasing function of the still basic stream bit rate of difference Tmax-Tmin.

Under the situation of the transmission stream type of multiplexed inlet flow, the repeating transmission minimum time Tmin of packets of information by packets of information to this module input time Te so that the function of the stand-by period in above-mentioned situation calculates, but also the function of the strategy of taking as the multiplexer of front.This strategy represents that processor 26 utilizes testing circuit 22 can read these fields in the LTW field of TP title of stream or description field.The minimum time Tmin that is calculated with respect to time of the delay of Te+T1 for example corresponding to the window shifts of from this stream, reading (LTW_offset).Under the situation of multiplexed inlet flow, the maximum time Tmax of repeating transmission is according to the function calculation of the type of stream.For the basic stream of the great majority that transmit stream, difference Tmax-Tmin value 4ms.Yet for some special situation, this difference may be increased, so that loosen the restriction to this multiplexing module.

Function according to the multiplexing strategy that basic stream adopted that comprises this packets of information obtains the ideal time that packets of information transmits.This time T ideal can be defined by the skew with respect to minimum time Tmin, and this displacement is that fix or proportional with the width Tmax-Tmin that transmits window." early " strategy is corresponding quite near a kind of time T ideal of minimum time Tmin.A kind of like this strategy helps being positioned at the encoder or the multiplex adapter of upstream, and they can use the less output buffer memory of capacity." evening ", strategy was quite far away from minimum time Tmin corresponding to time T ideal.This strategy helps being positioned at the decoder in downstream or divides multiplex adapter again, because the capacity of its input buffering region memorizer can be reduced.Between " early " and " evening " strategy, there is a universe.

In typical embodiment, the election parameter that leaves among the parameter storage ZMi is the desirable delivery time Tideal of 20 codings, the difference Tideal-Tmin of 15 codings, so that the difference Tmax-Tideal of 15 codings, each parameter is represented with respect to the 90KHz reference clock.These parameters are stored in memory PMi in the associated address, address with relevant packets of information.

And parameter that be stored among parameter storage ZMis relevant with certain packets of information comprises that further modification parameter, these parameters allow multiplexing modules 14 can come the update package title according to the function of its delivery time when needed.For example, these modification parameters comprise:

The position whether-expression PCR type field that detected by logic 25 or LTW type field exist, only these just can be updated when the accurate output time of this packets of information is known, and requirement base very accurately the time.Under the situation of PCR type field, its position was fixed with respect to the beginning of bag, and available one is illustrated in whether there is such field in this bag.Under the situation of LTW type field, its position is variable, revises parameter and also indicates the position of this field in bag;

-comprise the size (pay(useful) load) of data division.This information is useful when multiplexing module 14 is further carried out the coding of bag;

-Bao identification parameter PID.This information is used in the application of division multiplexing again, allows multiplexing module 14 to determine whether to need to change this parameter (being assigned under the situation that is included in a plurality of basic streams in this inlet flow at identical identification parameter PID).

The structure of multiplexing module 14 is represented by Fig. 6.This module comprises microprocessor 40 and election circuit 42 on the one hand, handles the data that are comprised among the parameter storage ZMi, then comprises transfer sequence generator 44 on the other hand, and the bag of the output buffer 46 of control from packet memory PMi to equipment transmits.Should be appreciated that multiplexing module 14 may comprise other element, for example, be used for before Jiang Bao writes output buffer element the packet encoder that is transmitted.

The multiplexing module further comprises another packet memory PM0 and relevant parameter storage ZM0.Memory PM0 comprise output multiplexed with the packets of information (PSI) of program special use, they especially illustrate the identification parameter PID (seeing 2,4.4 chapters of document ISO/IEC13818-1) of each program flow.By the signal source (not expression) that also belongs to this multiplexing module 14 these are wrapped among the PSI write memory PMO.Election parameter, Tmin, Tmax and the Tideal relevant with these bags are also by this signal source write memory ZM0.The time restriction of PSI bag is not very harsh, and the delivery time window of these bags can be obtained quite wide.

It seems from the viewpoint of multiplexing module 14, packet memory PM0, PM1 ... PMm is counted as the individual address space.Equally, with respect to read operation, parameter storage ZM0, ZM1 ... ZMm also is counted as the individual address space.Fig. 6 has provided data/address bus 10D and the address bus 10A that is contained in the packet bus 10.These two bus 10A and 10D are connected to address and the data input pin of each packet memory PMi respectively.Address on the bus 10A produces by transmitting sequencer 44 under the supervision of processor 40.Data/address bus 10D also is connected to the input of output buffer 46, and writing by sequencer 44 of data controlled.

Fig. 6 gives data/address bus 12D and address bus 12A, and they are supervised and be included in the parameter bus 12 by processor 40.These two bus 12A and 12D are connected to address and the data input pin of each parameter storage ZMi respectively.Packet bus 10 and parameter bus 12 are connected together by triple gate 48, make processor 40 to order packet bus 10.For command sequence generator 44 the transmission bag of one 188 byte is delivered to output buffer, processor 40 provides initial address on address bus 12A.This initial address is delivered to bus 10A by gate circuit 48, and sequencer 44 and address counter are initialized as the value of this initial address, and 188 bytes that increase progressively then up to this bag all are sent out.

Address bus 10A and 12A are enough wide for packet memory PMi and parameter storage ZMi, are enough to be regarded as single addressing space by processor 40.24 address bus is applicable to jumbo multiplexer or division multiplexing device (for example m≤128) again.In order to improve output speed, data/address bus 10D and 12D can be 16 buses, transmit two bytes simultaneously.

Sequencer 44 is independent of processor 40, so that when previous multiplexed bag just is transmitted under the control at sequencer, processor 40 and circuit 42 can be carried out the transmission of bag in multiplexed and handle operation.This just makes multiplexing module 14 can adapt to the desired big transmission bit rate of MPEG2 standard.

The processing operation of carrying out before bag of transmission comprises:

-select also to determine to be provided for the initial address of sequencer 44 to guarantee transmission to this bag from the packet memory PMi that wherein reads this bag;

Modification parameter and may revise that-analysis is relevant with selected bag to respective field.

Processor 40 receives from the device that is arranged in device downstream and is used for the multiplexed signal CK of clock control output.Processor 40 calculates the time T S that next bag transmits according to signal CK.

Choose from wherein extracting the packet memory of next bag so that appear at election parameter Tmin, Tmax in first group of position of parameter storage ZMi and Tideal according to this delivery time TS, in other words, to be used with the relevant election parameter of first bag at each packet memory PMi etc.

The appendix 1 that this specification provides has later provided the example of an election algorithm of writing with the C language, can be used to select therefrom to extract one group of packet memory of one group of multiplexed bag.In appendix 1 and note, the nb_sources correspondence can be attached to the number of the packet memory of packet bus 10 (when using all told of multiplexing module 14, nb_sources=m+1), valid_TP_flag[] be the table of nb_sources for length, form by more such distribution variables, for example, if if actual position current_channel and this packet memory of being connected to of packet memory PMi comprises one at least and waits for the bag that transmits, valid_TP_flag[current_channel then] be true, table Tmin[], Tmax[] and Tideal[] be included in the election parameter of first bag of waiting in each packet memory, current_priority is the priority coefficient that calculates for first bag that waits in memory PM (current_channel), elected_TP_priority then is the priority factor of the maximum that obtained by election algorithm, and correspondence is included in the selected bag among the memory PM (elected_TP_channel).

Priority factor-1 is assigned to the filling bag in certain address of for example leaving memory PM0 in, and the memory number of distributing to this address is-1.If the neither one packet memory comprises a bag that has obtained its minimum delivery time Tmin, then should fill bag by default selection.The scale of supposing this equipment for its inlet flow bit rate and less than the bit rate of output stream, then after its maximum time Tmax, bag can not normally be transmitted.

Fig. 7 and Fig. 8 be illustrated under " early " strategy (Fig. 7) situation and under " evening " tactful situation (Fig. 8) have the priority factor of bag of given transmission window [Tmin, Tmax] with the variation of delivery time TS.As can be seen, for certain given delivery time and identical window, election algorithm helps being defined as the stream of " early " strategy.

When the multiplexed bag of front just had been transmitted, the election algorithm that provided in the appendix 1 can be provided processor 40.In this case, processor 40 must be held the read operation to parameter storage ZMi, handles and carries out this algorithm again.These tasks need certain processor times, and why Here it is will preferably use as shown in Figure 6 the reason of independently electing circuit 42 in the application of high bit rate.Hard-wired circuit 42 can be carried out the election operation quickly than processor, and can make processor 40 avoid bearing the corresponding calculated task.

Multiplexing module 14 comprises the dual-ported memory 50 that is connected to parameter bus 12, so that provide the useful parameter of election circuit 42.Processor 40 is read from corresponding parameters memory ZMi and is waited for first relevant election parameter Tideal, Tmax-Tideal of bag in each packet memory PMi and Tideal-Tmin and write on the address AD D that equals packet memory number in the memory 50.Write the position BM that also has the corresponding defined Boolean variable valid_TP_flag in front in the memory 50 by processor 40: if if the position one-tenth person who does not have packet memory to be connected to corresponding to address AD D is connected to the wait bag that does not comprise relevant moment corresponding to the locational packet memory of address AD D, then BM=0.

Fig. 9 is the schematic diagram of hardwired election circuit.This circuit 42 comprises register 52, and processor 40 is write the value of next delivery time TS in this register.The operation that sequencer 54 is performed according to the election order EC supervisory electronic circuit that receives from processor 40 42.Earlier with content value of being initialized as-1 (default to and fill bag) of two registers 56 and 58, one of them is as the address AD DS that comprises corresponding selected packet memory at the beginning for sequencer 54, and another is then as comprising corresponding priorities FACTOR P RIO.Sequencer 54 then produces order and reads working storage 50.On each read cycle, 54 pairs of sequencers provide the address counter of reading the address to increase progressively a unit, therefore sequentially read and various possible relevant B parameter M, Tideal, Tmax-Tideal and the Tideal-Tmin in address.Election circuit 42 comprises subtracter 60, receives the delivery time TS that is sent by register 52 on its positive input terminal, receives the ideal time Tideal that is sent by memory 50 on its negative input end.The signal bits control multiplexer 62 of subtracter 60 outputs, the parameter Tmax-Tideal of one of its input (positive signal) reception memorizer 50, other input (negative signal) then receives the parameter Tideal-Tmin from memory 50.Merchant between the output of divider 64 calculating subtracters 60 and the output of multiplexer 62.Then the priority factor of the current bag that divider 64 is provided is sent to an input of comparator 66, and the content of other input receiving register 58 of comparator 66.AND gate circuit 68 receives and the current position BM that is surrounded by the pass on the one hand, then receives the comparison position that is produced by comparator 66 on the other hand.If the current packet priority coefficient that is calculated is greater than the coefficient that is recorded in the register 58, then this comparison position is 1, otherwise is 0.In order to reach synchronous purpose, 70 pairs in shift register is sent to number of cycles that the position BM of AND gate circuit 68 postpones and equals the required periodicity of calculating carried out by element 60 to 66.At all after dates that postponed similar number by shift register 72, the address AD D that sequencer 54 is produced is sent to register 56.The priority factor that is produced by divider 64 is sent to register 58.Sequencer 54 offers register 56 and 58 so that it upgrades with cycle clock CCK, but this renewal only could be carried out under AND gate circuit 68 is output as 1 condition.

Above-mentioned circuit 42 can be carried out the election algorithm of appendix 1 in a short period of time.In case the election circuit has scanned all possible address, just can in register 56, obtain, the address AD DS of corresponding certain memory PMi, next bag will be read from this memory PMi.Then, processor can pass through parameter bus 12 read registers 56.

In case processor 40 is known selected packet memory PMi thus, it will bear following operation:

-modification the parameter of from relevant parameter storage ZMi, reading selected bag;

-processor 40 is analyzed these and is revised parameter, and if necessary, carries out the corresponding modify that should wrap among the memory PMi.In order to revise a bag, processor 40 is given an order by 48 pairs of packet bus 10 of gate circuit, can release the modified address from number number and the modification parameter of selected memory.The function of the delivery time TS that the time data (PCR or LTW) that is modified is calculated as the front.Modified logo field PID if desired, processor 40 uses the multiplexed mapping (enum) data (PSI) of output.When 40 pairs of packet bus 10 of processor were given an order, sequencer 44 interrupted ongoing bag and transmits.

-as the function of several ADDS of selected packet memory, processor 40 is determined to offer and is transmitted the initial address that sequencer 44 is used to transmit next multiplexed bag OS; Processor is determined this initial address with a kind of like this method, so that obey each bag is input to order in each packet memory;

-from relevant parameter storage ZMi, read the bag election parameter on the second place that is placed among the selected memory PMi and it is write in the working storage on the corresponding address; Second if there is no such bag, corresponding position BM is changed to 0 in working storage 50;

-processor 40 calculates the delivery time TS of next bag and provides it to election circuit 42, also as next election order EC.

Certainly, processor 40 also can be carried out other function, does not describe in detail here, because and the not direct relation of the present invention.

The recommended structure of this multiplexing module adapts to the restriction that MPEG2 system standard is made very much.The packetize module provides such information for the multiplexing module, thereby can make arriving at of each bag be best distribution in time, these information not only provide the desirable airtime of each bag for it, but also minimum time and maximum time are provided, make it can obey the input block of the decoder that is positioned at the downstream.

The unnecessary multiplexing characteristic (bit rate, the crucial multiplexing factor) of knowing the source information that it is managed of multiplexing module.Therefore, can define a kind of general multiplexing card, it can topped multiplexing and the various aspects of dividing multiplexing again, can reach goodish flexibility like this.

The multiplexing processor is freed, so that the problem of management of processing configuration (these problems all are being huge with unmanageable aspect the number of basic stream and times speed), and does not need too high computing capability.Multiplexed process is very systematized, and can partly be installed in the very fast hardwired logic, for example elects circuit 42.

The restriction that only is subjected to multiplexing module's address highway width of the number m of the basic stream that can manage.This has sizable flexibility, deletes because the packetize module can be added on the multiplexing module or from the multiplexing module easily.When power initiation and when defining how many packetize modules, equipment can also be write its data in the address of packet bus and parameter bus in self-configuration.

Election of each bag is with to revise desired parameter be consistent and the type of the stream that the packetize module is managed is irrelevant.Therefore, the multiplexing module is ignored the character of the stream of its institute's multiplexing.The source how many transmission bags it only defines simply links together with it, and work systematically (also being to work quickly therefore).In the structure of recommending, each that waits each source in the bag memory space wraps in all spendable relevant range in the parameter memory space.

Figure 10 has provided another embodiment of Fig. 1 equipment.In this different embodiment, packetize module C1 ..., the interface between Cn and the multiplexing module 14 comprises packet memory PM1,, PMm is used to receive the memory ZM1 of the election parameter of bag ... ZMm, and the memory YM1 that is used to receive each modification parameter of wrapping ... YMm.Therefore, each packetize module will be revised parameter and write among also relevant with the packet memory PMi memory YMi, but YMi and election parameter storage ZMi different (at least in addressing).The bus 12 that allows multiplexing module 14 to regard memory ZMi group as single addressing space only is used to read the election parameter in such an embodiment.Between multiplexing module 14 and memory YMi, provide a similar bus 16, so that read the modification parameter.Therefore, memory YMi is also regarded as single addressing space by the multiplexing module.When a kind of like this structure is selected a packet memory when the election circuit for the next one bag of the multiplexed OS of output, allow the processor of multiplexing module that one or more bags of having selected are made amendment, can select several bags in advance so as can be seen, what can shift to an earlier date passes on time T S.For example, when bag N withdrawed from output buffer, bag N+1 can be written to output buffer, and bag N+2 can be modified and can choose bag N+3 in its packet memory.Therefore, by increasing the parallelization degree of operation, can provide higher carry-out bit speed.

Appendix 1

int election (int Ts, nb_sources, valid_TP_flag[], Tmin[], Tideal[] and, Tmax []) { int current_channel, elected_TP_channel; Float current_priority, elected_TP_Priority; / * is initialized as its default value with the TP that is selected: the priority with-1 is filled bag */elected_TP_channel=-1; Elected_TP_Priority=-1.0; Major cycle */for (current channel=0 of/* scan source information; Current_channel＜nb_sources; Current_channel++) if (valid_TP_flag[current_channel])/* calculate current TP priority */if (Tideal[current_channel]＜=Ts) current_priority=(Ts-Tideal[current_channel])/(Tmax[current_channel]-Tideal[current_ channel]); Else current_priority=(Ts-Tideal[current_channel])/(Tideal[current_channel]-Tmin[current_ channel]); (current_priority＞elected_TP_priority) {/* upgrades parameter */elected_TP_Priority=current_priority of selected TP for the TP that/* is more selected and current TP*/if; Elected_TP_channel=current_channel; }＜!--SIPO<dP n="17">--<dp n="d17"/>Return elected_TP_channel; 

Claims (7)

1. produce the equipment of time division multiplexing digital packet, comprise and receive digital input stream (IS1, IS2, ISn) a plurality of packetize module (C1, C2, Cn), a plurality of packet memory (PM1 of the bag that reception is sent from packetize module separately, PM2, PMm), and select also continuously described bag to be sent to the multiplexing device (14) of the output of equipment from the packet memory that wherein extracts multiplexed bag, it is characterized in that, each bag in the packet memory is all elected parameter correlation with one group, this group parameter is calculated by the packetize module that this bag is offered described memory, and these election parameters represent that at least its feature also is by a minimum delivery time (Tmin) of the described bag of multiplexing device transmission and maximum delivery time (Tmax), according to delivery time (Ts) of described bag so as respectively with wait relevant one group of first bag in each packet memory to elect parameter, the multiplexing device is chosen from wherein extracting the packet memory of each multiplexed bag.

2. according to the equipment of claim 1, it is characterized in that multiplexing device (14) is so designed, make when delivery time of this bag when waiting for minimum delivery time of all first bags in packet memory, transmits a filling and wraps.

3. according to the equipment of claim 1 or 2, it is characterized in that, wrap the desirable delivery time (Tideal) that the further expression of relevant election parameter transmits described bag by the multiplexing device with one.

4. according to the equipment of claim 3, it is characterized in that, select the operation of packet memory to comprise for transmit certain bag at time T s to having each packet memory calculating priority level coefficient of waiting for bag at least, if Ts 〉=Tideal, priority factor equals (TS-Tideal)/(Tmax-Tideal), if Ts＜Tideal, then priority factor equals (Ts-Tideal)/(Tideal-Tmin), Tmin, Tmax and Tideal represent that respectively first waits for the minimum delivery time of bag, maximum delivery time and desirable delivery time, the packet memory that is selected is the priority factor maximum.

5. according to any one equipment in the claim 1 to 4, it is characterized in that, multiplexing device (14) comprises that control transmits the processor (40) of the output of the equipment that wraps from selected packet memory, and according to etc. the relevant election parameter of first bag in each packet memory select hardwired of packet memory to elect circuit (42).

6. according to the equipment of claim 5, it is characterized in that the multiplexing device comprises dual-ported memory (50), processor (40) will wait the election parameter of first bag in packet memory to write in this memory, and therefrom read described parameter by election circuit (42), so that select packet memory.

7. according to any one equipment in the claim 1 to 6, it is characterized in that, existed in the parameter storage (ZMi) relevant with the relevant election parameter of each bag of grade in packet memory (PMi) with described packet memory, its feature also is, multiplexing device (14) comprises that intrinsic parameter bus (12) is connected to the processing unit (40 of parameter storage, 42), so that select packet memory with the relevant election parameter of in each packet memory, waiting for of first bag by analyzing respectively, also comprise by packet bus (10) be connected to packet memory and by processing unit control so that from selected each packet memory, extract the conveyer (44) of multiplexed bag continuously, when conveyer transmitted previous multiplexed bag from the packet memory of choosing previously, processing unit is selected will be from wherein extracting the packet memory of multiplexed bag.

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