CN107682716B

CN107682716B - Code rate control method and device

Info

Publication number: CN107682716B
Application number: CN201610626194.5A
Authority: CN
Inventors: 郝旭东; 陈冰; 胡义群
Original assignee: Sumavision Technologies Co Ltd
Current assignee: Sumavision Technologies Co Ltd
Priority date: 2016-08-02
Filing date: 2016-08-02
Publication date: 2019-12-27
Anticipated expiration: 2036-08-02
Also published as: CN107682716A

Abstract

The invention discloses a code rate control method and a code rate control device, which are used for ensuring that audio and video TS (transport stream) is output under a stable code rate and improving the code rate control precision and audio and video output quality. The code rate control method comprises the following steps: receiving a first Transport Stream (TS) packet, wherein a packet header of the first TS packet carries identification information, and the identification information comprises a decoding time tag (DTS) and a Packet Identification (PID) of the first TS packet; preprocessing the first TS packet to obtain a second TS packet; and storing the second TS packet in a partition mode according to the PID; and aiming at the second TS packet stored in each partition, performing code rate control on the second TS packet read from the corresponding partition according to the DTS in the second TS packet and the program clock reference PCR corresponding to the second TS packet.

Description

Code rate control method and device

Technical Field

The invention relates to the technical field of digital televisions, in particular to a code rate control method and a code rate control device.

Background

In a digital Television, due to the popularization of HDTV (High Definition Television) and SDTV (Standard Definition Television) High Definition televisions, people have higher and higher requirements on the quality of audio/video images when watching programs, so that higher requirements on the code rate of audio/video at an output end are required, however, the audio/video code rate is affected by certain factors such as bandwidth level and the like in the transmission process, so that the code rate of the audio/video at the output end is unstable, and the quality of the audio/video at the output end is poor, and therefore, how to control the code rate at the output end is a problem to be solved urgently in order to ensure the output of High-quality audio/video data.

Before audio/video information transmission in digital television, digital television audio/video program data needs to be encoded to form an ES stream (Elementary Streams), wherein the ES stream is a continuous bit rate; dividing the ES stream as required, and adding a corresponding packet header to form a PES stream (packed Elementary stream), where the packet header of the PES stream carries a PTS flag (Presentation Time Stamp, Presentation Time tag)/DTS (Decoding Time Stamp, Decoding Time tag) in each frame, and the PES packet may be discontinuous from packet to packet, and the packet length of the PES packet may be variable; in order to make the output end output with a fixed length, the PES Packet content is further divided into a series of TS (Transport Stream) packets with fixed lengths, and PCR (Program Clock Reference) and PID (Packet Identifier) are added to the TS Packet header to obtain a TS Stream, and the TS Stream is transmitted. At the receiving end, the decoder can distinguish the TS packets of different programs in the TS packets according to the PID in the TS packet header and restore the original ES stream.

However, when audio/video data is transmitted under the condition of large code rate jitter, the output audio/video data is unstable, the problem of asynchronism may occur, and even the audio/video data is lost, the DTS-PCR difference index is poor, the problem of PCR interval is influenced, and the quality of the output image is reduced.

At present, for networks with large rate variation, two commonly used rate control methods are VBR (variable bit rate) and CBR (Constant bit rate). Under a VBR channel, aiming at videos with high image motion amount and more image texture information, more efficient bandwidth sharing can be obtained by distributing more bandwidths, constant image quality can be obtained, and output traffic of each video source can be adjusted and limited according to time-varying network conditions and requirements. The CBR channel is beneficial to smoothing code streams, and the two modes have different applications under the condition of solving different requirements. For the coded audio data, the code rate is generally close to a constant code rate, and a CBR code rate control mode is suitable for being adopted; the code rate of each frame of the coded video data is relatively large in change, the larger the code rate is, the more information is contained, the clearer the corresponding image and audio are, and the VBR code rate control method is more suitable for being adopted for the same coding format.

However, both of these two code rate control methods have their own disadvantages, for example, in a CBR channel, although large buffering is beneficial to smooth the code rate, a certain delay is introduced, so that the video service cannot achieve real-time transmission; moreover, as the bandwidth in the CBR channel is unchanged, the code rate is unchanged, but the motion amount of the image exceeds the code rate bearing capacity, the image has the phenomenon of edge blurring; in the VBR channel, the quality of the output video image is limited by the bandwidth due to the influence of the bandwidth itself, and in addition, when the fluctuation of the bit rate at the output end is large, video data may be lost, thereby resulting in that the output audio/video is not synchronous.

Disclosure of Invention

The embodiment of the invention provides a code rate control method and a code rate control device, which are used for ensuring uniform and stable output of audio and video and improving the code rate control precision.

The embodiment of the invention provides a code rate control method, which comprises the following steps:

receiving a first Transport Stream (TS) packet, wherein a packet header of the first TS packet carries identification information, and the identification information comprises a decoding time tag (DTS) and a Packet Identification (PID) of the first TS packet;

preprocessing the first TS packet to obtain a second TS packet; and

performing partition storage on the second TS packets according to the PID;

and aiming at the second TS packet stored in each partition, performing code rate control on the second TS packet read from the corresponding partition according to the DTS in the second TS packet and the program clock reference PCR corresponding to the second TS packet.

An embodiment of the present invention provides a code rate control apparatus, including:

a receiving unit, configured to receive a first transport stream TS packet, where a packet header of the first TS packet carries identification information, and the identification information includes a decoding time tag DTS and a packet identification PID of the first TS packet;

the processing unit is used for preprocessing the first TS packet to obtain a second TS packet;

the storage unit is used for storing the second TS packets in a partition mode according to the PID;

and the first determining unit is used for performing code rate control on the second TS packets read from the corresponding partitions according to the DTS in the second TS packets and the program clock reference PCR corresponding to the second TS packets aiming at the second TS packets stored in each partition.

The beneficial effects of the invention include:

the code rate control method provided by the embodiment of the invention receives a first transport stream TS packet, wherein the packet head of the first TS packet carries identification information, the identification information comprises a decoding time label DTS and a packet identification PID of the first TS packet, the received first TS packet is preprocessed to obtain a second TS packet, the second TS packet is stored in a partition mode according to the PID, and for the second TS packet stored in each partition mode, code rate control is carried out on the second TS packet read from the corresponding partition mode according to the DTS in the second TS packet and a program clock reference PCR corresponding to the second TS packet, so that audio and video TS streams are output under stable code rate, and the code rate control precision and the audio and video output quality are improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic block diagram of a code rate control method implemented by using a coding chip and an FPGA according to an embodiment of the present invention;

fig. 2a is a schematic diagram of an implementation flow of a code rate control method according to an embodiment of the present invention;

fig. 2b is a schematic diagram of an implementation flow of a method for adding identification information to a packet header of a first TS packet in a code rate control method according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a code rate control apparatus according to an embodiment of the present invention.

Detailed Description

In order to ensure efficient transmission of audio and video data at a given code rate and improve the code rate control precision and the audio and video data output quality, the embodiment of the invention provides a code rate control method and a device.

The code rate control method provided by the embodiment of the invention is suitable for audio and video data in a digital television, but some parameters in the code rate control method provided by the embodiment of the invention may be different for the audio and video data, so for convenience of description, the embodiment of the invention takes the video data as an example for description.

The preferred embodiments of the present invention will be described below with reference to the accompanying drawings of the specification, it being understood that the preferred embodiments described herein are merely for illustrating and explaining the present invention, and are not intended to limit the present invention, and that the embodiments and features of the embodiments in the present invention may be combined with each other without conflict.

When encoding audio and video data and controlling a code rate, the encoding may be implemented by using an encoding chip and an FPGA (Field Programmable Gate Array), and a schematic block diagram of the code rate control method implemented by using the encoding chip and the FPGA, which is provided in an embodiment of the present invention, is shown in fig. 1, where: audio and video data are firstly input into an encoding chip 11 to be encoded to obtain an ES packet, and then the obtained ES packet is divided into M PES packets; dividing each PES packet into N first TS packets with fixed packet lengths, wherein M and N are integers; after N first TS packets are obtained, for each first TS packet, determining a corresponding decoding time tag (DTS) according to the sequence number of the first TS packet obtained by dividing, adding the DTS corresponding to each obtained first TS packet and a preset Packet Identifier (PID) into the packet header of the first TS packet, adding the corresponding DTS and the preset PID into the packet header of each N first TS packet based on the DTS and the preset PID, sending the N first TS packets to an FPGA, and executing code rate control operation by the FPGA.

The FPGA 12 executes the following processes:

firstly, after receiving each first TS packet sent by the encoding chip 11, the FPGA 12 realizes synchronization of the first TS packets by using a synchronization byte carried in a packet header of the first TS packet, such as 0X 47; the synchronization operation facilitates the FPGA to count the code rate and detect the first TS packet entering the FPGA.

Secondly, the synchronized first TS packet is subjected to DDR (Double Data Rate, Double Data Rate synchronous dynamic random access memory) preprocessing to obtain a second TS packet, in order to increase the bandwidth Rate, the embodiment of the present invention may adopt multiple DDRs to achieve the effect, here, taking two DDRs 3 as an example for explanation, the input of the two DDR3 is 64 bits, and the output is 128 bits. Therefore, before the first TS packet is subjected to DDR preprocessing, bit width conversion, packet length conversion, and clock domain conversion need to be performed, that is, the first TS packet with a bit width of 8 bits is converted into a second TS packet with a bit width of 64 bits; before the conversion process, 188 × 8/64 cannot be divided completely when the packet length of each first TS packet is 188B and the bit width is 8bit and the conversion is 64bit, so that the first TS packet with the packet length of 188B is converted into a second TS packet with the packet length of 192B, and in addition, in order to distinguish programs from different programs or programs with different port numbers, the extra 4 bytes are used for increasing information such as port numbers when the packet length conversion is carried out; the clock domain of the first TS packet is then converted to the clock domain of the DDR3, upon which a converted second TS packet is obtained.

It should be noted that, because the first TS packet output by the encoding chip 11 and the second TS packet obtained by performing bit width, packet length, and clock domain conversion may be obtained by encoding audio and video data from multiple ports or multiple programs, it is necessary to map to a corresponding DDR3 port number according to a self-defined PID [7:0] in a packet header of the second TS packet, that is, for the second TS packet obtained by encoding and converting audio and video data from different port numbers or different programs, the positions stored in the DDR3 are also different, and three programs are exemplified, such as a program a, a program B, and a program C, and N second TS packets are obtained after processing, where N is an integer, if the audio and video data in the 1 st to i second TS packets are from the program a, and PIDs of the i second TS packets are all 00000001; audio and video data in the (i + 1) th to the kth second TS packets come from a program B, and the PIDs of the k-i second TS packets are 00000010; audio and video data in the (k + 1) th to the Nth second TS packets come from a program C, and PIDs of the N-k second TS packets are 00000100; when the DDR3 predefines the corresponding relation between the DDR3 port number and the PID, for example, the PID is 00000001, the memory address allocated to the DDR3 is 0-03A 6; when the PID is 00000010, the DDR3 allocates the memory addresses 03A 7-076D for the memory addresses; when the PID is 00000001, the DDR3 allocates the memory addresses 076E-0 AF 4. After the DDR3 finds the corresponding relation, the second TS packets corresponding to the program A, the program B and the program C are respectively stored into three different partitions of the DDR3, and the starting addresses of the three different partitions in the DDR3 are different.

When the second TS packet is stored in the DDR3, the second TS packet is already stored in a partition according to the difference between the port number and the PID, so that reading the second TS packet data from the corresponding partition of the DDR3 is divided into three ways, and corresponding delay control is performed according to the DTS value carried in the packet header of each second TS packet. Specifically, the audio and video data only can be output at a stable code rate within a preset range by requiring the difference (DTS-PCR) between the DTS and the program clock reference PCR during transmission, and if the audio and video data requires the DTS-PCR to be controlled to be about 80 ms; for video data, the DTS-PCR is required to be controlled to be about 400 ms; therefore, when performing delay control on reading each second TS packet from the corresponding partition of the DDR3, it is required to obtain each corresponding DTS value from the packet header of each second TS packet, then the local clock of the FPGA is divided into 90KHz pulses by the 300 frequency divider and sent to a 33-bit counter to generate a 90KHz base value, and forms a 42-bit counter together with the count of the system clock, the 42-bit counter performs counting, the delay control unit is configured to compare the DTS value with the value generated by the counter, when the delay control unit determines that the difference between the DTS value and the value generated by the counter is within a preset range, the high 33 bits of the counter at the current time of the counter are taken as the finally obtained PCR value, the delay control unit outputs a read command to the DDR3 memory, and when the DDR3 memory receives the read command, the second TS packet in the corresponding partition is sent to the delay control unit, and the delay control unit completes the operation of reading the second TS packet from the corresponding partition of the DDR3 with stable code rate, or when the delay control unit determines that the difference value between the DTS and the value generated by the counter is within the preset range, on one hand, the high 33 bits of the 42-bit counter are taken as the final PCR value, and on the other hand, the delay control unit directly reads from the corresponding partition of the DDR3, on the basis, the second TS packet in the DDR3 can be read according to the difference value between the DTS value corresponding to each second TS packet and the PCR value corresponding to the second TS packet generated when the counter passes the counting, which is within the preset range, and the second TS packet data is read from the DDR3 at a stable code rate.

It should be noted that, in order to prevent the second TS packet from overflowing in the DDR3If the delay control unit is out of order, a protection operation can be added to the delay control unit, for example, when the counter in the delay control unit is out of order, the delay control unit does not determine that the difference value between the DTS and the value generated by the counter is within the preset range, and the delay control unit can reset a threshold value such as T_{Maximum value}When the delay control unit detects that the difference value between the DTS and the value generated by the counter is greater than T_{Maximum value}In time, the delay control unit can feed back a reading command to the DDR3 memory without judging whether the difference value between the DTS and the value generated by the counter is within the preset range, and the DDR3 outputs the second TS packet of the corresponding partition and sends the second TS packet to the delay control unit, or the delay control unit directly reads the second TS packet from the corresponding partition of the DDR 3.

Further, when each second TS packet data read from the DDR3 is output as a 128-bit second TS packet, and each second TS packet to be transmitted should be 8bit, so that it is further necessary to perform bit width conversion on the 128-bit second TS packet read from the DDR3 to obtain an 8-bit second TS packet, perform packet length conversion on the 192B second TS packet to obtain a 188B second TS packet, divide one second TS packet data TS stream into n data streams according to the port number information carried in the packet header of the second TS packet, update the corresponding DTS value in the packet header of each second TS packet to obtain a third TS packet, and before performing TS transmission, perform TS multiplexing on each third TS packet obtained by independent processing on the three branches to obtain one TS transport stream, and then perform transmission.

In summary, the operation of transmitting audio and video data at a stable code rate is completed by using the encoding chip 11 and the FPGA 12, firstly, the encoding chip 11 encodes audio and video information to be encoded to obtain an elementary stream ES, and the ES is divided into M packetized elementary stream PES packets; dividing each PES packet into N first TS packets according to a fixed packet length, and determining a corresponding decoding time tag DTS according to the serial number of the divided first TS packets, wherein the N first TS packets are corresponding to each first TS packet; adding the obtained DTS and a preset packet identifier PID into the packet header of the first TS packet; then, receiving a first TS packet by using the FPGA 12, wherein the packet header of the first TS packet carries identification information, and the identification information comprises a decoding time tag DTS and a packet identification PID of the first TS packet; preprocessing the first TS packet to obtain a second TS packet; and storing the second TS packet in a partition mode according to the PID; and aiming at the second TS packet stored in each partition, performing code rate control on the second TS packet read from the corresponding partition according to the DTS in the second TS packet and the program clock reference PCR corresponding to the second TS packet, thereby ensuring that audio and video data are transmitted at a stable code rate and improving the code rate control precision and the audio and video data output quality.

The following describes the code rate control method and apparatus provided by the present invention in detail with specific embodiments in conjunction with the accompanying drawings.

The first embodiment,

As shown in fig. 2a, an implementation flow diagram of the code rate control method provided in the embodiment of the present invention may include the following steps:

and S21, receiving a first Transport Stream (TS) packet, wherein the packet header of the first TS packet carries identification information, and the identification information comprises a Decoding Time Stamp (DTS) and a Packet Identification (PID) of the first TS packet.

In specific implementation, the first TS packet header carries identification information, and for each first TS packet, the identification information is added to the first TS packet according to the method shown in fig. 2 b:

s211, encoding audio and video information to be encoded to obtain elementary stream ES, and dividing the ES into M packaged elementary stream PES packets.

In specific implementation, before audio and video data is transmitted in a digital television, according to the structure of MPEG-2, audio and video and some auxiliary data need to be digitized, then the digitized audio and video and some auxiliary data and a compression layer are subjected to compression coding of a signal source to respectively form an audio ES stream, a video ES stream and other auxiliary ES streams, and then the audio ES stream, the video ES stream and other auxiliary ES streams are respectively subjected to segmentation processing.

S212, each PES packet is divided into N first TS packets according to a fixed packet length.

Because each PES packet obtained by dividing in step S211 may have a variable or fixed packet length, and the PES packet is an original data stream of audio and video, and also includes some necessary system information, such as a group header, a system header, a program stream map, a program stream directory, and the like. In order to normally transmit audio and video data of one or more programs under a transmission environment with a possibility of serious errors, a PES needs to be converted into a TS transport stream according to the requirements of a transmission protocol, so that each PES packet is divided into N first TS packets according to a fixed packet length, wherein N is an integer, preferably, the fixed packet length can be 188 bytes, and the unit is B, that is, the packet length divided into the N first TS packets is 188B.

And S213, determining a corresponding decoding time tag DTS according to the sequence number of the first TS packet obtained by dividing for each first TS packet.

Specifically, when the ES stream is divided into M PES packets, although the packet length of the M PES packets may not be fixed, the packet length of each PES packet is fixed, so when each PES packet is divided into N first TS packets, since the packet length of the first TS packet is fixed, for each first TS packet, the corresponding DTS value may be determined according to the sequence number of the first TS packet obtained by the division, specifically, if the packet length of a certain PES packet is 900B, that is, the packet length of a valid PES packet is 900, since the packet length of the first TS packet includes a packet header and a payload, the packet header is 8 bytes, and the payload is 180 bytes, the PES packet may be divided into 900/180 ═ 5 first TS packets, when the ES stream is packed into PES packets, the system adds a decoding display time DTS in advance to the packet header of the PES packet, and according to the requirements of the national television standard, the ES stream may be divided into N-system and P-system programs, the N system program requires 30 frames to be transmitted every second, the P system program requires 25 frames to be transmitted every second, and the PES is packaged according to each frame when being divided into first TS packets, therefore, the time occupied by the transmission of one frame of audio and video data according to the N system is not higher than 33.3ms, the time occupied by the transmission of one frame of audio and video data according to the P system is not higher than 40ms, the P system is taken as an example for explanation, when the PES is divided into 5 first TS packets, the time occupied by each first TS packet is not higher than 8ms, and the DTS value of the first TS packet is DTS; the DTS value of the second TS packet is DTS +8, and so on, the DTS values corresponding to the 5 first TS packets can be obtained.

It should be noted that, when the encoding chip is used to encode the audio/video data to finally obtain the TS packet, there may be a certain delay in the encoding chip, for example, the delay is represented by "delta", and for different encoding chips, the delta values may be different, but when one encoding chip is used to process the audio/video data, the delta values are the same, so in specific implementation, it is further necessary to add the encoding delay delta value to the DTS value corresponding to each obtained first TS packet to be the final DTS value corresponding to each first TS packet.

S214, adding the obtained DTS and the preset packet identification PID into the packet header of the first TS packet.

In specific implementation, the PID is an 8-bit private packet identifier, and a user can customize the PID as required to identify which program or which port number the first TS packet data comes from.

It should be noted that, for the first TS packet, the format thereof is basically defined according to the standard TS packet format, and the difference points are: and when the Pusi is 1, the first TS packet is the first TS packet of the current audio and video frame. The header of the first TS packet has 8 bytes, and includes: the packet header definition may refer to the packet header format as shown in table 1, including the sync byte, the packet identification PID, the number of valid PES packet data bytes LEN, pun, DTS, the first TS packet data, and possibly trailer invalid data:

TABLE 1

Synchronous byte

PID

LEN

Pusi

Dummy byte

DTS

Data LEN bytes

Invalid data

0x47

8bit

1bit

6bit

33bit

8bit

Optionally

The sync byte in table 1 is used for synchronization of the first TS packet, has 8 bits, and may be 0x 47; the packet identifier PID is used for distinguishing different first TS packets from different audio and video data, and the TS packets are 8 bits; LEN [7:0] for indicating the number of bytes of valid PES packet data in the current first TS packet; the value of LEN is generally 180; the present invention is directed to a system for determining whether a current first TS packet is a first TS packet of a certain audio/video frame, and whether the current first TS packet is a first TS packet of a certain audio/video frame when the signal is 0, or 1, or a first TS packet of a certain audio/video frame. For example, it may be defined that when the puni is 1, it indicates that the current first TS packet is the first TS packet of a certain audio/video frame, and when the puni is 0, it indicates that the current first TS packet is not the first TS packet of a certain audio/video frame.

In table 1, the DTS [0:32] is 33 bits, and the DTS value is the decoding time stamp DTS corresponding to each first TS packet determined according to the sequence number of the first TS packet obtained by dividing in step 213. Data LEN number of bytes indicates: when a PES packet is divided into N first TS packets, the valid PES packet data in each first TS packet is generally 180B, and only in the last first TS packet, if the valid PES packet data is less than 180B, invalid data may be added to the tail of the valid PES packet data included in the last first TS packet, so as to ensure that the data in the last first TS packet is 180B.

And S22, preprocessing the first TS packet to obtain a second TS packet.

In specific implementation, before preprocessing the first TS packet, a synchronization operation is further performed, specifically: the synchronization of the first TS packet is realized by using a synchronization byte carried in the packet header of the first TS packet, such as 0X 47; the synchronization operation facilitates the FPGA to count the code rate and detect the first TS packet entering the FPGA.

The synchronized first TS packet is subjected to DDR (Double Data Rate, Double Data Rate synchronous dynamic random access memory) preprocessing to obtain a second TS packet, in order to increase the bandwidth Rate, the embodiment of the present invention may implement this effect by using multiple DDRs, here, taking two DDRs 3 as an example for explanation, the input of the two DDRs 3 is 64 bits, and the output is 128 bits. Therefore, before the first TS packet is subjected to DDR preprocessing, bit width conversion, packet length conversion, and clock domain conversion need to be performed, that is, the first TS packet with a bit width of 8 bits is converted into a second TS packet with a bit width of 64 bits; before the conversion process, 188 × 8/64 cannot be divided completely when the packet length of each first TS packet is 188B and the bit width is 8bit and the conversion is 64bit, so that the first TS packet with the packet length of 188B is converted into a second TS packet with the packet length of 192B, and in addition, in order to distinguish programs from different programs or programs with different port numbers, the extra 4 bytes are used for increasing information such as port numbers when the packet length conversion is carried out; the clock domain of the first TS packet is then converted to the clock domain of the DDR3, upon which a converted second TS packet is obtained.

And S23, storing the second TS packets in a partition mode according to the PID.

Since the second TS packet obtained through bit width, packet length, and clock domain conversion may be obtained by encoding audio/video data from multiple ports or multiple programs, the second TS packet needs to be stored in a partitioned manner, specifically: mapping to a corresponding DDR3 port number according to a self-defined PID [7:0] in a second TS packet header, namely, aiming at a second TS packet obtained by encoding and converting audio and video data from different port numbers or different programs, the positions stored in a DDR3 are also different, and explaining by taking three programs as an example, such as a program A, a program B and a program C, processing to obtain N second TS packets, wherein N is an integer, and if the audio and video data in the 1 st to ith second TS packets are from the program A, the PIDs of the i second TS packets are 00000001; audio and video data in the (i + 1) th to the kth second TS packets come from a program B, and the PIDs of the k-i second TS packets are 00000010; audio and video data in the (k + 1) th to the Nth second TS packets come from a program C, and PIDs of the N-k second TS packets are 00000100; when the DDR3 predefines the corresponding relation between the DDR3 port number and the PID, for example, the PID is 00000001, the memory address allocated to the DDR3 is 0-03A 6; when the PID is 00000010, the DDR3 allocates the memory addresses 03A 7-076D for the memory addresses; when the PID is 00000001, the DDR3 allocates the memory addresses 076E-0 AF 4. After the DDR3 finds the corresponding relation, the second TS packets corresponding to the program A, the program B and the program C are respectively stored into three different partitions of the DDR3, and the starting addresses of the three different partitions in the DDR3 are different.

And S24, aiming at the second TS packets stored in each partition, performing code rate control on the second TS packets read from the corresponding partition according to the DTS in the second TS packets and the program clock reference PCR corresponding to the second TS packets.

In specific implementation, when the second TS packet is stored in the DDR3, the second TS packet is already stored in a partition according to the difference between the port number and the PID, so that reading the second TS packet data from the corresponding partition of the DDR3 is divided into three partitions, and corresponding delay control is performed according to the DTS value carried in the packet header of each second TS packet. Specifically, the audio and video data only can be output at a stable code rate within a preset range by requiring the difference (DTS-PCR) between the DTS and the program clock reference PCR during transmission, and if the audio and video data requires the DTS-PCR to be controlled to be about 80 ms; for video data, the DTS-PCR is required to be controlled to be about 400 ms; therefore, when performing delay control on reading each second TS packet from the corresponding partition of the DDR3, it is required to obtain each corresponding DTS value from the packet header of each second TS packet, then the local clock of the FPGA is divided into 90KHz pulses by the 300 frequency divider and sent to a 33-bit counter to generate a 90KHz base value, and forms a 42-bit counter together with the counting of the system clock, the 42-bit counter performs counting, the delay control unit is configured to compare the DTS value with the value generated by the counter, when the delay control unit determines that the difference between the DTS value and the value generated by the counter is within a preset range, the high 33 bits of the counter at the current time of the counter are taken as a finally obtained PCR value, the delay control unit outputs a read command to the DDR3 memory, when the DDR3 memory receives the read command, the second TS packet in the corresponding partition is sent to the delay control unit, and the delay control unit completes the operation of reading the second TS packet from the corresponding partition of the DDR3 with stable code rate, or when the delay control unit determines that the difference value between the DTS and the value generated by the counter is within the preset range, on one hand, the high 33 bits of the 42-bit counter are taken as the final PCR value, on the other hand, the second TS packet is directly read from the corresponding partition of the DDR3, on the basis, the PCR value corresponding to each TS packet can be obtained according to the DTS value corresponding to the TS packet, and the second TS packet data is guaranteed to be read from the DDR3 at a stable code rate.

It should be noted that, in order to prevent the overflow problem of the second TS packet in the DDR3, a protection operation may be further added to the delay control unit, for example, when the counter in the delay control unit is out of order, the delay control unit may not determine that the difference between the DTS and the value generated by the counter is within the preset range, and the delay control unit may further set a threshold, such as T_{Maximum value}When the delay control unit detects that the difference value between the DTS and the value generated by the counter is greater than T_{Maximum value}In time, the delay control unit can feed back a reading command to the DDR3 memory without judging whether the difference value between the DTS and the value generated by the counter is within the preset range, the DDR3 outputs a second TS packet of a corresponding partition and sends the second TS packet to the delay control unit, or the delay control unit directly sends the second TS packet to the delay control unit from the DDR3The DDR3 reads the second TS packet in the corresponding partition.

In summary, in the code rate control method provided in the embodiment of the present invention, a first TS packet is received, where a packet header of the first TS packet carries identification information, and the identification information includes a decoding time tag DTS and a packet identification PID of the first TS packet; preprocessing the first TS packet to obtain a second TS packet; and storing the second TS packet in a partition mode according to the PID; and aiming at the second TS packet stored in each partition, performing code rate control on the second TS packet read from the corresponding partition according to the DTS in the second TS packet and the program clock reference PCR corresponding to the second TS packet, thereby ensuring that audio and video data are transmitted at a stable code rate and improving the code rate control precision and the audio and video data output quality.

Example II,

Based on the same inventive concept, embodiments of the present invention further provide a code rate control apparatus, and because the principle of the apparatus for solving the problem is similar to that of the code rate control method, the implementation of the apparatus may refer to the implementation of the method, and repeated details are not repeated.

As shown in fig. 3, a schematic structural diagram of a code rate control apparatus provided in an embodiment of the present invention includes: a receiving unit 31, a processing unit 32, a storage unit 33 and a first determining unit 34, wherein:

a receiving unit 31, configured to receive a first transport stream TS packet, where a packet header of the first TS packet carries identification information, and the identification information includes a decoding time tag DTS and a packet identification PID of the first TS packet.

And the processing unit 32 is configured to pre-process the first TS packet to obtain a second TS packet.

In a specific implementation, the processing unit 32 is specifically configured to perform bit width conversion, packet length conversion, and clock domain conversion on each first TS packet to obtain a second TS packet corresponding to the first TS packet.

And a storage unit 33, configured to store the second TS packet in a partitioned manner according to the PID.

The first determining unit 34 is configured to perform, for the second TS packet stored in each partition, rate control on the second TS packet read from the corresponding partition according to the DTS in the second TS packet and the program clock reference PCR corresponding to the second TS packet.

In specific implementation, the first determining unit 34 specifically includes a determining subunit, a first control subunit, and a second control subunit, where;

and the determining subunit is used for determining the difference value between the DTS in the second TS packet and the PCR corresponding to the second TS packet.

And a first control subunit, configured to allow the second TS packet to be read from the corresponding partition if the difference value is within a preset range.

And a second control subunit, configured to disallow reading of the second TS packet from the corresponding partition if the difference value is not within the preset range.

In specific implementation, the apparatus further comprises: an updating unit 35 and a transmitting unit 36, wherein:

the updating unit 35 is configured to update, for the second TS packet stored in each partition, a corresponding DTS value in the packet header of the second TS packet to obtain a third TS packet.

And a transmission unit 36, configured to perform TS multiplexing on the third TS packet output by each partition, and then transmit the third TS packet.

Preferably, the apparatus further comprises: an encoding unit 37, a segmentation unit 38, a second determination unit 39 and a first addition unit 310, wherein:

and the encoding unit 37 is configured to encode the audio/video information to be encoded to obtain an elementary stream ES, and divide the ES into M packetized elementary stream PES packets.

A dividing unit 38 for dividing each PES packet into N first TS packets according to a fixed packet length.

The second determining unit 39 is configured to determine, for each first TS packet, a corresponding decoding time stamp DTS according to the sequence number of the first TS packet obtained by splitting.

A first adding unit 310, configured to add the obtained DTS and a preset packet identifier PID to a packet header of the first TS packet; wherein M and N are integers.

For convenience of description, the above parts are separately described as modules (or units) according to functional division. Of course, the functionality of the various modules (or units) may be implemented in the same or in multiple pieces of software or hardware in practicing the invention. For example, the code rate control device provided by the second embodiment of the present invention may be disposed in the encoding chip and the FPGA chip, and the encoding chip and the FPGA chip together complete the code rate control on the audio and video data.

The embodiment of the invention provides a code rate control method and a device, wherein a first TS packet is received, the packet head of the first TS packet carries identification information, and the identification information comprises a decoding time tag DTS and a packet identification PID of the first TS packet; preprocessing the first TS packet to obtain a second TS packet; and storing the second TS packet in a partition mode according to the PID; and aiming at the second TS packet stored in each partition, performing code rate control on the second TS packet read from the corresponding partition according to the DTS in the second TS packet and the program clock reference PCR corresponding to the second TS packet, thereby ensuring that audio and video data are transmitted at a stable code rate and improving the code rate control precision and the audio and video data output quality.

The code rate control apparatus provided in the embodiments of the present application may be implemented by a computer program. It should be understood by those skilled in the art that the above-mentioned block division is only one of many block division, and if the block division is divided into other blocks or not, it is within the scope of the present application as long as the rate control has the above-mentioned function.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A method for rate control, comprising:

preprocessing the first TS packet to obtain a second TS packet; and

performing partition storage on the second TS packets according to the PID;

2. The method of claim 1, wherein performing rate control on the second TS packets read from the corresponding partitions according to the DTSs in the second TS packets and the program clock reference PCRs corresponding to the second TS packets specifically comprises:

determining the difference value between the DTS in the second TS packet and the PCR corresponding to the second TS packet;

if the difference value is within a preset range, allowing the second TS packet to be read from the corresponding partition;

if the difference is not within the preset range, the second TS packet is not allowed to be read from the corresponding partition.

3. The method of claim 1, further comprising:

for the second TS packet stored in each partition, updating a corresponding DTS value in the packet header of the second TS packet to obtain a third TS packet;

and TS multiplexing is carried out on the third TS packet output by each subarea and then the third TS packet is transmitted.

4. The method of claim 1, wherein preprocessing the first TS packet to obtain a second TS packet specifically comprises:

and for each first TS packet, carrying out bit width conversion, packet length conversion and clock domain conversion on the first TS packet to obtain a second TS packet corresponding to the first TS packet.

5. The method of claim 1, wherein the identification information is added to the header of each first TS packet according to the following method:

coding audio and video information to be coded to obtain elementary stream ES, and dividing the ES into M packed elementary stream PES packets;

dividing each PES packet into N first TS packets according to a fixed packet length;

for each first TS packet, determining a corresponding decoding time tag DTS according to the sequence number of the first TS packet obtained by segmentation; and are

Adding the obtained DTS and a preset packet identifier PID into the packet header of the first TS packet;

wherein M and N are integers.

6. An apparatus for controlling a code rate, comprising:

7. The apparatus according to claim 6, wherein the first determining unit specifically includes:

a determining subunit, configured to determine a difference between a DTS in the second TS packet and a PCR corresponding to the second TS packet;

a first control subunit, configured to allow reading of the second TS packet from the corresponding partition if the difference value is within a preset range;

8. The apparatus of claim 6, further comprising:

a first adding unit, configured to update, for a second TS packet stored in each partition, a corresponding DTS value in a packet header of the second TS packet to obtain a third TS packet;

and the transmission unit is used for performing TS multiplexing on the third TS packet output by each subarea and then transmitting the third TS packet.

9. The apparatus of claim 6,

the processing unit is specifically configured to, for each first TS packet, perform bit width conversion, packet length conversion, and clock domain conversion on the first TS packet to obtain a second TS packet corresponding to the first TS packet.

10. The apparatus of claim 6, wherein the apparatus further comprises:

the encoding unit is used for encoding audio and video information to be encoded to obtain elementary stream ES and dividing the ES into M packed elementary stream PES packets;

a dividing unit for dividing each PES packet into N first TS packets according to a fixed packet length;

a second determining unit, configured to determine, for each first TS packet, a decoding time stamp DTS corresponding to the first TS packet according to the sequence number of the first TS packet obtained by splitting;

a second adding unit, configured to add the obtained DTS and a preset packet identifier PID to the packet header of the first TS packet;

wherein M and N are integers.