CN116686041A

CN116686041A - Driving circuit and display device

Info

Publication number: CN116686041A
Application number: CN202180089489.2A
Authority: CN
Inventors: 陈远龙; 洪炜翔; 杨汝辉; 张帆
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-01-28
Filing date: 2021-01-28
Publication date: 2023-09-01
Also published as: WO2022160208A1; EP4276812A1; EP4276812A4

Abstract

A driving circuit and a display device are provided for reducing system power consumption while accelerating a charge and discharge rate of a capacitor in a liquid crystal display. The driving circuit includes: a digital-to-analog converter (401) for outputting an analog signal; an amplifier (402) for generating a drive signal based on the analog signal, wherein the amplifier (402) comprises an amplifying circuit for amplifying the analog signal and a current source circuit for controllably providing a bias current for the amplifying circuit; and a comparison control circuit (403) for comparing the voltage value of the driving signal with a preset voltage value and controlling the current source circuit to output the bias current based on the comparison result.

Description

Driving circuit and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a driving circuit and a display device.

Background

The liquid crystal display is an indispensable component of electronic products such as televisions and computers. In general, the pixel units of the lcd may be formed by a resistor-capacitor (RC) network, where the RC network is formed by n×n pixel units, where N > 1, and each pixel unit includes a capacitor 101 and a resistor 102. In each pixel unit, the voltage values at both ends of the capacitor 101 are different, and the twist angles of the corresponding liquid crystals are also different. By controlling the charge and discharge of each capacitor 101 in the RC network, the torsion angle of the liquid crystal in the liquid crystal display can be controlled, so that the transmittance of the liquid crystal is controlled, and different display effects are achieved.

A nematic liquid crystal display and its driving circuit can be shown in FIG. 1. The Red Green Blue (RGB) data is processed by the data processing unit and the level shifter to obtain a plurality of control signals, and each control signal is used for controlling a column of pixel units. Specifically, a plurality of control signals are respectively input to a plurality of analog-to-digital converters (digital to analog converter, DACs), each DAC being coupled to a column of pixel cells through an amplifier. The driving signal output by the amplifier controls the charge and discharge of the capacitor 101 by controlling the on and off of the switching tube 103 coupled with each pixel unit, thereby achieving different display effects. The amplifier may also be referred to as a channel buffer (channel buffer) or an output buffer.

As the resolution of the lcd increases (e.g., from 4k to 8 k), the RC network becomes larger (i.e., the number of pixel units increases), and the channel buffer load becomes larger; meanwhile, with the increase of the data refresh rate of the liquid crystal display (for example, from 60Hz to 120 Hz), the requirement for the charge and discharge speed of the channel buffer is also increased. It is understood that a high-speed charge and discharge driving circuit is required as a support for the improvement of performance requirements of the liquid crystal display.

In order to improve the charge and discharge rate of the channel buffer, the scheme provided by the prior art is that a larger bias current is provided for the channel buffer within a fixed period of time (i.e. a fast charge current is added on the basis of the original bias current, so that the bias current is increased), so that the channel buffer can rapidly complete the charge and discharge of the capacitor 101 in the liquid crystal display screen. As shown in fig. 2, a Load Data (LD) signal is an RGB data refresh flag, and when the LD signal transitions from a low level to a high level, i.e., a data refresh time, it is generally necessary to perform data refresh a plurality of times when each frame of picture is displayed; the digital high-speed driving (digital high driving, DHDR) signal is a flag signal that the channel buffer introduces a large bias current, when the DHDR signal is at a high level, the channel buffer introduces a large bias current (for example, the fast charging current is superimposed on the original bias current), and when the DHDR signal is at a low level, the channel buffer introduces a small bias current. The DHDR duration is a fixed value.

By adopting the scheme provided by the prior art, the DHDR duration is a fixed value, and in order to ensure that the DHDR duration can meet the requirements of different loads, the DHDR duration is usually taken as a larger value. The channel buffer can cause great power consumption overhead after a long time of introducing a large bias current. Because the load demand is high or low when data refreshing is performed each time, the DHDR duration is taken to be a larger fixed value to meet the high load demand, which can cause the increase of the system power consumption.

In summary, the driving scheme provided in the prior art has a problem of higher system power consumption.

Disclosure of Invention

The embodiment of the application provides a driving circuit and a display device, which are used for reducing the system power consumption while accelerating the charge and discharge rate of a capacitor in a liquid crystal display.

In a first aspect, an embodiment of the present application provides a driving circuit, including: a digital-to-analog converter for outputting an analog signal; an amplifier for generating a driving signal based on the analog signal, wherein the amplifier includes an amplifying circuit for amplifying the analog signal and a current source circuit for controllably providing a bias current to the amplifying circuit; and the comparison control circuit is used for comparing the voltage value of the driving signal with a preset voltage value and controlling the current source circuit to output bias current based on the comparison result.

The comparison control circuit can be realized through two functional modules of a comparator and a controller. The comparator is used for comparing the voltage value of the driving signal with a preset voltage value; the controller is used for controlling the current source circuit to output bias current based on the comparison result of the comparator.

By adopting the scheme, the current source circuit in the amplifier can controllably provide bias current for the amplifying circuit. When the bias current of the amplifying circuit is smaller, the charge and discharge rate of a capacitor in the liquid crystal display coupled with the amplifying circuit is slower; when the bias current of the amplifying circuit is larger, the charge and discharge rate of the capacitor in the liquid crystal display coupled with the amplifying circuit is faster. The comparison control circuit 403 compares the voltage value of the driving signal output from the amplifier with a preset voltage value, and controls the current source circuit to output a bias current based on the comparison result. By the test mode, the comparison control circuit can control the bias current provided by the current source circuit based on the real comparison result of the voltage value of the driving signal and the preset voltage value, and the charge and discharge rate of the capacitor in the liquid crystal display coupled with the driving circuit is improved. Compared with the mode of setting the DHDR duration to a larger fixed value in the prior art, the bias current provided by the current source circuit is controlled in a mode of testing by the driving circuit, so that the bias current output by the current source circuit is more accurately adapted to the capacitance in the liquid crystal display, and the system power consumption is reduced.

In one possible design, a digital-to-analog converter is used in particular: outputting an analog signal at a first time; the current source circuit is specifically used for: providing a first bias current for the amplifying circuit before a first moment, and providing a second bias current for the amplifying circuit at the first moment, wherein the current value of the second bias current is larger than that of the first bias current; the controller is specifically for: and determining the difference between the second moment and the first moment when the driving signal turns over as the fast charge time, and controlling the current source circuit to output the bias current according to the fast charge time.

By adopting the scheme, under the condition that the amplifying circuit is supplied with the second bias current, the driving signal output by the amplifier can be changed from the maximum voltage value to the minimum voltage value or from the minimum voltage value to the maximum voltage value along with the input analog signal in the time period from the first moment to the second moment, so that the quick charge time determined by adopting the scheme can meet the charge and discharge time required by all the capacitors coupled with the operational amplifier in the liquid crystal display.

Specifically, the controller is specifically configured to, when controlling the current source circuit to output the bias current according to the fast charge duration: and when the liquid crystal display coupled with the driving circuit performs data refreshing each time, controlling the duration of outputting the second bias current by the current source circuit to be the fast charge duration.

In one possible design, the difference between the maximum voltage value and the minimum voltage value of the analog signal is greater than or equal to the maximum charge voltage value of the capacitor in the liquid crystal display; the preset voltage value is the maximum voltage value or the minimum voltage value of the analog signal.

By adopting the scheme, the difference between the maximum voltage value and the minimum voltage value of the analog signal is equal to the maximum charging voltage value of the capacitor in the liquid crystal display, or the difference between the maximum voltage value and the minimum voltage value of the analog signal is slightly larger than the maximum charging voltage value of the capacitor in the liquid crystal display, so that the quick charging time determined by adopting the scheme can meet the charging and discharging requirements of all the capacitors in the liquid crystal display, and the quick charging time can be shortened as much as possible, thereby reducing the power consumption of a system.

In one possible design, the analog signal is a first step signal, the voltage value of which increases from a first voltage value to a second voltage value at a first time; the comparator is used for comparing the voltage value of the driving signal with the second voltage value, and the moment when the output signal of the comparator is inverted from the low level to the high level is the second moment.

By adopting the scheme, the driving signal can be increased to the maximum voltage value of the analog signal from the minimum voltage value of the analog signal along with the input analog signal from the first time to the second time, and the difference between the maximum voltage value and the minimum voltage value of the analog signal is larger than or equal to the maximum charging voltage value of the capacitor in the liquid crystal display, so that the quick charging time determined by adopting the scheme can meet the charging and discharging time required by all the capacitors coupled with the amplifier in the liquid crystal display.

In another possible design, the analog signal is a second step signal, the voltage value of which decreases from the third voltage value to the fourth voltage value at the first moment; the comparator is used for comparing the voltage value of the driving signal with the fourth voltage value, and the moment when the output signal of the comparator is turned from the high level to the low level is the second moment.

By adopting the scheme, the driving signal can be reduced to the minimum voltage value of the analog signal from the maximum voltage value of the analog signal along with the input analog signal from the first time to the second time, and the difference between the maximum voltage value and the minimum voltage value of the analog signal is larger than or equal to the maximum charging voltage value of the capacitor in the liquid crystal display, so that the quick charging time determined by adopting the scheme can meet the charging and discharging time required by all the capacitors coupled with the amplifier in the liquid crystal display.

In addition, the first time and the second time may be located in a blanking region between a first frame and a second frame displayed by the liquid crystal display, and a display time of the first frame is earlier than a display time of the second frame.

By adopting the scheme, when the liquid crystal display displays pictures, a blanking area interval exists before refreshing each frame of displayed pictures, no signal is input into the liquid crystal display in the blanking area time period, and a viewer can not perceive that the liquid crystal display does not display pictures in the blanking area time period. Therefore, the scheme of determining the quick charge duration described above may be performed during a blanking region period before the first frame has been displayed and the second frame has not been displayed.

In one possible design, the digital-to-analog converter is also used to: performing digital-to-analog conversion on the digital control signal corresponding to the second frame of picture to obtain an analog control signal; the amplifying circuit is also used for: amplifying the analog control signal; the controller is further configured to: at a third moment when the amplifying circuit receives the analog control signal, the current source circuit is controlled to output a second bias current, at a fourth moment, the current source circuit is controlled to output a first bias current, and the time difference between the fourth moment and the third moment is the fast charge duration.

By adopting the scheme, the quick charge time length can be determined to be applied to the display of the second frame of pictures after the second moment.

In one possible design, the driving circuit provided in the first aspect may further include: the data processing unit is used for carrying out serial-parallel conversion on the red, green and blue RGB data to obtain parallel RGB data; and the level shifter is coupled with the data processing unit and is used for carrying out shift processing on the parallel RGB data to obtain the digital control signal.

In one possible design, the first time is the time at which the liquid crystal display is refreshed with data.

By adopting the scheme, the liquid crystal display needs to carry out data refreshing for a plurality of times when displaying each frame of picture. In practical applications, the LD signal may indicate the liquid crystal display to perform data refresh, for example, the LD signal may be a periodic pulse signal, and the time when the LD signal jumps from low level to high level (i.e. the time when the LD signal is valid) is the time when the liquid crystal display performs data refresh. The LD signal is a periodic signal, and is output in a blanking region before or during display of a screen by the liquid crystal display. The digital-to-analog converter can select a first moment when the LD signal is effective to output an analog signal to the amplifier, and the amplifier increases the bias current (from the first bias current to the second bias current) at the first moment.

In a second aspect, embodiments of the present application further provide a display device, which includes a liquid crystal display and a driving circuit provided in the first aspect and any possible designs thereof.

It should be noted that, the technical effects of the second aspect and any of the possible design manners thereof may refer to the technical effects of the different design manners in the first aspect, which are not described herein.

Drawings

Fig. 1 is a schematic diagram of a structure of a liquid crystal display and a driving circuit thereof according to the prior art;

FIG. 2 is a timing diagram of a digital LD signal and a DHDR signal according to the prior art;

fig. 3 is a schematic structural diagram of an amplifier according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a first driving circuit according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a second driving circuit according to an embodiment of the present application;

FIG. 6 is a timing diagram of signals in a driving circuit according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a third driving circuit according to an embodiment of the present application;

FIG. 8 is a timing diagram of signals in another driving circuit according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

The application scenario of the embodiment of the present application is first described below.

The embodiment of the application can be applied to the display device shown in fig. 1, which comprises a liquid crystal display and a driving circuit. The driving circuit controls the transmittance of liquid crystal in the liquid crystal display according to the received RGB data so as to achieve different display effects.

Specifically, the data processing unit in the driving circuit is used for performing serial-parallel conversion on the RGB data and outputting parallel RGB data; the level shifter is used for carrying out shift processing on the parallel RGB data to obtain a plurality of control signals; the DAC is used for performing digital-to-analog conversion on the control signal; the amplifier is used for buffering and outputting the control signal to obtain a driving signal.

Specifically, the liquid crystal display includes a resistor-capacitor (RC) network, where the RC network is composed of n×n pixel units, N > 1, and each pixel unit includes a capacitor 101 and a resistor 102. Each pixel unit is further coupled to a switching tube 103, and the driving signal output by the amplifier is used for controlling the on and off time of the switching tube 103, so as to control the charge and discharge process of the capacitor 101 in the pixel unit. Wherein each set of DAC and amplifier is used to control a column of pixel cells in the liquid crystal display.

The display device shown in fig. 1 further includes a Row Driver (Row Driver). The Row Driver is coupled to a control terminal (e.g., gate or base) of the switching transistor 103 in the lcd, and the Row Driver cooperates with a driving circuit to control the switching transistor 103 to be turned on or off.

It should be noted that, in the embodiment of the present application, when performing image display, specific functions and operations of the data processing unit, the level shifter and the DAC in the driving circuit may be implemented by using the prior art, which is not described herein. In the embodiment of the application, only how to increase the charge and discharge rate and reduce the system power consumption when the capacitor 101 in the liquid crystal display is charged and discharged by the driving circuit is concerned.

In practical application, when the capacitor 101 in the liquid crystal display is charged and discharged through the driving circuit, a larger bias current can be introduced into the power supply end of the amplifier, so as to improve the charging and discharging rate of the capacitor 101 in the liquid crystal display. Specifically, when the liquid crystal display displays each frame of picture, multiple times of data refreshing are needed; the power supply terminal of the amplifier can be supplied with a larger bias current each time data refreshing is performed.

Fig. 3 shows a schematic diagram of an amplifier, in which V _in V being the input of the amplifier _out Is the output of the amplifier. The example a of fig. 3 shows the overall structure of the amplifier, and the example b shows the internal structure of the amplifier. In example b, V _DD Is the power supply terminal of the amplifier and is used for inputting bias current. A small bias current is introduced into a power end of the amplifier, namely, bias current Iss is introduced into the power end; and a large bias current is introduced into the power supply end of the amplifier, namely, I1 is added on the basis of introducing Iss into the power supply end, and the current value of I1 is larger. When the bias current of the amplifier is large, the charge and discharge rate of the capacitor 101 in the pixel cell coupled to the amplifier is faster.

Although the charging and discharging rate of the capacitor 101 can be improved by applying a larger bias current to the power supply terminal of the amplifier, a large power consumption overhead is caused by applying a large bias current to the amplifier for a long time. Therefore, how to determine the duration of the amplifier that is fed with the large bias current, so that the charging duration can meet the load requirement (meet the requirement of rapid charging and discharging of the capacitor 101) and cannot cause larger system power consumption overhead is an implementation purpose of the embodiment of the application.

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

In the embodiment of the present application, the plurality means two or more. In addition, in the description of the present application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not be construed as indicating or implying a relative importance or order.

The embodiment of the application provides a driving circuit. Referring to fig. 4, the driving circuit 400 includes a digital-to-analog converter 401, an amplifier 402, and a comparison control circuit 403.

The digital-to-analog converter 401 is used for outputting an analog signal; an amplifier 402 is coupled to the digital-to-analog converter 401 for generating a drive signal based on the analog signal, wherein the amplifier 402 comprises an amplifying circuit for amplifying the analog signal and a current source circuit for controllably providing a bias current to the amplifying circuit; the comparison control circuit 403 is configured to compare a voltage value of the driving signal with a preset voltage value, and control the current source circuit to output a bias current based on a comparison result.

In practical application, the driving circuit 400 can be coupled with the liquid crystal display, and the driving circuit 400 can control the charge and discharge of the capacitor in the liquid crystal display, so that the torsion angle of the liquid crystal in the liquid crystal display can be controlled, the transmittance of the liquid crystal is controlled, and different display effects are achieved.

In the driving circuit 400, the amplifying circuit may be an operational amplifier. The current source circuit is used for providing bias current for the amplifying circuit. Specifically, the magnitude of the bias current supplied from the current source circuit to the amplifying circuit may be controlled by the comparison control circuit 403. When the current value of the bias current provided by the current source circuit is small, the rate of charging and discharging the capacitor in the liquid crystal display by the driving circuit 400 is slow; when the current value of the bias current supplied from the current source circuit is large, the rate of charging and discharging the capacitor in the liquid crystal display by the driving circuit 400 is high.

Specifically, the comparison control circuit 403 may include a comparator for comparing a voltage value of the driving signal with a preset voltage value, and a controller; the controller is used for controlling the current source circuit to output bias current based on the comparison result of the comparator. That is, the function of the comparison control circuit 403 can be realized by two functional blocks.

Further, the digital-to-analog converter 401 is specifically configured to: outputting an analog signal at a first time (hereinafter referred to as T1 time); the current source circuit is specifically used for: providing a first bias current for the amplifying circuit before a first moment, and providing a second bias current for the amplifying circuit at the first moment, wherein the current value of the second bias current is larger than that of the first bias current; the controller is specifically for: and determining the difference between the second moment (hereinafter referred to as T2 moment) when the output signal of the comparator turns and the first moment as the fast charge duration, and controlling the current source circuit to output the bias current according to the fast charge duration.

It can be seen that from time T1, the current source circuit provides a large bias current for the amplifying circuit. As the bias current increases, the driving signal output from the amplifying circuit changes. The output signal of the comparator will vary according to the variation with the drive signal. The moment when the output signal of the comparator toggles is defined as the T2 moment. The difference between the time at the time T2 and the time at the time T1 is the quick charge duration. The controller may control the current source to output the bias current according to the fast charge duration.

Specifically, the controller may control the duration of the current source circuit outputting the second bias current to be the fast charge duration each time the liquid crystal display coupled to the driving circuit 400 performs data refresh. Namely, the time for controlling the amplifying circuit to be electrified with the large bias current is the fast charging time.

Assume that the duration of one data refresh is Tr and the fast charge duration is Tf. Then the controller may control the current source circuit to supply the second bias current (large bias current) to the amplifying circuit for a period Tf and control the current source circuit to supply the first bias current (small bias current) to the amplifying circuit for a period Tr-Tf during the Tr period.

When the liquid crystal display performs data refreshing, the bias current of the amplifying circuit is increased, so that the charge and discharge rate of the capacitor in the liquid crystal display can be increased, the data refreshing rate of the liquid crystal display is further increased, and the performance of the liquid crystal display is improved.

Specifically, the driving circuit 400 may perform the above scheme in the Blanking region (V-Blanking) between the first frame and the second frame to determine the quick charge period. Wherein, the display time of the first frame picture is earlier than the display time of the second frame picture. That is, the time T1 and the time T2 are both located in the blanking region between the first frame and the second frame displayed by the liquid crystal display.

When the liquid crystal display displays pictures, a Blanking area interval exists before each frame of pictures to be displayed are refreshed, no signal is input into the liquid crystal display in the V-Blanking time period, and a viewer can not visually perceive that the liquid crystal display does not display pictures in the V-Blanking time period. Therefore, the above scheme of determining the quick charge time period can be performed in a V-Blanking period before the first frame has been displayed and the second frame has not been displayed. Then, after the second time, the fast charge duration is applied when the liquid crystal display performs data refresh.

It should be noted that, the fast charging time period obtained by adopting the scheme provided by the embodiment of the application can be only applied to display of the second frame of picture, and can also be applied to display of other pictures after the second frame of picture. The application range of the quick charge duration in the embodiment of the present application is not particularly limited.

In a specific example, the driving circuit 400 may perform the above scheme in the blanking area before each frame is displayed, and the obtained fast charge period is only applied to the display of the next frame.

In another example, the driving circuit 400 may perform the above scheme only once, and the acquired quick charge period is applied to the display of all pictures.

In yet another example, the driving circuit 400 may periodically perform the above scheme, and the obtained fast charge period is applied to the display of all pictures in one period. For example, the driving circuit 400 executes the above scheme once every five frames of pictures are displayed, and the obtained fast charge time period is applied to the display of the next five frames of pictures.

When the fast charge period is applied to the display of the second frame after the second time, specifically, when the second frame is displayed, the digital-to-analog converter 401 is further configured to: performing digital-to-analog conversion on the digital control signal corresponding to the second frame of picture to obtain an analog control signal; the amplifying circuit is also used for: amplifying the analog control signal; the controller is further configured to: at a third moment when the amplifying circuit receives the analog control signal, the current source circuit is controlled to output a second bias current, at a fourth moment, the current source circuit is controlled to output a first bias current, and the difference between the fourth moment and the third moment is the fast charge duration.

That is, the controller controls the duration of the second bias current (large bias current) output by the current source circuit to be the aforementioned quick charge duration.

As described above, when displaying the second frame of image, the lcd needs to perform multiple data refreshing. Then, when the second frame of picture is displayed, it is assumed that the duration of one data refresh is Tr and the fast charge duration is Tf. Then the controller may control the current source circuit to supply the second bias current (large bias current) to the amplifying circuit for a period Tf and control the current source circuit to supply the first bias current (small bias current) to the amplifying circuit for a period Tr-Tf during the Tr period.

In addition, the driving circuit 400 may further include: a data processing unit for performing serial-parallel conversion on the RGB data inputted to the driving circuit 400 to obtain parallel RGB data; and the level shifter is coupled with the data processing unit and is used for carrying out shift processing on the parallel RGB data to obtain a digital control signal corresponding to the second frame picture.

The execution time and the application of the quick charge time period of the embodiment of the application are introduced, and the specific scheme for determining the quick charge time period in the embodiment of the application is introduced.

In the embodiment of the present application, at time T1, the digital-to-analog converter 401 outputs an analog signal to the amplifier 402; meanwhile, at time T1, the bias current supplied to the power supply terminal of the amplifier 402 increases from the first bias current to the second bias current. After the above steps are performed, the driving signal output by the amplifier 402 will change according to the change of the input analog signal, the comparison control circuit 403 compares the driving signal output by the amplifier 402 with a preset voltage value (the maximum voltage value or the minimum voltage value of the analog signal), the moment when the output signal of the comparison control circuit 403 turns over is defined as the T2 moment, and the difference between the T2 moment and the T1 moment is the fast charge duration.

The difference between the time T2 and the time T1 can be acquired by a pulse sampling circuit (pulse sample circuit) in the controller. The specific structure and function of the pulse sampling circuit can be described in the prior art, and will not be described here.

In addition, in the embodiment of the present application, the first time may be a time when the data refresh is performed on the liquid crystal display.

As described above, the lcd needs to perform data refresh multiple times when displaying each frame. In practical applications, the LD signal may indicate the liquid crystal display to perform data refresh, for example, the LD signal may be a periodic pulse signal, and the time when the LD signal jumps from low level to high level (i.e. the time when the LD signal is valid) is the time when the liquid crystal display performs data refresh. The LD signal is a periodic signal, and is output in both the blanking region during and before the display of the screen by the liquid crystal display. Then, in the blanking region between the first frame and the second frame, the LD signal is also output. In executing the scheme of the embodiment of the present application, the digital-to-analog converter 401 may select the time T1 when the LD signal is valid to output the analog signal to the amplifier 402, and the bias current of the amplifier 402 is also increased from the first bias current to the second bias current at the time T1.

In the embodiment of the application, the difference between the maximum voltage value and the minimum voltage value of the analog signal is greater than or equal to the maximum charge voltage value of the capacitor in the liquid crystal display. In particular, the types of analog signals may be varied, and different types of analog signals are described below by way of several specific examples.

Example one

The analog signal may be a first step signal, the voltage value of the first step signal increasing from a first voltage value to a second voltage value at a first time; the comparison control circuit 403 is configured to compare the voltage value of the driving signal with the second voltage value, and the time when the output signal of the comparison control circuit 403 is inverted from the low level to the high level is the second time.

It can be seen that in example one, the minimum voltage value of the analog signal is a first voltage value, and the maximum voltage value is a second voltage value.

In the embodiment of the present application, the power supply terminal of the amplifier 402 is supplied with the second bias current while the first step signal is input to the amplifier 402. The amplifier 402 buffers and outputs the first step signal. Under the combined action of the first step signal and the second bias current, the amplifier 402 charges the capacitance in the liquid crystal display. The voltage value of the driving signal output by the amplifier 402 is gradually increased from the first voltage value, the comparison control circuit 403 compares the voltage value of the driving signal with the maximum voltage value (i.e., the second voltage value) of the analog signal, when the voltage value of the driving signal is increased to the second voltage value, the output signal of the comparison control circuit 403 is turned from low level to high level, the time when the output signal of the comparison control circuit 403 is turned is defined as the time T2, and the difference between the time T2 and the time T1 is the fast charge duration.

It should be noted that, in the first example, the comparison control circuit 403 is configured to compare the voltage value of the driving signal with the maximum voltage value of the analog signal, that is, the same-directional input terminal of the comparator in the comparison control circuit 403 is configured to receive the driving signal, and the opposite-directional input terminal is configured to receive the maximum voltage value (i.e., the second voltage value) of the analog signal. Therefore, when the voltage value of the drive signal is smaller than the maximum voltage value of the analog signal, the comparison control circuit 403 outputs a low level; when the voltage value of the drive signal is greater than or equal to the maximum voltage value of the analog signal, the comparison control circuit 403 outputs a high level. Then, when the voltage value of the drive signal increases to the maximum voltage value of the analog signal, the output signal of the comparison control circuit 403 is inverted from low to high, and the timing at which the output signal of the comparison control circuit 403 is inverted from low to high is the timing T2. If the receiving signals of the same-direction input terminal and the opposite-direction input terminal of the comparator are exchanged (i.e., the same-direction input terminal of the comparator is used for receiving the maximum voltage value of the analog signal, and the opposite-direction input terminal is used for receiving the driving signal), when the voltage value of the driving signal increases to the maximum voltage value of the analog signal, the output signal of the comparison control circuit 403 is turned from high level to low level, and the time when the output signal of the comparison control circuit 403 is turned from high level to low level is T2.

The driving signal output by the amplifier 402 can be increased from the minimum voltage value of the analog signal to the maximum voltage value of the analog signal along with the input analog signal in the period from the time T1 to the time T2, and the difference between the maximum voltage value and the minimum voltage value of the analog signal is greater than or equal to the maximum charge voltage value of the capacitor in the liquid crystal display, so the fast charge duration determined by the scheme can satisfy the charge and discharge time required by all the capacitors coupled with the amplifier 402 in the liquid crystal display.

In practical applications, the voltage applied to the liquid crystal (i.e. the voltage applied to the capacitor) in the liquid crystal display may be referred to as a gamma voltage, where the gamma voltage may be represented by VGMA <1>, VGMA <2>, VGMA <3>, … …, VGMA <14>, where the voltage value corresponding to VGMA <1> is the smallest, the voltage value corresponding to VGMA <14> is the largest, and the voltage values corresponding to VGMA <1> →vgma <14> sequentially increase. For a certain capacitor in the liquid crystal display, the voltage variation range of the capacitor may be 0-VGMA <7>, for example, corresponding to 0V-9V, or may be VGMA <8> -VGMA <14>, for example, corresponding to 9V-18V. It is clear that in this liquid crystal display, the maximum charge voltage value of the capacitor is 9V. Then, in example one, the minimum voltage value of the first step signal (i.e., the first voltage value) may be 0V and the maximum voltage value of the first step signal (i.e., the second voltage value) may be VGMA <7>.

Fig. 5 shows a schematic diagram of a driving circuit according to an embodiment of the present application, which includes a DAC, an amplifier AMP, a current source circuit, and a comparator Comp. In addition, the driving circuit may further include a controller, not shown in fig. 5. The DAC inputs the digital signal, and outputs the analog signal after digital-to-analog conversion. The output analog signal is a step signal (also referred to as an Hline pattern signal) from 0 to VGMA <7>, and the bias current of AMP is increased by the current source circuit, at this time, the AHDR signal is set to a high level, the AHDR signal is a signal for indicating the fast charge duration defined in the embodiment of the present application, and the time when the AHDR signal jumps high can be understood as the aforementioned time T1. The output signal CH1 of AMP is compared with the high reference voltage VGMA <7> outputted from the gamma voltage generating circuit, when AMP charges the capacitor in the LCD, CH1 outputs the high reference voltage VGMA <7>, the magnitude of CH1 and the high reference voltage VGMA <7> can be judged by the comparator Comp with offset voltage, when the comparator output is high, AHDR becomes low (the moment when AHDR signal becomes low can be understood as the moment T2), and the bias current stops increasing. The effective AHDR width is obtained by sampling by a controller (not shown in fig. 5), that is, the aforementioned quick charge duration. After the V-Blanking interval is finished, a large bias current interval with the same width as AHDR is given to AMP every time data refreshing (LD), so that the purpose of quick charging is achieved.

Fig. 6 is a timing chart of signals in the driving circuit shown in fig. 5. As can be seen from fig. 6, when the above scheme is performed in the V-Blanking interval, the DAC outputs an Hline pattern signal to AMP at the time when the LD is active, and the AHDR signal is set to high level; the output CH1 of AMP gradually rises from 0 to VGMA <7>, when CH1 reaches VGMA <7>, comp's output changes from low to high, at which time the AHDR signal is set low; the duration of the high level of the AHDR signal is a fast charging duration, and the fast charging duration is taken as an acceleration duration for AMP during each data refresh when the picture is displayed later (i.e., active interval).

Example two

The analog signal may be a second step signal, the voltage value of which decreases from the third voltage value to the fourth voltage value at the first moment; the comparison control circuit 403 is configured to compare the voltage value of the driving signal with the fourth voltage value, and the time when the output signal of the comparison control circuit 403 is inverted from the high level to the low level is the second time.

It can be seen that in example two, the minimum voltage value of the analog signal is the fourth voltage value, and the maximum voltage value is the third voltage value.

In the embodiment of the present application, the second bias current is introduced to the power supply terminal of the amplifier 402 while the second step signal is input to the amplifier 402. The amplifier 402 buffers and outputs the second step signal. Under the combined action of the second step signal and the second bias current, the amplifier 402 discharges the capacitance in the liquid crystal display. The voltage value of the driving signal output by the amplifier 402 is gradually reduced from the third voltage value, the comparison control circuit 403 compares the voltage value of the driving signal with the minimum voltage value (i.e., the fourth voltage value) of the analog signal, when the voltage value of the driving signal is reduced to the fourth voltage value, the output signal of the comparison control circuit 403 is turned from high level to low level, the time when the output signal of the comparison control circuit 403 is turned is defined as the time T2, and the difference between the time T2 and the time T1 is the fast charge duration.

It should be noted that, in the second example, the comparison control circuit 403 is configured to compare the voltage value of the driving signal with the minimum voltage value of the analog signal, that is, the same-directional input terminal of the comparator in the comparison control circuit 403 is configured to receive the driving signal, and the opposite-directional input terminal is configured to receive the minimum voltage value (i.e., the fourth voltage value) of the analog signal. Therefore, when the voltage value of the drive signal is greater than the minimum voltage value of the analog signal, the comparison control circuit 403 outputs a high level; when the voltage value of the drive signal is less than or equal to the minimum voltage value of the analog signal, the comparison control circuit 403 outputs a low level. Then, when the voltage value of the drive signal decreases to the minimum voltage value of the analog signal, the output signal of the comparison control circuit 403 is turned from high to low, and the time at which the output signal of the comparison control circuit 403 is turned from high to low is T2. If the receiving signals of the same-direction input terminal and the opposite-direction input terminal of the comparator are exchanged (i.e., the same-direction input terminal of the comparator is used for receiving the minimum voltage value of the analog signal, and the opposite-direction input terminal is used for receiving the driving signal), when the voltage value of the driving signal decreases to the minimum voltage value of the analog signal, the output signal of the comparison control circuit 403 is turned from low level to high level, and the time when the output signal of the comparison control circuit 403 is turned from low level to high level is T2.

The driving signal output by the amplifier 402 can be reduced from the maximum voltage value of the analog signal to the minimum voltage value of the analog signal along with the input analog signal from the time T1 to the time T2, and the difference between the maximum voltage value and the minimum voltage value of the analog signal is greater than or equal to the maximum charge voltage value of the capacitor in the liquid crystal display, so the fast charge duration determined by the scheme can satisfy the charge and discharge time required by all the capacitors coupled with the amplifier 402 in the liquid crystal display.

Fig. 7 shows a schematic diagram of a driving circuit according to an embodiment of the present application, which includes a DAC, an amplifier AMP, a current source circuit, and a comparator Comp. In addition, the driving circuit may further include a controller, not shown in fig. 7. The DAC inputs the digital signal, and outputs the analog signal after digital-to-analog conversion. The output analog signal is a step signal from VGMA <14> to VGMA <8>, and the bias current of AMP is increased by the current source circuit, at this time, the AHDR signal is set to be high level, the AHDR signal is the signal which is defined in the embodiment of the application and is used for indicating the fast charge duration, and the time of the jump-up of the AHDR signal can be understood as the time T1. The output CH1 of AMP is compared with the low reference voltage VGMA <8> outputted by the gamma voltage generating circuit, when the AMP finishes discharging the capacitor in the liquid crystal display, CH1 outputs the low reference voltage VGMA <8>, the magnitudes of CH1 and the low reference voltage VGMA <8> can be judged by a comparator Comp with offset voltage, and when the comparator output is low, AHDR becomes low (the moment when the AHDR signal becomes low can be understood as the moment T2), and the bias current stops increasing. The effective AHDR width is obtained by sampling by a controller (not shown in fig. 7), that is, the aforementioned quick charge duration. After the V-Blanking interval is finished, a large bias current interval with the same width as AHDR is given to AMP every time data refreshing (LD), so that the purpose of quick charging is achieved.

Fig. 8 is a timing chart of signals in the driving circuit shown in fig. 7. As can be seen from fig. 8, when the above scheme is performed in the V-Blanking interval, the DAC outputs an Hline pattern signal to AMP at the time when the LD is active, and the AHDR signal is set to high level; the output CH1 of AMP gradually decreases from VGMA <14> to VGMA <8>, when CH1 reaches VGMA <8>, comp's output goes from high to low, at which time the AHDR signal is set low; the duration of the high level of the AHDR signal is a fast charging duration, and the fast charging duration is taken as an acceleration duration for AMP during each data refresh when the picture is displayed later (i.e., active interval).

It should be noted that, in the embodiment of the present application, the current source circuit in the amplifier 402 may controllably provide the bias current to the amplifying circuit. When the bias current of the amplifying circuit is smaller, the charge and discharge rate of a capacitor in the liquid crystal display coupled with the amplifying circuit is slower; when the bias current of the amplifying circuit is larger, the charge and discharge rate of the capacitor in the liquid crystal display coupled with the amplifying circuit is faster. The comparison control circuit 403 compares the voltage value of the driving signal output from the amplifier 402 with a preset voltage value, and controls the current source circuit to output a bias current based on the comparison result. By this test mode, the comparison control circuit can control the bias current provided by the current source circuit based on the real comparison result of the voltage value of the driving signal and the preset voltage value, so as to improve the charge and discharge rate of the capacitor in the liquid crystal display coupled with the driving circuit 400. Compared with the mode of setting the DHDR duration to a larger fixed value in the prior art, the bias current provided by the current source circuit is controlled by the mode of testing by the driving circuit 400, so that the bias current output by the current source circuit can be more accurately adapted to the capacitance in the liquid crystal display, and the system power consumption is reduced.

Further, the current source circuit may be configured to supply a first bias current to the amplifying circuit before the first time, and to supply a second bias current to the amplifying circuit at the first time, the second bias current having a current value larger than that of the first bias current. The controller in the comparison control circuit 403 determines the difference between the second time and the first time at which the comparator in the comparison control circuit 403 toggles as the fast charge duration. Then, in the case that the amplifier 402 is supplied with the second bias current, the driving signal can follow the input analog signal from the maximum voltage value to the minimum voltage value or from the minimum voltage value to the maximum voltage value in the period from the first time to the second time, and then the fast charge duration determined by this scheme can satisfy the charge and discharge time required for all the capacitors coupled to the amplifier 402 in the liquid crystal display. In addition, the difference between the maximum voltage value and the minimum voltage value of the analog signal is equal to the maximum charging voltage value of the capacitor in the liquid crystal display, or the difference between the maximum voltage value and the minimum voltage value of the analog signal is slightly larger than the maximum charging voltage value of the capacitor in the liquid crystal display, so that the quick charging time determined by adopting the scheme can meet the charging and discharging requirements of all the capacitors in the liquid crystal display, and the quick charging time can be shortened as much as possible, thereby further reducing the system power consumption.

Based on the same inventive concept, the embodiment of the application also provides a display device. As shown in fig. 9, the display device 900 includes a liquid crystal display 901 and the driving circuit 400.

The driving circuit 400 is used for driving the liquid crystal display 901. The specific operation of the driving circuit 400 may be referred to in the foregoing description, and will not be described herein.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the scope of the embodiments of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims and the equivalents thereof, the present application is also intended to include such modifications and variations.

Claims

A driving circuit, characterized by comprising:

a digital-to-analog converter for outputting an analog signal;

an amplifier for generating a drive signal based on the analog signal, wherein the amplifier comprises an amplifying circuit for amplifying the analog signal and a current source circuit for controllably providing a bias current for the amplifying circuit;

and the comparison control circuit is used for comparing the voltage value of the driving signal with a preset voltage value and controlling the current source circuit to output bias current based on a comparison result.
The drive circuit of claim 1, wherein the comparison control circuit comprises:

the comparator is used for comparing the voltage value of the driving signal with a preset voltage value;

and a controller for controlling the current source circuit to output a bias current based on a comparison result of the comparator.
The drive circuit of claim 2, wherein the digital-to-analog converter is specifically configured to:

outputting the analog signal at a first time;

the current source circuit is specifically used for:

providing a first bias current for the amplifying circuit before the first moment, and providing a second bias current for the amplifying circuit at the first moment, wherein the current value of the second bias current is larger than that of the first bias current;

the controller is specifically used for: and determining the difference between the second moment when the driving signal turns and the first moment as a fast charge time length, and controlling the current source circuit to output bias current according to the fast charge time length.
The drive circuit of claim 3, wherein the controller is configured to, when controlling the current source circuit to output a bias current in accordance with the fast charge duration:

And controlling the duration of outputting the second bias current by the current source circuit to be the fast charge duration when the liquid crystal display coupled with the driving circuit performs data refreshing every time.
The drive circuit according to any one of claims 1 to 4, wherein a difference between a maximum voltage value and a minimum voltage value of the analog signal is greater than or equal to a maximum charge voltage value of a capacitor in a liquid crystal display coupled to the drive circuit; the preset voltage value is the maximum voltage value or the minimum voltage value of the analog signal.
A drive circuit according to any one of claims 3 to 5, wherein the analogue signal is a first step signal, the voltage value of the first step signal increasing from a first voltage value to a second voltage value at the first instant; the comparator is used for comparing the voltage value of the driving signal with the second voltage value, and the moment when the output signal of the comparator is turned from low level to high level is the second moment.
A driving circuit according to any one of claims 3 to 5, wherein the analogue signal is a second step signal whose voltage value decreases from a third voltage value to a fourth voltage value at the first moment; the comparator is used for comparing the voltage value of the driving signal with the fourth voltage value, and the moment when the output signal of the comparator is turned from high level to low level is the second moment.
The driving circuit according to any one of claims 3 to 7, wherein the first time and the second time are located in a blanking region between a first frame and a second frame displayed by a liquid crystal display coupled to the driving circuit, the display time of the first frame being earlier than the display time of the second frame.
The drive circuit of claim 8, wherein the digital-to-analog converter is further to:

performing digital-to-analog conversion on the digital control signal corresponding to the second frame of picture to obtain an analog control signal;

the amplifying circuit is further configured to:

amplifying the analog control signal;

the controller is further configured to: and at a third moment when the amplifying circuit receives the analog control signal, controlling the current source circuit to output the second bias current, and at a fourth moment, controlling the current source circuit to output the first bias current, wherein the time difference between the fourth moment and the third moment is the quick charge duration.
A driving circuit according to any one of claims 3 to 9, wherein the first time is a time at which the liquid crystal display performs data refresh.
A display device, comprising: a liquid crystal display device and a driving circuit according to any one of claims 1 to 10.