CN116685140A

CN116685140A - Manufacturing method of semiconductor device, semiconductor device and stacking device

Info

Publication number: CN116685140A
Application number: CN202210157645.0A
Authority: CN
Inventors: 邵光速
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-02-21
Filing date: 2022-02-21
Publication date: 2023-09-01
Also published as: WO2023155339A1

Abstract

The embodiment of the disclosure discloses a manufacturing method of a semiconductor device, the semiconductor device and a stacked device, wherein the manufacturing method comprises the following steps: forming a common bottom plate on a substrate; forming an isolation layer and a plurality of sacrificial layers which are defined by the isolation layer, extend along a first direction and are arranged along a second direction on the shared lower polar plate; forming a first conductive layer extending in a first direction on the sacrificial layer; forming a first insulating layer on the first conductive layer, the sacrificial layer and the isolation layer; etching the first insulating layer to form a first trench extending along the second direction and exposing the plurality of sacrificial layers; removing the sacrificial layer through the first groove to form a plurality of hole structures communicated with the first groove; forming a first dielectric layer and a second dielectric layer in the hole structure and the first groove respectively; etching the first insulating layer to form a second groove and a third groove on two sides of the second dielectric layer respectively; and forming a second conductive layer and a third conductive layer in the second groove and the third groove respectively.

Description

Manufacturing method of semiconductor device, semiconductor device and stacking device

Technical Field

The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor device, and a stacked device.

Background

Semiconductor devices, such as Dynamic Random Access Memory (DRAM), typically include a substrate, a transistor within the substrate, and a capacitor on the substrate for storing charge, the transistor and the capacitor constituting a memory cell.

However, in the related art, the capacitor generally extends in a fixed direction, and the surface area of the capacitor is small, resulting in a low charge storage amount of the capacitor; in addition, the capacitor tends to have a larger depth, and the capacitor can be accommodated in a unit volume is smaller, and the storage density of the semiconductor device is lower.

Disclosure of Invention

The embodiment of the disclosure provides a manufacturing method of a semiconductor device, comprising the following steps:

providing a substrate;

forming a common bottom plate on the substrate;

forming an isolation layer and a plurality of sacrificial layers which are defined by the isolation layer and extend along a first direction on the shared lower polar plate, wherein the sacrificial layers are distributed in a second direction;

forming a plurality of first conductive layers extending in the first direction on the plurality of sacrificial layers;

forming a first insulating layer on the first conductive layer, the sacrificial layer and the isolation layer;

etching the first insulating layer to form a first trench extending along the second direction, wherein the first trench exposes a plurality of the sacrificial layers;

Removing the sacrificial layers through the first grooves to form a plurality of hole structures communicated with the first grooves;

forming a first dielectric layer in the hole structures and forming a second dielectric layer in the first groove;

etching the first insulating layer to form a plurality of second grooves exposing the first dielectric layer and a plurality of third grooves exposing the common lower electrode plate, wherein the second grooves and the third grooves are arranged on two sides of the second dielectric layer;

and forming a second conductive layer and a third conductive layer in the second groove and the third groove respectively.

In some embodiments, removing the plurality of sacrificial layers through the first trench includes: introducing etching liquid into the first groove, wherein the etching liquid removes the plurality of sacrificial layers; wherein the etching rate of the sacrificial layer is greater than the etching rate of the isolation layer.

In some embodiments, after forming the first insulating layer, the method further comprises:

a plurality of channel layers extending in the first direction and a buried layer located between the plurality of channel layers are formed on the first insulating layer, the plurality of channel layers being arranged in the second direction.

In some embodiments, the channel layer and the buried layer are formed prior to forming the first trench, the second trench, and the third trench all extending through the channel layer; the method further comprises the steps of:

a first separation layer is formed within the channel layer and the buried layer extending in the second direction and cutting off the channel layer, the first separation layer and the first trench separating the channel layer into discrete active regions.

In some embodiments, the channel layer and the buried layer are formed after the second conductive layer and the third conductive layer are formed, the channel layer and the buried layer covering the first insulating layer, the second conductive layer, the third conductive layer, and the second dielectric layer, the channel layer being in contact with the second conductive layer and the third conductive layer; the method further comprises the steps of:

forming first and second separation layers within the channel layer and the buried layer, the first and second separation layers separating the channel layer into discrete active regions, the first and second separation layers extending in the second direction and cutting off the plurality of channel layers; wherein the second separation layer covers the second dielectric layer.

In some embodiments, the method further comprises:

forming a third dielectric layer on the channel layer and the buried layer, and forming a word line material layer on the third dielectric layer;

etching the word line material layer to form a word line layer extending along the second direction;

and forming a fourth dielectric layer on the substrate, wherein the fourth dielectric layer covers the third dielectric layer and the word line layer.

In some embodiments, the method further comprises:

forming a second insulating layer on the fourth dielectric layer;

etching the second insulating layer, the fourth dielectric layer and the third dielectric layer until the channel layer is exposed, so as to form a plurality of bit line contact holes which are distributed along the second direction;

forming a bit line contact plug in the bit line contact hole;

and forming a plurality of bit line layers extending along the first direction on the bit line contact plug and the second insulating layer, wherein the plurality of bit line layers are arranged along the second direction.

The embodiment of the disclosure also provides a semiconductor device, including:

a substrate and a common bottom plate on the substrate;

the isolation layers are positioned on the shared lower polar plate, the first dielectric layers are limited by the isolation layers and extend along a first direction, and the first dielectric layers are distributed in a second direction;

A plurality of first conductive layers respectively located on the plurality of first dielectric layers and extending along the first direction;

a first insulating layer covering the first conductive layer, the first dielectric layer, and the isolation layer; the first insulating layer is internally provided with a first groove extending along the second direction, a plurality of second grooves and a plurality of third grooves which are arranged on two sides of the first groove; wherein the second trench exposes the first dielectric layer, and the third trench exposes the common lower plate;

the second dielectric layer, the second conductive layer and the third conductive layer are respectively positioned in the first groove, the second groove and the third groove.

In some embodiments, in the first direction, both ends of the first conductive layer are recessed relative to both ends of the first dielectric layer; in the second direction, both ends of the first conductive layer protrude outward with respect to both ends of the first dielectric layer.

In some embodiments, the semiconductor device further comprises: a plurality of channel layers extending in the first direction on the first insulating layer, and a buried layer between the plurality of channel layers, the plurality of channel layers being arranged in the second direction.

In some embodiments, the first trench, the second trench, and the third trench all extend through the channel layer; the semiconductor device further includes: a first separation layer extending in the second direction, the first separation layer being located within the channel layer and the buried layer and cutting off a plurality of the channel layers, the first separation layer and the first trench separating the channel layers into discrete active regions.

In some embodiments, the channel layer is located above the second conductive layer, the third conductive layer, and the second dielectric layer, the channel layer being in contact with the second conductive layer and the third conductive layer; the semiconductor device further includes: a first separation layer and a second separation layer extending in the second direction, the first separation layer and the second separation layer being located in the channel layer and the buried layer and cutting off the plurality of channel layers, the first separation layer and the second separation layer separating the channel layer into a plurality of active regions; wherein the second separation layer covers the second dielectric layer.

In some embodiments, the semiconductor device further comprises: the third dielectric layer covers the channel layer and the buried layer; a word line layer extending along the second direction, the word line layer being located on the third dielectric layer; and the fourth dielectric layer covers the third dielectric layer and the word line layer.

In some embodiments, the semiconductor device further comprises: a second insulating layer covering the fourth dielectric layer; a plurality of bit line layers extending in the first direction, located on the second insulating layer and arranged in the second direction; and the bit line contact plug is connected with the bit line layer and the channel layer.

The disclosed embodiments also provide a stacked device, including:

a substrate and a plurality of memory structures stacked on the substrate;

the storage structure includes:

sharing a lower polar plate;

a first insulating layer covering the first conductive layer, the first dielectric layer, and the isolation layer; the first insulating layer is internally provided with a first groove extending along the second direction, a plurality of second grooves and a plurality of third grooves which are arranged on two sides of the first groove; wherein the second trench exposes the first conductive layer, and the third trench exposes the common lower plate;

The embodiment of the disclosure discloses a manufacturing method of a semiconductor device, the semiconductor device and a stacked device, wherein the manufacturing method comprises the following steps: providing a substrate; forming a common bottom plate on the substrate; forming an isolation layer and a plurality of sacrificial layers which are defined by the isolation layer and extend along a first direction on the shared lower polar plate, wherein the sacrificial layers are distributed in a second direction; forming a plurality of first conductive layers extending in the first direction on the plurality of sacrificial layers; forming a first insulating layer on the first conductive layer, the sacrificial layer and the isolation layer; etching the first insulating layer to form a first trench extending along the second direction, wherein the first trench exposes a plurality of the sacrificial layers; removing the sacrificial layers through the first grooves to form a plurality of hole structures communicated with the first grooves; forming a first dielectric layer in the hole structures and forming a second dielectric layer in the first groove; etching the first insulating layer to form a plurality of second grooves exposing the first dielectric layer and a plurality of third grooves exposing the common lower electrode plate, wherein the second grooves and the third grooves are arranged on two sides of the second dielectric layer; and forming a second conductive layer and a third conductive layer in the second groove and the third groove respectively. The common lower electrode plate, the first conductive layer, the second conductive layer, the third conductive layer, the first dielectric layer and the second dielectric layer form a capacitor for storing charges, wherein the extending directions of the first conductive layer and the second conductive layer are different, namely the capacitor in the embodiment of the disclosure extends along two different directions, and compared with the capacitor extending along only one direction in the related art, the capacitor provided by the embodiment of the disclosure has larger surface area and thus larger charge storage capacity; meanwhile, compared with the capacitor in the related art, the capacitor in the embodiment of the disclosure can have a smaller depth, so that the semiconductor device can accommodate more capacitors in a unit volume, and the storage density of the semiconductor device can be improved. In addition, a supporting structure for supporting the capacitor is not needed in the embodiment of the disclosure, so that the manufacturing process of the semiconductor device is simplified.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

Fig. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 2a to 18b are process flow diagrams of a semiconductor device provided in an embodiment of the present disclosure;

fig. 19a to 25b are process flow diagrams of a semiconductor device according to another embodiment of the present disclosure;

fig. 26 is a schematic diagram of a stacked device provided by an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Based on this, the following technical solutions of the embodiments of the present disclosure are provided:

the embodiment of the disclosure provides a method for manufacturing a semiconductor device, and particularly please refer to fig. 1. As shown, the method comprises the steps of:

step 101, providing a substrate;

102, forming a common lower polar plate on the substrate;

step 103, forming an isolation layer and a plurality of sacrificial layers defined by the isolation layer and extending along a first direction on the shared lower polar plate, wherein the sacrificial layers are distributed in a second direction;

104, forming a plurality of first conductive layers extending along the first direction on the plurality of sacrificial layers;

Step 105, forming a first insulating layer on the first conductive layer, the sacrificial layer and the isolation layer;

step 106, etching the first insulating layer to form a first groove extending along the second direction, wherein the first groove exposes a plurality of the sacrificial layers;

step 107, removing a plurality of the sacrificial layers through the first grooves to form a plurality of hole structures communicated with the first grooves;

step 108, forming a first dielectric layer in the hole structures and forming a second dielectric layer in the first groove;

step 109, etching the first insulating layer to form a plurality of second trenches exposing the first dielectric layer and a plurality of third trenches exposing the common bottom plate, where the second trenches and the third trenches are disposed on two sides of the second dielectric layer;

and 110, forming a second conductive layer and a third conductive layer in the second groove and the third groove respectively.

The common lower electrode plate, the first conductive layer, the second conductive layer, the third conductive layer, the first dielectric layer and the second dielectric layer form a capacitor for storing charges, and the extending directions of the first conductive layer and the second conductive layer are different, namely, the capacitor in the embodiment of the disclosure extends along two different directions, and compared with the capacitor extending along only one direction in the related art, the capacitor provided by the embodiment of the disclosure has larger surface area, so that the capacitor can have larger charge storage capacity; meanwhile, the capacitor in the embodiment of the disclosure can have a smaller depth, so that the semiconductor device can accommodate more capacitors in unit volume, and the storage density of the semiconductor device can be improved. In addition, a supporting structure for supporting the capacitor is not needed in the embodiment of the disclosure, so that the manufacturing process of the semiconductor device is simplified.

The manufacturing method provided by the embodiment of the disclosure can be used for manufacturing a Dynamic Random Access Memory (DRAM), but is not limited to the method, and any semiconductor device with a capacitor can be manufactured by adopting the method provided by the embodiment of the application.

The following detailed description of specific embodiments of the present disclosure refers to the accompanying drawings. In describing embodiments of the present disclosure in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the disclosure.

Fig. 2a to 18b are process flow diagrams of a semiconductor device according to an embodiment of the present disclosure, and fig. 19a to 25b are process flow diagrams of a semiconductor device according to another embodiment of the present disclosure; wherein fig. 2a, fig. 3a, fig. 4a, fig. 5a, fig. 6a, fig. 7a, fig. 8a, fig. 9a, fig. 10a, fig. 11a, fig. 12a, fig. 13a, fig. 14a, fig. 15a, fig. 16a, fig. 17a, fig. 18a are schematic top views of the semiconductor device manufacturing method provided in the embodiments of the present disclosure in different process steps, and fig. 2b, fig. 3b, fig. 4b, fig. 5b, fig. 6b, fig. 7b, fig. 8b, fig. 9b, fig. 10b, fig. 11b, fig. 12b, fig. 13b, fig. 14b, fig. 15b, fig. 16b, fig. 17b, fig. 18b are schematic cross-sectional views taken along lines AA' of fig. 2a, fig. 3a, fig. 4a, fig. 5a, fig. 6a, fig. 7a, fig. 8a, fig. 9a, fig. 10a, fig. 11a, fig. 12a, fig. 13a, fig. 14a, fig. 15a, fig. 16a, fig. 17a, fig. 18 a; fig. 19a, 20a, 21a, 22a, 23a, 24a, and 25a are schematic top views of a semiconductor device manufacturing method according to another embodiment of the present disclosure in different process steps, and fig. 19b, 20b, 21b, 22b, 23b, 24b, and 25b are schematic cross-sectional structure views taken along line AA' of fig. 19a, 20a, 21a, 22a, 23a, 24a, and 25a, respectively. The method of manufacturing the semiconductor device according to the embodiments of the present disclosure will be described in further detail below with reference to fig. 2a to 25 b.

First, step 101 is performed, as shown in fig. 2a to 2b, to provide a substrate 20.

The substrate may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a particular embodiment, the substrate is a silicon substrate, which may be doped or undoped.

Next, step 102 is performed, as shown in fig. 3a to 3b, to form a common bottom plate 32 on the substrate 20.

The material of the common bottom plate 32 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloys, for example, titanium nitride (TiN).

Referring again to fig. 3b, in one embodiment, prior to forming the common bottom plate 32 on the substrate 20, the method further comprises: an interlayer insulating layer 31 is formed on the substrate 20, the interlayer insulating layer 31 being located under the common lower plate 32 for electrically isolating the substrate 20 from the common lower plate 32. The interlayer insulating layer 31 may be formed using a Chemical Vapor Deposition (CVD), a Plasma Enhanced CVD (PECVD), a Physical Vapor Deposition (PVD), an Atomic Layer Deposition (ALD), or the like, and optionally, a planarization process, such as a Chemical Mechanical Polishing (CMP) and/or an etching process, may be further used to planarize the upper surface of the interlayer insulating layer 31 after forming the interlayer insulating layer 31. The material of the interlayer insulating layer 31 may be oxide, for example, silicon oxide.

Next, step 103 is performed, as shown in fig. 4a to 4b, to form an isolation layer 33 and a plurality of sacrificial layers 34 defined by the isolation layer 33 and extending along the first direction on the common bottom plate 32, wherein the plurality of sacrificial layers 34 are arranged and distributed along the second direction.

In an embodiment, the first direction and the second direction are parallel to the surface of the substrate 20. In some embodiments, the first direction is perpendicular to the second direction. However, the first direction may be inclined to the second direction.

It should be noted that, the number and arrangement of the plurality of sacrificial layers 34 are not limited to those shown in fig. 4a, the number of the sacrificial layers 34 may be further increased, and the plurality of sacrificial layers 34 may be arranged in an array. In one embodiment, the sacrificial layers 34 are arranged in an array along the first direction and the second direction, respectively.

As shown in fig. 4b, the lower surface of the sacrificial layer 34 is in contact with the common lower plate 32, and the upper surface of the sacrificial layer 34 is flush with the upper surface of the isolation layer 33. The forming method of the isolation layer 33 and the sacrificial layer 34 may be, for example: first, the separator 33 is formed on the common lower plate 32; then, a plurality of openings (not identified) exposing the common lower plate 32 and extending in the first direction are formed on the separator 33, the plurality of openings (not identified) being arranged in the second direction; finally, the sacrificial layer 34 is formed within the opening (not identified). The material of the isolation layer 33 is an insulating material. An etching process is then performed to remove the sacrificial layer 34 and to leave the isolation layer 33, so that under preset etching conditions, the etching rate of the sacrificial layer 34 should be much greater than the etching rate of the isolation layer 33, i.e. the sacrificial layer 34 and the isolation layer 33 have a large etching selectivity, so that only the sacrificial layer 34 can be removed and the isolation layer 33 can be left in the subsequent process. In one embodiment, the etching selectivity is greater than 10, for example, between 20 and 100, the material of the sacrificial layer 34 is, for example, polysilicon, and the material of the isolation layer 33 is, for example, silicon nitride.

Next, step 104 is performed, as shown in fig. 5a to 5b, to form a plurality of first conductive layers 35 extending along the first direction on the plurality of sacrificial layers 34.

In some embodiments, in the first direction, the two ends of the first conductive layer 35 are retracted inward with respect to the two ends of the sacrificial layer 34, so that the two ends of the first conductive layer 35 can be prevented from contacting other conductive layers; in the second direction, both ends of the first conductive layer 35 protrude outward with respect to both ends of the sacrificial layer 34, and thus, the first conductive layer 35 has a larger surface area, increasing the surface area of the capacitor C (see fig. 11a to 11 b) formed in the subsequent process, and thus, the charge storage amount of the capacitor C can be increased. The material of the first conductive layer 35 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, for example, titanium nitride (TiN). In one embodiment, the first conductive layer 35 is the same material as the common bottom plate 32.

Next, step 105 is performed, as shown in fig. 6a to 6b, to form a first insulating layer 36 on the first conductive layer 35, the sacrificial layer 34 and the isolation layer 33.

The material of the first insulating layer 36 may be an oxide, such as silicon oxide. In one embodiment, the material of the first insulating layer 36 is the same as the material of the interlayer insulating layer 31.

Next, step 106 is performed, as shown in fig. 7a to 7b, to etch the first insulating layer 36 to form a first trench T1 extending along the second direction, where the first trench T1 exposes a plurality of the sacrificial layers 34.

In one embodiment, the first insulating layer 36 is etched from top to bottom in a direction perpendicular to the surface of the substrate 20 to form the first trench T1, the first trench T1 extending downward in a direction perpendicular to the surface of the substrate 20.

In an embodiment, after etching the first insulating layer 36 in the process of forming the first trench T1, etching a portion of the sacrificial layer 34 and/or a portion of the isolation layer 33 until the common bottom plate 32 is exposed, the sidewalls of the first trench T1 expose the plurality of sacrificial layers 34, and simultaneously expose the isolation layer 33 between the plurality of sacrificial layers 34. In some embodiments, the sidewalls of the first trench T1 expose one of the two ends of the sacrificial layer 34 in the first direction.

Next, step 107 is performed, as shown in fig. 8a to 8b, to remove the sacrificial layers 34 through the first trench T1, so as to form a plurality of hole structures S1 communicating with the first trench T1.

In one embodiment, removing the plurality of sacrificial layers 34 through the first trench T1 includes: introducing an etching solution into the first trench T1, wherein the etching solution removes the plurality of sacrificial layers 34; wherein the etching rate of the sacrificial layer 34 is greater than the etching rate of the isolation layer 33, so that the isolation layer 33 is maintained while removing the sacrificial layer 34 to form a plurality of hole structures S1, the plurality of hole structures S1 extend in the first direction and are arranged in the second direction, and the plurality of hole structures S1 are separated by the isolation layer 33.

Next, step 108 is performed, as shown in fig. 9a to 9b, forming a first dielectric layer 41 in the hole structures S1, and forming a second dielectric layer 42 in the first trench T1.

Here, the number of the first dielectric layers 41 is plural, and the plural first dielectric layers 41 extend in the first direction and are arranged in the second direction; the second dielectric layer 42 extends in the second direction and is connected to the plurality of first dielectric layers 41. The material of the first dielectric layer 41 and the material of the second dielectric layer 42 may be a high dielectric constant material, for example, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, barium strontium titanate, or the like. In a more specific embodiment, the material of the first dielectric layer 41 and the material of the second dielectric layer 42 are the same.

Next, step 109 is performed, as shown in fig. 10a to 10b, to etch the first insulating layer 36 to form a plurality of second trenches T2 exposing the first dielectric layer 41 and a plurality of third trenches T3 exposing the common bottom plate 32, where the second trenches T2 and the third trenches T3 are disposed on two sides of the second dielectric layer 42.

As shown in fig. 10b, the bottom of the second trench T2 exposes the first dielectric layer 41, and the sidewall of the second trench T2 exposes the first conductive layer 35; in the process of forming the third trench T3, after etching the first insulating layer 36, etching the isolation layer 33 is further included to expose the common lower plate 32.

In an embodiment, the second trenches T2 and the third trenches T3 are perpendicular to the surface of the substrate 20, and are arranged along the second direction. In some embodiments, the second trench T2 and the third trench T3 are symmetrically disposed on both sides of the second dielectric layer 42.

Next, step 110 is performed, as shown in fig. 11a to 11b, the second conductive layer 43 and the third conductive layer 44 are formed in the second trench T2 and the third trench T3, respectively.

The number of the second conductive layers 43 and the number of the third conductive layers 44 are all plural, the plural second conductive layers 43 and the plural third conductive layers 44 are respectively arranged along the second direction on both sides of the second dielectric layer 42, the plural second conductive layers 43 are connected with the plural first conductive layers 35 in one-to-one correspondence, and the plural third conductive layers 44 are connected with the common lower electrode plate 32.

In the embodiment of the disclosure, the first dielectric layer 41 is formed first, the second dielectric layer 42 is formed in the first trench T1, then the second conductive layer 43 connected to the first conductive layer 35 and the third conductive layer 44 connected to the common lower plate 32 are formed on both sides of the second dielectric layer 42, instead of forming the second conductive layer 43 in the first trench T1 first, so that the second conductive layer 43 is prevented from being connected to the first conductive layer 35 and the common lower plate 32 at the same time under the condition that the bottom of the first trench T1 exposes the common lower plate 32, and a short circuit phenomenon is avoided. The common bottom plate 32, the first conductive layers 35, the second conductive layers 43, the third conductive layers 44, the first dielectric layers 41 and the second dielectric layers 42 form a plurality of capacitors C for storing charges, and the capacitors C are arranged along the second direction. The extending directions of the first conductive layer 35 and the second conductive layer 43 and the third conductive layer 44 are different, that is, the capacitor C in the embodiment of the disclosure extends along two different directions, and compared with the capacitor extending along only one direction in the related art, the capacitor C provided in the embodiment of the disclosure has a larger surface area, so that a larger charge storage amount can be provided; meanwhile, the capacitor C in the embodiments of the present disclosure may have a smaller depth than the capacitor in the related art, so that the semiconductor device can accommodate more capacitors C per unit volume, and the storage density of the semiconductor device may be improved. In addition, the capacitor C provided in the embodiment of the present disclosure is buried by the first insulating layer 36, so that the structure of the capacitor C is more stable, no additional support structure for supporting the capacitor C is required, and a plurality of capacitors C have the same common bottom plate 32, which simplifies the manufacturing process of the semiconductor device.

It should be noted that, the number and arrangement manner of the capacitors C are not limited to those shown in fig. 11a, the number of the capacitors C may be more, and a plurality of the capacitors C may be arranged in an array. In an embodiment, the plurality of capacitors C are arranged in an array along the first direction and the second direction, respectively. In some embodiments, the two ends of the first conductive layer 35 are inwardly retracted with respect to the two ends of the first dielectric layer 41 in the first direction, so that the first conductive layer 35 of one of the two capacitors C adjacent in the first direction and the third conductive layer 44 of the other are prevented from being connected to each other, thereby enabling reduction of leakage.

The materials of the second conductive layer 43 and the third conductive layer 44 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy. In an embodiment, the second conductive layer 43 and the third conductive layer 44 are made of the same material as the common bottom plate 32, such as titanium nitride (TiN).

In an embodiment, after forming the first insulating layer 36, the method further comprises: a plurality of channel layers 37 extending in the first direction and buried layers 38 between the plurality of channel layers 37 are formed on the first insulating layer 36, and the plurality of channel layers 37 are arranged in the second direction as shown in fig. 12a to 12 b.

In one embodiment, the material of the channel layer 37 includes one or more of silicon, germanium, silicon germanium, indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide. The channel layer 37 may be doped or undoped. When an Indium Gallium Zinc Oxide (IGZO) material is used as the channel layer 37, electron mobility can be improved, thereby improving writing speed.

Referring again to fig. 12 a-12 b, in one embodiment, the channel layer 37 and the buried layer 38 are formed after the second conductive layer 43 and the third conductive layer 44 are formed, the channel layer 37 and the buried layer 38 cover the first insulating layer 36, the second conductive layer 43, the third conductive layer 44, and the second dielectric layer 42, the channel layer 37 being in contact with the second conductive layer 43 and the third conductive layer 44; the method further comprises the steps of: forming first and second separation layers 39, 53 extending in the second direction and cutting off a plurality of the channel layers 37 within the channel layers 37 and the buried layers 38, the first and second separation layers 39, 53 separating the channel layers 37 into discrete active regions AA; wherein the second separation layer 53 covers the second dielectric layer 42 and is in contact with the second dielectric layer 42. The number of the active areas AA is plural, and the plural active areas AA are arranged along the second direction. In a more specific embodiment, the projections of the second separation layer 53 and the second dielectric layer 42 in a direction perpendicular to the substrate 20 overlap.

In one embodiment, the active area AA includes a first source/drain doped region (not identified) located at one end of the active area AA and adjacent to the first separation layer 39, and a second source/drain doped region (not identified) located at the other end of the active area AA and in contact with the second conductive layer 43, wherein the first source/drain doped region (not identified) and the second source/drain doped region (not identified) may be formed in the active area AA by ion implantation. In a specific embodiment, the first source/drain doped region (not identified) and the second source/drain doped region (not identified) are of the same conductivity type, such as n-type. In a more specific embodiment, the middle region of the active area AA has p-type doping.

In an embodiment, the method further comprises:

forming a third dielectric layer 45 on the channel layer 37 and the buried layer 38, and forming a word line material layer 46 on the third dielectric layer 45, as shown in fig. 13a to 13 b;

etching the word line material layer 46 to form a word line layer 47 extending in the second direction, as shown in fig. 14a to 14 b;

a fourth dielectric layer 48 is formed on the substrate 20, and the fourth dielectric layer 48 covers the third dielectric layer 45 and the word line layer 47, as shown in fig. 15a to 15 b.

The word line material layer 46 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloys. Referring again to fig. 13 a-13 b, in one embodiment, the word line material layer 46 includes a first sub-layer 461 and a second sub-layer 462 located on the first sub-layer 461, the first sub-layer 461 and the second sub-layer 462 being of different materials; etching the word line material layer 46 to form the word line layer 47 includes: etching the second sub-layer 462 to form a second word line sub-layer 472; the first sub-layer 461 is etched to form a first word line sub-layer 471, as shown in fig. 14 a-14 b. In some embodiments, using a metal material as the word line layer 47, resistance can be reduced.

In one embodiment, the word line layer 47 is formed between the first separation layer 39 and the second conductive layer 43, and the first conductive layer 35 and the first dielectric layer 41 are located under the word line layer 47, so that a space under the word line layer 47 is utilized, thereby improving a space utilization rate of the semiconductor device and further improving a storage density of the semiconductor device. In some embodiments, the wordline layer 47 is disposed over a middle region of the active area AA, separating the first source/drain doped region (not identified) and the second source/drain doped region (not identified).

In one embodiment, the third dielectric layer 45 covers both the first separation layer 39 and the second separation layer 53. The material of the third dielectric layer 45 may include an oxide, such as silicon oxide. The material of the fourth dielectric layer 48 includes, but is not limited to, nitride, such as silicon nitride, for protecting the third dielectric layer 45 and the word line layer 47.

In an embodiment, the method further comprises:

forming a second insulating layer 49 on the fourth dielectric layer 48; etching the second insulating layer 49, the fourth dielectric layer 48, and the third dielectric layer 45 until the channel layer 37 is exposed, and forming a plurality of bit line contact holes S2 arranged along the second direction, as shown in fig. 16a to 16 b;

forming a bit line contact plug 51 in the bit line contact hole S2 as shown in fig. 17a to 17 b;

a plurality of bit line layers 52 extending in the first direction are formed on the bit line contact plugs 51 and the second insulating layer 49, and the plurality of bit line layers 52 are arranged in the second direction, as shown in fig. 18a to 18 b.

Here, the bit line contact hole S2 is located between the first separation layer 39 and the word line layer 47, exposing the active area AA, and the bit line layer 52 contacts the active area AA through the bit line contact plug 51. In one embodiment, in the first direction, the number of the active areas AA is plural, and each of the bit line layers 52 is connected to a plurality of the active areas AA. In one embodiment, the bit line layer 52 is connected to the first source/drain doped region (not identified). The material of the bit line layer 52 and the bit line contact plug 51 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy.

The channel layer 37 and the buried layer 38 shown in fig. 12a to 18b are formed after the second conductive layer 43 and the third conductive layer 44 are formed. In another embodiment of the present disclosure, the channel layer 37 and the buried layer 38 are formed before the first trench T1 is formed, and the first trench T1, the second trench T2, and the third trench T3 each penetrate through the channel layer 37, as shown in fig. 19a to 25 b.

Specifically, as shown in fig. 19a to 19b, a plurality of channel layers 37 extending in the first direction and arranged in the second direction and a buried layer 38 located between the plurality of channel layers 37 are formed on the first insulating layer 36 before the first trench T1 is formed.

Next, as shown in fig. 20a to 20b, the channel layer 37, the buried layer 38 and the first insulating layer 36 are etched to form a first trench T1 extending in the second direction, the first trench T1 exposing the plurality of sacrificial layers 34.

Referring again to fig. 19 a-20 b, in one embodiment, the method further comprises: a first separation layer 39 extending in the second direction and cutting off the channel layer 37 is formed within the channel layer 37 and the buried layer 38, the first separation layer 39 and the first trench T1 separating the channel layer 37 into discrete active regions AA.

Next, as shown in fig. 21a to 21b, a plurality of the sacrificial layers 34 are removed through the first trenches T1, and a plurality of hole structures S1 communicating with the first trenches T1 are formed.

Next, as shown in fig. 22a to 22b, a first dielectric layer 41 is formed in the plurality of hole structures S1, and a second dielectric layer 42 is formed in the first trench T1.

Next, as shown in fig. 23a to 23b, the channel layer 37 and the first insulating layer 36 are etched to form a plurality of second trenches T2 exposing the first dielectric layer 41 and a plurality of third trenches T3 exposing the common bottom plate 32, wherein the second trenches T2 and the third trenches T3 are disposed at both sides of the second dielectric layer 42.

Next, as shown in fig. 24a to 24b, a second conductive layer 43 and a third conductive layer 44 are formed in the second trench T2 and the third trench T3, respectively.

Finally, as shown in fig. 25a to 25b, the third dielectric layer 45, the word line layer 47, the fourth dielectric layer 48, the second insulating layer 49, the bit line contact hole S2, the bit line contact plug 51, and the bit line layer 52 are formed in the same manner as in the previous embodiment, and the third dielectric layer 45 covers the channel layer 37, the buried layer 38, the first separation layer 39, the second conductive layer 43, the third conductive layer 44, and the second dielectric layer 42. The above layers are described in the foregoing embodiments, and are not repeated here.

It should be noted that one skilled in the art could change the order of the steps described above without departing from the scope of the present disclosure.

The embodiment of the present disclosure further provides a semiconductor device, as shown in fig. 18a to 18b, including: a substrate 20 and a common bottom plate 32 on said substrate 20; the isolation layer 33 is positioned on the shared lower polar plate 32, a plurality of first dielectric layers 41 which are limited by the isolation layer 33 and extend along a first direction, and the plurality of first dielectric layers 41 are distributed along a second direction; a plurality of first conductive layers 35 respectively located on the plurality of first dielectric layers 41 and extending along the first direction; a first insulating layer 36 covering the first conductive layer 35, the first dielectric layer 41, and the isolation layer 33; the first insulating layer 36 has therein a first trench T1 extending in the second direction, and a plurality of second trenches T2 and a plurality of third trenches T3 disposed on both sides of the first trench T1; wherein the second trench T2 exposes the first dielectric layer 41, and the third trench T3 exposes the common bottom plate 32; the second dielectric layer 42, the second conductive layer 43 and the third conductive layer 44 are respectively located in the first trench T1, the second trench T2 and the third trench T3.

As shown in fig. 18b, the lower surface of the first dielectric layer 41 is in contact with the common lower plate 32, and the upper surface of the first dielectric layer 41 is flush with the upper surface of the isolation layer 33. The material of the isolation layer 33 is an insulating material, for example, silicon oxide.

In an embodiment, the bottom of the first trench T1 exposes the common bottom plate 32, the sidewalls of the first trench T1 expose the plurality of first dielectric layers 41, and the second dielectric layer 42 located in the first trench T1 extends along the second direction and is connected to the plurality of first dielectric layers 41. In a specific embodiment, the sidewall of the first trench T1 exposes one of two ends of the first dielectric layer 41 in the first direction. The material of the first dielectric layer 41 and the material of the second dielectric layer 42 may be a high dielectric constant material, for example, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, barium strontium titanate, or the like. In an embodiment, the material of the first dielectric layer 41 and the material of the second dielectric layer 42 are the same.

In an embodiment, the first trench T1, the second trenches T2, and the third trenches T3 are perpendicular to the surface of the substrate 20, and the second dielectric layer 42, the second conductive layer 43, and the third conductive layer 44 are also perpendicular to the surface of the substrate 20.

The second trenches T2 and the third trenches T3 are respectively arranged along the second direction at two sides of the first trench T1; the number of the second conductive layers 43 and the number of the third conductive layers 44 are all plural, the plural second conductive layers 43 and the plural third conductive layers 44 are respectively arranged along the second direction on both sides of the second dielectric layer 42, the plural second conductive layers 43 are connected with the plural first conductive layers 35 in one-to-one correspondence, and the plural third conductive layers 44 are connected with the common lower electrode plate 32. In an embodiment, the second trench T2 and the third trench T3 are symmetrically disposed at two sides of the first trench T1, and the second conductive layer 43 and the third conductive layer 44 are symmetrically disposed at two sides of the second dielectric layer 42. The materials of the common bottom plate 32, the first conductive layer 35, the second conductive layer 43, and the third conductive layer 44 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy. In an embodiment, the materials of the first conductive layer 35, the second conductive layer 43, and the third conductive layer 44 are the same as the material of the common bottom plate 32, for example, titanium nitride (TiN).

The common bottom plate 32, the first conductive layers 35, the second conductive layers 43, the third conductive layers 44, the first dielectric layers 41 and the second dielectric layers 42 form a plurality of capacitors C for storing charges, and the capacitors C are arranged along the second direction. The extending directions of the first conductive layer 35 and the second conductive layer 43 and the third conductive layer 44 are different, that is, the capacitor C in the embodiment of the disclosure extends along two different directions, and compared with the capacitor extending along only one direction in the related art, the capacitor C provided in the embodiment of the disclosure has a larger surface area, so that a larger charge storage amount can be provided; meanwhile, the capacitor C in the embodiments of the present disclosure may have a smaller depth than the capacitor in the related art, so that the semiconductor device can accommodate more capacitors C per unit volume, and the storage density of the semiconductor device may be improved. In addition, in the embodiment of the disclosure, a supporting structure for supporting the capacitor C is not required, and a plurality of capacitors C have the same common bottom plate 32, so that the manufacturing process of the semiconductor device is simplified.

The capacitors C can also be arranged in an array. In an embodiment, the plurality of capacitors C are arranged in an array along the first direction and the second direction, respectively. In some embodiments, in the first direction, both ends of the first conductive layer 35 are inwardly retracted with respect to both ends of the first dielectric layer 41, so that the first conductive layer 35 of one of the two capacitors C adjacent in the first direction and the third conductive layer 44 of the other are prevented from being connected to each other; in the second direction, both ends of the first conductive layer 35 protrude outward with respect to both ends of the first dielectric layer 41, so that the first conductive layer 35 has a larger surface area, increasing the charge storage amount of the capacitor C.

In an embodiment, the semiconductor device further comprises an interlayer insulating layer 31, and the interlayer insulating layer 31 is located below the common bottom plate 32 and is used for electrically isolating the substrate 20 and the common bottom plate 32. The material of the interlayer insulating layer 31 may be oxide, for example, silicon oxide.

In an embodiment, the semiconductor device further includes: a plurality of channel layers 37 extending in the first direction on the first insulating layer 36, and a buried layer 38 between the plurality of channel layers 37, the plurality of channel layers 37 being arranged in the second direction.

As shown, in a specific embodiment, the channel layer 37 is located above the second conductive layer 43, the third conductive layer 44, and the second dielectric layer 42, and the channel layer 37 is in contact with the second conductive layer 43 and the third conductive layer 44; the semiconductor device further includes: a first separation layer 39 and a second separation layer 53 extending in the second direction, the first separation layer 39 and the second separation layer 53 being located within the channel layer 37 and the buried layer 38 and cutting off the plurality of channel layers 37, the first separation layer 39 and the second separation layer 53 separating the channel layer 37 into a plurality of active regions AA; wherein the second separation layer 53 covers the second dielectric layer 42. The number of the active areas AA is plural, and the plural active areas AA are arranged along the second direction. In a more specific embodiment, the projections of the second separation layer 53 and the second dielectric layer 42 in a direction perpendicular to the substrate 20 overlap.

In an embodiment, the semiconductor device further includes: a third dielectric layer 45, the third dielectric layer 45 covering the channel layer 37 and the buried layer 38; a word line layer 47 extending along the second direction, the word line layer 47 being located on the third dielectric layer 45; and a fourth dielectric layer 48, wherein the fourth dielectric layer 48 covers the third dielectric layer 45 and the word line layer 47.

In one embodiment, the third dielectric layer 45 covers both the first separation layer 39 and the second separation layer 53. The material of the third dielectric layer 45 may include an oxide, such as silicon oxide.

In one embodiment, the word line layer 47 is located between the first separation layer 39 and the second conductive layer 43, and the first conductive layer 35 and the first dielectric layer 41 are located under the word line layer 47, so that the space under the word line layer 47 is utilized, thereby improving the space utilization of the semiconductor device and further improving the storage density of the semiconductor device. In one embodiment, the word line layer 47 is disposed over a middle region of the active area AA, separating the first source/drain doped region (not identified) and the second source/drain doped region (not identified). The material of the word line layer 47 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy. In one embodiment, the wordline layer 47 includes a first wordline sublayer 471 and a second wordline sublayer 472 on the first wordline sublayer 471, the first wordline sublayer 471 and the second wordline sublayer 472 being of different materials. The material of the fourth dielectric layer 48 includes, but is not limited to, nitride, such as silicon nitride, for protecting the third dielectric layer 45 and the word line layer 47.

In an embodiment, the semiconductor device further includes: a second insulating layer 49, wherein the second insulating layer 49 covers the fourth dielectric layer 48; a plurality of bit line layers 52 extending in the first direction, disposed on the second insulating layer 49 and arranged in the second direction; and a bit line contact plug 51, wherein the bit line contact plug 51 is connected to the bit line layer 52 and the channel layer 37.

Here, the bit line contact plug 51 is located between the first separation layer 39 and the word line layer 47, and the bit line layer 52 is in contact with the active area AA through the bit line contact plug 51. In one embodiment, in the first direction, the number of the active areas AA is plural, and each of the bit line layers 52 is connected to a plurality of the active areas AA. In one embodiment, the bit line layer 52 is connected to the first source/drain doped region (not identified). The material of the bit line layer 52 and the bit line contact plug 51 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy.

The channel layer 37 and the buried layer 38 shown in fig. 18a to 18b are formed after the second conductive layer 43 and the third conductive layer 44 are formed. In another embodiment of the present disclosure, the channel layer 37 and the buried layer 38 may also be formed before the first trench T1 is formed, as shown in fig. 25a to 25 b. In this embodiment, before forming the first trench T1, the channel layer 37 and the buried layer 38 are formed on the first insulating layer 36, and then the first trench T1, the first dielectric layer 41, the second dielectric layer 42, the second trench T2, the third trench T3, the second conductive layer 43 and the third conductive layer 44 are formed, wherein the first trench T1, the second trench T2 and the third trench T3 penetrate through the channel layer 37; the semiconductor device further includes: a first separation layer 39 extending in the second direction, the first separation layer 39 being located within the channel layer 37 and the buried layer 38 and cutting off a plurality of the channel layers 37, the first separation layer 39 and the first trench T1 separating the channel layers 37 into discrete active regions AA; finally, the third dielectric layer 45, the word line layer 47, the fourth dielectric layer 48, the second insulating layer 49, the bit line contact plug 51, and the bit line layer 52 are formed in the same manner as in the previous embodiment, and the third dielectric layer 45 covers the channel layer 37, the buried layer 38, the first separation layer 39, the second conductive layer 43, the third conductive layer 44, and the second dielectric layer 42. The above layers are described in the foregoing embodiments, and are not repeated here.

The embodiment of the present disclosure further provides a stacked device, as shown in fig. 26, including: a substrate 20 and a plurality of memory structures 30 stacked on the substrate 20; the storage structure 30 includes: a common lower plate 32; the isolation layer 33 is positioned on the shared lower polar plate 32, a plurality of first dielectric layers 41 which are limited by the isolation layer 33 and extend along a first direction, and the plurality of first dielectric layers 41 are distributed along a second direction; a plurality of first conductive layers 35 respectively located on the plurality of first dielectric layers 41 and extending along the first direction; a first insulating layer 36 covering the first conductive layer 35, the first dielectric layer 41, and the isolation layer 33; the first insulating layer 36 has therein a first trench T1 extending in the second direction, and a plurality of second trenches T2 and a plurality of third trenches T3 disposed on both sides of the first trench T1; wherein the second trench T2 exposes the first dielectric layer 41, and the third trench T3 exposes the common bottom plate 32; the second dielectric layer 42, the second conductive layer 43 and the third conductive layer 44 are respectively located in the first trench T1, the second trench T2 and the third trench T3. The embodiment of the present disclosure improves the integration and storage density of the memory device by stacking a plurality of memory structures 30 on a substrate 20, the plurality of memory structures 30 being separated by an interlayer insulating layer 31 (e.g., a silicon oxide layer), the stacked memory structures 30 being disposed.

It should be noted that the foregoing description is only an alternative embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure, and any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a common bottom plate on the substrate;

2. The method of manufacturing of claim 1, wherein removing the plurality of sacrificial layers through the first trench comprises: introducing etching liquid into the first groove, wherein the etching liquid removes the plurality of sacrificial layers; wherein the etching rate of the sacrificial layer is greater than the etching rate of the isolation layer.

3. The manufacturing method according to claim 1, wherein after forming the first insulating layer, the method further comprises:

4. The method of manufacturing according to claim 3, wherein the channel layer and the buried layer are formed before the first trench is formed, and the first trench, the second trench, and the third trench each penetrate through the channel layer; the method further comprises the steps of:

5. The manufacturing method according to claim 3, wherein the channel layer and the buried layer are formed after the second conductive layer and the third conductive layer are formed, the channel layer and the buried layer cover the first insulating layer, the second conductive layer, the third conductive layer, and the second dielectric layer, and the channel layer is in contact with the second conductive layer and the third conductive layer; the method further comprises the steps of:

6. A method of manufacturing according to claim 3, wherein the method further comprises:

7. The method of manufacturing according to claim 6, further comprising:

forming a second insulating layer on the fourth dielectric layer;

forming a bit line contact plug in the bit line contact hole;

8. A semiconductor device, the semiconductor device comprising:

a substrate and a common bottom plate on the substrate;

9. The semiconductor device according to claim 8, wherein both ends of the first conductive layer are recessed with respect to both ends of the first dielectric layer in the first direction; in the second direction, both ends of the first conductive layer protrude outward with respect to both ends of the first dielectric layer.

10. The semiconductor device according to claim 8, wherein the semiconductor device further comprises: a plurality of channel layers extending in the first direction on the first insulating layer, and a buried layer between the plurality of channel layers, the plurality of channel layers being arranged in the second direction.

11. The semiconductor device of claim 10, wherein the first trench, the second trench, and the third trench each extend through the channel layer; the semiconductor device further includes: a first separation layer extending in the second direction, the first separation layer being located within the channel layer and the buried layer and cutting off a plurality of the channel layers, the first separation layer and the first trench separating the channel layers into discrete active regions.

12. The semiconductor device according to claim 10, wherein the channel layer is over the second conductive layer, the third conductive layer, and the second dielectric layer, the channel layer being in contact with the second conductive layer and the third conductive layer; the semiconductor device further includes: a first separation layer and a second separation layer extending in the second direction, the first separation layer and the second separation layer being located in the channel layer and the buried layer and cutting off the plurality of channel layers, the first separation layer and the second separation layer separating the channel layer into a plurality of active regions; wherein the second separation layer covers the second dielectric layer.

13. The semiconductor device according to claim 10, wherein the semiconductor device further comprises: the third dielectric layer covers the channel layer and the buried layer; a word line layer extending along the second direction, the word line layer being located on the third dielectric layer; and the fourth dielectric layer covers the third dielectric layer and the word line layer.

14. The semiconductor device according to claim 13, wherein the semiconductor device further comprises: a second insulating layer covering the fourth dielectric layer; a plurality of bit line layers extending in the first direction, located on the second insulating layer and arranged in the second direction; and the bit line contact plug is connected with the bit line layer and the channel layer.

15. A stacked device, the stacked device comprising:

a substrate and a plurality of memory structures stacked on the substrate;

the storage structure includes:

sharing a lower polar plate;