CN116684659A

CN116684659A - Video output control module, method, equipment and server of BMC chip

Info

Publication number: CN116684659A
Application number: CN202310963494.2A
Authority: CN
Inventors: 张贞雷; 李拓; 邹晓峰; 满宏涛; 刘同强; 周玉龙; 王贤坤
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-08-02
Filing date: 2023-08-02
Publication date: 2023-09-01
Anticipated expiration: 2043-08-02
Also published as: CN116684659B

Abstract

The invention relates to the technical field of servers and discloses a video output control module, a method, equipment and a server of a BMC chip, wherein the video output control module comprises a data receiving buffer, a frame state buffer, a frame information buffer, a buffer control sub-module, a buffer read-write control module and a write time sequence control module; the buffer control submodule is in communication connection with the data receiving buffer and is used for controlling writing and reading of data in the data receiving buffer, detecting the full state of the data receiving buffer and repairing incomplete frames caused by the full state in the data receiving buffer; the buffer read-write control module is respectively in communication connection with the buffer control sub-module, the frame state buffer and the frame information buffer. The invention solves the problem of frame loss caused by the link of transmitting video data to DDR.

Description

Video output control module, method, equipment and server of BMC chip

Technical Field

The invention relates to the technical field of servers, in particular to a video output control module, method, equipment and a server of a BMC chip.

Background

BMC (baseboard management controller) is a controller for providing intelligent management to a motherboard based on IPMI technical design specifications, and is widely applied to servers. The BMC is divided into two parts, namely hardware and BMC software, wherein the BMC hardware is a system on chip, comprises a BMC chip serving as a processor, and also comprises matched devices such as DDR (double data rate) and the like, and the running of the BMC is independent of the running of an operating system of a server, so that the BMC can run independently only by powering on the server. BMC is a small operating system independent of a server system and is used for monitoring health states such as temperatures, voltages and the like of various components (CPU, memory, hard disk, fans, machine frames and the like) of the server.

In order to facilitate monitoring and operation of the server, the BMC chip has two video functions, so that an operation interface of the server is displayed, one is locally displayed, and the other is transmitted to a remote terminal for display through a network after video data are compressed, wherein the original video data are derived from an operation system operated by a server host. In general, the complete flow of video data transmission is: video data of the server host is transmitted to a VGA module of the BMC chip through a PCIe bus, original video data is converted into data in an RGB format through VGA processing, the RGB data is converted into a YUV format through processing of a color space conversion module, the data in the YUV format is then transmitted to a video compression module at a later stage for compression, and finally the data in the YUV format or the compressed data are output to the DDR through a video output control module.

In the video output control module, a first-in first-out data receiving buffer, namely, a data receiving buffer, is generally used for receiving video data sent by a server host, when one frame of video data is not received completely, the capacity of the data receiving buffer, namely, the data receiving buffer, is full, and the part of the current frame which is not received is discarded, so that the frame loss problem is caused. Therefore, a scheme is needed to solve the problem of frame loss caused by the link from video transmission to DDR in the BMC video transmission function.

Disclosure of Invention

In view of the above, the present invention provides a video output control module, method, device and server of a BMC chip, so as to solve the problem of frame loss caused by the link of transmitting video data to DDR.

In a first aspect, the present invention provides a video output control module of a BMC chip, including: the system comprises a data receiving buffer, a frame state buffer, a frame information buffer, a buffer control sub-module, a buffer read-write control module and a write time sequence control module; the data receiving buffer is used for receiving compressed video data or YUV format video data; the buffer control submodule is in communication connection with the data receiving buffer and is used for controlling writing and reading of data in the data receiving buffer, detecting the full state of the data receiving buffer and repairing incomplete frames caused by the full state in the data receiving buffer; the buffer read-write control module is respectively in communication connection with the buffer control submodule, the frame state buffer and the frame information buffer, and is used for reading the frame state and the frame information of each frame identified by the buffer control submodule and storing the corresponding frame state and the frame information into the frame state buffer and the frame information buffer respectively; the write time sequence control module is in communication connection with the buffer control submodule and is used for reading the video data processed by the buffer control submodule and uploading the processed video data to the DDR.

In an alternative implementation mode, the buffer control submodule comprises a comprehensive control module and a frame loss correction module; the comprehensive control module is respectively in communication connection with the data receiving buffer, the buffer read-write control module, the write time sequence control module and the frame loss correction module, and is used for controlling the writing and reading of data in the data receiving buffer, detecting the full state of the data receiving buffer, sending the frame state and the frame information of each frame to the buffer read-write control module, enabling the write time sequence control module to read the processed video data and calling the frame loss correction module when the full signal of the data receiving buffer is detected; the frame loss correction module is used for calculating the written data quantity of the current frame in the data receiving buffer, judging whether the written data quantity reaches a preset data quantity threshold, and filling the tail of the current frame by utilizing the tail backup information of the previous frame on the reading side of the data receiving buffer when the written data quantity reaches the preset data quantity threshold to obtain the complete current frame.

In an optional implementation manner, when the current frame is YUV format video data, the integrated control module obtains resolution information of the current frame when a frame header of the current frame enters the data receiving buffer, and the frame loss correction module includes: a pixel calculation unit for determining all pixel points of the current frame through resolution information; the written pixel counting unit is used for counting the number of written pixel points of the current frame as the written data quantity; a writing proportion calculating unit for calculating the ratio of the number of written pixels to the number of all pixels; the patching condition judging unit is used for judging whether the pixel point number ratio is larger than or equal to a preset ratio threshold value, wherein the preset ratio threshold value is a preset data volume threshold value; and the patching unit is used for filling the tail part of the current frame by utilizing the tail backup information of the previous frame on the reading side of the data receiving buffer when the pixel point number ratio is greater than or equal to a preset ratio threshold value, so as to obtain the complete current frame.

In an alternative embodiment, the buffer control sub-module further includes a frame size estimation module, the frame size estimation module being communicatively coupled to the integrated control module; when the current frame is compressed video data, the comprehensive control module calls a frame size estimation module, wherein the frame size estimation module is used for estimating the number of compressed pixels of the current frame according to the actual number of pixels of the transmitted compressed video and sending the number of compressed pixels to a frame loss correction module; the frame loss correction module is used for executing the writing proportion calculation unit by taking the number of the compressed pixels as the total pixel point number.

In an alternative embodiment, the frame size estimation module includes: the compressed video pixel statistics unit is used for counting the actual pixel number of a plurality of transmitted compressed videos in a first historical time period from the current moment; and the compressed pixel number calculating unit is used for calculating the average value of the actual pixel number of each transmitted compressed video and taking the average value as the compressed pixel number.

In an optional implementation manner, the buffer control submodule further includes a write correction module, the write correction module is in communication connection with the comprehensive control module, and when the comprehensive control module detects a full signal of the data receiving buffer, the comprehensive control module further judges whether the current frame only writes the frame header in the data receiving buffer, and when the current frame only writes the frame header, the write correction module is called; the write correction module includes: a first rate detection unit configured to detect whether a read-side rate of the data reception buffer is equal to or greater than a write-side rate; a temporary buffer unit, configured to buffer data to be written in a current frame into a preconfigured internal register group when the read-side rate is greater than or equal to the write-side rate; and the data transmission unit is used for moving the data in the internal register group into the data receiving buffer according to the buffer sequence when the data receiving buffer is not full.

In an alternative embodiment, the write correction module further comprises: and the first frame loss unit is used for controlling the data receiving buffer to discard the current frame by the feedback integrated control module when the reading side rate is smaller than the writing side rate.

In an alternative embodiment, the first rate detection unit includes: a continuous rate detection unit, configured to detect a read-side continuous rate and a write-side continuous rate of the data receiving buffer in a second historical period of time from a current time; a rate index calculation unit for calculating a read rate index and a write rate index based on the read-side continuous rate and the write-side continuous rate, respectively; and the rate judging unit is used for judging whether the reading rate index is larger than or equal to the writing rate index by taking the reading rate index as a reading side rate and taking the writing rate index as a writing side rate.

In an alternative embodiment, the rate indicator calculation unit includes: an average read rate calculation unit for calculating a readout side average rate of the readout side in the second history period based on the readout side continuous rate; an average write rate calculation unit that calculates a write-side average rate of the write-side over a second history period based on the write-side continuous rate; and a rate index definition unit configured to take the readout-side average rate as a readout rate index and the write-side average rate as a write rate index.

In an optional implementation manner, the buffer control sub-module further comprises an active complement module, the active complement module is in communication connection with the comprehensive control module, and the comprehensive control module calls the active complement module when detecting an empty signal of the data receiving buffer; the active complement module comprises: a second rate detection unit configured to detect whether a read-side rate of the data reception buffer is greater than a write-side rate; the written data quantity analysis unit is used for calculating the written data quantity of the current frame in the data receiving buffer when the reading side speed is larger than the writing side speed, and judging whether the written data quantity reaches a preset data quantity threshold value or not; the active repair unit is used for filling the tail of the current frame by utilizing the frame tail backup information of the last frame on the read-out side of the data receiving buffer when the written data volume reaches a preset data volume threshold value to obtain a complete current frame; and the residual data discarding unit is used for controlling the data receiving buffer to discard the residual data by the feedback comprehensive control module when detecting that the residual data of the current frame reaches the writing side of the data receiving buffer.

In an optional implementation manner, the buffer control submodule further includes a capacity prediction module, the capacity prediction module is in communication connection with the integrated control module, the integrated control module invokes the capacity prediction module before the current frame is written into the data receiving buffer, and the capacity prediction module includes: a remaining capacity acquisition unit configured to acquire a remaining capacity of the data reception buffer; the writing judging unit is used for judging whether the current frame to be written can be completely written into the data receiving buffer according to the residual capacity; and the feedback writing unit is used for controlling the data receiving buffer to start to receive the writing of the current frame by the feedback integrated control module when the current frame is judged to be capable of being completely written into the data receiving buffer.

In an alternative embodiment, the writing decision unit comprises: the third speed detection unit is used for calculating a second reading speed index and a second writing speed index of the data receiving buffer in a third historical time period from the current moment, and the third historical time period is larger than the second historical time period; a frame size obtaining unit for obtaining the complete data volume of the current frame; the first time estimation unit is used for calculating the ratio of the complete data quantity to the second read rate index to obtain the read estimation time; the second time estimation unit is used for subtracting the whole data volume from the residual capacity and calculating the ratio of the subtracting result to the second writing rate index to obtain writing estimation time; the first judging unit is used for judging that the current frame can be completely written into the data receiving buffer when the writing estimated time is more than or equal to the reading estimated time; and the second judging unit is used for judging that the current frame cannot be completely written into the data receiving buffer when the writing estimated time is smaller than the reading estimated time.

In an alternative embodiment, the capacity estimation module further includes: and the second frame loss unit is used for controlling the data receiving buffer to discard the current frame by the feedback integrated control module when the current frame is judged to be incapable of being completely written into the data receiving buffer.

In an alternative embodiment, the integrated control module includes: and the third frame loss unit is used for controlling the data receiving buffer to discard the current frame when the current frame is written with partial data except the frame head of the data receiving buffer and the written data quantity does not reach the preset data quantity threshold value.

In an optional implementation manner, the video output control module further includes a write pointer rollback module, where the write pointer rollback module is respectively connected with the write timing control module and the frame status buffer in a communication manner, and the write pointer rollback module is configured to backup a write address of the current frame when the write timing control module writes the frame header of the current frame into the DDR, and to control the next frame to continue writing from the write address of the current frame when the status of the current frame indicates that the current frame is not completely written into the DDR.

In a second aspect, the present invention provides a video output control method of a BMC chip, applied to a buffer control submodule in a video output control module, where the method includes: controlling a data receiving buffer to receive compressed video data or YUV format video data; detecting a full state of the data receiving buffer; when the data receiving buffer reaches a full state, repairing incomplete frames caused by the full state in the data receiving buffer, and identifying the frame state and frame information of each frame by a buffer control submodule; responding to a read request of the buffer read-write control module, and sending the frame state and frame information of each frame to the buffer read-write control module so that the buffer read-write control module stores the corresponding frame state and frame information into a frame state buffer and a frame information buffer respectively; and responding to the read request of the write timing control module, and sending the processed video data to the write timing control module so that the write timing control module can upload the processed video data to the DDR.

In an alternative embodiment, patching an incomplete frame in a data reception buffer caused by a full state comprises: calculating the written data quantity of the current frame in a data receiving buffer, and judging whether the written data quantity reaches a preset data quantity threshold value or not; and when the written data quantity reaches a preset data quantity threshold value, filling the tail of the current frame by utilizing the tail backup information of the previous frame on the read side of the data receiving buffer to obtain the complete current frame.

In an alternative embodiment, when the current frame is YUV format video data, calculating the written data amount of the current frame in the data receiving buffer, and determining whether the written data amount reaches a preset data amount threshold, includes: when the frame head of the current frame enters a data receiving buffer, acquiring resolution information of the current frame; determining all pixel points of the current frame through resolution information; counting the number of written pixel points of the current frame as the written data quantity; calculating the ratio of the number of written pixels to the number of all pixels; judging whether the pixel point number ratio is larger than or equal to a preset ratio threshold, wherein the preset ratio threshold is a preset data quantity threshold; and when the pixel point number ratio is greater than or equal to a preset ratio threshold, filling the tail of the current frame by using the frame tail backup information of the previous frame on the reading side of the data receiving buffer to obtain the complete current frame.

In an alternative embodiment, the method further comprises: when the current frame is compressed video data, estimating the number of compressed pixels of the current frame according to the actual number of pixels of the transmitted compressed video; and returning the compressed pixel number as the total pixel number to calculate the ratio of the written pixel number to the total pixel number.

In an alternative embodiment, estimating the number of compressed pixels of the current frame from the actual number of pixels of the compressed video that has been transmitted includes: counting the actual pixel number of a plurality of transmitted compressed videos in a first historical time period from the current moment; an average value of the actual number of pixels of each compressed video that has been transmitted is calculated, and the average value is taken as the number of compressed pixels.

In an alternative embodiment, the method further comprises: when the full signal of the data receiving buffer is detected, judging whether the current frame only writes the frame head in the data receiving buffer; when the current frame only writes in the frame head, detecting whether the reading side speed of the data receiving buffer is more than or equal to the writing side speed; when the reading side speed is larger than or equal to the writing side speed, caching the data which need to be written in the current frame in sequence into a preset internal register group; when the data receiving buffer is not full, the data in the internal register group is moved into the data receiving buffer according to the buffer sequence.

In an alternative embodiment, the method further comprises: when the read-side rate is smaller than the write-side rate, the data receiving buffer is controlled to discard the current frame.

In an alternative embodiment, detecting whether the read-side rate of the data receiving buffer is equal to or greater than the write-side rate includes: detecting the continuous speed of the read side and the continuous speed of the write side of the data receiving buffer in a second historical time period from the current moment; calculating a read rate index and a write rate index based on the read-side continuous rate and the write-side continuous rate, respectively; and judging whether the reading rate index is larger than or equal to the writing rate index by taking the reading rate index as a reading side rate and taking the writing rate index as a writing side rate.

In an alternative embodiment, calculating the read rate index and the write rate index based on the read side continuous rate and the write side continuous rate, respectively, includes: calculating a readout-side average rate of the readout side over a second historical period based on the readout-side continuous rate; calculating a write side average rate of the write side over a second historical period of time based on the write side continuous rate; the read-side average rate is used as a read rate index, and the write-side average rate is used as a write rate index.

In an alternative embodiment, the method further comprises: when detecting the empty signal of the data receiving buffer, detecting whether the read-out side speed of the data receiving buffer is larger than the write-in side speed; when the reading side speed is larger than the writing side speed, calculating the written data quantity of the current frame in the data receiving buffer, and judging whether the written data quantity reaches a preset data quantity threshold value or not; when the written data quantity reaches a preset data quantity threshold value, filling the tail of the current frame by utilizing the frame tail backup information of the previous frame on the read side of the data receiving buffer to obtain a complete current frame; when detecting that the residual data of the current frame reaches the writing side of the data receiving buffer, the data receiving buffer is controlled to discard the residual data.

In an alternative embodiment, the method further comprises: before the current frame is written into the data receiving buffer, the residual capacity of the data receiving buffer is obtained; judging whether the current frame to be written can be completely written into a data receiving buffer or not according to the residual capacity; when the current frame is judged to be capable of being completely written into the data receiving buffer, the feedback comprehensive control module controls the data receiving buffer to start to receive writing of the current frame.

In an alternative embodiment, determining whether the current frame to be written can be completely written into the data receiving buffer according to the remaining capacity includes: calculating a second read rate index and a second write rate index of the data receiving buffer within a third historical time period from the current moment, wherein the third historical time period is larger than the second historical time period; acquiring the complete data volume of the current frame; calculating the ratio of the complete data quantity to the second read rate index to obtain the read estimated time; subtracting the residual capacity from the complete data volume, and calculating the ratio of the subtracting result to the second writing rate index to obtain writing estimated time; when the estimated writing time is greater than or equal to the estimated reading time, judging that the current frame can be completely written into the data receiving buffer; when the estimated write time is less than the estimated read time, it is determined that the current frame cannot be completely written into the data receiving buffer.

In an alternative embodiment, the method further comprises: when the current frame is judged to be unable to be completely written into the data receiving buffer, the data receiving buffer is controlled to discard the current frame.

In an alternative embodiment, the method further comprises: when the current frame is written with partial data except the frame head of the data receiving buffer and the written data quantity does not reach the preset data quantity threshold value, the data receiving buffer is controlled to discard the current frame.

In an alternative embodiment, the method further comprises: when the write time sequence control module writes the frame header of the current frame into the DDR, the write address of the current frame is backed up, and when the state of the current frame represents that the write of the current frame into the DDR is incomplete, the next frame is controlled to continue to be written from the write address of the current frame.

In a third aspect, the present invention provides a BMC device, including a DDR device and a BMC chip, where the BMC chip includes a VGA module, a color space conversion module, a video compression module, a network module, and a video output control module provided by any one of the optional embodiments of the first aspect, where the VGA module is communicatively connected to the color space conversion module, the color space conversion module is communicatively connected to the video compression module, the video output control module is communicatively connected to the color space conversion module and the video compression module at the same time, the video output control module is communicatively connected to the DDR device, the DDR device is communicatively connected to the network module, and the VGA module is configured to receive original video data sent by a server.

In a fourth aspect, the present invention provides a server, including a server memory, a server processor, and a BMC device, where the server memory and the server processor are communicatively coupled to each other, and the BMC device and the server processor are communicatively coupled to each other.

The technical scheme provided by the invention has the following advantages:

the technical scheme provided by the embodiment of the invention improves a video output control module of the related technology, adds a buffer control submodule except a data receiving buffer, a frame state buffer, a frame information buffer, a buffer read-write control module and a write time sequence control module, connects the added buffer control submodule between the data receiving buffer and the buffer read-write control module, controls the read-write of the data receiving buffer through the buffer control submodule alone, and the original buffer read-write control module is only used for controlling the frame state buffer and the frame information buffer. In the process of data writing, the buffer control submodule detects the full state of the data receiving buffer in real time, when the data receiving buffer generates a full signal, the buffer control submodule repairs incomplete frames caused by the full state in the data receiving buffer, the incomplete frames are complemented completely, so that the repaired incomplete frames are considered to be complete frames, the corresponding identification complete frame states and frame information can be stored in the frame state buffer and the frame information buffer, the writing time sequence control module uploads the processed video data to the DDR to be considered to be complete, and when a subsequent driver reads the data from the DDR, most of the data can be judged to be complete data, so that the data is read from the DDR, a large amount of useless data is prevented from remaining in the DDR, the occupation of storage resources of the DDR and the waste of bandwidth are reduced, meanwhile, the frame loss of an output video picture is less, and the frame loss problem caused by the link of transmitting the video to the DDR is remarkably solved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a video transmission function in a BMC device of the related art;

FIG. 2 is a schematic diagram of a related art video output control module;

FIG. 3 is a schematic diagram of a video output control module according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a buffer control sub-module according to an embodiment of the present invention;

FIG. 5 is a flow chart of a video output control method according to an embodiment of the invention;

FIG. 6 is a schematic diagram of a BMC device according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a server according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As shown in fig. 1, in some BMC video remote transmission scenarios, the video transmission flow is: video data of the server host is transmitted to a VGA module of the BMC chip through a PCIe bus, original video data is converted into data in RGB format through VGA processing, the RGB data is processed by a color space conversion module, the RGB format is converted into YUV format, and the internal conversion process is completed by using the following matrix conversion formula: y= (0.257×r) + (0.504×g) + (0.098×b) +16, u = 0.148×r-0.291×g+0.439×b+128, v = 0.439×r-0.368×g-0.071×b+128. And then, sending the data in the YUV format to a video compression module at a later stage for compression, wherein various video compression formats such as H.264, JPEG, AVS and the like are adopted, and finally, outputting the data in the YUV format or the compressed data to the DDR through a video output control module.

The related art discloses a method for video compression dynamic frame compensation, which provides a solution for a frame loss phenomenon of the above scene. The special scenarios for such techniques are: the DDR controller used for controlling the DDR is shared, a plurality of functions can occupy the DDR controller, so that the DDR controller can be occupied by other functional modules after the compression module of the BMC chip completes data compression, the compression module cannot write data into the DDR, and the BMC usually discards the frame of compressed video data, so that the frame loss phenomenon is caused. In order to solve the problem, the related art proposes that a frame compensating control module is deployed in advance, and before compressed data is written into the DDR, the frame compensating control module firstly obtains the control right of the DDR controller, if the control right is obtained, the frame compensating control module writes the compressed data into the DDR, if the control right is not obtained, the frame compensating control module waits until the DDR control right is obtained, and then writes the compressed data into the DDR, so that the frame data is not discarded, and the problem of frame loss caused by occupation of other functions of the DDR controller is solved. In addition, the frame supplementing control module also has the function of supplementing line data, if some line data is missing between the frame head and the frame tail for one frame of image before the frame of image data is compressed, the frame of image is not complete, the frame supplementing control module also can interpolate by utilizing the upper and lower adjacent line data of the missing line data, supplement the missing line, enable the frame of image to be complete, and then compress.

Although the above-described technique solves the problem of frame loss of video images to some extent, in this scenario where the BMC transmits video, not only frame loss is caused by occupied DDR control rights, but also a part of frame loss generally occurs in a video output control module of the BMC chip as shown in fig. 1, which is used to transmit video data from the BMC chip to the DDR.

In the video output control module, as shown in fig. 2, a first-in first-out data receiving buffer, namely, a receiver_fifo, is generally used to receive compressed video data or YUV format data, while the buffer read-write control module detects the Full state of the receiver_fifo, if the receiver_fifo has a Full signal (i.e., a Full signal), the buffer read-write control module will cause stopping of writing video data into the receiver_fifo, if only a part of a frame of image has written the receiver_fifo, the remaining data of the current frame will be discarded until the frame head waiting for the next frame arrives and the receiver_fifo is in a non-Full state, and writing of data of the next frame will begin. In the above process, the write timing control module may continuously read data from the receiver_fifo and transmit the data to the DDR, resulting in that only missing data with a frame header and no frame tail enters the DDR. Meanwhile, the buffer read-write control module also detects the frame end of one frame of data, if one frame of data is detected at the read-out side of the receiver_fifo, the frame end is indicated to be one frame of complete data, so that the buffer read-write control module writes the state of the current frame into the frame state buffer info_fifo as 2 to indicate that the current frame is a complete frame, and if the buffer read-write control module does not detect the frame end of one frame of data, the buffer read-write control module writes the state of the current frame into the frame state buffer as 1 to indicate that the current frame is an incomplete frame. In addition, the buffer read-write control module only updates the frame information of the complete frame to the frame information buffer state_fifo for driving reading, and typically, the frame information includes the first address of the video frame in DDR, the length of the frame, and the like. When video data is required to be remotely sent through the network module, a designated driver judges which data in the DDR are complete according to the state in the info_fifo, and then reads corresponding information according to the information recorded in the state_fifo to a designated address in the DDR and sends the corresponding information through the network module. Because the driver only reads the complete video frame from the DDR to the network module and sends the complete video frame through the network module, incomplete data which is missing in the DDR is not read, so that the problem of video frame loss is caused, and meanwhile, residual data in the DDR also causes waste of DDR storage resources and transmission bandwidth. The scheme provided by the related art only considers the frame loss caused by the DDR control right, and does not consider that even if the DDR control right exists, the frame loss problem caused by the data receiving link cannot be completely solved because the frame loss is generated due to the full state of the receiver_fifo in the process of transmitting the data to the DDR.

Based on the above, the invention provides a new scheme for solving the problem of frame loss caused by the link from video transmission to DDR in the BMC video transmission function, and the specific scheme is as follows. "module" in this embodiment refers to an ASIC (Application Specific Integrated Circuit ) circuit, a processor and memory executing one or more software or firmware programs, and/or other devices that can provide the above-described functionality. The term "unit" is a software program that can realize a predetermined function.

According to an embodiment of the present invention, there is provided a video output control module of a BMC chip, as shown in fig. 3, including: the data receiving buffer memory receives_fifo, the frame state buffer memory info_fifo, the frame information buffer memory state_fifo, the buffer memory control sub-module C1, the buffer memory read-write control module C2 and the write time sequence control module W1; the data receiving buffer receiver_fifo is used for receiving compressed video data or YUV format video data; the buffer control submodule C1 is in communication connection with the data receiving buffer receiver_fifo and is used for controlling writing and reading of data in the data receiving buffer receiver_fifo, detecting the full state of the data receiving buffer receiver_fifo and repairing an incomplete frame caused by the full state in the data receiving buffer receiver_fifo; the buffer read-write control module C2 is respectively in communication connection with the buffer control submodule C1, the frame state buffer info_fifo and the frame information buffer state_fifo, and the buffer read-write control module C2 is used for reading the frame state and the frame information of each frame identified by the buffer control submodule C1 and storing the corresponding frame state and the frame information into the frame state buffer info_fifo and the frame information buffer state_fifo; the write timing control module W1 is communicatively connected to the buffer control submodule C1, and in this embodiment, the write time Xu Mokuai W1 is based on an AXI bus protocol implementation, and is configured to read video data processed by the buffer control submodule C1, and upload the processed video data to the DDR.

Specifically, the embodiment of the invention improves a video output control module of the related art, adds a buffer control submodule C1 in addition to a data receiving buffer receiver_fifo, a frame status buffer info_fifo, a frame information buffer state_fifo, a buffer read-write control module C2 and a write time sequence control module W1, connects the added buffer control submodule C1 between the data receiving buffer receiver_fifo and the buffer read-write control module C2, and controls the read-write of the data receiving buffer receiver_fifo by the buffer control submodule C1 alone, wherein the original buffer read-write control module C2 is only used for controlling the frame status buffer info_fifo and the frame information buffer state_fifo, thereby performing functional separation. In the process of writing data, the buffer control submodule C1 detects the full state of the data receiving buffer receive_fifo in real time, when the data receiving buffer receive_fifo generates a full signal, the buffer control submodule C1 provided in this embodiment repairs an incomplete frame caused by the full state in the data receiving buffer receive_fifo, so as to supplement the incomplete data to be complete, so that the repaired incomplete frame is considered to be a complete frame, the frame state corresponding to the repaired data is characterized as 2, the frame state is stored in the frame state buffer info_fifo, the corresponding frame information is stored in the frame information buffer state_fifo, and then the write timing control module W1 uploads the processed video data to the DDR and is considered to be complete. When the step of reading data from the DDR by the driver is executed subsequently, most data in the DDR can be judged to be complete data according to the state cached in the frame state buffer info_fifo, so that one frame of data can be read out from the DDR by the driver, a large amount of useless data is prevented from remaining in the DDR, the occupation of storage resources and the waste of bandwidth of the DDR are reduced, the frame loss of an output video picture is fewer, the picture is more complete, and the frame loss problem caused by the link of transmitting video to the DDR is remarkably solved.

In some alternative embodiments, the buffer control sub-module C1 includes an integrated control module and a frame loss correction module. As shown in fig. 4, the integrated control module is respectively connected with the data receiving buffer receiver_fifo, the buffer read-write control module C2, the write timing control module W1 and the frame loss correction module in a communication manner, and is used for controlling writing and reading of data in the data receiving buffer receiver_fifo, detecting a full state of the data receiving buffer receiver_fifo, sending frame states and frame information of each frame to the buffer read-write control module C2, enabling the write timing control module W1 to read the processed video data, and calling the frame loss correction module when a full signal of the data receiving buffer receiver_fifo is detected; the frame loss correction module is used for calculating the written data quantity of the current frame in the data receiving buffer memory receiver_fifo, judging whether the written data quantity reaches a preset data quantity threshold, and filling the tail of the current frame by utilizing the frame tail backup information of the previous frame on the reading side of the data receiving buffer memory receiver_fifo when the written data quantity reaches the preset data quantity threshold, so as to obtain the complete current frame.

Specifically, in the embodiment of the present invention, a comprehensive control module and a frame loss correction module are respectively installed in a buffer control submodule C1, where the comprehensive control module is used as a master control module for communication, monitoring and interaction, and the frame loss correction module is called by the comprehensive control module and is used for repairing incomplete frame data in a data receiving buffer receiver_fifo. In practical applications, there is a lot of data written in the current frame (such as 95%), but when the frame is about to be written in the end of the frame, the full signal appears in the data receiving buffer, the frame is to be discarded in the related art, the drive cannot obtain the information of the frame in the DDR, and waste of the DDR buffer and the DDR bus bandwidth is caused, because the data is written in the DDR, but the drive cannot read, therefore, the data is in invalid writing, and the frame loss rate is high. In this embodiment, mainly solves the problem in this scenario, whether the current frame has already written most data when the full signal is generated is determined by the preset data amount threshold, for example, but not limited to, the preset data amount threshold is configured according to the user requirement, and in this embodiment, considering that if most of the data is missing in one frame, the effect of correction may cause tearing of the picture, the preset data amount threshold is preferably set to be between 50% and 100%, so that only the data missing between 0% and 50% is corrected. When the written data volume reaches the preset data volume threshold, the embodiment fills the tail of the current frame with the tail backup information of the previous frame (for example, 5% of data of the tail part of the frame is backed up in advance in each frame of data transmission) at the read side of the data receiving buffer receiver_fifo, so as to obtain the complete current frame. Because the video is continuously displayed, the display of a very small portion of the individual frames does not coincide with the original frames and does not affect the remote end display effect, which is the root cause of being able to design a lost frame correction module. By the correction of the frame loss correction module, the frames are not calculated as frame loss any more, but are calculated as normal frames, namely, the state value written into the frame state buffer info_fifo is 2, and the frame information buffer state_fifo can normally store information, so that the problem of frame loss is solved. Meanwhile, the embodiment repairs the current frame by utilizing the data at the tail of the last frame, on one hand, two frames of data are relatively close, the repaired picture has smaller influence, on the other hand, the data transmitted by the last frame are automatically backed up in the BMC chip in the transmission process, and the backup information of the tail of the last frame is directly cut, so that the backup process is simple and feasible without additional configuration of backup data.

In some optional embodiments, when the current frame is YUV format video data, the integrated control module acquires resolution information of the current frame when a frame header of the current frame enters the data receiving buffer receiver_fifo. Meanwhile, the frame loss correction module comprises the following software program units: a pixel calculation unit for determining all pixel points of the current frame through resolution information; the written pixel counting unit is used for counting the number of written pixel points of the current frame as the written data quantity; a writing proportion calculating unit for calculating the ratio of the number of written pixels to the number of all pixels; the patching condition judging unit is used for judging whether the pixel point number ratio is larger than or equal to a preset ratio threshold value, wherein the preset ratio threshold value is a preset data volume threshold value; and the patching unit is used for filling the tail part of the current frame by utilizing the frame tail backup information of the previous frame on the reading side of the data receiving buffer receiver_fifo when the pixel point number ratio is greater than or equal to a preset ratio threshold value, so as to obtain the complete current frame.

Specifically, in the present embodiment, a patching scheme for YUV format video data from a color space conversion module is provided. In order to correct the frame data of the lost frame end, the most important link is to judge whether the written data reaches the preset data quantity threshold value, if not, the repair is not performed. Therefore, in this embodiment, when the YUV format data is written into the data receiving buffer receiver_fifo, the integrated control module first obtains the resolution information of the current frame when the frame header of the current frame enters the data receiving buffer receiver_fifo, for example, the resolution information of the current frame is 1920×1200, and the resolution information is the self-characteristics of the YUV format video data, and can be directly obtained. After that, the frame loss repair module runs a preset code program, and firstly determines all pixel points of the current frame through resolution information, for example, the resolution information is 1920×1200, then all pixel points of the current frame are 1920×1200, and each pixel point occupies 24bits (RGB 888 is converted into YUV444 format).

Then, the written pixel point count cur_frame_pixel_cnt of the current frame is detected in real time in the frame loss repair module, and the total pixel point count of the frame is marked as cur_frame_pixel_num, taking a preset data quantity threshold value of 95% as an example: when the full state signal appears in the data receiving buffer receiver_fifo and the current frame is 95% of the current frame, the current frame is considered to reach the repair condition, so that the tail of the current frame is filled at the reading side of the data receiving buffer receiver_fifo by using the frame tail backup information of the previous frame, the complete current frame is obtained, and the problem of frame loss is solved. Particularly, because the amount of original video data in YUV format is huge, in practical application, when the YUV video frame is just about to be completely written into the data receiving buffer receiver_fifo, the full state signal is pulled up, so that the current frame has to be discarded, and the most extreme case is that all or all of continuous multi-frame YUV data cannot be completely written into DDR, so that the driver cannot read relevant frame information, and the display effect of the remote end is greatly affected.

In some optional implementations, as shown in fig. 4, the buffer control submodule C1 provided in the embodiment of the present invention further includes a frame size estimation module, where the frame size estimation module is communicatively connected to the integrated control module; when the current frame is compressed video data, the comprehensive control module calls a frame size estimation module, wherein the frame size estimation module is used for estimating the number of compressed pixels of the current frame according to the actual number of pixels of the transmitted compressed video and sending the number of compressed pixels to a frame loss correction module; the frame loss correction module is used for executing the writing proportion calculation unit by taking the number of the compressed pixels as the total pixel point number.

Specifically, the present embodiment provides a patching scheme for a scenario in which the data received by the data receiving buffer receive_fifo is compressed data, and if the video data is in a compressed format (JPEG, h.264, etc.), before the end of frame actually arrives, the frame loss correction module cannot know the actual size of the current frame (occupied Bytes data), because in practical application, the compression ratio of each frame of video compression is different. In this case, the present embodiment adds a frame size estimation module, and the function of this sub-module is to estimate the current frame according to the actual size of the compressed video that has been transmitted, so as to obtain the compressed pixel number cur_frame_pixel_num_estimate of the current frame. Further, the number of written pixels of the current frame and the number of compressed pixels of the current frame are used for judging, taking a preset data amount threshold value of 95% as an example, when the cur_frame_pixel_cnt/cur_frame_pixel_num_estimate is more than 95%, the data receiving buffer receiver_fifo is full, at this time, the writing of data is stopped at the writing side of the data receiving buffer receiver_fifo, and at the reading side, the frame tail part of the current frame is filled with the backup information of the frame tail of the previous frame so as to be spliced into a complete frame. By the scheme provided by the embodiment, whether the two types of data reach the repair condition can be flexibly judged for the YUV format video data or the compressed video data, so that the flexibility of the repair data is improved, the frame loss phenomenon is further reduced, and the DDR loss is reduced.

In some alternative embodiments, the frame size estimation module includes: the compressed video pixel statistics unit is used for counting the actual pixel number of a plurality of transmitted compressed videos in a first historical time period from the current moment; and the compressed pixel number calculating unit is used for calculating the average value of the actual pixel number of each transmitted compressed video and taking the average value as the compressed pixel number.

Specifically, in this embodiment, by counting the actual pixel numbers of the plurality of transmitted compressed videos in a period of time, and calculating an average value of the actual pixel numbers of the compressed videos in a period of time according to the actual pixel numbers of the respective compressed videos, the compression capability of the compressed videos by the average value estimation compression module is more accurate, so that the calculated average value is used as the compressed pixel number, and the accuracy of the compressed pixel number estimation is improved.

In some alternative embodiments, as shown in fig. 4, the buffer control sub-module C1 further includes a write correction module, where the write correction module is communicatively connected to the integrated control module, and when detecting a full signal of the data receiving buffer receiver_fifo, the integrated control module further determines whether the current frame has only a frame header written in the data receiving buffer receiver_fifo, and invokes the write correction module when the current frame has only a frame header written therein. The writing correction module specifically comprises: a first rate detection unit configured to detect whether a read-side rate of the data reception buffer receiver_fifo is equal to or greater than a write-side rate; a temporary buffer unit, configured to buffer data to be written in a current frame into a preconfigured internal register group when the read-side rate is greater than or equal to the write-side rate; and the data transmission unit is used for moving the data in the internal register group into the data receiving buffer memory according to the caching sequence when the data receiving buffer memory is not full. The first frame loss unit is used for controlling the data receiving buffer receiver_fifo to discard the current frame when the reading side rate is smaller than the writing side rate.

Specifically, in practical application, there is a special case that the data is only partially written when the data receiving buffer is full. That is, when the frame header appears in the current frame, the full signal appears in the data receiving buffer receiver_fifo, and such frames need to be discarded in the related art, but there may be a scene that the data receiving buffer receiver_fifo is not full soon, for example, when the second clock cycle and the third clock cycle of the frame header of the current frame are the second clock cycle and the third clock cycle, the data receiving buffer receiver_fifo is not full and allows writing, but because the frame header is just missed, such frames are discarded, resulting in a higher frame loss rate. Because the frame has no effective data writing except the frame head, the data of the previous frame is utilized to repair the current frame, so that the direct adoption of the repair scheme is not suitable, not only occupies a larger backup space, but also has longer repair time. Considering that the reading and writing of the data receiving buffer receiver_fifo are asynchronous two operations, the present embodiment further deploys a write correction module, when the data receiving buffer receiver_fifo is full and the data receiving buffer receiver_fifo only writes one frame header, the write correction module is invoked to first verify whether the reading side rate of the data receiving buffer receiver_fifo is greater than or equal to the writing side rate, if the reading side rate is greater than or equal to the writing side rate, it means that the data receiving buffer receiver_fifo can release a certain space due to the reading of data soon, so the present embodiment divides an internal register set in the BMC chip by using registers, temporarily stores the data to be written in subsequently of the current frame into the preconfigured internal register set, and since the space of the data receiving buffer receiver_fifo can be released soon, the space in the internal register set is not excessively long enough, and the data in the internal register set should not be covered for the storage time. When the write correction module detects that the data receiving buffer receiver_fifo releases the space, the data in the internal register group is immediately moved into the data receiving buffer receiver_fifo according to the buffer sequence, so that the aim of normally writing the current frame into the data receiving buffer receiver_fifo is fulfilled, the problem of missing frame heads is avoided, and the occurrence of frame loss is further reduced. It should be noted that, in the subsequent writing process of the frame header having been written into the data receiving buffer, if the data receiving buffer, is full again, the data to be written is written into the internal register set again until the data receiving buffer, is not full, and then writing is performed normally. When the read-side rate is smaller than the write-side rate, the write-in amount of the data receiving buffer receiver_fifo is larger than the read-out amount, and the data receiving buffer receiver_fifo cannot release space in a short time, so that the current frame cannot continue waiting, and at the moment, the write-correction module feeds back the integrated control module to control the data receiving buffer receiver_fifo to discard the current frame, so that the reliability of overall data transmission is improved.

In some optional embodiments, the first rate detection unit specifically includes: a continuous rate detection unit, configured to detect a read-side continuous rate and a write-side continuous rate of the data receiving buffer receive_fifo in a second historical period of time from the current time; a rate index calculation unit for calculating a read rate index and a write rate index based on the read-side continuous rate and the write-side continuous rate, respectively; and the rate judging unit is used for judging whether the reading rate index is larger than or equal to the writing rate index by taking the reading rate index as a reading side rate and taking the writing rate index as a writing side rate.

Specifically, in order to further improve the accuracy of detection of the read-side rate and the write-side rate of the data receiving buffer receive_fifo, considering that asynchronous operation may cause a certain rate fluctuation, if the rate at the very statistical time fluctuates, a detection result that the read-side rate is smaller than the write-side rate may occur, but most of the time is that the read-side rate is greater than or equal to the write-side rate, resulting in erroneous judgment and unnecessary frame loss. Therefore, in this embodiment, the read-side continuous rate and the write-side continuous rate of the data receiving buffer receiver_fifo in the second historical time period from the current time are detected, and the corresponding read-side continuous rate index and write-side continuous rate index, such as an average value, a mode, and the like, are calculated by using the read-side continuous rate and the write-side continuous rate to characterize the read-side rate and the write-side rate of the data receiving buffer receiver_fifo in a period of time, and finally, whether the read-side continuous rate index is greater than or equal to the write-side continuous rate index is determined by using the read-side continuous rate and the write-side continuous rate, so that the accuracy of rate determination is improved, and therefore, the frame loss phenomenon is further reduced, and the frame loss problem is solved.

In some optional embodiments, the rate indicator calculating unit specifically includes: an average read rate calculation unit for calculating a readout side average rate of the readout side in the second history period based on the readout side continuous rate; an average write rate calculation unit that calculates a write-side average rate of the write-side over a second history period based on the write-side continuous rate; and a rate index definition unit configured to take the readout-side average rate as a readout rate index and the write-side average rate as a write rate index.

Specifically, in this embodiment, the average rate of the data receiving buffer receiver_fifo on the read side and the average rate of the data receiving buffer receiver_fifo on the write side in a period of time are used to measure whether the data receiving buffer receiver_fifo is fast to read data or fast to write data, so that the reliability is stronger and the accuracy is better for judging whether the condition of the write correction module is satisfied, and the accuracy of the write correction module can be further improved, so that only the subsequent data of the frame header is provided in the internal register set, thereby further reducing the occurrence of the frame loss.

In some optional embodiments, as shown in fig. 4, the buffer control sub-module C1 further includes an active complement module, where the active complement module is communicatively connected to the integrated control module, and the integrated control module invokes the active complement module when detecting an empty signal of the data receiving buffer receive_fifo; the active complement module comprises: a second rate detection unit configured to detect whether a read-side rate of the data reception buffer receive_fifo is greater than a write-side rate; the written data amount analysis unit is used for calculating the written data amount of the current frame in the data receiving buffer receiver_fifo when the read-side rate is larger than the write-side rate, and judging whether the written data amount reaches a preset data amount threshold; the active repair unit is used for filling the tail of the current frame by utilizing the frame tail backup information of the last frame on the reading side of the data receiving buffer receiver_fifo when the written data volume reaches a preset data volume threshold value to obtain a complete current frame; the feedback integrated control module is used for controlling the data receiving buffer receiver_fifo to discard the residual data when detecting that the residual data of the current frame reaches the writing side of the data receiving buffer receiver_fifo.

Specifically, in practical application, there is a phenomenon that, although frame loss of video data is not caused, a large waste of DDR memory resources and bandwidth is caused, and this scenario is specifically: the read side speed of the data receiving buffer memory receiver_fifo is higher, the write side speed is lower, the written video data volume is smaller, the first half part of one frame of data in the data receiving buffer memory receiver_fifo is read out earlier, and the second half part is in a scene of being not delayed, so that the data receiving buffer memory receiver_fifo is in an empty state, the current frame is written to the frame tail immediately, but the current DDR bus is in an idle state, and no data is written, so that the DDR bus bandwidth is wasted. For this scenario, the present embodiment provides an active complement module, which monitors in real time whether the read-side rate of the data receiving buffer receiver_fifo is greater than the write-side rate (the specific method of monitoring the rate in this step is the same as the method of counting the rate in the second historical period in the foregoing embodiment, and is not repeated here), when the read-side rate is greater than the write-side rate, it indicates that the data receiving buffer receiver_fifo will be soon emptied, so as to calculate in real time the written data amount of the current frame in the data receiving buffer receiver_fifo, and determine whether the written data amount reaches a preset data amount threshold (for example, 95% for determining whether the current frame is fast written to the end of the frame, the embodiment is only limited by this example, and the preferred threshold is the same as the foregoing embodiment), and once the written data amount of the data receiving buffer receiver_fifo reaches the preset data amount threshold, the active complement module calculates the written data amount of the current frame in the data receiving buffer receiver_fifo on the read-side of the data receiving buffer receiver_fifo, and uses the written data amount of the current frame as the full frame to be immediately before the current frame is completed, and the current frame is completed. When the subsequent detection that the residual data of the current frame reaches the writing side of the data receiving buffer receiver_fifo, the comprehensive control module controls the writing enabling signal of the data receiving buffer receiver_fifo, discards the residual data, waits for the frame head of the next frame, and then starts writing enabling. For example: assuming that 100 pixels exist in the current frame, when the video data of the last 5 pixels are transmitted to the 95 th pixel, the DDR bus is in an idle state at the moment, because the reading speed of the data receiving buffer receiver_fifo is detected to be faster than the writing speed, the active complement module directly uses the video data corresponding to the last 5 pixels of the previous frame to actively complement the current frame in response to the state, and when the actual last 5 pixels of the current frame arrive, the video data of the data receiving buffer receiver_fifo is not written any more and is directly abandoned. The active complement module provided by the embodiment has the advantages that the display effect is not affected because the complement data are very few, so that the bandwidth of the DDR is fully utilized under the condition that the display effect is not affected, and the utilization rate of the DDR bus is improved.

In some optional embodiments, as shown in fig. 4, the buffer control sub-module C1 further includes a capacity estimation module, where the capacity estimation module is communicatively connected to the integrated control module, and the integrated control module invokes the capacity estimation module before the current frame is written into the data receiving buffer receive_fifo, where the capacity estimation module includes: a residual capacity acquisition unit configured to acquire a residual capacity of the data reception buffer receiver_fifo; a writing judging unit for judging whether the current frame to be written can be completely written into the data receiving buffer receiver_fifo according to the residual capacity; the feedback writing unit is used for controlling the data receiving buffer memory to start to receive the writing of the current frame by the feedback comprehensive control module when the current frame is judged to be capable of being completely written into the data receiving buffer memory; and the second frame loss unit is used for controlling the data receiving buffer receiver_fifo to discard the current frame by the feedback comprehensive control module when the current frame is judged to be incapable of being completely written into the data receiving buffer receiver_fifo.

Specifically, in practical applications, there is also a case where it is difficult to repair, as in the foregoing embodiment, assuming that the amount of data written in the current frame reaches 50% or less than 50%, the amount of data written in the current frame is less than the preset data amount threshold, the repair effect is poor due to the large amount of missing data, and in general, such a frame will not be repaired and needs to be discarded directly. In order to reduce the occurrence of frame loss events as much as possible, the embodiment of the invention also adds a capacity estimation module for reducing the occurrence of the situation that the frame loss is required. In this embodiment, before writing a frame of data (i.e. before writing a frame header), the capacity estimation module first obtains the remaining capacity of the data receiving buffer receiver_fifo, and then analyzes according to the remaining capacity to determine whether the current frame to be written can be completely written into the data receiving buffer receiver_fifo, for example: the embodiment can determine whether the size of the current frame is smaller than the remaining capacity, and if so, it is indicated that the data receiving buffer receiver_fifo can also accommodate the next complete current frame. Thus, only when it is determined that the current frame can be completely written into the data receiving buffer receiver_fifo, the data receiving buffer receiver_fifo is controlled to start receiving the writing of the current frame, and when it is determined that the current frame cannot be written, the current frame is discarded, instead of half of the writing finding that the current frame cannot be written and discarded again. Through the capacity estimation module provided by the embodiment, the situation that the frame has to be lost due to less written data can be obviously reduced.

In some optional embodiments, the writing determination unit includes: the third rate detection unit is used for calculating a second read rate index and a second write rate index of the data receiving buffer receiver_fifo in a third historical time period from the current moment, wherein the third historical time period is larger than the second historical time period; a frame size obtaining unit for obtaining the complete data volume of the current frame; the first time estimation unit is used for calculating the ratio of the complete data quantity to the second read rate index to obtain the read estimation time; the second time estimation unit is used for subtracting the whole data volume from the residual capacity and calculating the ratio of the subtracting result to the second writing rate index to obtain writing estimation time; a first determining unit, configured to determine that the current frame can be completely written into the data receiving buffer receiver_fifo when the writing estimated time is greater than or equal to the reading estimated time; and the second judging unit is used for judging that the current frame cannot be completely written into the data receiving buffer receiver_fifo when the writing estimated time is smaller than the reading estimated time.

Specifically, considering that the reading and writing of the data receiving buffer receiver_fifo is an asynchronous operation, if it is estimated whether the current frame can be written according to the size relationship between the remaining capacity of the data receiving buffer receiver_fifo and the current frame, the data writing speed is obviously reduced, resulting in slower video data transmission, thereby bringing new problems. To address this problem, the present embodiment further optimizes the decision logic of whether the current frame can be written completely. First, in the present embodiment, the second read rate indicator and the second write rate indicator of the data receiving buffer receive_fifo are calculated within the third historical period from the current time (the calculation method for the second read rate indicator and the second write rate indicator is the same as that of the previous embodiment, and is not described herein again), and it is noted that, since the third historical period needs to be larger than the second historical period because the probability of the complete writing of the current frame for a whole frame needs to be estimated. Then, the complete data amount cur_frame_pixel_num of the current frame is obtained (e.g. 1920×1200), and then the ratio of the complete data amount to the second read rate index rd_speed is calculated to obtain the read estimated time T1 of the complete current frame from the data receiving buffer receiver_fifo, for example, the following formula:

T1=(cur_frame_pixel_num)/rd_speed

The complete data amount is then subtracted from the remaining capacity space_space, which represents the space that can be written immediately, cur_frame_pixel_num_space_space represents the part to be written in addition to the part to be written immediately, and then the ratio of the subtraction result to the second write rate index wr_speed is calculated to obtain the write estimation time T2, for example, the following formula

T2=（cur_frame_pixel_num-space_remain)/wr_speed

If the above formula T1 is equal to or greater than T2, the present embodiment considers that, when the current frame is written, a portion to be written is not faster than a portion to be written immediately, and thus the current frame should be able to be completely written into the data receiving buffer receiver_fifo, and the present embodiment determines that the current frame can be completely written into the data receiving buffer receiver_fifo, based on which the data to be written into can be immediately written into the data receiving buffer receiver_fifo without waiting for the remaining capacity to be greater than that of the current frame. Conversely, if T1 is less than or equal to T2, then it is considered that writing is not possible, and the current frame is discarded. By the logic provided by the embodiment, the judgment accuracy of whether the current frame can be completely written into the data receiving buffer memory receiver_fifo is further improved, the waiting time for writing data is reduced, and the data transmission efficiency is improved.

In some optional implementations, based on the solutions provided by the foregoing embodiments, the integrated control module further includes: and the third frame loss unit is used for controlling the data receiving buffer receiver_fifo to discard the current frame when the current frame is written with partial data except the frame header and the written data quantity does not reach the preset data quantity threshold value.

Specifically, the embodiment discards the data frames which can not be repaired (i.e. the condition of the preset data quantity threshold is not met) or can not be cached in advance (i.e. the scene of only writing in the frame header) through the internal register group, thereby remarkably reducing the occurrence of the frame loss phenomenon and improving the reliability of data transmission.

In some optional embodiments, as shown in fig. 3, the video output control module further includes a write pointer rollback module W2, where the write pointer rollback module W2 is respectively connected to the write timing control module W1 and the frame status buffer info_fifo in a communication manner, and the write pointer rollback module W2 is configured to backup a write address of the current frame when the write timing control module W1 writes the frame header of the current frame into the DDR, and to control the next frame to continue to write from the write address of the current frame when the state of the current frame indicates that the current frame is not completely written into the DDR.

Specifically, the write pointer rollback module W2 provided in this embodiment performs data coverage on data that has been already written into the DDR in a frame that is not completely written, so as to reuse the DDR memory space. The writing address is backed up at the moment when the frame head of each frame is written into the DDR, the writing pointer is rolled back when the state of the current frame indicates that the current frame is incomplete, and the next frame starts to be written from the writing address backed up by the current frame, so that the data coverage of the incomplete frame and the reuse of the DDR space are realized, and the waste of DDR storage resources is further reduced.

In an embodiment of an actual application scenario, through each module provided in the above embodiment, before writing one frame of data into the data receiving buffer receiver_fifo, firstly, calling a capacity estimating module to estimate whether the current frame can be completely written, and if the current frame is estimated to be capable of being written with a high probability, then writing; then in the actual writing process, firstly avoiding the frame loss caused by the frame head missing of the current frame through a writing correction module, then repairing the frame loss caused by the frame loss indeed through a frame loss correction module, and if the frame loss is not caused, actively repairing the frame with slower data transmission speed through an active complement module, thereby improving the bandwidth utilization rate of the DDR; finally, even if a frame of data passes through the previous module without solving the problem of frame loss, incomplete data is caused to enter the DDR, the embodiment also uses the write pointer rollback module W2 to cover the DDR space occupied by the current frame by using the next frame of data, thereby avoiding waste of the DDR space. Through the steps, the technical scheme provided by the embodiment of the invention not only well solves the problem of frame loss, but also avoids waste of DDR storage resources and bandwidth.

The embodiments of the present invention also provide a method for controlling video output of a BMC chip, which is applied to a buffer control sub-module in a video output control module, and it should be noted that, the steps shown in the flowchart of the accompanying drawings may be performed in a computer system such as a set of computer executable instructions, and although a logic sequence is shown in the flowchart, in some cases, the steps shown or described may be performed in a sequence different from that shown or described herein.

Fig. 5 is a flowchart of a video output control method of a BMC chip according to an embodiment of the present invention, where the flowchart includes the following steps:

in step S101, the data receiving buffer is controlled to receive compressed video data or YUV format video data.

Step S102, detecting a full state of the data receiving buffer.

Step S103, when the data receiving buffer reaches the full state, the incomplete frames caused by the full state in the data receiving buffer are repaired, and the buffer control submodule identifies the frame state and the frame information of each frame.

Step S104, in response to the read request of the buffer read-write control module, the frame state and the frame information of each frame are sent to the buffer read-write control module, so that the buffer read-write control module stores the corresponding frame state and the frame information into the frame state buffer and the frame information buffer respectively.

Step S105, in response to the read request from the write timing control module, sends the processed video data to the write timing control module, so that the write timing control module uploads the processed video data to the DDR.

Specifically, the explanation of the principles of the embodiment of the present method may refer to the related description of the embodiment of the video output control module, which is not repeated herein.

In some alternative embodiments, the step S103 includes:

step a1, calculating the written data quantity of the current frame in the data receiving buffer, and judging whether the written data quantity reaches a preset data quantity threshold value.

And a2, when the written data quantity reaches a preset data quantity threshold value, filling the tail of the current frame by utilizing the tail backup information of the previous frame on the read side of the data receiving buffer to obtain the complete current frame.

In some alternative embodiments, when the current frame is YUV format video data, step a1 includes:

and b1, acquiring resolution information of the current frame when the frame header of the current frame enters the data receiving buffer.

And b2, determining the total pixel number of the current frame through the resolution information.

And b3, counting the number of written pixel points of the current frame as the written data quantity.

And b4, calculating the ratio of the number of the written pixels to the number of the total pixels.

And b5, judging whether the pixel point number ratio is larger than or equal to a preset ratio threshold, wherein the preset ratio threshold is a preset data volume threshold.

And b6, when the pixel point number ratio is greater than or equal to a preset ratio threshold, filling the tail of the current frame by utilizing the tail backup information of the previous frame on the read-out side of the data receiving buffer to obtain the complete current frame.

The embodiment of the invention also provides a BMC device, as shown in fig. 6, comprising a DDR device 10 and a BMC chip 20, wherein the BMC chip 20 comprises a VGA module 30, a color space conversion module 40, a video compression module 50, a network module 60 and the video output control module 70 shown in fig. 3, the VGA module 30 is in communication connection with the color space conversion module 40, the color space conversion module 40 is in communication connection with the video compression module 50, the video output control module 70 is simultaneously in communication connection with the color space conversion module 40 and the video compression module 50, the video output control module 70 is in communication connection with the DDR device 10, the DDR device 10 is in communication connection with the network module 60, and the VGA module 30 is used for receiving original video data sent by a server. In this embodiment, the network module 60 adopts an EMAC network module, and for the application of the video output control module 70 in the BMC chip, reference may be made to the description related to the above embodiment of the video output control module, which is not repeated here.

The embodiment of the present invention further provides a server, as shown in fig. 7, including a server memory 80, a server processor 90, and a BMC device 100, where the server memory 80 and the server processor 90 are communicatively connected to each other, and the BMC device 100 and the server processor 90 are communicatively connected to each other.

The server memory 80 may include at least one or more server memories 80, and the server memory 80 may be a central processor, a network processor, or a combination thereof. The server memory 80 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the server memory 80 stores instructions executable by the at least one server processor 90 to cause the at least one server processor 90 to perform a method for implementing the embodiments described above.

The server memory 80 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the server memory 80 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, server memory 80 may optionally include memory located remotely from server processor 90, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The server memory 80 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The server also includes a communication interface 110 for the computer device to communicate with other devices or communication networks.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. A video output control module of a BMC chip, comprising: the system comprises a data receiving buffer, a frame state buffer, a frame information buffer, a buffer control sub-module, a buffer read-write control module and a write time sequence control module;

the data receiving buffer is used for receiving compressed video data or YUV format video data;

the buffer control submodule is in communication connection with the data receiving buffer and is used for controlling writing and reading of data in the data receiving buffer, detecting the full state of the data receiving buffer and repairing incomplete frames caused by the full state in the data receiving buffer;

the buffer read-write control module is respectively in communication connection with the buffer control submodule, the frame state buffer and the frame information buffer, and is used for reading the frame state and the frame information of each frame identified by the buffer control submodule and respectively storing the corresponding frame state and the frame information into the frame state buffer and the frame information buffer;

The write time sequence control module is in communication connection with the buffer control submodule and is used for reading the video data processed by the buffer control submodule and uploading the processed video data to the DDR.

2. The video output control module according to claim 1, wherein the buffer control submodule includes a comprehensive control module and a frame loss correction module;

the comprehensive control module is respectively in communication connection with the data receiving buffer, the buffer read-write control module, the write time sequence control module and the frame loss correction module, and is used for controlling the writing and reading of data in the data receiving buffer, detecting the full state of the data receiving buffer, sending the frame state and frame information of each frame to the buffer read-write control module, enabling the write time sequence control module to read the processed video data, and calling the frame loss correction module when the full signal of the data receiving buffer is detected;

the frame loss correction module is used for calculating the written data quantity of the current frame in the data receiving buffer, judging whether the written data quantity reaches a preset data quantity threshold, and filling the tail of the current frame by utilizing the frame tail backup information of the last frame on the reading side of the data receiving buffer when the written data quantity reaches the preset data quantity threshold to obtain the complete current frame.

3. The video output control module according to claim 2, wherein when the current frame is YUV format video data, the integrated control module obtains resolution information of the current frame when a frame header of the current frame enters the data receiving buffer, the frame loss correction module includes:

a pixel calculation unit, configured to determine all pixel points of the current frame according to the resolution information;

a written pixel counting unit for counting the number of written pixel points of the current frame as the written data quantity;

a writing proportion calculating unit for calculating the ratio of the number of written pixel points to the number of all pixel points;

the patching condition judging unit is used for judging whether the pixel point number ratio is larger than or equal to a preset ratio threshold value or not, wherein the preset ratio threshold value is used as the preset data quantity threshold value;

and the patching unit is used for filling the tail part of the current frame by utilizing the frame tail backup information of the previous frame on the reading side of the data receiving buffer when the pixel point number ratio is greater than or equal to a preset ratio threshold value, so as to obtain the complete current frame.

4. The video output control module of claim 3, wherein the buffer control submodule further comprises a frame size estimation module communicatively coupled to the integrated control module; when the current frame is compressed video data, the comprehensive control module calls the frame size estimation module, wherein the frame size estimation module is used for estimating the number of compressed pixels of the current frame according to the actual number of pixels of the transmitted compressed video and sending the number of compressed pixels to the frame loss correction module; the frame loss correction module is configured to execute the write ratio calculation unit with the compressed pixel number as the total pixel number.

5. The video output control module of claim 4, wherein the frame size estimation module comprises:

the compressed video pixel statistics unit is used for counting the actual pixel number of a plurality of transmitted compressed videos in a first historical time period from the current moment;

and the compressed pixel number calculating unit is used for calculating the average value of the actual pixel number of each transmitted compressed video and taking the average value as the compressed pixel number.

6. The video output control module according to claim 2 or 5, wherein the buffer control submodule further comprises a write correction module, the write correction module is in communication connection with the integrated control module, the integrated control module further determines whether the current frame has written only a frame header in the data reception buffer when detecting a full signal of the data reception buffer, and invokes the write correction module when the current frame has written only a frame header; the write correction module includes:

a first rate detection unit configured to detect whether a read-side rate of the data reception buffer is equal to or greater than a write-side rate;

a temporary buffer unit, configured to buffer, when the read-out side rate is greater than or equal to the write-in side rate, data to be written into by the current frame in a preset internal register set;

And the data transmission unit is used for moving the data in the internal register group into the data receiving buffer according to the buffer sequence when the data receiving buffer is not full.

7. The video output control module of claim 6, wherein the write modification module further comprises:

and the first frame loss unit is used for feeding back the integrated control module to control the data receiving buffer to discard the current frame when the reading side rate is smaller than the writing side rate.

8. The video output control module of claim 6, wherein the first rate detection unit comprises:

a continuous rate detection unit, configured to detect a read-side continuous rate and a write-side continuous rate of the data receiving buffer in a second historical period from a current time;

a rate index calculation unit configured to calculate a read rate index and a write rate index based on the read-side continuous rate and the write-side continuous rate, respectively;

and a rate determination unit configured to determine whether the read rate index is equal to or greater than the write rate index by using the read rate index as the read-side rate and the write rate index as the write-side rate.

9. The video output control module according to claim 8, wherein the rate index calculation unit includes:

an average read rate calculation unit configured to calculate a readout side average rate of the readout side in the second history period based on the readout side continuous rate;

an average write rate calculation unit configured to calculate a write-side average rate of the write-side over the second history period based on the write-side continuous rate;

and a rate index defining unit configured to take the readout-side average rate as the readout rate index and the write-side average rate as the write-rate index.

10. The video output control module of claim 9, wherein the buffer control submodule further comprises an active complement module communicatively coupled to the integrated control module, the integrated control module invoking the active complement module when detecting an empty signal of the data receive buffer; the active complement module comprises:

a second rate detection unit configured to detect whether a read-side rate of the data reception buffer is greater than a write-side rate;

A written data amount analysis unit, configured to calculate a written data amount of a current frame in the data receiving buffer when the read-side rate is greater than the write-side rate, and determine whether the written data amount reaches a preset data amount threshold;

the active patching unit is used for filling the tail of the current frame by utilizing the frame tail backup information of the last frame on the read side of the data receiving buffer when the written data volume reaches a preset data volume threshold value to obtain a complete current frame;

and the residual data discarding unit is used for feeding back the comprehensive control module to control the data receiving buffer to discard the residual data when detecting that the residual data of the current frame reaches the writing side of the data receiving buffer.

11. The video output control module of claim 10, wherein the buffer control sub-module further comprises a capacity prediction module communicatively coupled to the integrated control module, the integrated control module invoking the capacity prediction module prior to writing a current frame to the data receiving buffer, the capacity prediction module comprising:

A remaining capacity acquisition unit configured to acquire a remaining capacity of the data reception buffer;

a writing judging unit for judging whether the current frame to be written can be completely written into the data receiving buffer according to the residual capacity;

and the feedback writing unit is used for feeding back the comprehensive control module to control the data receiving buffer to start receiving the current frame when the current frame is judged to be capable of being completely written into the data receiving buffer.

12. The video output control module according to claim 11, wherein the writing determination unit includes:

a third rate detection unit, configured to calculate a second read rate indicator and a second write rate indicator of the data receiving buffer in a third historical period of time from the current time, where the third historical period of time is greater than the second historical period of time;

a frame size obtaining unit for obtaining the complete data volume of the current frame;

a first time estimation unit, configured to calculate a ratio of the complete data amount to the second read rate indicator to obtain a read estimation time;

the second time estimation unit is used for subtracting the residual capacity from the complete data volume and calculating the ratio of the subtraction result to the second writing rate index to obtain writing estimation time;

A first determining unit configured to determine that the current frame can be completely written into the data receiving buffer when the writing estimated time is equal to or greater than the reading estimated time;

and the second judging unit is used for judging that the current frame cannot be completely written into the data receiving buffer when the writing estimated time is smaller than the reading estimated time.

13. The video output control module of claim 12, wherein the capacity estimation module further comprises:

and the second frame loss unit is used for feeding back the comprehensive control module to control the data receiving buffer to discard the current frame when the current frame is judged to be incapable of being completely written into the data receiving buffer.

14. The video output control module of claim 13, wherein the integrated control module comprises:

and the third frame loss unit is used for controlling the data receiving buffer to discard the current frame when the current frame is written with partial data except the frame header of the data receiving buffer and the written data quantity does not reach the preset data quantity threshold value.

15. The video output control module of claim 1, further comprising a write pointer rollback module in communication with the write timing control module and the frame status buffer, respectively, the write pointer rollback module configured to back up a write address of a current frame when the write timing control module writes a frame header of the current frame to the DDR, and to control a next frame to continue writing from the write address of the current frame when a status of the current frame indicates that the current frame is not completely written to the DDR.

16. The video output control method of the BMC chip is characterized by being applied to a buffer control submodule in a video output control module, and comprises the following steps of:

controlling a data receiving buffer to receive compressed video data or YUV format video data;

detecting a full state of the data receiving buffer;

when the data receiving buffer reaches a full state, repairing incomplete frames caused by the full state in the data receiving buffer, and identifying the frame state and frame information of each frame;

responding to a read request of a buffer read-write control module, and sending frame states and frame information of each frame to the buffer read-write control module so that the buffer read-write control module stores the corresponding frame states and frame information into a frame state buffer and a frame information buffer respectively;

and responding to the read request of the write timing control module, and sending the processed video data to the write timing control module so that the write timing control module can upload the processed video data to the DDR.

17. The method of claim 16, wherein patching an incomplete frame in the data receiving buffer caused by a full state comprises:

Calculating the written data quantity of the current frame in the data receiving buffer, and judging whether the written data quantity reaches a preset data quantity threshold value or not;

and when the written data quantity reaches a preset data quantity threshold value, filling the tail of the current frame by utilizing the tail backup information of the last frame on the read side of the data receiving buffer to obtain the complete current frame.

18. The method of claim 17, wherein when the current frame is YUV format video data, calculating the amount of written data of the current frame in the data receiving buffer, and determining whether the amount of written data reaches a preset data amount threshold, comprises:

when the frame head of the current frame enters the data receiving buffer, acquiring resolution information of the current frame;

determining all pixel points of the current frame through the resolution information;

counting the number of written pixel points of the current frame as the written data quantity;

calculating the ratio of the pixel points of the written pixel points to the pixel points of all the pixel points;

judging whether the pixel point number ratio is larger than or equal to a preset ratio threshold value, wherein the preset ratio threshold value is the preset data quantity threshold value;

And when the pixel point number ratio is greater than or equal to a preset ratio threshold, filling the tail of the current frame by using the tail backup information of the previous frame on the read-out side of the data receiving buffer to obtain the complete current frame.

19. The BMC device is characterized by comprising a DDR device and a BMC chip, wherein the BMC chip comprises a VGA module, a color space conversion module, a video compression module, a network module and the video output control module according to any one of claims 1-15, the VGA module is in communication connection with the color space conversion module, the color space conversion module is in communication connection with the video compression module, the video output control module is simultaneously in communication connection with the color space conversion module and the video compression module, the video output control module is in communication connection with the DDR device, the DDR device is in communication connection with the network module, and the VGA module is used for receiving original video data sent by a server.

20. The server is characterized by comprising a server memory, a server processor and a BMC device, wherein the server memory and the server processor are in communication connection with each other, and the BMC device and the server processor are in communication connection with each other.