CN116683906B - BG starting circuit and radio frequency chip - Google Patents
BG starting circuit and radio frequency chip Download PDFInfo
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- CN116683906B CN116683906B CN202310976220.7A CN202310976220A CN116683906B CN 116683906 B CN116683906 B CN 116683906B CN 202310976220 A CN202310976220 A CN 202310976220A CN 116683906 B CN116683906 B CN 116683906B
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- 239000003990 capacitor Substances 0.000 claims abstract description 51
- 238000001514 detection method Methods 0.000 claims abstract description 45
- 238000002347 injection Methods 0.000 claims abstract description 42
- 239000007924 injection Substances 0.000 claims abstract description 42
- 238000010586 diagram Methods 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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Abstract
The invention relates to the technical field of electronics, and discloses a BG starting circuit and a radio frequency chip, wherein the BG starting circuit comprises a signal input end, a starting circuit, a BG main body circuit and a signal output end, and the starting circuit comprises an inverter link, a bias branch, a capacitor charging branch, a starting detection branch and a current injection branch which are electrically connected in sequence; the signal input end is used for connecting an enabling signal of the whole circuit; the input end of the inverter link outputs a first reverse signal and a second reverse signal respectively; the output end of the bias branch circuit outputs bias voltage; the capacitor charging branch circuit outputs a charging signal; starting a detection branch to output a voltage detection signal; the input end of the current injection branch circuit converts the voltage detection signal into a current signal; the BG main body circuit receives the current signal and the second reverse signal respectively to realize the starting of the circuit. The BG starting circuit disclosed by the invention is simple in structure, low in power consumption and good in reliability.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a BG starting circuit and a radio frequency chip.
Background
At present, global voltage or current bias is often used in a chip, so that when the bias cannot work normally, the whole circuit system cannot work and breaks down, and the transient starting of the bias circuit is likely to fail. The start-up circuit is generated and after the start-up circuit is in effect, the start-up circuit needs to maintain 0 power consumption or very low power consumption as the bias set-up is completed.
In the related art, for a BG (band gap) circuit, a common starting manner of the BG circuit is to apply a forced pull-down signal to an operational amplifier output terminal thereof, so as to force a BG loop to be established.
However, this method can cause an overshoot to occur when the BG is powered up, and in general, the BG circuit is used for providing the bias voltage of LDO (Low Dropout Regulator), where the LDO is called a low dropout linear regulator, which belongs to a linear power supply, when the BG circuit is in overshoot, if the LDO is turned on at the same time, the output of the LDO will also have an overshoot, which may cause unnecessary influence to the load circuit carried by the LDO, even burn the load circuit, and have poor reliability.
Disclosure of Invention
The embodiment of the invention aims to provide a BG starting circuit, which is used for solving the problem of poor reliability of the BG starting circuit in the related art.
In order to solve the technical problem, in a first aspect, an embodiment of the present invention provides a BG start circuit, where the BG start circuit includes a signal input end, a start circuit, a BG main body circuit, and a signal output end, and the start circuit includes an inverter link, a bias branch, a capacitor charging branch, a start detection branch, and a current injection branch that are electrically connected in sequence;
the signal input end is used for connecting an enabling signal of the whole circuit;
the input end of the inverter link is used for receiving the enabling signal, and the output end of the inverter link sequentially outputs a first reverse signal and a second reverse signal respectively;
the input end of the bias branch circuit receives the first reverse signal, and the output end of the bias branch circuit outputs bias voltage;
the input end of the capacitor charging branch circuit receives the bias voltage, and the output end of the capacitor charging branch circuit outputs a charging signal;
the input end of the starting detection branch circuit receives the charging signal and detects the charging signal, and the output end of the starting detection branch circuit outputs a voltage detection signal;
the current injection branch is used for receiving the voltage detection signal, converting the voltage detection signal into a current signal and outputting the current signal to the first input end of the BG main body circuit;
the first input end and the second input end of the BG main body circuit respectively receive the current signal and the second reverse signal, and the output end of the BG main body circuit is connected with the signal output end;
the signal output end is used for outputting the current signal to realize circuit starting.
Preferably, the bias branch circuit comprises a first MOS tube, a second MOS tube and a first resistor; the source electrode of the first MOS tube is connected to a power supply voltage, the grid electrode of the first MOS tube is used as a first output end of the bias branch and is connected to the input end of the capacitor charging branch, the drain electrode of the first MOS tube is used as a second output end of the bias branch and is connected to the input end of the current injection branch, and the grid electrode of the first MOS tube is connected with the drain electrode of the first MOS tube; the source electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, the grid electrode of the second MOS tube is used as the input end of the bias branch, the drain electrode of the second MOS tube is connected with the first end of the first resistor, and the second end of the first resistor is grounded.
Preferably, the capacitor charging branch circuit comprises a third MOS tube, a fourth MOS tube and a first capacitor, wherein a source electrode of the third MOS tube is connected to a power supply voltage, a grid electrode of the third MOS tube is used as an input end of the capacitor charging branch circuit, a drain electrode of the third MOS tube is used as an output end of the capacitor charging branch circuit, a drain electrode of the fourth MOS tube is respectively connected with a drain electrode of the third MOS tube and a first end of the first capacitor, a grid electrode of the fourth MOS tube is used for receiving the first reverse signal, and a source electrode of the fourth MOS tube and a second end of the first capacitor are respectively grounded.
Preferably, the starting detection branch circuit includes a fifth MOS tube, a source electrode of the fifth MOS tube is connected to a power supply voltage, a gate electrode of the fifth MOS tube is connected to an output voltage of the operational amplifier, and a drain electrode of the fifth MOS tube is used as an input end of the starting detection branch circuit and an output end of the starting detection branch circuit.
Preferably, the current injection branch circuit comprises a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor, wherein a source electrode of the sixth MOS transistor is connected to a power supply voltage, a gate electrode of the sixth MOS transistor is used as a first input end of the current injection branch circuit to be connected to a second output end of the bias branch circuit, and a drain electrode of the sixth MOS transistor is connected to a source electrode of the seventh MOS transistor; the grid electrode of the seventh MOS tube is used as the second input end of the current injection branch and is connected to the output end of the starting detection branch, and the drain electrode of the seventh MOS tube is used as the output end of the current injection branch and is connected with the drain electrode of the eighth MOS tube; and the grid electrode of the eighth MOS tube is connected with the first reverse signal, and the source electrode of the eighth MOS tube is grounded.
Preferably, the BG main circuit includes a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, an operational amplifier, a first triode, and a second triode;
the source electrode of the ninth MOS tube and the source electrode of the tenth MOS tube are respectively connected with a power supply voltage, and the grid electrode of the ninth MOS tube is used as a second input end of the BG main body circuit and is used for receiving the second reverse signal; the drain electrode of the ninth MOS tube is connected with the grid electrode of the tenth MOS tube and is commonly connected to the output end of the operational amplifier; the first end of the second resistor is connected with the first end of the fourth resistor, the drain electrode of the tenth MOS tube and the drain electrode of the eleventh MOS tube respectively; the second end of the second resistor is connected with the first end of the third resistor, the second end of the third resistor is respectively connected with the negative input end of the operational amplifier and the collector electrode of the first triode, and the emitter electrode of the first triode and the base electrode of the first triode are respectively grounded;
the second end of the fourth resistor is connected with the first end of the fifth resistor, and the second end of the fifth resistor is respectively connected with the positive input end of the operational amplifier and the first end of the sixth resistor; the second end of the sixth resistor is connected with the collector electrode of the second triode, and the emitter electrode of the second triode and the base electrode of the second triode are respectively grounded;
the grid electrode of the eleventh MOS tube is connected with the output end of the inverter branch circuit and used for receiving the first reverse signal, and the source electrode of the eleventh MOS tube is grounded;
the second end of the second resistor is used as a first input end of the BG main body circuit and is connected with the output end of the circuit injection branch.
In a second aspect, an embodiment of the present invention provides a radio frequency chip, where the radio frequency chip includes a BG start circuit as described above.
Compared with the related art, the BG starting circuit is used for being connected with an enabling signal of the whole circuit through the signal input end; the input end of the inverter link is used for receiving the enabling signal, and the corresponding first reverse signal and second reverse signal are output by the respective output ends of the inverter link; the input end of the bias branch receives the first reverse signal for processing, and the output end of the bias branch outputs bias voltage; the input end of the capacitor charging branch circuit receives the bias voltage, and the output end of the capacitor charging branch circuit outputs a charging signal; the input end of the starting detection branch receives the charging signal and detects the charging signal, and the output end of the starting detection branch outputs a voltage detection signal; the input end of the current injection branch is used for receiving a voltage detection signal and converting the voltage detection signal into a current signal; outputting a current signal to a first input end of the BG main body circuit through an output end of the current injection branch; the first input end and the second input end of the BG main body circuit respectively receive a current signal and a second reverse signal, and the output end of the BG main body circuit is connected with the signal output end; the signal output end is used for outputting a current signal to realize the starting of the circuit; the capacitor charging branch circuit is connected with the starting detection branch circuit to realize the detection of the starting circuit, and the corresponding current signal is output to the BG main body circuit through the circuit injection branch circuit to realize the BG starting function. The BG starting circuit is simple in structure, low in circuit cost and power consumption, capable of avoiding overshooting of the BG during power-on and high in reliability.
Drawings
For a clearer description of the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
fig. 1 is a circuit diagram of a BG start circuit according to an embodiment of the present invention;
fig. 2 is a timing waveform diagram of a BG start circuit according to an embodiment of the present invention.
In the figure, 100 parts of a BG starting circuit, 1 part of a signal input end, 2 parts of a starting circuit, 21 parts of an inverter link, 22 parts of a bias branch, 23 parts of a capacitor charging branch, 24 parts of a starting detection branch, 25 parts of a current injection branch, 3 parts of a BG main body circuit, and 4 parts of a signal output end.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1-2, an embodiment of the present invention provides a BG start circuit 100, where the BG start circuit 100 includes a signal input end 1, a start circuit 2, a BG main body circuit 3, and a signal output end 4, and the start circuit 2 includes an inverter link 21, a bias branch 22, a capacitor charging branch 23, a start detection branch 24, and a current injection branch 25 that are electrically connected in sequence. Alternatively, the electrical connection may be a circuit wire connection, an electrical signal connection, etc., and the specific connection manner is not limited to the above two, but other manners may be used according to actual requirements, which will not be described herein.
The signal input terminal 1 is used for connecting an enable signal EN of the whole circuit;
the input end of the inverter link 21 is configured to receive the enable signal EN, and the output end of the inverter link 21 sequentially outputs a corresponding first inverted signal ENB and a corresponding second inverted signal ENA respectively; the inverter chain 21 is a common inverter.
The input end of the bias branch 22 receives the first reverse signal ENB, and the output end of the bias branch 22 outputs a bias voltage;
the input end of the capacitor charging branch 23 receives the bias voltage, and the output end of the capacitor charging branch 23 outputs a charging signal;
the input end of the start detection branch 24 receives the charging signal and detects the charging signal, and the output end of the start detection branch 24 outputs a voltage detection signal;
the input end of the current injection branch 25 is used for receiving the voltage detection signal and converting the voltage detection signal into a current signal; outputting the current signal to a first input terminal of the BG body circuit 3 through an output terminal of the current injection branch 25;
the first input end and the second input end of the BG main body circuit 3 respectively receive the current signal and the second reverse signal ENA, and the output end of the BG main body circuit 3 is connected with the signal output end 4;
the signal output terminal 4 is used for outputting the current signal to realize circuit starting.
Specifically, the enable signal EN is input to the inverter link 21 through the signal input terminal 1, the first reverse signal ENB and the second reverse signal ENA are respectively output to the bias branch 22 and the BG main circuit 3 through the inverter link 21, the bias branch 22 is respectively connected to the capacitor charging branch 23 and the current injection branch 25 for respectively providing bias voltages, and the current injection branch 25 is connected to the start detection branch 24 for outputting the current signal to the BG main circuit 3, so as to realize the start function of the BG circuit. The BG starting circuit 100 is simple in structure, low in circuit cost and power consumption, capable of avoiding overshooting of the BG during power-on and high in reliability.
In this embodiment, the BIAS branch 22 (BIAS branch) includes a first MOS transistor M1, a second MOS transistor M2, and a first resistor R1; the source electrode of the first MOS transistor M1 is connected to the power supply voltage VDD, the gate electrode of the first MOS transistor M1 is connected to the input end of the capacitor charging branch 23 as the first output end of the bias branch 22, the drain electrode of the first MOS transistor M1 is connected to the input end of the current injection branch 25 as the second output end of the bias branch 22, and the gate electrode of the first MOS transistor M1 is connected to the drain electrode of the first MOS transistor M1; the source electrode of the second MOS tube M2 is connected with the drain electrode of the first MOS tube M1, the grid electrode of the second MOS tube M2 is used as the input end of the bias branch 22, the drain electrode of the second MOS tube M2 is connected with the first end of the first resistor R1, and the second end of the first resistor R1 is grounded. The bias branch 22 is turned on and off by controlling the gate of the first MOS transistor M1, when the first inversion signal ENB is 1, the first MOS transistor M1 is turned off, the bias branch 22 is turned off, and when the first inversion signal ENB is 0, the first MOS transistor M1 is in a deep linear region, approximately short-circuited, and the bias branch 22 is turned on. The BIAS branch circuit provides voltage BIAS for the capacitor charging branch circuit 23 and the current injection branch circuit 25 respectively, so that the capacitor charging branch circuit 23 and the current injection branch circuit 25 mirror the current of the BIAS branch circuit, and the second MOS transistor M2 is an enabling transistor, and 0 is effective.
The first inverted signal ENB is a high level, and the first inverted signal ENB is a low level, when it is a 1.
Alternatively, the bias branch 22 is not a fixed architecture, so long as a voltage bias to subsequent circuitry can be generated.
In this embodiment, the capacitor charging branch 23 includes a third MOS transistor M3, a fourth MOS transistor M4, and a first capacitor C1, where a source of the third MOS transistor M3 is connected to a power supply voltage VDD, a gate of the third MOS transistor M3 is used as an input end of the capacitor charging branch 23, a drain of the third MOS transistor M3 is used as an output end of the capacitor charging branch 23, a drain of the fourth MOS transistor M4 is respectively connected to a drain of the third MOS transistor M3 and a first end of the first capacitor C1, and a gate of the fourth MOS transistor M4 is used to connect to the first inversion signal ENB, and a source of the fourth MOS transistor M4 and a second end of the first capacitor C1 are respectively grounded.
In the capacitor charging branch 23, when the first reverse signal ENB is 1, the third MOS transistor M3 has no mirror current, the fourth MOS transistor M4 is turned on, the voltage at point a is pulled to 0 by the fourth MOS transistor M4, and when the first reverse signal ENB is changed from 1 to 0, the fourth MOS transistor M4 charges the first capacitor C1 with a fixed current, the voltage at point a starts to rise from 0 and finally rises to the power supply voltage VDD, and the input terminal of the current injection branch 25 is turned off.
Optionally, the rising speed of the voltage at the point a of the capacitor charging branch 23 depends on the magnitude of the first capacitor C1 and the magnitude of the current of the third MOS transistor M3, and the currents of the first capacitor C1 and the third MOS transistor M3 can be selected as appropriate according to the requirement.
In this embodiment, the start-up detection branch 24 includes a fifth MOS transistor M5, a source of the fifth MOS transistor M5 is connected to the power supply voltage VDD, a gate of the fifth MOS transistor M5 is connected to the operational amplifier output voltage VG, and a drain of the fifth MOS transistor M5 is used as an input end of the start-up detection branch 24 and an output end of the start-up detection branch 24.
In this embodiment, the current injection branch 25 includes a sixth MOS transistor M6, a seventh MOS transistor M7, and an eighth MOS transistor M8, where a source of the sixth MOS transistor M6 is connected to the power supply voltage VDD, a gate of the sixth MOS transistor M6 is used as a first input end of the current injection branch 25 to be connected to the second output end of the bias branch 22, and a drain of the sixth MOS transistor M6 is connected to a source of the seventh MOS transistor M7; the gate of the seventh MOS transistor M7 is connected to the output end of the start-up detection branch 24 as the second input end of the current injection branch 25, and the drain of the seventh MOS transistor M7 is respectively connected to the drain of the eighth MOS transistor M8 as the output end of the current injection branch 25; the gate of the eighth MOS transistor M8 is configured to be connected to the first reverse signal ENB, and the source of the eighth MOS transistor M8 is grounded.
When the first inversion signal ENB is changed from 1 to 0, the fourth MOS transistor M4 charges the first capacitor C1 with a fixed current, and the voltage at the point a starts to rise from 0 and finally rises to the power supply voltage VDD, so that the seventh MOS transistor M7 of the current injection branch 25 is turned off.
The drain node of the seventh MOS transistor M7 is connected to the point C of the BG main circuit 3 and the drain of the eighth MOS transistor M8, when the first inversion signal ENB is 1, the eighth MOS transistor M8 is turned on, the voltage at the point C is pulled to 0, when the first inversion signal ENB is changed from 1 to 0, the bias branch 22 is turned on, the current of the sixth MOS transistor M6 is injected into the point C through the seventh MOS transistor M7, so that the BG loop starts to be established, when the BG loop is established, the voltage at the point a is the power voltage VDD, the seventh MOS transistor M7 is turned off, and the current injection branch 25 has no current.
Optionally, the enabling tube for controlling the on/off of the eighth MOS tube M8 may be an N tube, and the gate control signal may be changed to EN.
In this embodiment, the BG main circuit 3 includes a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, an operational amplifier, a first triode Q1, and a second triode Q2;
the source electrode of the ninth MOS transistor M9 and the source electrode of the tenth MOS transistor M10 are respectively connected to the power supply voltage VDD, and the gate electrode of the ninth MOS transistor M9 is used as the second input end of the BG main circuit 3, and is configured to receive the second reverse signal ENA; the drain electrode of the ninth MOS tube M9 is connected with the grid electrode of the tenth MOS tube M10 and is commonly connected to the output end of the operational amplifier; the first end of the second resistor R2 is connected with the first end of the fourth resistor R4, the drain electrode of the tenth MOS transistor M10, and the drain electrode of the eleventh MOS transistor M11, respectively; the second end of the second resistor R2 is connected with the first end of the third resistor R3, the second end of the third resistor R3 is respectively connected with the negative input end of the operational amplifier and the collector electrode of the first triode Q1, and the emitter electrode of the first triode Q1 and the base electrode of the first triode Q1 are respectively grounded;
the second end of the fourth resistor R4 is connected with the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is respectively connected with the positive input end of the operational amplifier and the first end of the sixth resistor R6; the second end of the sixth resistor R6 is connected with the collector electrode of the second triode Q2, and the emitter electrode of the second triode Q2 and the base electrode of the second triode Q2 are respectively grounded;
the gate of the eleventh MOS transistor M11 is configured to receive the first reverse signal ENB, and the source of the eleventh MOS transistor M11 is grounded;
the second end of the second resistor R2 is used as a first input end of the BG body circuit 3 and is connected with the output end of the circuit injection branch.
In the BG main circuit 3, the sum of the second resistor R2 and the third resistor R3 is a fixed value, and the point C may be selected at the node between the second resistor R2 and the third resistor R3 as appropriate, that is, r2+r3 is a fixed value, and the ratio of the second resistor R2 to the third resistor R3 is variable. The point C is positioned in a positive feedback loop of the BG circuit, and after current is injected into the point C, the negative feedback loop starts to be established, so that the BG is finally stable to be established.
Specifically, the input terminal of the inverter link 21 is connected to the enable signal EN,1, and outputs the first inverted signal ENB and the second inverted signal ENA for providing the enable signal to the subsequent circuit.
The BIAS branch provides voltage BIAS for the capacitor charging branch 23 and the current injection branch 25, so that the fifth MOS transistor M5 and the sixth MOS transistor M6 mirror the current of the BIAS branch, and the second MOS transistor M2 is an enable transistor, and 0 is effective.
The point of the capacitor charging branch 23A is connected to the drain of the fifth MOS transistor M5 of the start-up detecting branch 24 and the gate of the seventh MOS transistor M7 of the current injection branch 25, and the gate of the fourth MOS transistor M4 is an enable end, and 0 is valid.
In the start detection branch 24, a gate of the fifth MOS transistor M5 is connected to the operational amplifier output voltage VG of the gate of the tenth MOS transistor M10, and a drain of the fifth MOS transistor M5 is connected to the gate of the seventh MOS transistor M7 and the first capacitor C1.
In the current injection branch 25, a gate of the sixth MOS transistor M6 is connected to the BIAS voltage generated by the BIAS branch, a gate of the M5 is connected to the point a of the first capacitor C1, and a drain of the seventh MOS transistor M7 is connected to the point C of the junction between the second resistor R2 and the third resistor R3 in the BG main circuit 3. The eighth MOS transistor M8 is an enable transistor, 1 is valid.
The operational amplifier output voltage VG of the gate of the fifth MOS transistor M5 of the start-up detection branch 24 depends on the voltage of the BG main circuit 3, i.e. the output voltage of the operational amplifier AMP. When EN is 0, the ninth MOS transistor M9 is enabled to be turned on, and the operational amplifier output voltage VG is the power voltage VDD, so the fifth MOS transistor M5 is turned off. When EN is changed from 0 to 1, BG starts to be built, the output voltage VG of the operational amplifier starts to decline from the power supply voltage VDD, and when the building is nearly finished, the output voltage VG of the operational amplifier enables the fifth MOS tube M5 to be started, and the point A is quickly raised to the power supply voltage VDD.
In this embodiment, the first to eleventh MOS transistors M1 to M11 may be PMOS transistors or NMOS transistors, and are specifically used according to actual needs.
In this embodiment, when the power supply voltage VDD is already powered on, but EN is 0, the second inverted signal ENA is 0, the first inverted signal ENB is the power supply voltage VDD, the first MOS transistor M1 is turned off, the fifth MOS transistor M5 is turned off, the fourth MOS transistor M4 is turned on, the eighth MOS transistor M8 is turned on, the tenth MOS transistor M10 is turned off, the ninth MOS transistor M9 is turned on, the eleventh MOS transistor M11 is turned on, the bias branch 22 is turned off, the point a voltage is 0, the point c voltage is 0, the operational amplifier output voltage VG is VDD, and the reference voltage VREF is 0. When EN is changed from 0 to VDD, the bias branch 22 is turned on, the current of the mirror image first MOS transistor M1 of the third MOS transistor M3 charges the first capacitor C1 with a fixed current, the voltage at the point a starts to rise from 0, and the seventh MOS transistor M7 is in the on state at this time, so that the current of the sixth MOS transistor M6 flows through the seventh MOS transistor M7 and then is injected into the point C, forcing the BG circuit to start rapidly. And the voltage at the point A continuously rises, when the starting of the BG circuit is completed, the output voltage VG of the operational amplifier is reduced to a fixed point from VDD, so that the fifth MOS tube M5 is conducted, the voltage at the point A is rapidly pulled up to VDD, the seventh MOS tube M7 is turned off, the current injection to the point C is stopped, and the starting of the BG circuit is completed. At this time, except for the bias branch 22, there is a fixed current, and no current is supplied to the other branches.
In this embodiment, according to the timing chart of the power-up of the BG circuit, when EN is changed from 0 to 1, the first capacitor C1 is charged by the fixed current flowing out of the third MOS transistor M3, the voltage at point a is linearly increased, the current is injected at point C, BG starts to be established, the voltage at point C is increased, the reference voltage VREF is also increased at the same time, and the output voltage VG of the operational amplifier starts to be decreased. After the preset time Ts, the establishment of the BG is completed, the output voltage VG of the operational amplifier turns on the fifth MOS tube M5, after the preset time Tp, the voltage at the point A is rapidly pulled up to the power supply voltage VDD, the seventh MOS tube M7 is closed to stop injecting current to the point C, and the starting of the BG is completed.
Example two
The embodiment of the invention provides a radio frequency chip, which comprises the BG start circuit 100 in the first embodiment. In the radio frequency chip, the BG starting circuit 100 has the advantages of simple structure, lower circuit cost, low power consumption, capability of avoiding overshooting of the BG during power-on and high reliability.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (6)
1. The BG starting circuit comprises a signal input end, a starting circuit, a BG main body circuit and a signal output end, and is characterized by comprising an inverter link, a bias branch, a capacitor charging branch, a starting detection branch and a current injection branch which are electrically connected in sequence;
the signal input end is used for connecting an enabling signal of the whole circuit;
the input end of the inverter link is used for receiving the enabling signal, and the output end of the inverter link sequentially outputs a first reverse signal and a second reverse signal respectively;
the input end of the bias branch circuit receives the first reverse signal, and the output end of the bias branch circuit outputs bias voltage;
the input end of the capacitor charging branch circuit receives the bias voltage, and the output end of the capacitor charging branch circuit outputs a charging signal;
the input end of the starting detection branch circuit receives the charging signal and detects the charging signal, and the output end of the starting detection branch circuit outputs a voltage detection signal;
the current injection branch is used for receiving the voltage detection signal, converting the voltage detection signal into a current signal and outputting the current signal to the first input end of the BG main body circuit;
the first input end and the second input end of the BG main body circuit respectively receive the current signal and the second reverse signal, and the output end of the BG main body circuit is connected with the signal output end;
the signal output end is used for outputting the current signal to realize circuit starting;
the BG main circuit comprises a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, an operational amplifier, a first triode and a second triode;
the source electrode of the ninth MOS tube and the source electrode of the tenth MOS tube are respectively connected with a power supply voltage, and the grid electrode of the ninth MOS tube is used as a second input end of the BG main body circuit and is used for receiving the second reverse signal; the drain electrode of the ninth MOS tube is connected with the grid electrode of the tenth MOS tube and is commonly connected to the output end of the operational amplifier; the first end of the second resistor is connected with the first end of the fourth resistor, the drain electrode of the tenth MOS tube and the drain electrode of the eleventh MOS tube respectively; the second end of the second resistor is connected with the first end of the third resistor, the second end of the third resistor is respectively connected with the negative input end of the operational amplifier and the collector electrode of the first triode, and the emitter electrode of the first triode and the base electrode of the first triode are respectively grounded;
the second end of the fourth resistor is connected with the first end of the fifth resistor, and the second end of the fifth resistor is respectively connected with the positive input end of the operational amplifier and the first end of the sixth resistor; the second end of the sixth resistor is connected with the collector electrode of the second triode, and the emitter electrode of the second triode and the base electrode of the second triode are respectively grounded;
the grid electrode of the eleventh MOS tube is connected with the output end of the inverter link and is used for receiving the first reverse signal, and the source electrode of the eleventh MOS tube is grounded;
the second end of the second resistor is used as a first input end of the BG main body circuit and is connected with the output end of the current injection branch.
2. The BG start-up circuit of claim 1, wherein the bias branch comprises a first MOS transistor, a second MOS transistor, and a first resistor; the source electrode of the first MOS tube is connected to a power supply voltage, the grid electrode of the first MOS tube is used as a first output end of the bias branch and is connected to the input end of the capacitor charging branch, the drain electrode of the first MOS tube is used as a second output end of the bias branch and is connected to the input end of the current injection branch, and the grid electrode of the first MOS tube is connected with the drain electrode of the first MOS tube; the source electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, the grid electrode of the second MOS tube is used as the input end of the bias branch, the drain electrode of the second MOS tube is connected with the first end of the first resistor, and the second end of the first resistor is grounded.
3. The BG starting circuit of claim 1, wherein the capacitor charging branch comprises a third MOS transistor, a fourth MOS transistor, and a first capacitor, a source of the third MOS transistor is connected to a power supply voltage, a gate of the third MOS transistor is used as an input end of the capacitor charging branch, a drain of the third MOS transistor is used as an output end of the capacitor charging branch, a drain of the fourth MOS transistor is respectively connected with a drain of the third MOS transistor and a first end of the first capacitor, a gate of the fourth MOS transistor is used for receiving the first reverse signal, and a source of the fourth MOS transistor and a second end of the first capacitor are respectively grounded.
4. The BG starting circuit of claim 1, wherein the starting detection branch comprises a fifth MOS transistor, a source of the fifth MOS transistor is connected to a power supply voltage, a gate of the fifth MOS transistor is connected to an operational amplifier output voltage, and a drain of the fifth MOS transistor is used as an input end of the starting detection branch and an output end of the starting detection branch.
5. The BG starting circuit of claim 2, wherein the current injection branch comprises a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor, wherein a source of the sixth MOS transistor is connected to a power supply voltage, a gate of the sixth MOS transistor is used as a first input end of the current injection branch to be connected to a second output end of the bias branch, and a drain of the sixth MOS transistor is connected to a source of the seventh MOS transistor; the grid electrode of the seventh MOS tube is used as the second input end of the current injection branch and is connected to the output end of the starting detection branch, and the drain electrode of the seventh MOS tube is used as the output end of the current injection branch and is connected with the drain electrode of the eighth MOS tube; and the grid electrode of the eighth MOS tube is connected with the first reverse signal, and the source electrode of the eighth MOS tube is grounded.
6. A radio frequency chip comprising a BG start circuit as claimed in any one of claims 1-5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310976220.7A CN116683906B (en) | 2023-08-04 | 2023-08-04 | BG starting circuit and radio frequency chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310976220.7A CN116683906B (en) | 2023-08-04 | 2023-08-04 | BG starting circuit and radio frequency chip |
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| CN116683906B true CN116683906B (en) | 2024-01-26 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667827A (en) * | 2009-08-04 | 2010-03-10 | 上海贝岭股份有限公司 | Auxiliary starting circuit of audio frequency power amplifier |
| CN110297514A (en) * | 2018-03-22 | 2019-10-01 | 华邦电子股份有限公司 | Electric power starting resetting circuit |
| US11086342B1 (en) * | 2020-09-14 | 2021-08-10 | Qualcomm Incorporated | Low power high speed maximum input supply selector |
| CN115756065A (en) * | 2022-12-08 | 2023-03-07 | 上海艾为电子技术股份有限公司 | Band-gap reference circuit, chip, band-gap reference voltage source and electronic equipment |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ITMI20022314A1 (en) * | 2002-10-31 | 2004-05-01 | Simicroelectronics S R L | DETECTION CIRCUIT OF A LOGICAL TRANSACTION WITH |
| US10622979B2 (en) * | 2018-08-20 | 2020-04-14 | Texas Instruments Incorporated | Delay cell |
| CN114623944A (en) * | 2022-03-22 | 2022-06-14 | 同济大学 | CMOS temperature sensor |
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- 2023-08-04 CN CN202310976220.7A patent/CN116683906B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667827A (en) * | 2009-08-04 | 2010-03-10 | 上海贝岭股份有限公司 | Auxiliary starting circuit of audio frequency power amplifier |
| CN110297514A (en) * | 2018-03-22 | 2019-10-01 | 华邦电子股份有限公司 | Electric power starting resetting circuit |
| US11086342B1 (en) * | 2020-09-14 | 2021-08-10 | Qualcomm Incorporated | Low power high speed maximum input supply selector |
| CN115756065A (en) * | 2022-12-08 | 2023-03-07 | 上海艾为电子技术股份有限公司 | Band-gap reference circuit, chip, band-gap reference voltage source and electronic equipment |
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