CN116682744A - Fan-out chip packaging method and structure - Google Patents

Fan-out chip packaging method and structure Download PDF

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Publication number
CN116682744A
CN116682744A CN202310653029.9A CN202310653029A CN116682744A CN 116682744 A CN116682744 A CN 116682744A CN 202310653029 A CN202310653029 A CN 202310653029A CN 116682744 A CN116682744 A CN 116682744A
Authority
CN
China
Prior art keywords
chip
substrate
adhesive
reinforcing substrate
reinforcing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310653029.9A
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Chinese (zh)
Inventor
田学春
王奎
张庆松
谢鸿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tongfu Microelectronics Co Ltd
Original Assignee
Tongfu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tongfu Microelectronics Co Ltd filed Critical Tongfu Microelectronics Co Ltd
Priority to CN202310653029.9A priority Critical patent/CN116682744A/en
Publication of CN116682744A publication Critical patent/CN116682744A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process

Abstract

The embodiment of the disclosure provides a fan-out chip packaging method and a structure, wherein the method comprises the following steps: providing a base plate, a reinforced substrate and a chip; the surface of the substrate is provided with a bonding pad, and the first surface of the chip is provided with a solder ball; adhering the reinforcing substrate to a second surface of the chip opposite to the first surface through adhesive; carrying out hot-press curing on the adhesive between the reinforcing substrate and the chip; carrying out reflow soldering on the solder balls of the chip and the bonding pads of the substrate to obtain an intermediate chip package; and stripping the reinforced substrate from the chip of the middle chip package body to obtain the target chip package body. According to the embodiment of the disclosure, the reinforcing substrate is adhered to the second surface of the chip, the reinforcing substrate supports and fixes the chip, the warping of the chip is changed, the chip is guaranteed to be unable to deform when the chip and the substrate are subjected to reflow soldering, the chip and the substrate are attached to each other, and the welding ball of the chip and the welding pad of the substrate are guaranteed to be well welded.

Description

Fan-out chip packaging method and structure
Technical Field
The embodiment of the disclosure belongs to the technical field of semiconductor chip packaging, and particularly relates to a fan-out chip packaging method and structure.
Background
With the development of advanced packaging technology, fan-out (Fan-out) chips have become the mainstream of packaging in recent years.
However, due to the stress collision of the resin material and the Silicon (SI) chip, fan-out is caused
The integral warping of the chip is increased, and the mounting difficulty is greatly increased. And the Fan-out chip can deform in the reflow process, the deformation direction and deformation amount are uncontrollable, and poor welding can be caused.
Disclosure of Invention
The embodiment of the disclosure aims to at least solve one of the technical problems in the prior art and provides a fan-out chip packaging method and structure.
One aspect of an embodiment of the present disclosure provides a fan-out chip packaging method. By a means of
The method comprises the following steps:
providing a base plate, a reinforced substrate and a chip; the surface of the substrate is provided with a bonding pad, and the first surface of the chip is provided with a solder ball;
adhering the reinforcing substrate to a second surface of the chip opposite to the first surface through adhesive;
carrying out hot-press curing on the adhesive between the reinforcing substrate and the chip;
carrying out reflow soldering on the solder balls of the chip and the bonding pads of the substrate to obtain an intermediate chip package;
and stripping the reinforced substrate from the chip of the middle chip package body to obtain the target chip package body.
Optionally, the attaching the reinforcing substrate on a second surface of the chip opposite to the first surface through adhesive glue includes:
placing the first surface of the chip on the surface of an operation table;
dispensing is carried out on the second surface of the chip, and the reinforcing substrate is adhered to the second surface of the chip.
Optionally, before the first surface of the chip is placed on the surface of the console, the method further includes:
and a high-temperature adhesive tape is arranged on the surface of the operating platform.
Optionally, the thermocompression curing of the adhesive between the reinforcing substrate and the chip includes:
placing the first surface of the chip on the surface of a heating table;
and placing a pressing piece in the central area of the reinforcing substrate, which is away from the chip, so as to carry out hot press curing on the adhesive.
Optionally, before the first surface of the chip is placed on the surface of the heating stage, the method further comprises:
and a high-temperature adhesive tape is arranged on the surface of the heating table.
Optionally, the peeling the reinforcing substrate from the chip of the intermediate chip package includes:
soaking the middle chip package body in an organic solvent and heating for a preset time;
after the bonding glue between the reinforcing substrate and the chip is softened, taking out the middle chip packaging body;
and stripping the reinforced substrate from the chip.
Optionally, the organic solvent is acetone.
Optionally, the reinforcing substrate is the same size as the chip.
Optionally, the reinforcing substrate is a silicon wafer or a metal sheet.
Another aspect of the embodiments of the present disclosure provides a fan-out chip package structure, obtained by using the above-described packaging method.
In the chip packaging method of the embodiment of the disclosure, the reinforcing substrate is adhered to the second surface of the chip through adhesive, the chip is supported and fixed, the warping of the chip is changed, and when the chip and the substrate are subjected to reflow soldering, the chip is ensured not to deform, so that the chip is attached to the substrate, and the welding ball of the chip and the welding pad of the substrate are ensured to be well soldered. The chip packaging method is simple, high in feasibility, low in cost, convenient to operate and capable of improving the product yield.
Drawings
FIG. 1 is a schematic diagram of a fan-out package process in the prior art;
FIG. 2 is a flow diagram of a fan-out chip packaging method according to an embodiment of the present disclosure;
fig. 3 to 8 are process diagrams of a fan-out chip packaging method according to an embodiment of the disclosure.
In the figure:
100. a chip; 110. a first surface; 120. solder balls; 130. a second surface;
200. reinforcing the substrate; 300. adhesive glue; 400. a pressurizing member; 500. a substrate; 510. a bonding pad; 600. an operation table; 700 heating table; 800. high temperature adhesive tape.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and detailed description.
The inventor of the present disclosure found that in the existing fan-out chip package, since the thermal expansion coefficients of the solder paste of the resin material and the silicon chip are different, there is a stress conflict, so that the chip can deform in the reflow soldering process, the deformation direction and deformation amount are uncontrollable, and poor soldering is caused.
Specifically, referring to fig. 1, fig. 1 is a schematic diagram of a fan-out type packaging process in the prior art. In the Flip Chip (FC) process of the Chip 100 and the substrate 500, the solder balls 120 on the first surface 110 of the Chip 100 and the pads 510 on the surface of the substrate 500 need to be soldered by reflow, and during the reflow, the solder flux and the Chip 100 have different coefficients of thermal expansion, which causes the central area of the Chip 100 to warp in a direction away from the substrate 500, which cannot ensure that the solder flux solder the pads of the substrate 500 to the solder balls on the warped portion, which easily causes poor soldering between the Chip 100 and the substrate 500 after reflow, and cannot ensure the product quality.
Based on this, the disclosure provides a fan-out chip packaging method, which is to paste a reinforcing substrate on a second surface of a chip, change the warpage of the chip after thermocompression curing, and prevent the chip from deforming during reflow soldering of the chip and a substrate, so that the chip is attached to the substrate, and the connection of soldering flux is ensured, so that the solder balls of the chip are well connected with the bonding pads of the substrate.
Referring to fig. 2, fig. 2 is a flow chart illustrating a fan-out chip packaging method according to an embodiment of the disclosure. The embodiment of the disclosure relates to a fan-out chip packaging method, the method S100 includes:
step S110, providing a base plate, a reinforced substrate and a chip; the surface of the substrate is provided with a bonding pad, and the first surface of the chip is provided with a solder ball.
Specifically, referring to fig. 3 and 7, fig. 3 and 7 are schematic structural diagrams of a chip with a reinforcing substrate attached thereto and a chip with a reinforcing substrate attached thereto after bonding the chip to a substrate, respectively. The chip 100 may be a silicon chip, and the first surface 110 of the chip 100 may be a front surface or a back surface of the chip 100, where the first surface 110 is provided with solder balls 120. The reinforcing substrate 200 is made of a solid material with a small thermal expansion coefficient, for example, the reinforcing substrate 200 is a metal sheet, a ceramic sheet, a silicon sheet or the like. The substrate 500 may be a ceramic substrate or a PCB board, and the surface of the substrate 500 may be provided with a bonding pad 510 according to actual needs, which is not easily understood that a circuit layer (not shown) is disposed inside the substrate 500, and the circuit layer is electrically connected to the bonding pad 510 disposed on the surface of the substrate 500.
And step S120, adhering the reinforcing substrate on a second surface of the chip opposite to the first surface through adhesive.
Specifically, referring to fig. 3, an adhesive 300 may be applied to the second surface 130 of the chip 100 opposite to the first surface 110, and then the stiffener 200 may be attached to the adhesive 300, so that the stiffener 200 is fixed to the second surface 130 of the chip 100. In this embodiment, the adhesive may be an adhesive that is strong in adhesiveness and is softened by a chemical solvent, for example, latex (latex) or the like, and the latex is strong in adhesiveness and is softened by a chemical solvent.
According to the embodiment of the disclosure, the reinforcing substrate is adhered to the second surface of the chip through the adhesive, and plays a role in supporting the chip, so that the warping of the chip is changed.
The thickness of the reinforcing substrate can be set according to practical conditions, and the thickness of the reinforcing substrate can be slightly thicker than that of the chip.
In an embodiment, referring to fig. 4, fig. 4 is a process flow chart of attaching a reinforcing substrate to a surface of a chip in an embodiment of the disclosure, where the step S120 specifically includes:
step S121, placing the first surface of the chip on the surface of the console.
In this embodiment of the disclosure, as shown in fig. 4, the first surface 110 of the chip 100 is placed on the surface of the console 600, the surface of the console needs to be leveled, the solder balls 120 of the chip are directly contacted with the surface of the console 600, and the second surface 130 of the chip faces upward to facilitate subsequent dispensing.
And step S122, dispensing is performed on the second surface of the chip, and the reinforcing substrate is adhered to the second surface of the chip.
In addition, when dispensing the second surface 130 of the chip, the adhesive used may be latex. The dispensing process may be performed according to actual situations, which is not described herein. After the second surface of the chip is uniformly coated with the adhesive, the reinforcing substrate 200 is adhered to the second surface 130 of the chip 100.
Prior to step S121, the method S100 further includes:
and a high-temperature adhesive tape is arranged on the surface of the operating platform.
Specifically, in the embodiment of the present disclosure, as shown in fig. 4, the high-temperature adhesive tape 800 is disposed on the operation table, where the high-temperature adhesive tape may protect solder balls of the chip from being damaged by pressure when the reinforcing substrate is adhered. The high-temperature adhesive tape is an adhesive tape used in a high-temperature operation environment.
In one embodiment, the stiffener substrate is the same size as the chip.
Specifically, as shown in fig. 3 and 7, the reinforcing substrate 200 has the same size as the chip 100, so that the reinforcing substrate 200 can be entirely covered on the second surface of the chip 100, and the warpage of the whole chip is changed.
And step 130, performing hot press curing on the adhesive between the reinforced substrate and the chip.
Specifically, in step S130, the bonding glue is cured by hot pressing, so as to increase the bonding speed between the reinforcing substrate and the chip, and maintain the structural stability of the reinforcing substrate and the chip.
In an embodiment, referring to fig. 5, fig. 5 is a process flow chart of hot press curing of the adhesive in the embodiment of the disclosure, and the step S130 specifically includes:
step S131, placing the first surface of the chip on the surface of the heating table.
Specifically, the chip 100 with the reinforcing substrate 200 adhered thereto in the step 120 is transferred to a heating table 700, where the first surface 110 of the chip 100 is placed on the surface of the heating table 700, the surface of the heating table 700 needs to be flat, the solder balls 120 of the chip directly contact with the surface of the heating table 700, the heating table may be a platform or a box structure capable of heating, and the heating table has a heater or an air heater, etc., so that the heating table heats uniformly, and may also have a fan, etc., and the specific structure of the heating table is not limited herein, and a person skilled in the art may select the heating table according to actual situations.
And S132, placing a pressing piece in the central area of the reinforcing substrate, which is away from the chip, so as to carry out hot press curing on the adhesive.
In the embodiment of the disclosure, referring to fig. 5 and 6, fig. 6 is a schematic structural diagram of a chip in a thermocompression curing process of an adhesive; the heating stage 700 in fig. 5 heats the chip and thermally cures the adhesive between the chip and the stiffener substrate. The pressing member 400 applies a certain pressing force to the reinforcing substrate 200 so that the adhesive 300 is pressure-cured. Wherein, the heating stage is adjusted to a proper temperature according to the curing temperature of the adhesive 300, and the adhesive 300 between the reinforcing substrate 200 and the chip 100 is cured by heating. When the adhesive is latex, the heating temperature is 30-90 degrees. The size and weight of the pressing member 400 may be set according to practical situations, but not limited to, the pressing member 400 may be a metal block or a weight, etc., the weight is relatively easy to obtain, and on the other hand, the size is smaller, the weight is moderate, the weight may not only press and cure the adhesive, but also further change the warpage of the chip, as can be seen from fig. 1, the central area of the chip 100 is warped away from the direction of the substrate 500, and the weight is placed in the central area of the chip, so that the pressing is balanced, and on the other hand, the central area of the chip may be further pressed, so as to change the warpage of the chip.
It should be noted that, before step S131, the method S100 further includes:
and a high-temperature adhesive tape is arranged on the surface of the heating table.
Specifically, in the embodiment of the present disclosure, a high-temperature adhesive tape (not shown in the drawing) may be disposed on the heating table, where the high-temperature adhesive tape may protect solder balls of the chip from being damaged by pressure during thermal compression and curing.
After the adhesive 300 between the reinforcing substrate and the chip 100 is cured by hot pressing, the chip 100 is taken out from the heating table and cooled. To facilitate the subsequent package acquisition of the chip 100, the chip 100 with the stiffener substrate 200 attached thereto may be placed in a raw wafer surface or tray.
And step 140, carrying out reflow soldering on the solder balls of the chip and the bonding pads of the substrate to obtain the intermediate chip package.
Specifically, referring to fig. 7, fig. 7 is a schematic structural diagram of an intermediate chip package obtained after bonding a chip with a reinforcing substrate to a substrate. Before the solder balls 120 of the chip 100 are soldered to the pads 510 of the substrate 500 by reflow, the chip 100 with the stiffener 200 attached thereto is mounted on the substrate 500 by using a chip mounter, and then fed into a reflow soldering apparatus for reflow, so as to complete the connection between the chip 100 and the substrate 500, thereby obtaining an intermediate chip package (not shown).
In step S140, since the second surface 130 of the chip 100 is adhered with the reinforcing substrate 200, the warpage of the chip is changed, and in the reflow soldering process of the chip 100 and the substrate 500, the reinforcing substrate ensures that the chip is not deformed, so that the chip is adhered to the substrate, and the solder balls of the soldering flux covering the chip are connected with the pads of the corresponding substrate, so that the chip and the substrate are soldered well.
And step S150, peeling the reinforcement substrate from the chip of the middle chip package body to obtain a target chip package body.
Specifically, in step S150, referring to fig. 8, fig. 8 is a schematic structural diagram of a target chip package obtained after the reinforcement substrate is peeled, after the chip 100 is soldered to the substrate 500, the reinforcement substrate 200 may be peeled to obtain the target chip package, so that the space occupied by the reinforcement substrate is saved, the size of the target chip package is ensured, and the subsequent process is facilitated.
The step S150 specifically includes:
step S151, soaking the intermediate chip package in an organic solvent and heating for a preset time.
Specifically, an appropriate organic solvent is selected according to the materials of the chip 100, the reinforcing substrate 200 and the adhesive 300 in the intermediate chip package, for example, the organic solvent should be such that the chip is insoluble in the organic solvent, the reinforcing substrate is insoluble in the organic solvent, or only weakly reacts with the organic solvent, and the adhesive is soluble in the organic solvent.
In step S151, the intermediate chip package is soaked in an organic solvent and heated for a preset time, so as to accelerate dissolution of the adhesive, and the heating temperature and heating time can be adjusted according to the use requirement of the organic solvent, which is not described herein.
The organic solvent may be acetone.
Specifically, the chip 100 is silicon, the reinforcing substrate 200 is a metal sheet or a silicon wafer, and the like, which is not easily dissolved in acetone, and when the adhesive 300 is latex, the latex is soluble in the acetone, and the heating is performed to make the latex dissolve rapidly, and the heating temperature and the heating time can be set according to practical situations.
And step S152, taking out the middle chip packaging body after the bonding glue between the reinforcing substrate and the chip is softened.
Specifically, in step S152, the reinforcing substrate 200 and the chip 100 are not dissolved in an organic solvent, only the adhesive 300 is dissolved in an organic solvent, and after the adhesive 300 is softened, the intermediate chip package is taken out of the organic solvent.
And step S153, peeling the reinforced substrate from the chip.
Specifically, after the adhesive 300 is softened, the reinforcing substrate 200 may be manually peeled off from the second surface 130 of the chip 100, and then the surface of the chip is wiped clean with alcohol, so as to ensure the cleanliness of the chip.
According to the chip packaging method, the reinforcing substrate is adhered to the second surface of the chip, the bonding adhesive between the reinforcing substrate and the chip is cured through hot pressing, so that the reinforcing substrate is firmly adhered to the chip, the warping of the chip is changed, the adhesion of a soldering flux coverage area (fluxcoverage) and the substrate can be ensured when the soldering ball on the first surface of the chip and the bonding pad on the surface of the substrate are subjected to reflow soldering, and the chip can be ensured not to deform in the reflow soldering process. The chip packaging technology of the embodiment of the disclosure is simple and has strong feasibility.
Another aspect of the embodiments of the present disclosure provides a fan-out chip package structure, obtained by using the above-described packaging method.
Specifically, the fan-out chip 100 packaging structure disclosed by the disclosure adopts the method that the reinforcing substrate 200 is adhered to the second surface 130 of the chip 100, and the bonding adhesive 300 between the reinforcing substrate 200 and the chip 100 is cured by hot pressing, so that the chip 100 and the reinforcing substrate 200 are firmly adhered, the warpage of the chip 100 is changed, the chip 100 is not warped when the chip 100 and the substrate 500 are subjected to reflow soldering, the chip and the substrate are ensured to be adhered to each other, and the connection of soldering flux is ensured, so that the chip packaging structure with good welding between the chip and the substrate is obtained.
It is to be understood that the above implementations are merely exemplary implementations employed to illustrate the principles of the disclosed embodiments, which are not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the embodiments of the disclosure, and these modifications and improvements are also considered to be within the scope of the embodiments of the disclosure.

Claims (10)

1. A fan-out chip packaging method, the method comprising:
providing a base plate, a reinforced substrate and a chip; the surface of the substrate is provided with a bonding pad, and the first surface of the chip is provided with a solder ball;
adhering the reinforcing substrate to a second surface of the chip opposite to the first surface through adhesive;
carrying out hot-press curing on the adhesive between the reinforcing substrate and the chip;
carrying out reflow soldering on the solder balls of the chip and the bonding pads of the substrate to obtain an intermediate chip package;
and stripping the reinforced substrate from the chip of the middle chip package body to obtain the target chip package body.
2. The method of claim 1, wherein the attaching the reinforcing substrate to a second surface of the chip opposite the first surface by adhesive comprises:
placing the first surface of the chip on the surface of an operation table;
dispensing is carried out on the second surface of the chip, and the reinforcing substrate is adhered to the second surface of the chip.
3. The method of claim 2, wherein prior to placing the first surface of the chip on the surface of the console, the method further comprises:
and a high-temperature adhesive tape is arranged on the surface of the operating platform.
4. The method of claim 1, wherein the thermocompression curing the adhesive between the stiffener substrate and the die comprises:
placing the first surface of the chip on the surface of a heating table;
and placing a pressing piece in the central area of the reinforcing substrate, which is away from the chip, so as to carry out hot press curing on the adhesive.
5. The method of claim 4, wherein prior to placing the first surface of the chip on the surface of the heating stage, the method further comprises:
and a high-temperature adhesive tape is arranged on the surface of the heating table.
6. The method of any one of claims 1 to 5, wherein the peeling the stiffener substrate from the die of the intermediate die package comprises:
soaking the middle chip package body in an organic solvent and heating for a preset time;
after the bonding glue between the reinforcing substrate and the chip is softened, taking out the middle chip packaging body;
and stripping the reinforced substrate from the chip.
7. The method of claim 6, wherein the organic solvent is acetone.
8. The method of any one of claims 1 to 5, wherein the stiffener substrate is the same size as the chip.
9. The method of any one of claims 1 to 5, wherein the reinforcing substrate is a silicon wafer or a metal sheet.
10. A fan-out chip package structure, characterized in that it is obtained by the packaging method according to any one of claims 1 to 9.
CN202310653029.9A 2023-06-05 2023-06-05 Fan-out chip packaging method and structure Pending CN116682744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310653029.9A CN116682744A (en) 2023-06-05 2023-06-05 Fan-out chip packaging method and structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310653029.9A CN116682744A (en) 2023-06-05 2023-06-05 Fan-out chip packaging method and structure

Publications (1)

Publication Number Publication Date
CN116682744A true CN116682744A (en) 2023-09-01

Family

ID=87790314

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310653029.9A Pending CN116682744A (en) 2023-06-05 2023-06-05 Fan-out chip packaging method and structure

Country Status (1)

Country Link
CN (1) CN116682744A (en)

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