CN116682482B - NAND flash quality classification method, NAND flash quality classification device, and storage medium - Google Patents
NAND flash quality classification method, NAND flash quality classification device, and storage medium Download PDFInfo
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- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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Abstract
The application provides a NAND flash quality grading method, a NAND flash quality grading device and a storage medium, comprising the following steps: acquiring a plurality of error correction levels and a plurality of voltage offsets, and extracting the maximum codeword max_cw of all pages of the NAND flash memory; for each error correction level, determining the total number of pages corresponding to the error correction level, counting the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc of each voltage offset under the total number of pages, and screening the optimal voltage offset from the voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc; extracting chip correction parameters of the NAND flash under each error correction level and the optimal voltage offset; and carrying out quality classification on the NAND flash memory according to the chip entanglement parameters. Because the quality classification can be carried out based on the chip correction parameters of the NAND flash under each error correction level and the optimal voltage offset, the quality classification standard of the NAND flash is defined, and therefore finer quality assessment can be carried out on the NAND flash.
Description
Technical Field
The present disclosure relates to the field of data processing technologies, and in particular, to a quality classification method for NAND flash memory, a quality classification device for NAND flash memory, and a storage medium.
Background
In the related art, a Nand-flash memory is one type of flash memory, and a nonlinear macro-cell mode is adopted in the Nand-flash memory, so that a cheap and effective solution is provided for the realization of a solid-state large-capacity memory. The Nand-flash memory has the advantages of larger capacity, high rewriting speed and the like, and is suitable for storing a large amount of data, so that the Nand-flash memory is widely applied in the industry.
However, with the current NAND flash memories, quality classification standards are not accurate enough, and thus it is difficult to perform finer and accurate quality assessment of the NAND flash memories.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art. For this reason, the present application proposes a NAND flash quality classification method, a NAND flash quality classification device, and a storage medium, aiming at classifying the quality of a NAND flash.
In a first aspect, an embodiment of the present application provides a quality classification method for a NAND flash memory, including:
acquiring a plurality of error correction levels and a plurality of voltage offsets, and extracting the maximum codeword max_cw of all pages of the NAND flash memory;
For each error correction level, determining the total number of pages corresponding to the error correction level, counting the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc of each voltage offset under the total number of the pages, and screening out the optimal voltage offset from a plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc;
extracting chip correction parameters of the NAND flash under each error correction level and the optimal voltage offset;
and carrying out quality grading on the NAND flash memory according to the chip entanglement parameter.
In some embodiments, said screening the best voltage offset from a plurality of said voltage offsets according to said maximum codeword max_cw, said maximum error correction capability max_ecc, and said average error correction capability mean_ecc comprises:
screening a plurality of candidate voltage offset values from a plurality of voltage offset values according to the maximum codeword max_cw and the maximum error correction capability max_ecc of each voltage offset value under the total number of pages;
and screening the optimal voltage offset from the candidate voltage offsets according to the average error correction capability mean_ecc of each voltage offset under the total number of pages.
In some embodiments, the selecting a number of candidate voltage offsets from the plurality of voltage offsets according to the maximum codeword max_cw and the maximum error correction capability max_ecc for each of the voltage offsets under the total number of pages includes at least one of:
discarding the voltage offset when the maximum codeword max_cw is greater than or equal to the maximum error correction capability max_ecc;
and when the maximum codeword max_cw is smaller than the maximum error correction capability max_ecc, reserving the voltage offset, and taking the voltage offset as a candidate voltage offset.
In some embodiments, said selecting an optimal voltage offset from a number of said candidate voltage offsets based on said average error correction capability mean_ecc for each said voltage offset over said total number of pages comprises:
sorting the average error correction capability mean_eccs of each voltage offset under the total number of pages according to the numerical value to obtain a plurality of sorted average error correction capability mean_eccs;
and screening the average error correction capability mean_eccs with the smallest value from the plurality of average error correction capability mean_eccs, and taking the candidate voltage offset corresponding to the average error correction capability mean_eccs with the largest value as the optimal voltage offset.
In some embodiments, before said counting the maximum error correction capability max_ecc and the average error correction capability mean_ecc for each of said voltage offsets at said total number of pages, said NAND flash quality classification method further comprises:
acquiring a voltage offset limit value;
when the voltage offset is smaller than the voltage offset limit value, reserving the voltage offset;
and discarding the voltage offset when the voltage offset is greater than or equal to the voltage offset limit value.
In some embodiments, after the obtaining the plurality of error correction levels and the plurality of voltage offsets, the NAND flash quality classification method further comprises:
and preprocessing the data of the NAND flash memory to convert unstructured data into structured data.
In some embodiments, said counting a maximum error correction capability max_ecc and an average error correction capability mean_ecc for each of said voltage offsets for said total number of pages, and screening an optimal voltage offset from a plurality of said voltage offsets according to said maximum codeword max_cw, said maximum error correction capability max_ecc and said average error correction capability mean_ecc comprises: calculating the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc of each voltage offset in the total number of pages and each operation scene, and screening the optimal voltage offset from a plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc;
The extracting the chip erasure parameters for each of the error correction levels and the optimal voltage offset for the NAND flash includes: extracting chip correction parameters of the NAND flash under each operation scene, each error correction level and the optimal voltage offset.
The quality grading of the NAND flash memory according to the chip entanglement parameter includes: and carrying out quality classification on the NAND flash memory under each operation scene according to the chip entanglement parameters.
In some embodiments, the quality grading the NAND flash memory according to the chip entanglement parameter comprises:
comparing the chip entanglement parameter with a preset entanglement parameter to obtain a comparison result;
and carrying out quality grading on the NAND flash memory according to the comparison result.
In a second aspect, an embodiment of the present application provides a NAND flash quality classification device, including:
the data acquisition unit is used for acquiring a plurality of error correction levels and a plurality of voltage offsets and extracting the maximum codeword max_cw of all pages of the NAND flash memory;
an offset screening unit, configured to determine, for each error correction level, a total number of pages corresponding to the error correction level, count a maximum error correction capacity max_ecc and an average error correction capacity mean_ecc of each voltage offset under the total number of pages, and screen an optimal voltage offset from a plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc;
A correction parameter extraction unit for extracting a chip correction parameter of the NAND flash under each error correction level and the optimal voltage offset;
and the quality grading unit is used for grading the quality of the NAND flash memory according to the chip entanglement parameter.
In a third aspect, embodiments of the present application provide a computer-readable storage medium storing computer-executable instructions for performing the NAND flash quality classification method of the first aspect described above.
According to the technical scheme of the embodiment of the application, the method has at least the following beneficial effects: firstly, the embodiment of the application acquires a plurality of error correction levels and a plurality of voltage offsets, and extracts the maximum codeword max_cw of all pages of the NAND flash memory; then, for each error correction level, the embodiment of the application determines the total number of pages corresponding to the error correction level, counts the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc of each voltage offset under the total number of pages, and screens out the optimal voltage offset from the plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc; then, the embodiment of the application extracts the chip correction parameters of the NAND flash under each error correction level and the optimal voltage offset; finally, the embodiments of the present application perform quality classification on the NAND flash memory according to the chip entanglement parameters. According to the embodiment of the application, the chip correction parameters of the NAND flash under each error correction level and the optimal voltage offset can be obtained, and the quality classification is carried out based on the chip correction parameters, so that the quality classification standard of the NAND flash is defined, and further finer quality assessment can be carried out on the NAND flash.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a flow chart of steps of a method for quality classification of NAND flash memory according to one embodiment of the present application;
FIG. 2 is a flow chart of steps of a method for quality classification of NAND flash memory according to another embodiment of the present application;
FIG. 3 is a flow chart of steps of a method for quality classification of NAND flash memory according to another embodiment of the present application;
FIG. 4 is a flow chart of steps of a method for quality classification of NAND flash memory according to another embodiment of the present application;
FIG. 5 is a flow chart of steps of a method for quality classification of NAND flash memory according to another embodiment of the present application;
FIG. 6 is a flow chart of steps of a method for quality classification of NAND flash memory according to another embodiment of the present application;
FIG. 7 is a flow chart of steps of a method for quality classification of NAND flash memory according to another embodiment of the present application;
FIG. 8 is a flow chart of steps of a method for quality classification of NAND flash memory according to another embodiment of the present application;
FIG. 9 is a flow chart of steps of a method for quality classification of NAND flash memory according to another embodiment of the present application;
FIG. 10 is a flowchart of overall steps of a method for quality classification of NAND flash memory provided in one embodiment of the present application;
FIG. 11 is a schematic diagram of an electronic device for performing a NAND flash quality classification method according to one embodiment of the present application;
fig. 12 is a schematic structural diagram of a NAND flash quality classification device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it should be understood that references to orientation descriptions, such as directions of up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the description of the present application, the meaning of a number is one or more, the meaning of a number is two or more, greater than, less than, exceeding, etc. are understood to not include the present number, and the meaning of a number above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present application, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present application can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical solution.
In some cases, the Nand-flash memory is one type of flash memory, and a nonlinear macro-cell mode is adopted in the Nand-flash memory, so that a cheap and effective solution is provided for the realization of a solid-state large-capacity memory. The Nand-flash memory has the advantages of larger capacity, high rewriting speed and the like, and is suitable for storing a large amount of data, so that the Nand-flash memory is widely applied in the industry. However, with the current NAND flash memories, there is no clear quality grading standard, so it is difficult to perform finer quality assessment on the NAND flash memories.
Based on the above, the embodiments of the present application provide a quality classification method for NAND flash memory, a quality classification device for NAND flash memory, and a computer-readable storage medium, which aim to classify the quality of NAND flash memory.
The quality classification method of the NAND flash memory according to the embodiment of the application is further described below with reference to the accompanying drawings.
As shown in fig. 1, fig. 1 is a flowchart illustrating steps of a quality classification method for a NAND flash memory according to an embodiment of the present application. The NAND flash quality grading method of the embodiment of the present application may include, but is not limited to, step S110, step S120, step S130, and step S140.
Step S110, acquiring a plurality of error correction levels and a plurality of voltage offsets, and extracting the maximum codeword max_cw of all pages of the NAND flash memory;
step S120, for each error correction level, determining the total number of pages corresponding to the error correction level, counting the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc of each voltage offset under the total number of pages, and screening out the optimal voltage offset from the plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc;
step S130, extracting chip correction parameters of the NAND flash under each error correction level and the optimal voltage offset;
And step S140, quality grading is carried out on the NAND flash memory according to the chip entanglement parameter.
In an embodiment, first, the embodiment of the present application can set a plurality of error correction levels, and different error correction levels correspond to different total numbers of pages, and also extract the maximum codeword max_cw of all the pages of the NAND flash memory; then, for each error correction level, the embodiment of the present application may count the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc of each voltage offset under the total page number, and compare and analyze the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc, so as to screen out the optimal voltage offset; then, extracting and obtaining chip correction parameters of the NAND flash under each error correction level and the optimal voltage offset according to the rules; finally, according to the embodiment of the application, the quality of the NAND flash memory can be graded according to the chip entanglement parameter, for example, the higher the chip entanglement parameter is, the better the quality grade of the NAND flash memory is; the lower the chip erasure parameter, the poorer the quality level of the NAND flash memory.
It is noted that, since the embodiment of the present application can obtain the chip correction parameters of the NAND flash under each error correction level and the optimal voltage offset, and perform quality classification based on the chip correction parameters, the embodiment of the present application specifies the quality classification standard of the NAND flash, so as to perform finer quality assessment on the NAND flash.
Note that, regarding the above-mentioned page type, the above-mentioned page type may be of FLC type, MLC type, SLC type, SMLC type, TLC type, or other type, and the embodiment of the present application is not limited specifically.
In addition, it should be noted that, regarding the above voltage offset, refer to Retry, where a plurality of groups of voltage offsets are pre-stored during the factory, where the number of voltage offsets may be 5 groups or 10 groups, and the number of pre-stored voltage offsets is not specifically limited in the embodiment of the present application.
In addition, regarding the maximum codeword max_cw, if the value is larger, the correction complexity is higher; if the value is smaller, the correction complexity is lower.
Note that, regarding the maximum error correction capability max_ecc described above, if the value is larger, the higher the maximum error correction capability is indicated; the smaller the value, the worse the maximum error correction capability is indicated.
In addition, regarding the average error correction capability mean_ecc described above, if the value is larger, it indicates that the correction speed is faster; if the value is smaller, the correction speed is lower.
Note that, the chip correction parameter may be a chip correction ratio or a chip correction amount, and the embodiment of the present application is not particularly limited thereto.
In addition, as shown in fig. 2, fig. 2 is a flowchart illustrating steps of a quality classification method for a NAND flash memory according to another embodiment of the present application. Regarding the filtering of the optimal voltage offset from the plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capability max_ecc, and the average error correction capability mean_ecc in the above-mentioned step S120, it may include, but is not limited to, step S210 and step S220.
Step S210, screening a plurality of candidate voltage offset values from a plurality of voltage offset values according to the maximum codeword max_cw and the maximum error correction capacity max_ecc of each voltage offset value under the total page number;
step S220, the optimal voltage offset is screened out from a plurality of candidate voltage offsets according to the average error correction capability mean_ecc of each voltage offset under the total number of pages.
In an embodiment, the maximum codeword max_cw and the maximum error correction capability max_ecc may be compared, a plurality of candidate voltage offsets with sufficient error correction capability may be screened from a plurality of voltage offsets according to the comparison result, and then screening may be performed on the candidate voltage offsets, and specifically, a candidate voltage offset with the fastest error correction speed may be screened from the plurality of candidate voltage offsets through average error correction capability mean_ecc as a candidate optimal voltage offset.
It is to be understood that, regarding the number of candidate voltage offsets in the step S210, there may be one or more candidate voltage offsets, and the number of candidate voltage offsets is not specifically limited in the embodiment of the present application.
It should be noted that, regarding the maximum codeword max_cw and the maximum error correction capability max_ecc of each voltage offset under the total number of pages in the above step S210, a plurality of candidate voltage offsets are selected from the plurality of voltage offsets, which may include, but are not limited to, two implementation cases in fig. 3 or fig. 4, specifically as follows:
as shown in fig. 3, fig. 3 is a step flowchart of a quality grading method for a NAND flash memory according to another embodiment of the present application. Regarding the above step S210, step S310 and step S320 may be included, but are not limited thereto.
Step S310, when the maximum codeword max_cw is greater than or equal to the maximum error correction capability max_ecc;
step S320, discarding the voltage offset.
As shown in fig. 4, fig. 4 is a flowchart illustrating steps of a quality classification method for a NAND flash memory according to another embodiment of the present application. Regarding the above step S210, step S410 and step S420 may be included, but are not limited thereto.
Step S410, when the maximum codeword max_cw is smaller than the maximum error correction capability max_ecc;
Step S420, the voltage offset is reserved, and the voltage offset is used as a candidate voltage offset.
In an embodiment, if the maximum codeword max_cw corresponding to the voltage offset is greater than or equal to the maximum error correction capability max_ecc, then the error correction capability is not sufficient, and at this time, the embodiments of the present application discard the voltage offset; if the maximum codeword max_cw corresponding to the voltage offset is smaller than the maximum error correction capability max_ecc, which indicates that the error correction capability is sufficient, then the embodiment of the application reserves the voltage offset and takes the voltage offset as a candidate voltage offset.
In addition, as shown in fig. 5, fig. 5 is a step flowchart of a quality classification method for a NAND flash memory according to another embodiment of the present application. Regarding the above-mentioned step S220, the selection of the optimal voltage offset from the several candidate voltage offsets according to the average error correction capability mean_ecc of each voltage offset under the total number of pages may include, but is not limited to, step S510 and step S520.
Step S510, sorting the average error correction capability mean_eccs of each voltage offset under the total number of pages according to the numerical value, and obtaining a plurality of sorted average error correction capability mean_eccs;
and S520, selecting the average error correction capability mean_ecc with the smallest value from the plurality of average error correction capability mean_eccs, and taking the candidate voltage offset corresponding to the average error correction capability mean_ecc with the largest value as the optimal voltage offset.
In an embodiment, the embodiment of the present application may sort the values of the plurality of average error correction capacities mean_eccs, where the larger the value of the average error correction capacity mean_eccs, the faster the correction speed is indicated; the smaller the value of the average error correction capability mean_ecc, the slower the correction speed is indicated; then, the embodiment of the application can screen the average error correction capability mean_ecc with the largest value from the plurality of sequenced average error correction capability mean_eccs, and take the candidate voltage offset corresponding to the average error correction capability mean_ecc with the largest value as the candidate optimal voltage offset, so that the candidate optimal voltage offset can be ensured to ensure certain error correction capability and achieve the fastest error correction speed.
In addition, as shown in fig. 6, fig. 6 is a step flowchart of a quality classification method of a NAND flash memory according to another embodiment of the present application. The NAND flash memory quality grading method of the embodiment of the present application may further include, but is not limited to, step S610, step S620, and step S630 before performing the above-described statistics of the maximum error correction capability max_ecc and the average error correction capability mean_ecc for each voltage offset under the total number of pages in step S120.
Step S610, obtaining a voltage offset limit value;
Step S620, when the voltage offset is smaller than the voltage offset limit value, reserving the voltage offset;
step S630, discarding the voltage offset when the voltage offset is greater than or equal to the voltage offset limit value.
In an embodiment, the voltage offset is compared with the voltage offset limit value, if the voltage offset is smaller than the voltage offset limit value, the voltage offset can be used normally, and then the voltage offset is reserved; if the voltage offset is greater than or equal to the voltage offset limit value, indicating that the voltage offset cannot be used normally, embodiments of the present application discard the voltage offset.
In addition, as shown in fig. 7, fig. 7 is a step flowchart of a quality classification method of a NAND flash memory according to another embodiment of the present application. After the above-described acquisition of the plurality of error correction levels and the plurality of voltage offsets in step S110 is performed, the NAND flash quality classification method of the embodiment of the present application may further include, but is not limited to, step S700.
Step S700, preprocessing the data of the NAND flash memory to convert unstructured data into structured data.
In addition, as shown in fig. 8, fig. 8 is a step flowchart of a quality classification method for a NAND flash memory according to another embodiment of the present application. Regarding the above-described steps S110 to S140, it may include, but is not limited to, step S810, step S820, step S830, and step S840.
Step S810, obtaining a plurality of error correction levels and a plurality of voltage offsets, and extracting the maximum codeword max_cw of all pages of the NAND flash memory;
step S820, for each error correction level, determining the total number of pages corresponding to the error correction level, counting the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc of each voltage offset in the total number of pages and each operation scene, and screening out the optimal voltage offset from the voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc;
step S830 extracts the chip correction parameters of the NAND flash under each operation scene, each error correction level and the optimal voltage offset.
Step S840, quality grading is carried out on the NAND flash memory under each operation scene according to the chip entanglement parameters.
In an embodiment, experiments can be performed for different operation scenes, so that chip correction parameters of the NAND flash under each operation scene, each error correction level and the optimal voltage offset are obtained, and quality classification is performed on the NAND flash under each operation scene according to the chip correction parameters.
It should be noted that, regarding the above operation scenario, the above operation scenario may be a high-temperature writing scenario, a high Wen Douqu scenario, a high-refresh frequency scenario, a low-refresh frequency scenario, or other types of operation scenarios, and the type of operation scenario is not specifically limited in this embodiment of the present application.
In addition, as shown in fig. 9, fig. 9 is a step flowchart of a quality classification method of a NAND flash memory according to another embodiment of the present application. Regarding the quality classification of the NAND flash memory according to the chip entanglement parameters in the above-described step S140, it may include, but is not limited to, step S910 and step S920.
Step S910, comparing the chip entanglement parameter with a preset entanglement parameter to obtain a comparison result;
and step S920, quality grading is carried out on the NAND flash memory according to the comparison result.
In an embodiment, the method can compare the chip entanglement parameter with a preset entanglement parameter, and then quality grade the NAND flash memory based on a comparison result. For example, if the chip entanglement ratio is greater than or equal to the highest preset entanglement ratio, it may be classified as good; if the chip correction ratio is between the highest preset correction ratio and the next highest preset correction ratio, the chip correction ratio can be classified as a next good product; if the chip entanglement ratio is smaller than the preset entanglement ratio of the next highest, it may be classified as defective.
It should be noted that, regarding the above-mentioned preset correction parameter, the value of the correction parameter may be set independently according to the actual requirement.
Based on the NAND flash quality classification method of the above embodiments, overall embodiments of the NAND flash quality classification method of the present application are presented below.
As shown in fig. 10, fig. 10 is a flowchart illustrating overall steps of a quality classification method for a NAND flash memory according to an embodiment of the present application. The overall embodiment of the NAND flash quality classification method of the present application includes, but is not limited to, steps S1001 to S1011.
Step S1001, start;
step S1002, acquiring read data through different scene experiments;
step S1003, preprocessing data, namely converting unstructured data into structured data;
step S1004, extracting max_cw of all pages of each chip;
step S1005, counting the total number of pages, max_ecc, mean_ecc and other data of each retry under different page types according to the ecc_limit level;
step S1006, calculating an optimal retry according to the data;
step S1007, extracting data of different ecc_limit levels of the optimal retry;
step S1008, calculating a chip correction ratio corresponding to each ecc_limit level of each scene;
step S1009, classifying chips of each scene;
step S1010, integrating all scenes to grade chips, and checking whether the proportion of each grade accords with an expected standard;
step S1011 ends.
For nand classification, the embodiment of the application can use the retry group number as a classification standard, so that the yield conditions of different levels are reflected. Through the steps, whether the provided index can be used as a nand grading standard or not can be accurately and completely presented, and the estimated yield condition can be accurately provided.
Based on the NAND flash quality classification method of the above embodiments, various embodiments of the electronic device, the NAND flash quality classification apparatus, and the computer-readable storage medium of the present application are respectively presented below.
As shown in fig. 11, fig. 11 is a schematic structural diagram of an electronic device for performing a quality classification method of a NAND flash memory according to an embodiment of the present application. The electronic device 100 implemented by the present application includes: processor 110, memory 120, and a computer program stored on memory 120 and executable on processor 110, where one processor 110 and one memory 120 are illustrated in fig. 11.
The processor 110 and the memory 120 may be connected by a bus or otherwise, which is illustrated in fig. 11 as a bus connection.
Memory 120, as a non-transitory computer-readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer-executable programs. In addition, memory 120 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some implementations, the memory 120 optionally includes memory 120 remotely located relative to the processor 110, the remote memory 120 being connectable to the electronic device 100 through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Those skilled in the art will appreciate that the apparatus structure shown in fig. 11 is not limiting of the electronic device 100 and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
In the electronic device 100 shown in fig. 11, the processor 110 may be configured to invoke the NAND flash quality classification program stored in the memory 120, thereby implementing the NAND flash quality classification method described above. Specifically, a non-transitory software program and instructions required to implement the NAND flash quality classification method of the above-described embodiments are stored in the memory 120, which when executed by the processor 110, performs the NAND flash quality classification method of the above-described embodiments.
It should be noted that, since the electronic device 100 of the embodiment of the present application is capable of executing the NAND flash memory quality classification method of any one of the embodiments described above, reference may be made to the specific implementation and technical effects of the NAND flash memory quality classification method of any one of the embodiments described above.
Further, as shown in fig. 12, fig. 12 is a schematic structural diagram of a NAND flash quality classification device according to an embodiment of the present application. The NAND flash quality classification device 200 implemented in the present application includes, but is not limited to, a data acquisition unit 210, a first filtering unit 220, a entanglement parameter extraction unit 230, and a quality classification unit 240.
Specifically, the data obtaining unit 210 is configured to obtain a plurality of error correction levels and a plurality of voltage offsets, and extract a maximum codeword max_cw of all pages of the NAND flash memory; the first filtering unit 220 is configured to determine, for each error correction level, a total number of pages corresponding to the error correction level, count a maximum error correction capacity max_ecc and an average error correction capacity mean_ecc of each voltage offset under the total number of pages, and filter an optimal voltage offset from the plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc; the erasure parameter extracting unit 230 is configured to extract chip erasure parameters of the NAND flash under each error correction level and the optimal voltage offset; the quality classification unit 240 is used for quality classification of the NAND flash memory according to the chip entanglement parameter.
In an embodiment, the first filtering unit 220 is further configured to filter a plurality of candidate voltage offsets from the plurality of voltage offsets according to a maximum codeword max_cw and a maximum error correction capability max_ecc of each voltage offset under the total number of pages; and screening the optimal voltage offset from the plurality of candidate voltage offsets according to the average error correction capability mean_ecc of each voltage offset under the total number of pages.
In an embodiment, when the maximum codeword max_cw is greater than or equal to the maximum error correction capability max_ecc, the first filtering unit 220 is further configured to discard the voltage offset; when the maximum codeword max_cw is smaller than the maximum error correction capability max_ecc, the first filtering unit 220 is further configured to reserve the voltage offset, and take the voltage offset as a candidate voltage offset.
In an embodiment, the first filtering unit 220 is further configured to sort the average error correction capability mean_eccs of each voltage offset under the total number of pages according to the numerical value, to obtain a plurality of sorted average error correction capability mean_eccs; and screening the average error correction capability mean_eccs with the largest value from the plurality of average error correction capability mean_eccs, and taking the candidate voltage offset corresponding to the average error correction capability mean_eccs with the smallest value as the optimal voltage offset.
In one embodiment, the NAND flash quality grading device 200 implemented in the present application further includes, but is not limited to, a second filtering unit 250, where the second filtering unit 250 is configured to obtain a voltage offset limit value; when the voltage offset is smaller than the voltage offset limit value, the second filtering unit 250 is configured to retain the voltage offset; when the voltage offset is greater than or equal to the voltage offset limit value, the second filtering unit 250 is configured to discard the voltage offset.
In an embodiment, the NAND flash quality classification device 200 implemented in the present application further includes, but is not limited to, a preprocessing unit 260, where the preprocessing unit 260 is configured to preprocess data of the NAND flash memory so as to convert unstructured data into structured data.
In an embodiment, the first filtering unit 220 is further configured to count a maximum error correction capability max_ecc and an average error correction capability mean_ecc of each voltage offset in the total number of pages and each operation scene, and filter an optimal voltage offset from the plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capability max_ecc and the average error correction capability mean_ecc.
In an embodiment, the erasure parameter extracting unit 230 is further configured to extract chip erasure parameters of the NAND flash under each operation scenario, each error correction level and the optimal voltage offset.
In an embodiment, the quality classification unit 240 is further configured to perform quality classification on the NAND flash memory under each operation scene according to the chip entanglement parameters.
In an embodiment, the quality classification unit 240 is further configured to compare the chip entanglement parameter with a preset entanglement parameter to obtain a comparison result; and classifying the quality of the NAND flash memory according to the comparison result.
It should be noted that, since the NAND flash memory quality classification device 200 of the embodiment of the present application corresponds to the NAND flash memory quality classification method of any one of the embodiments described above, reference may be made to the specific implementation and technical effects of the NAND flash memory quality classification device 200 of any one of the embodiments described above.
The apparatus embodiments described above are merely illustrative, in which modules illustrated as separate components may or may not be physically separate, i.e., may be located in one place, or may be distributed over multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules described above is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
The modules described above as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules.
In addition, an embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions for performing the NAND flash quality classification method described above. Illustratively, the method steps in fig. 1-10 described above are performed.
It should be noted that, since the computer readable storage medium of the embodiment of the present application can perform the NAND flash memory quality classification method of any one of the embodiments described above, reference may be made to the specific implementation and technical effects of the NAND flash memory quality classification method of any one of the embodiments described above.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and may include any information delivery media.
According to the NAND flash quality grading method, the electronic equipment, the NAND flash quality grading device and the storage medium, chip correction parameters of the NAND flash under each error correction level and the optimal voltage offset can be obtained, and quality grading is carried out based on the chip correction parameters.
The embodiments described in the embodiments of the present application are for more clearly describing the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application, and as those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.
It will be appreciated by those skilled in the art that the technical solutions shown in the figures do not constitute limitations of the embodiments of the present application, and may include more or fewer steps than shown, or may combine certain steps, or different steps.
Those of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.
The terms "first," "second," "third," "fourth," and the like in the description of the present application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
While the preferred embodiments of the present application have been described in detail, the present application is not limited to the above embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit and scope of the present application, and these equivalent modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (7)
1. A method for quality classification of NAND flash memory, comprising:
acquiring a plurality of error correction levels and a plurality of voltage offsets, and extracting the maximum codeword max_cw of all pages of the NAND flash memory;
for each error correction level, determining the total number of pages corresponding to the error correction level, counting the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc of each voltage offset under the total number of the pages, and screening out the optimal voltage offset from a plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc;
extracting chip correction parameters of the NAND flash under each error correction level and the optimal voltage offset;
performing quality classification on the NAND flash memory according to the chip entanglement parameters;
wherein said selecting an optimal voltage offset from a plurality of said voltage offsets based on said maximum codeword max_cw, said maximum error correction capability max_ecc, and said average error correction capability mean_ecc comprises:
screening a plurality of candidate voltage offset values from a plurality of voltage offset values according to the maximum codeword max_cw and the maximum error correction capability max_ecc of each voltage offset value under the total number of pages;
Screening the optimal voltage offset from a plurality of candidate voltage offsets according to the average error correction capability mean_ecc of each voltage offset under the total number of pages;
wherein, according to the maximum codeword max_cw and the maximum error correction capability max_ecc of each voltage offset under the total number of pages, a plurality of candidate voltage offsets are screened from a plurality of voltage offsets, including at least one of the following:
discarding the voltage offset when the maximum codeword max_cw is greater than or equal to the maximum error correction capability max_ecc;
when the maximum codeword max_cw is smaller than the maximum error correction capability max_ecc, reserving the voltage offset, and taking the voltage offset as a candidate voltage offset;
wherein the selecting, according to the average error correction capability mean_ecc of each voltage offset under the total number of pages, an optimal voltage offset from a plurality of candidate voltage offsets includes:
sorting the average error correction capability mean_eccs of each voltage offset under the total number of pages according to the numerical value to obtain a plurality of sorted average error correction capability mean_eccs;
And screening the average error correction capability mean_eccs with the smallest value from the plurality of average error correction capability mean_eccs, and taking the candidate voltage offset corresponding to the average error correction capability mean_eccs with the largest value as the optimal voltage offset.
2. The NAND flash quality classification method of claim 1, characterized in that before said counting the maximum error correction capability max_ecc and the average error correction capability mean_ecc for each of said voltage offsets under said total number of pages, said NAND flash quality classification method further comprises:
acquiring a voltage offset limit value;
when the voltage offset is smaller than the voltage offset limit value, reserving the voltage offset;
and discarding the voltage offset when the voltage offset is greater than or equal to the voltage offset limit value.
3. The NAND flash quality classification method of claim 1, wherein after the acquiring a plurality of error correction levels and a plurality of voltage offsets, the NAND flash quality classification method further comprises:
and preprocessing the data of the NAND flash memory to convert unstructured data into structured data.
4. The NAND flash quality grading method of claim 1 wherein said counting a maximum error correction capability max_ecc and an average error correction capability mean_ecc for each of said voltage offsets for said total number of pages, and screening an optimal voltage offset from a plurality of said voltage offsets based on said maximum codeword max_cw, said maximum error correction capability max_ecc and said average error correction capability mean_ecc comprises: calculating the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc of each voltage offset in the total number of pages and each operation scene, and screening the optimal voltage offset from a plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc;
The extracting the chip erasure parameters for each of the error correction levels and the optimal voltage offset for the NAND flash includes: extracting chip correction parameters of the NAND flash under each operation scene, each error correction level and the optimal voltage offset;
the quality grading of the NAND flash memory according to the chip entanglement parameter includes: and carrying out quality classification on the NAND flash memory under each operation scene according to the chip entanglement parameters.
5. The method for quality classification of NAND flash memory according to claim 1, wherein said quality classification of the NAND flash memory according to the chip entanglement parameter comprises:
comparing the chip entanglement parameter with a preset entanglement parameter to obtain a comparison result;
and carrying out quality grading on the NAND flash memory according to the comparison result.
6. A NAND flash quality grading device, comprising:
the data acquisition unit is used for acquiring a plurality of error correction levels and a plurality of voltage offsets and extracting the maximum codeword max_cw of all pages of the NAND flash memory;
an offset screening unit, configured to determine, for each error correction level, a total number of pages corresponding to the error correction level, count a maximum error correction capacity max_ecc and an average error correction capacity mean_ecc of each voltage offset under the total number of pages, and screen an optimal voltage offset from a plurality of voltage offsets according to the maximum codeword max_cw, the maximum error correction capacity max_ecc and the average error correction capacity mean_ecc;
A correction parameter extraction unit for extracting a chip correction parameter of the NAND flash under each error correction level and the optimal voltage offset;
the quality grading unit is used for grading the quality of the NAND flash memory according to the chip entanglement parameter;
wherein said selecting an optimal voltage offset from a plurality of said voltage offsets based on said maximum codeword max_cw, said maximum error correction capability max_ecc, and said average error correction capability mean_ecc comprises:
screening a plurality of candidate voltage offset values from a plurality of voltage offset values according to the maximum codeword max_cw and the maximum error correction capability max_ecc of each voltage offset value under the total number of pages;
screening the optimal voltage offset from a plurality of candidate voltage offsets according to the average error correction capability mean_ecc of each voltage offset under the total number of pages;
wherein, according to the maximum codeword max_cw and the maximum error correction capability max_ecc of each voltage offset under the total number of pages, a plurality of candidate voltage offsets are screened from a plurality of voltage offsets, including at least one of the following:
Discarding the voltage offset when the maximum codeword max_cw is greater than or equal to the maximum error correction capability max_ecc;
when the maximum codeword max_cw is smaller than the maximum error correction capability max_ecc, reserving the voltage offset, and taking the voltage offset as a candidate voltage offset;
wherein the selecting, according to the average error correction capability mean_ecc of each voltage offset under the total number of pages, an optimal voltage offset from a plurality of candidate voltage offsets includes:
sorting the average error correction capability mean_eccs of each voltage offset under the total number of pages according to the numerical value to obtain a plurality of sorted average error correction capability mean_eccs;
and screening the average error correction capability mean_eccs with the smallest value from the plurality of average error correction capability mean_eccs, and taking the candidate voltage offset corresponding to the average error correction capability mean_eccs with the largest value as the optimal voltage offset.
7. A computer-readable storage medium storing computer-executable instructions for performing the NAND flash quality classification method of any one of claims 1 to 5.
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| WO2023047149A1 (en) * | 2021-09-23 | 2023-03-30 | Micron Technology, Inc. | Improved ecc configuration in memories |
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