CN116681752A - Method and device for calculating void ratio of void defects of DBC solder layer - Google Patents

Method and device for calculating void ratio of void defects of DBC solder layer Download PDF

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CN116681752A
CN116681752A CN202310966656.8A CN202310966656A CN116681752A CN 116681752 A CN116681752 A CN 116681752A CN 202310966656 A CN202310966656 A CN 202310966656A CN 116681752 A CN116681752 A CN 116681752A
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dbc
solder layer
void
image
area
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CN116681752B (en
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仉曾祥
侯杰仁
薛永康
张泞铄
张一铭
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Shandong Mokron Intelligent Technology Co ltd
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Shandong Mokron Intelligent Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/60—Analysis of geometric attributes
    • G06T7/62—Analysis of geometric attributes of area, perimeter, diameter or volume
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/04—Analysing solids
    • G01N29/06—Visualisation of the interior, e.g. acoustic microscopy
    • G01N29/0654—Imaging
    • G01N29/0681—Imaging by acoustic microscopy, e.g. scanning acoustic microscopy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/12—Edge-based segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/136—Segmentation; Edge detection involving thresholding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/40—Analysis of texture
    • G06T7/41—Analysis of texture based on statistical description of texture
    • G06T7/44—Analysis of texture based on statistical description of texture using image operators, e.g. filters, edge density metrics or local histograms
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N2291/00—Indexing codes associated with group G01N29/00
    • G01N2291/02—Indexing codes associated with the analysed material
    • G01N2291/028—Material parameters
    • G01N2291/0289—Internal structure, e.g. defects, grain size, texture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10132—Ultrasound image
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30152—Solder

Abstract

The invention relates to a method and a device for calculating void ratio of a DBC solder layer void defect. Providing a DBC solder layer ultrasonic image, and performing contour extraction on a DBC solder layer region image in the DBC solder layer ultrasonic image to generate a DBC solder layer segmentation image after contour extraction; searching a cavity area with cavity defects in the ultrasonic image of the DBC solder layer; and determining the void ratio of the current ultrasonic image of the DBC solder layer based on the ultrasonic image of the DBC solder layer and the searched void area, wherein the void ratio comprises the total void ratio of the whole solder layer. The method can quickly and effectively realize the void ratio calculation of the void defects of the DBC solder layer, and meets the detection requirement of the solder layer on the DBC on the industrial assembly line.

Description

Method and device for calculating void ratio of void defects of DBC solder layer
Technical Field
The invention relates to a void ratio calculating method and device, in particular to a void ratio calculating method and device for a void defect of a DBC solder layer.
Background
The ultrasonic scanning imaging is an image obtained by analyzing and processing by utilizing different propagation characteristics of ultrasonic waves in different media through an ultrasonic microscope, and can be used for detecting impurity particles, impurities, sediment, cavities, bubble gaps and the like of materials.
In the packaging field of power semiconductor devices, DBC (Dircet Bonding Copper) is often required, and when packaging is performed by using DBC, a solder layer is generally required to be prepared on the DBC, but the solder layer on the DBC may have defects such as voids due to the preparation process and the like.
At present, detection of a hole of a solder layer on a DBC mainly depends on manual observation, during manual observation, an ultrasonic image of the DBC solder layer is manually adjusted to a proper binarization extraction threshold value to extract a white area where the hole is located in the image, and due to the fact that the hole part is smaller, only a few pixels exist, gray areas exist at the edge of the DBC, manual frame selection is influenced by burrs at the edge of the DBC, and the like, a plurality of problems of uneven judgment standards, time and labor waste, high accuracy and the like exist by means of human eye judgment, and more energy is consumed to complete detection tasks during mass production.
In addition, the research on the detection algorithm of the defects of the solder layer on the DBC is less at present, and the detection algorithm is difficult to label small defects of only a few pixels when a general image segmentation model is directly labeled, so that the labeling cost is high; when the common segmentation and detection models Unet, yolo and the like are applied to an industrial pipeline, the reasoning speed of the method is also greatly limited compared with that of the traditional algorithm; in addition to cost control of the industrial pipeline, ultrahigh standard requirements on the model IOU and accuracy are caused, and many deep learning models often have unsatisfactory effects.
In summary, on an industrial assembly line, how to effectively realize the rapid and effective calculation of the void ratio of the DBC solder layer under the defect is a technical problem which needs to be solved urgently at present.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a method and a device for calculating the void ratio of the void defect of a DBC solder layer, which can quickly and effectively calculate the void ratio of the void defect of the DBC solder layer and meet the detection requirement of the solder layer on the DBC on an industrial assembly line.
According to the technical scheme provided by the invention, the void ratio calculating method for the void defects of the DBC solder layer comprises the following steps:
providing a DBC solder layer ultrasonic image, wherein the DBC solder layer ultrasonic image at least comprises a DBC solder layer area image corresponding to a solder layer;
performing contour extraction on a DBC solder layer region image in a DBC solder layer ultrasonic image to generate a DBC solder layer segmentation image after contour extraction, wherein the DBC solder layer segmentation image comprises a DBC solder layer region and a non-DBC solder layer region positioned on the outer ring of the DBC solder layer region, and the DBC solder layer region comprises a DBC solder layer edge contour and a solder layer positioned in the DBC solder layer edge contour;
searching a cavity area with cavity defects in the ultrasonic image of the DBC solder layer;
and determining the void ratio of the current ultrasonic image of the DBC solder layer based on the ultrasonic image of the DBC solder layer and the searched void area, wherein the void ratio comprises the total void ratio of the whole solder layer.
The DBC solder layer region further comprises a subarea dividing line for separating two adjacent DBC subareas, so that a plurality of DBC subareas are formed in the DBC solder layer region by utilizing the subarea dividing line;
when searching for a cavity area, determining a DBC subarea where any cavity area is located;
the void ratio of the current DBC solder layer ultrasonic image also comprises the void ratio of the sub-region of the solder layer corresponding to each DBC sub-region.
When the DBC solder layer area image is subjected to contour extraction to generate a DBC solder layer segmentation image, the method comprises a coarse screening processing step and a fine screening processing step which are sequentially carried out, wherein,
in the coarse screening treatment step, binarizing treatment is carried out on the ultrasonic image of the DBC solder layer, morphological open operation is carried out after the binarization treatment, and a DBC solder layer segmentation image is generated after the open operation;
in the fine screening process step, the DBC solder layer region obtained in the coarse screening process step is processed to obtain a sub-region dividing line for separating two adjacent DBC sub-regions in the DBC solder layer region.
The step of coarse screening treatment, when binarizing the ultrasonic image of the DBC solder layer, obtaining an ultrasonic binarized image of the DBC solder layer, wherein the ultrasonic binarized image of the DBC solder layer comprises the following steps:
；
wherein ,is the DBC solder layer in the ultrasonic image>Gray value of dot pixel +.>Inside the ultrasound binary image for DBC solder layer +.>Gray value after point pixel binarization processing, < >>、/>A binary division threshold value is generated based on the gray value distribution state of the DBC solder layer ultrasonic image.
When morphological open operation is carried out, the operation core of the morphological open operation comprises an open operation square core, wherein,
the size of the open operation square kernel is 12 dimensions.
The fine screening treatment step comprises the following steps:
performing horizontal projection on the ultrasonic binary image of the DBC solder layer to obtain a horizontal projection matrixThe method comprises the steps of carrying out a first treatment on the surface of the Horizontal projection matrix->Performing gradient calculation to obtain gradient matrix +.>；
In step sizeTraversing gradient matrix->If in a step +.>Positive peak value and negative peak value are simultaneously present in the main frame, and the absolute value of the positive peak value or the absolute value of the negative peak value is larger than the peak value threshold +.>When the method is used, taking the mean value of the position of the positive peak value and the position of the negative peak value as the ordinate value of the boundary, and generating a subarea boundary based on the ordinate value of the boundary;
and dividing the DBC solder layer into a plurality of mask areas by taking the generated subarea boundary as a boundary, and carrying out morphological closing operation on each mask area to obtain a plurality of DBC subareas positioned in the DBC solder layer area, wherein adjacent DBC subareas are separated by the subarea boundary.
Each DBC sub-region is subjected to a masking boundary burring process, wherein,
when shielding boundary burr treatment is carried out, carrying out morphological corrosion operation on each DBC subarea, wherein an operation core of the morphological corrosion operation comprises a corrosion operation square core;
the size of the corrosion operation square kernel is 3 dimensions.
When searching for a cavity area in the DBC solder layer, performing dynamic binary segmentation on the ultrasonic image of the DBC solder layer to form an ultrasonic dynamic binary segmentation image of the DBC solder layer, wherein the dynamic binary segmentation comprises:
；
wherein ,is the DBC solder layer in the ultrasonic image>Gray value of dot pixel +.>Is the DBC solder layer in the ultrasonic image>Gray value of dynamic binarization of dot pixels,>dividing threshold for dynamic binarization, +.>、/>Dividing threshold coefficients for dynamic binarization, +.>To->Preset area centered on point->A mean value of the set of included pixels;
on the DBC solder layer ultrasonic dynamic binary segmentation image, all gray valuesThe position or area where 255 is located is a void area where void defects exist.
For the total void fraction, there are:
；
wherein ,for total void fraction, ++>Is the area of the hollow area>For the pixel area of the DBC solder layer region, < >>Is an intersection operation;
the subzone void ratio is as follows:
；
wherein ,for the subzone void fraction, & lt + & gt>For the pixel area of the DBC subregion, +.>Is the area of the sub-area cavity area in the DBC sub-areaAccumulation of pathogenic qi>Is an intersection operation.
A device for calculating the void ratio of a void defect of a DBC solder layer is characterized by comprising a void ratio calculating processor for calculating the void ratio, wherein,
and for any DBC solder layer ultrasonic image, the void ratio calculation processor calculates the void ratio by adopting the method.
The invention has the advantages that: the DBC solder layer ultrasonic image is segmented to obtain a DBC solder layer segmentation image, and a DBC solder layer region can be accurately obtained; the dynamic binarization segmentation is carried out on the DBC solder layer ultrasonic image, so that the searching and the determination of the cavity area can be realized, the defect quantification of the lowest single pixel can be realized when the cavity area is searched by adopting a dynamic binarization mode, and the corresponding actual cavity area is about 0.01A variety of adjustable interpretable parameter thresholds accommodate complex production environments on a pipeline. Based on the DBC solder layer area obtained by segmentation and the void area obtained by searching, the total void ratio and/or the sub-area void ratio can be calculated, namely, the void ratio calculation of the void defect of the DBC solder layer can be rapidly and effectively realized, and the detection requirement of the solder layer on the DBC on the industrial assembly line is met.
Drawings
Fig. 1 is a flowchart of void fraction calculation according to an embodiment of the present invention.
FIG. 2 is a schematic representation of an ultrasonic image of a DBC solder layer in accordance with an embodiment of the present invention.
FIG. 3 is a schematic diagram of a DBC solder layer segmented image according to an embodiment of the present invention.
FIG. 4 is a schematic illustration of a DBC solder layer segment image including sub-region boundaries according to an embodiment of the present invention.
FIG. 5 is a schematic diagram of a search for a determined hole area in an embodiment of the present invention.
Fig. 6 is a schematic illustration of the determination of void area within the DBC solder layer region depicted in fig. 5.
FIG. 7 is a schematic diagram of a gray value histogram of an ultrasonic image of a DBC solder layer in accordance with an embodiment of the present invention.
FIG. 8 is a schematic representation of a forward gradient in an embodiment of the invention.
FIG. 9 is a schematic representation of a negative gradient in an embodiment of the invention.
Reference numerals illustrate: 10. a non-DBC solder layer region; 20. a DBC solder layer region; 30. dividing lines of subareas; 40. a void region; 50. DBC subregion.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
In order to quickly and effectively realize the calculation of the void ratio of the void defect of the DBC solder layer, and meet the detection requirement of the solder layer on the DBC on an industrial production line, the calculation method of the void ratio of the void defect of the DBC solder layer comprises the following steps:
providing a DBC solder layer ultrasonic image, wherein the DBC solder layer ultrasonic image at least comprises a DBC solder layer area image corresponding to a solder layer;
performing contour extraction on a DBC solder layer region image in a DBC solder layer ultrasonic image to generate a DBC solder layer segmentation image after contour extraction, wherein the DBC solder layer segmentation image comprises a DBC solder layer region 20 and a non-DBC solder layer region 10 positioned on the outer ring of the DBC solder layer region, and the DBC solder layer region 20 comprises a DBC solder layer edge contour and a solder layer positioned in the DBC solder layer edge contour;
searching for a cavity region 40 having a cavity defect in the ultrasonic image of the DBC solder layer;
based on the inside of the ultrasonic image of the DBC solder layer and the searched void area 40, the void ratio of the ultrasonic image of the current DBC solder layer is determined, wherein the void ratio comprises the total void ratio of the whole solder layer.
Fig. 1 shows a flowchart of an embodiment of the present invention when the cavitation is calculated, and as can be seen from fig. 1, it is necessary to provide an ultrasonic image of the DBC solder layer first when the cavitation is calculated.
An exemplary embodiment of a DBC solder layer ultrasound image is shown in fig. 2, and the DBC solder layer ultrasound image may be generally obtained by scanning a DBC board with a conventional ultrasonic scanning imaging device, and the manner and process of specifically obtaining or generating the DBC solder layer ultrasound image may be consistent with the conventional method, so as to obtain the desired DBC solder layer ultrasound image.
The DBC board generally comprises a ceramic substrate and copper foil layers arranged on the ceramic substrate, wherein the number of the copper foil layers on the ceramic substrate is generally multiple, and the copper foil layers are adjacently and correspondingly distributed on the ceramic substrate, so that the specific condition of the DBC board can be consistent with the prior art. The solder layer is generally coated or disposed on the copper foil layer, and the manner and process of preparing the solder layer on the copper foil layer may be consistent with the prior art. And the DBC solder layer void defect is the void defect existing on the prepared solder layer. Therefore, the ultrasonic image of the DBC solder layer includes at least an image of the DBC solder layer region corresponding to the solder layer, that is, at least an area where the solder layer on the ceramic substrate is located needs to be subjected to ultrasonic scanning imaging, and at this time, in the ultrasonic image of the DBC solder layer, the image of the DBC solder layer region corresponds to the solder layer, specifically, the image of the DBC solder layer region includes at least all the solder layers.
Generally, the image of the entire DBC board is included in the ultrasonic image of the DBC solder layer, as shown in fig. 2, and in fig. 2, the DBC solder layer region 20 and the non-DBC solder layer region 10 are included, wherein the DBC solder layer region 20 is a region covered by the solder layer, and the non-DBC solder layer region 10 is a region not including the solder layer, such as a ceramic substrate and a region outside the solder layer on the ceramic substrate.
For the provided ultrasonic image of the DBC solder layer, contour extraction is required for the DBC solder layer region, and after contour extraction, a DBC solder layer segmentation image can be generated/obtained. As can be seen from the above description, the DBC solder layer division image includes a DBC solder layer region 20 and a non-DBC solder layer region 10 located at the outer periphery of the DBC solder layer region, one embodiment of the DBC solder layer division image is shown in fig. 3, and as can be seen from fig. 2 and 3, the white region is the DBC solder layer region 20, and the black region is the non-DBC solder layer region 10.
As can be seen from the above description, the DBC solder layer region 20 in the DBC solder layer division image generally includes a DBC solder layer edge profile, and in fig. 3, the boundary line between the white region and the black region is the DBC solder layer edge profile, and of course, the region position where the solder layer is located in fig. 2 is within the DBC solder layer edge profile.
As can be seen from the above description, the ceramic substrate generally includes at least two copper foil layers, which are adjacent to and independent of each other on the ceramic substrate. Thus, the DBC solder layer region 20 may be further processed, in which case the DBC solder layer region 20 further comprises a sub-region dividing line 30 for separating two adjacent DBC sub-regions 50, so that a number of DBC sub-regions 50 are formed separately in the DBC solder layer region 20 by means of said sub-region dividing line 30, as shown in fig. 4. The DBC sub-region 50 is the location area where the copper foil layer is located.
In the ultrasonic image of the DBC solder layer, it is necessary to search for the void region 40 in which the void defect is determined to exist. When searching the hole area 40, the DBC sub-area 50 where any hole area 40 is located may also be determined according to the position of the hole area 40. Therefore, based on the DBC solder layer division image, the searched cavity area 40 and the DBC sub-area 50 where the cavity area 40 is located, the cavity rate of the current DBC solder layer ultrasonic image is determined, where the cavity rate includes the total cavity rate of the entire solder layer and/or the sub-area cavity rate of the solder layer corresponding to each DBC sub-area 50.
In one embodiment of the invention, when the profile extraction is carried out on the DBC solder layer region image to generate the DBC solder layer segmentation image, the method comprises a coarse screening processing step and a fine screening processing step which are sequentially carried out, wherein,
in the coarse screening treatment step, binarizing treatment is carried out on the ultrasonic image of the DBC solder layer, morphological open operation is carried out after the binarization treatment, and a DBC solder layer segmentation image is generated after the open operation;
in the fine screening process step, the DBC solder layer region 20 obtained in the coarse screening process step is processed to obtain a sub-region dividing line 30 for separating two adjacent DBC sub-regions 50 within the DBC solder layer region 20.
Specifically, the DBC solder layer ultrasonic images are sequentially processed by the rough screening process step and the fine screening process step, after which the DBC solder layer divided images can be obtained, and after the fine screening process, the sub-region dividing line 30 can be further obtained. The course of the coarse screening process step and the fine screening process step will be specifically described in detail below.
In one embodiment of the present invention, when the step of coarse screening is performed to binarize the ultrasonic image of the DBC solder layer, an ultrasonic binarized image of the DBC solder layer is obtained, and the step of performing binarization on the ultrasonic image of the DBC solder layer includes:
；
wherein ,is the DBC solder layer in the ultrasonic image>Gray value of dot pixel +.>Inside the ultrasound binary image for DBC solder layer +.>Gray value after point pixel binarization processing, < >>、/>A binary division threshold value is generated based on the gray value distribution state of the DBC solder layer ultrasonic image.
In particular, the method comprises the steps of,、/>ultrasonic imaging for DBC solder layerX-axis coordinates and y-axis coordinates of the pixel points in the pixel coordinate system. When binarizing an ultrasonic image of a DBC solder layer, it is necessary to first arrange a binarization division threshold value +.>Binarized segmentation threshold +.>. In determining the binarized segmentation threshold +.>Binarized segmentation threshold +.>In this case, the gray value distribution of pixels in the ultrasonic image of the DBC solder layer may be counted in the form of a histogram, etc., as shown in fig. 7, which shows a histogram of the gray value distribution, and in fig. 7, the abscissa represents the gray value and the ordinate represents the number of pixels of the gray value. From the gray value distribution histogram, the interval of gray value concentrated distribution can be determined, and in fig. 7, the interval of gray value concentrated distribution is 71 to 118, and at this time, there are: />，/>。
When the pixel gray value in the ultrasonic image of the DBC solder layer is other, the corresponding binary segmentation threshold value can be obtained by referring to the above descriptionBinarized segmentation threshold +.>After that, binarization processing can be performed in the above-described manner to obtain an ultrasonic binarized image of the DBC solder layer.
In one embodiment of the present invention, when performing a morphological open operation, the operation core of the morphological open operation includes an open operation square core, wherein,
the size of the open operation square kernel is 12 dimensions.
Specifically, the method is mainly used for eliminating boundary noise when morphological open operation is carried out on the ultrasonic binary image of the DBC solder layer. The size of the open operation square kernel is 12 dimensions, specifically, the open operation square kernel can be characterized as a 12-order square matrix, of course, the size of the open operation square kernel can also take other dimensions, and can be specifically selected according to requirements. The method and process of performing morphological open operation on the ultrasonic binary image of the DBC solder layer by using the open operation square check can be consistent with the prior art, and will not be repeated here.
In one embodiment of the present invention, the fine screening processing step includes:
performing horizontal projection on the ultrasonic binary image of the DBC solder layer to obtain a horizontal projection matrix；
For horizontal projection matrixPerforming gradient calculation to obtain gradient matrix +.>；
In step sizeTraversing gradient matrix->If in a step +.>Positive peak value and negative peak value are simultaneously present in the main frame, and the absolute value of the positive peak value or the absolute value of the negative peak value is larger than the peak value threshold +.>When the peak value is in the positive peak position and the peak value is in the negative peak position, the average value is taken as the ordinate value of the boundary line, and the boundary line is based onGenerates a subregion boundary 30;
with the generated sub-region dividing line 30 as a boundary, dividing the DBC solder layer region 20 into a plurality of mask regions, and performing morphological closing operation on each mask region to obtain a plurality of DBC sub-regions 50 located in the DBC solder layer region, wherein adjacent DBC sub-regions 50 are separated by the sub-region dividing line 30.
Specifically, in the horizontal projection, specifically, the ultrasonic binary image of the DBC solder layer after morphological open operation is subjected to horizontal projection, and after the horizontal projection, the horizontal projection matrix is subjected to horizontal projectionThe following steps are: />，/>An example of the ultrasonic binary image of the DBC solder layer is shown in fig. 3, which is the gray scale value of the ultrasonic binary image of the DBC solder layer after morphological open operation. In horizontal projection, i.e. the gray values of all pixels in the same row in the pixel coordinate system are accumulated, then the horizontal pixel matrix is +.>For column vectors, horizontal pixel matrix +.>The number of lines of the ultrasonic binary image of the DBC solder layer is consistent with the number of lines of the ultrasonic binary image of the DBC solder layer.
For horizontal projection matrixWhen gradient calculation is performed, the following steps are: />The method comprises the steps of carrying out a first treatment on the surface of the Thus, the calculated gradient matrix +.>Also column vector, gradient matrix->Row number ratio horizontal projection matrix->One less line number. />There is->，/>Namely gradient matrix->The first element in->For the first element in the horizontal projection matrix, < +.>For the second element in the horizontal projection matrix, < >>For other values, reference is made to the description here, so that in determining the horizontal projection matrix +.>After that, a gradient matrix can be obtained>。
Step sizeTraversing gradient matrix->In particular the gradient matrix>Inner firstThe elements traverse towards the last element, the positive peak value specifically means increasing the gradient and appearing the peak value, the negative peak value specifically means decreasing the gradient and appearing the peak value, and at the moment, the positive peak value is namely in the gradient matrix +.>The element values in the matrix increase and peak occurs, the negative peak is in the gradient matrix +.>The element values within become smaller and peaks appear.
Step sizeThe selection of the gradient matrix can be made according to the distance to the minimum of the ordinate of the positive and negative peaks, e.g. 25, at which time the initial traversal is chosen>The first element and the 25 th element in the tree are used for judging whether positive peak values and negative peak values exist at the same time, and the other traversing conditions are sequentially carried out according to the initial traversing conditions until a gradient matrix is->The traversal is complete.
For peak threshold valueIn particular in the gradient matrix +.>In, the minimum absolute value of the peak value at the dividing line can be clamped; and takes the mean of the positions of the positive peak and the negative peak as the ordinate value of the boundary point, at this time, the sub-region dividing line 30 is generated based on the ordinate value of the dividing line, as shown in fig. 4.
Gradient matrix is shown in fig. 8 and 9In FIGS. 8 and 9The abscissa is the gradient matrix->Is the gradient matrix on the ordinate>The gradient magnitude of the inner element, i.e. gradient matrix +.>At this time, gradient matrices ++are shown in FIGS. 8 and 9>600 rows. Gradient matrix +.from FIGS. 8 and 9>The value of the internal element can be set to be the peak threshold +.>. In practice, the same peak threshold value is generally selected for the same batch of DBC solder layer ultrasonic images>。
Using the sub-area dividing line 30 as a boundary, the DBC solder layer area 20 may be divided into a plurality of mask areas, and the mask areas may be subjected to a morphological closing operation to close the boundary by using the morphological closing operation, and at this time, a corresponding DBC sub-area 50 may be obtained. In the morphological closing operation, the morphological closing operation also adopts a closing operation square kernel, and the size of the closing operation square kernel can be 21 dimensions, namely, the closing operation square kernel is a 21-order square matrix.
After obtaining the sub-region dividing line 30 and the DBC sub-region 50, it further includes: each DBC sub-region 50 is subjected to a masking boundary burring process, wherein,
performing morphological erosion operation on each DBC subregion 50 when performing shielding boundary burr treatment, wherein operation cores of the morphological erosion operation comprise erosion operation square cores;
the size of the corrosion operation square kernel is 3 dimensions.
From the above description, the size of the corrosion operation square kernel is 3 dimensions, specifically, the corrosion operation square kernel may be characterized as a 3-order square matrix, and of course, the corrosion operation square kernel may also take the size of other dimensions, which may be specifically selected according to needs. According to the corrosion operation square kernel, shielding boundary burr treatment can be performed by a morphological corrosion operation mode commonly used in the technical field, and the specific process can be consistent with the prior art and is not repeated here.
In one embodiment of the present invention, when searching for the void area 40 in the DBC solder layer, dynamic binary segmentation is performed on the DBC solder layer ultrasonic image to form a DBC solder layer ultrasonic dynamic binary segmented image, the dynamic binary segmentation comprising:
；
wherein ,is the DBC solder layer in the ultrasonic image>Gray value of dot pixel +.>Is the DBC solder layer in the ultrasonic image>Gray value of dynamic binarization of dot pixels,>dividing threshold for dynamic binarization, +.>、/>Dividing threshold coefficients for dynamic binarization, +.>To->Preset area centered on point->A mean value comprising a set of pixels;
on the DBC solder layer ultrasonic dynamic binary segmentation image, all gray valuesThe location or region where 255 is located is the void region 40 where void defects exist.
The cavity area 40 with cavity defects is searched for in the provided or acquired ultrasonic image of the DBC solder layer, and the specific situation of the cavity defects and the cavity area 40 can be consistent with the prior art. In one embodiment of the present invention, the search hole area 40 is segmented in a dynamic binary manner. In dynamic binary segmentation, a dynamic binary segmentation threshold value needs to be determined. Coefficients ofThe value range of (2) is 0.5-1.5; the value range of the coefficient b can be 0-255.
For a preset areaGenerally, a square matrix is selected, and the center of the preset area is +.>Point, preset areaThe size of (2) can be selected according to the need, for example, a 51-dimensional square array can be selected, i.e., the preset area +.>A pixel size area of 51×51.
In determining dynamic binary segmentation thresholdThen, dynamic binary segmentation is performed on the ultrasonic image of the DBC solder layer, and a dynamic binary segmentation image of the ultrasonic image of the DBC solder layer is formed, as shown in FIGS. 5 and 6.
For the hollow area 40, it can be generally: gray scale valueA pixel of 255, or a plurality of gray valuesA connection region constituted by 255 pixels.
In the DBC solder layer ultrasonic dynamic binarized divided image, there may be a gray value of 255 in the non-DBC solder layer region 10, but in calculating the void ratio, the void region 40 can be a region in which the gray value of 255 is 255 in the DBC solder layer region 20, and thus, in fig. 6, the void region 40 necessary for calculating the void ratio is green-filled in the region in which the gray value of 255 is 255 in the DBC solder layer region 20.
In one embodiment of the present invention, for the total void fraction, there are:
；
wherein ,for total void fraction, ++>For the pixel area of the hollow area 40 +.>For the pixel area of the DBC solder layer region 20, < >>Is an intersection operation;
the subzone void ratio is as follows:
；
wherein ,for the subzone void fraction, & lt + & gt>For the pixel area of the DBC sub-area 50, < >>For the area of the sub-area void area within said DBC sub-area 50,>is an intersection operation.
In practice, the intersection of the DBC solder layer region 20 and the cavity region 40 can be determined by using the bitwise_and function of opencv. Using the count_nonzero function in numpy, the number of non-zero pixels of the intersection mask image can be quickly calculated, resulting in the pixel area of the hole area 40. numpy is a third party application toolkit commonly used in python, and the details of numpy are consistent with the prior art.
Thus, after obtainingAnd the pixel area of the void area 40, the total void fraction and the sub-region void fraction can be calculated using the above formula.
In summary, a device for calculating the void fraction of a DBC solder layer void defect is provided, which in one embodiment of the invention comprises a void fraction calculation processor for the void fraction calculation process, wherein,
and for any DBC solder layer ultrasonic image, the void ratio calculation processor calculates the void ratio by adopting the method.
Specifically, the cavitation rate calculation processor may take the form of a conventional device, such as a computer, and the specific type may be selected as required. The manner and process of the void fraction calculation by the void fraction calculation processor may be referred to the above description, and will not be repeated here.
The DBC solder layer ultrasonic image is segmented to obtain a DBC solder layer segmented image, so that the DBC solder layer region 20 can be accurately obtained; by dynamically binarizing and dividing the ultrasonic image of the DBC solder layer, the searching and determining of the cavity area 40 can be realized, and when the cavity area is searched by adopting a dynamic binarizing mode, the cavity defect quantification of the lowest single pixel can be realized, and the corresponding actual cavity area is about 0.01A variety of adjustable interpretable parameter thresholds accommodate complex production environments on a pipeline. Based on the DBC solder layer area 20 obtained by segmentation and the void area 40 obtained by searching, the total void ratio and/or the sub-area void ratio can be calculated, namely, the void ratio calculation of the void defect of the DBC solder layer can be rapidly and effectively realized, and the detection requirement of the solder layer on the DBC on the industrial assembly line is met.
For the edge of the DBC solder layer region 20, the rough screening process and the fine screening process described above have a higher IOU (cross over ratio, intersection over Union) result to 1 pixel width, corresponding to an actual width of about 1.6The method comprises the steps of carrying out a first treatment on the surface of the The accuracy of the defect alignment actual cavity area is more than 99.95%, and the defect quantification effect is better than that of manual selection from the aspects of accuracy and standard uniformity.

Claims (10)

1. The method for calculating the void ratio of the void defect of the DBC solder layer is characterized by comprising the following steps:
providing a DBC solder layer ultrasonic image, wherein the DBC solder layer ultrasonic image at least comprises a DBC solder layer area image corresponding to a solder layer;
performing contour extraction on a DBC solder layer region image in a DBC solder layer ultrasonic image to generate a DBC solder layer segmentation image after contour extraction, wherein the DBC solder layer segmentation image comprises a DBC solder layer region and a non-DBC solder layer region positioned on the outer ring of the DBC solder layer region, and the DBC solder layer region comprises a DBC solder layer edge contour and a solder layer positioned in the DBC solder layer edge contour;
searching a cavity area with cavity defects in the ultrasonic image of the DBC solder layer;
and determining the void ratio of the current ultrasonic image of the DBC solder layer based on the ultrasonic image of the DBC solder layer and the searched void area, wherein the void ratio comprises the total void ratio of the whole solder layer.
2. The method of claim 1, further comprising dividing the DBC solder layer region by a sub-region dividing line for separating two adjacent DBC sub-regions, wherein the sub-region dividing line is used to divide the DBC solder layer region into a plurality of DBC sub-regions;
when searching for a cavity area, determining a DBC subarea where any cavity area is located;
the void ratio of the current DBC solder layer ultrasonic image also comprises the void ratio of the sub-region of the solder layer corresponding to each DBC sub-region.
3. The method for calculating the void fraction of DBC solder layer void defects according to claim 2, wherein the step of generating the DBC solder layer segment image by extracting the profile of the DBC solder layer region image comprises a coarse screening process step and a fine screening process step which are sequentially performed,
in the coarse screening treatment step, binarizing treatment is carried out on the ultrasonic image of the DBC solder layer, morphological open operation is carried out after the binarization treatment, and a DBC solder layer segmentation image is generated after the open operation;
in the fine screening process step, the DBC solder layer region obtained in the coarse screening process step is processed to obtain a sub-region dividing line for separating two adjacent DBC sub-regions in the DBC solder layer region.
4. The method for calculating the void fraction of the void defect of the DBC solder layer according to claim 3, wherein the step of performing the coarse screening process, when performing the binarization process on the ultrasonic image of the DBC solder layer, to obtain an ultrasonic binarized image of the DBC solder layer, comprises:；
wherein ,is the DBC solder layer in the ultrasonic image>Gray value of dot pixel +.>Inside the ultrasound binary image for DBC solder layer +.>Gray value after point pixel binarization processing, < >>、/>A binary division threshold value is generated based on the gray value distribution state of the DBC solder layer ultrasonic image.
5. The method for calculating the void fraction of the DBC solder layer void defect according to claim 3, wherein the operation core of the morphological open operation includes an open operation square core when the morphological open operation is performed,
the size of the open operation square kernel is 12 dimensions.
6. The method for calculating the void fraction of the void defects of the DBC solder layer according to claim 3, wherein the fine screening processing step comprises:
performing horizontal projection on the ultrasonic binary image of the DBC solder layer to obtain a horizontal projection matrixThe method comprises the steps of carrying out a first treatment on the surface of the Horizontal projection matrix->Performing gradient calculation to obtain gradient matrix +.>；
In step sizeTraversing gradient matrix->If in a step +.>Positive peak value and negative peak value are simultaneously present in the main frame, and the absolute value of the positive peak value or the absolute value of the negative peak value is larger than the peak value threshold +.>When the method is used, taking the mean value of the position of the positive peak value and the position of the negative peak value as the ordinate value of the boundary, and generating a subarea boundary based on the ordinate value of the boundary;
and dividing the DBC solder layer into a plurality of mask areas by taking the generated subarea boundary as a boundary, and carrying out morphological closing operation on each mask area to obtain a plurality of DBC subareas positioned in the DBC solder layer area, wherein adjacent DBC subareas are separated by the subarea boundary.
7. The method for calculating the void fraction of DBC solder layer void defects according to claim 6, wherein each DBC sub-area is subjected to a mask boundary burr treatment, wherein,
when shielding boundary burr treatment is carried out, carrying out morphological corrosion operation on each DBC subarea, wherein an operation core of the morphological corrosion operation comprises a corrosion operation square core;
the size of the corrosion operation square kernel is 3 dimensions.
8. The method of calculating the void fraction of the DBC solder layer void defect according to any one of claims 1 to 7, wherein the dynamic binary segmentation is performed on the DBC solder layer ultrasonic image to form a DBC solder layer ultrasonic dynamic binary segmented image when searching for a void area in the DBC solder layer, the dynamic binary segmentation comprising:
；
wherein ,is the DBC solder layer in the ultrasonic image>Gray value of dot pixel +.>Is the DBC solder layer in the ultrasonic image>Gray value of dynamic binarization of dot pixels,>dividing threshold for dynamic binarization, +.>、/>Dividing threshold coefficients for dynamic binarization, +.>To->Preset area centered on point->A mean value of the set of included pixels;
on the DBC solder layer ultrasonic dynamic binary segmentation image, all gray valuesThe position or area where 255 is located is a void area where void defects exist.
9. The method for calculating the void fraction of the void defects in the DBC solder layer according to any one of claims 1 to 7, wherein for the total void fraction, there are:
；
wherein ,for total void fraction, ++>Is the area of the hollow area>For the pixel area of the DBC solder layer region, < >>Is an intersection operation;
the subzone void ratio is as follows:
；
wherein ,for the subzone void fraction, & lt + & gt>For the pixel area of the DBC subregion, +.>For the area of the sub-area cavity area within the DBC sub-area, & lt/L>Is an intersection operation.
10. A device for calculating the void ratio of a void defect of a DBC solder layer is characterized by comprising a void ratio calculating processor for calculating the void ratio, wherein,
for any DBC solder layer ultrasound image, the void fraction calculation processor calculates the void fraction using the method of any one of the above claims 1-9.
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