CN116681025A - Signal line wiring method, device, equipment and storage medium - Google Patents
Signal line wiring method, device, equipment and storage medium Download PDFInfo
- Publication number
- CN116681025A CN116681025A CN202310548873.5A CN202310548873A CN116681025A CN 116681025 A CN116681025 A CN 116681025A CN 202310548873 A CN202310548873 A CN 202310548873A CN 116681025 A CN116681025 A CN 116681025A
- Authority
- CN
- China
- Prior art keywords
- signal line
- weight
- wiring
- time sequence
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 74
- 238000003860 storage Methods 0.000 title claims abstract description 10
- 230000003071 parasitic effect Effects 0.000 claims description 54
- 230000008569 process Effects 0.000 claims description 21
- 230000003068 static effect Effects 0.000 claims description 21
- 230000007306 turnover Effects 0.000 claims description 19
- 238000012300 Sequence Analysis Methods 0.000 claims description 12
- 230000008439 repair process Effects 0.000 claims description 8
- 238000004458 analytical method Methods 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims description 6
- 238000005457 optimization Methods 0.000 claims description 3
- 238000004364 calculation method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000004891 communication Methods 0.000 description 5
- 210000004027 cell Anatomy 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000013139 quantization Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000003786 synthesis reaction Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 210000003850 cellular structure Anatomy 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of chip design and discloses a signal wire wiring method, a device, equipment and a storage medium. The problems that in the prior art, the routing length of a key signal is excessively optimized, which possibly occurs because the signal wires are difficult to accurately weight, the whole time sequence of a chip is deteriorated, the routing of the chip is congested, the layout and the wiring are difficult to finish and the like are solved.
Description
Technical Field
The present invention relates to the field of chip design technologies, and in particular, to a signal line wiring method, apparatus, device, and storage medium.
Background
Along with the improvement of application scene demands, the working frequency of the chip is higher and higher, tens of thousands of gate units in the chip are in a high-speed overturning state, and the generated switching power consumption is higher and higher. Along with the improvement of the process node, the line capacitance of the signal line exceeds the load capacitance of the gate unit, and becomes a main source of the power consumption of the chip switch.
In the prior art, the standard gate units are clustered according to the signal turnover rate by combining circuit pre-simulation data in the layout and wiring stage, so that the wiring length of the high turnover rate signal is shortened to reduce the capacitance of the signal wire, but the difficulty is how to accurately weight the signal wire, so that the wiring length of the key signal is excessively optimized, the whole time sequence of the chip is deteriorated, the wiring congestion of the chip is caused, and the layout and the wiring are difficult to finish.
The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present invention and is not intended to represent an admission that the foregoing is prior art.
Disclosure of Invention
The invention mainly aims to provide a signal wire wiring method, a device, equipment and a storage medium, which aim to solve the technical problems of chip overall time sequence deterioration, chip wiring congestion and difficult completion of layout and wiring caused by inaccurate weighting of signal wires in the prior art.
In order to achieve the above object, the present invention provides a signal line wiring method for making signal line wiring reasonable by calculating a wiring weight of each signal line of an on-chip circuit, the method comprising:
determining a first wiring weight of a signal line based on the power consumption weight and the estimated time sequence weight of the signal line, and performing first wiring according to the first wiring weight;
when the first wiring is completed, extracting parasitic parameters of the circuit layout of the circuit in the chip based on a library file and a process file of the chip to obtain the parasitic parameters of the circuit in the chip;
determining an actual time sequence weight of the signal line based on the parasitic parameter and the estimated time sequence weight, determining a second wiring weight of the signal line according to the actual time sequence weight and the power consumption weight, and performing second wiring according to the second wiring weight.
Optionally, the step of determining the first routing weight of the signal line based on the power consumption weight and the estimated timing weight of the signal line specifically includes:
acquiring the turnover rate and the load capacitance of the signal line, and determining the power consumption weight of the signal line according to the turnover rate and the load capacitance of the signal line;
acquiring a timing margin of the signal line and an estimated line load of the signal line, and determining an estimated timing weight of the signal line based on the timing margin of the signal line and the estimated line load of the signal line;
and determining a first wiring weight of the signal line according to the power consumption weight and the estimated time sequence weight.
Optionally, the step of obtaining the turnover rate and the load capacitance of the signal line and determining the power consumption weight of the signal line according to the turnover rate and the load capacitance of the signal line specifically includes:
acquiring a switch internal exchange format file, and acquiring the signal turnover rate of the signal wire based on the switch internal exchange format file;
acquiring a library file of a standard gate unit, and acquiring a load capacitance of the signal line according to the library file of the standard gate unit;
and determining the quantized power consumption of the signal line according to the turnover rate of the signal line and the load capacitance of the signal line, and determining the power consumption weight of the signal line based on the quantized power consumption.
Optionally, the step of acquiring the timing margin of the signal line and the estimated line load of the signal line, and determining the estimated timing weight of the signal line based on the timing margin of the signal line and the estimated line load of the signal line specifically includes:
acquiring a time sequence constraint file, and performing static time sequence analysis on a gate-level netlist according to the time sequence constraint file to acquire a time sequence margin of the signal line;
acquiring an estimated line load of the signal line from the gate-level netlist based on a line load model;
and determining the estimated time sequence weight of the signal line according to the time sequence allowance of the signal line and the estimated line load of the signal line.
Optionally, the step of determining an actual timing weight of the signal line based on the parasitic parameter and the estimated timing weight, and determining a second routing weight of the signal line according to the actual timing weight and the power consumption weight specifically includes:
acquiring an actual timing weight of the signal line based on the parasitic parameter and a timing margin of the signal line;
and confirming the second wiring weight of the signal line according to the power consumption weight and the actual time sequence weight.
Optionally, after the step of determining an actual timing weight of the signal line based on the parasitic parameter and the estimated timing weight, and determining a second routing weight of the signal line according to the actual timing weight and the power consumption weight, the method further includes:
when the second wiring is completed, determining the time sequence of each signal wire in the chip circuit through static time sequence analysis, and when the signal wire with the time sequence violation exists in the chip circuit, performing time sequence repair on the signal wire;
and when no signal line with timing violations exists in the on-chip circuit, the power consumption optimization is completed.
Optionally, when the second routing is completed, determining a time sequence of each signal line in the on-chip circuit through static time sequence analysis, and when a signal line with a time sequence violation exists in the on-chip circuit, performing a time sequence repair on the signal line, wherein the method further includes:
and acquiring the overall congestion degree of the chip, and when the overall congestion degree of the chip is larger than a congestion threshold value, recalculating the weight of the signal line and wiring, wherein the weight comprises the first wiring weight and the second wiring weight.
In addition, in order to achieve the above object, the present invention also provides a signal line wiring device for calculating a wiring weight of each signal line of an on-chip circuit, the device comprising:
a first wiring module for determining a first wiring weight of a signal line based on a power consumption weight and an estimated timing weight of the signal line, and performing a first wiring according to the first wiring weight;
the parameter extraction module is used for extracting parasitic parameters of the circuit layout of the circuit in the chip based on the library file and the process file of the chip when the first wiring is completed, and obtaining the parasitic parameters of the circuit in the chip;
and the second wiring module is used for determining the actual time sequence weight of the signal line based on the parasitic parameter and the estimated time sequence weight, determining the second wiring weight of the signal line according to the actual time sequence weight and the power consumption weight, and carrying out second wiring according to the second wiring weight.
In addition, in order to achieve the above object, the present invention also proposes a signal line wiring device comprising: a memory, a processor, and a signal line routing program stored on the memory and executable on the processor, the signal line routing program configured to implement the steps of the signal line routing method as described above.
In addition, in order to achieve the above object, the present invention also proposes a storage medium having stored thereon a signal line wiring program which, when executed by a processor, implements the steps of the signal line wiring method as described above.
The embodiment determines a first wiring weight of the signal line based on the power consumption weight and the estimated time sequence weight of the signal line, and performs first wiring according to the first wiring weight; when the first wiring is completed, extracting parasitic parameters of a circuit layout of an on-chip circuit based on a library file and a process file of the chip to obtain the parasitic parameters in the chip; and determining the actual time sequence weight of the signal line based on the parasitic parameter and the estimated time sequence weight, determining the second wiring weight of the signal line according to the actual time sequence weight and the power consumption weight, and performing second wiring according to the second wiring weight. The first wiring weight of the signal line is determined through the power consumption weight and the estimated time sequence weight, then the first wiring is performed, and the parasitic parameter extraction is performed on the circuit layout of the circuit in the chip based on the library file and the process file, so that the second wiring weight of the signal line is determined, the wiring weight of the signal line is accurately obtained, the wiring length of the signal line is effectively shortened, and the power consumption and the congestion degree of the chip are reduced.
Drawings
Fig. 1 is a schematic diagram of a signal line wiring device of a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a first embodiment of a signal line routing method according to the present invention;
FIG. 3 is a schematic diagram of two data paths of an application scenario of the signal line routing method of the present invention;
FIG. 4 is a schematic diagram of an equivalent circuit of two data paths of the application scenario of the signal line routing method of the present invention;
FIG. 5 is a timing margin forward propagation reverse mark intent of a data path of a signal line routing method application scenario of the present invention;
FIG. 6 is a flow chart of a second embodiment of a signal line routing method of the present invention;
fig. 7 is a block diagram showing the structure of a first embodiment of the signal line wiring device of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, the signal line wiring device may include: a processor 1001, such as a central processing unit (Central Processing Unit, CPU), a communication bus 1002, a user interface 1003, a network interface 1004, a memory 1005. Wherein the communication bus 1002 is used to enable connected communication between these components. The user interface 1003 may include a Display, an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may further include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a Wireless interface (e.g., a Wireless-Fidelity (Wi-Fi) interface). The Memory 1005 may be a high-speed random access Memory (Random Access Memory, RAM) or a stable nonvolatile Memory (NVM), such as a disk Memory. The memory 1005 may also optionally be a storage device separate from the processor 1001 described above.
It will be appreciated by those skilled in the art that the structure shown in fig. 1 does not constitute a limitation of the signal line routing device, and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
As shown in fig. 1, an operating system, a network communication module, a user interface module, and a signal line wiring program may be included in the memory 1005 as one type of storage medium.
In the signal line wiring apparatus shown in fig. 1, the network interface 1004 is mainly used for data communication with a network server; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the signal line wiring apparatus of the present invention may be provided in a signal line wiring apparatus which calls a signal line wiring program stored in the memory 1005 through the processor 1001 and executes the signal line wiring method provided by the embodiment of the present invention.
An embodiment of the present invention provides a signal line wiring method, referring to fig. 2, fig. 2 is a schematic flow chart of a first embodiment of the signal line wiring method of the present invention.
It will be appreciated that the signal lines may be lines used in an electrical control circuit to communicate information and control information. Along with the improvement of application scene demands, the working frequency of the chip is higher and higher, and as tens of thousands of gate units in the chip are in a high-speed overturning state, the switching power consumption generated by the chip is higher and higher. With the improvement of the process node, the line capacitance of the signal line exceeds the load capacitance of the gate unit, which becomes a main source of the power consumption of the chip switch. An important factor in determining the line capacitance of the signal line is the distance between the gate units. Therefore, how to reasonably route to reduce the switching power consumption generated by the chip becomes a big problem to be solved in the chip design.
In this embodiment, the method is used for making the wiring of the signal lines reasonable by calculating the wiring weight of each signal line of the circuit in the chip, and the signal line wiring method includes the following steps:
step S100: a first wiring weight of a signal line is determined based on a power consumption weight and an estimated timing weight of the signal line, and a first wiring is performed according to the first wiring weight.
The execution body of the method of the present embodiment may be a terminal device having functions of data processing and program running, such as a personal computer, or may be an electronic device having the same or similar functions, such as the above-described signal line wiring device. The present embodiment and the following embodiments will be described below by taking a signal line wiring device (hereinafter referred to as a wiring device) as an example.
It is understood that the above-mentioned power consumption weight is a weight determined according to the power consumption of the signal line, and the power consumption of the signal line may be determined according to the flip rate of the signal line, the line capacitance of the signal line, the estimated line load of the signal line, and the like, which is not limited in this embodiment.
It should be noted that the timing weights may be used to constrain the impact of signal line weighting on circuit timing. In a sequential circuit, the circuit can effectively operate and needs to meet the requirements of the set-up time and the hold time, and all the triggers in the same clock domain are driven by a unified clock.
It should be appreciated that the estimated timing weights described above are weights determined from the estimated timing margin of the signal line. The timing margin is the difference between the actual time and the time required for design, a positive timing margin indicates that the timing margin with a negative satisfied timing is not satisfied, and an estimated timing margin is the estimated value of the timing margin.
In practical applications, the timing margin of the data path in the circuit may be calculated by a static timing analysis method. After the timing margin of the signal is obtained, the signal line delay is needed, but because the actual metal wiring is not completed at this time, the line delay cannot be accurately calculated, the estimated timing weight can be calculated by selecting to estimate through a WLM (Wire Load Model) Model.
In one implementation, the calculating manner of the estimated time sequence weight may include:
step A10: and acquiring a time sequence constraint file, and carrying out static time sequence analysis on the gate-level netlist according to the time sequence constraint file to obtain the time sequence margin of the signal line.
It can be understood that the static time sequence analysis is a manner of performing static analysis on the time sequence of the signal line in the chip design process, and the static time sequence analysis can analyze and verify whether the time sequence of the chip design meets the requirement, and can instruct the layout and the wiring of the wiring tool to obtain the wiring result meeting the requirement.
It should be noted that a netlist is a type of file that may be used to describe the connection of circuit elements to each other. Gate level refers to the level of circuit synthesis of the netlist description. A gate level netlist is a description of the circuit elements, mostly gates or elements at the same level as gates.
It should be explained that the wiring device may calculate the timing margin of each path in a forward propagation manner with respect to the timing margin of the obtained data path, thereby obtaining the timing weight of each signal line. Each signal line may correspond to a path, and a plurality of signal lines may constitute a data path.
It should be noted that the timing constraint file is a file capable of constraining the gate netlist of the signal line, and the timing margin of the signal line can be obtained by performing static timing analysis on the gate netlist by using the timing constraint file. In order to ensure that the circuit can operate orderly and stably, the circuit needs to satisfy two time sequence conditions: (1) Before the clock signal comes in, dataThe arrival at the input port requires a steady period of time, i.e. the setup time t setup The method comprises the steps of carrying out a first treatment on the surface of the (2) After the arrival of the clock signal, the data needs to be held at the input port for a period of time, i.e., hold time t hold 。
It should be explained that, to ensure that the registers in the circuit can operate synchronously, the time required for the data to remain stable is not less than the set-up time t of the registers when the rising edge of the register clock comes setup And a holding time t hold A certain timing margin needs to be reserved in the data path.
Timing margin T of setup time s-slack The calculation formula (1-1) of (2) is as follows:
T s-slack ＝T+T clk-arr -t setup -T data-arr (1-1)
wherein T is a time period, T clk-arr Is the time of arrival of the clock signal, T data-arr Is the time of arrival of the data signal.
Timing margin T of hold time h-slack The calculation formula (1-2) of (2) is as follows:
T h-slack ＝T data-arr -t hold -T clk-arr (1-2)
the switching power consumption is optimized for the signal lines, so a certain anti-scaling method is required to propagate the timing margin of the data path to all paths in the data path. The reverse mark of the timing margin adopts a forward propagation method, takes the end point of a data path as a starting point, and propagates forward step by step along a signal node according to the time delay characteristic of the circuit. In the theory of static time sequence analysis, the starting point of a time sequence path in the circuit is the Q end of an input pin or a register, and the end point of the time sequence path is the D end of an output pin or the register. The timing margin slack (s, t) of the data path between any two nodes s, t on the timing path. The calculation formula (1-3) is as follows:
slack(s,t)＝min{RWQ(t)-ARR(s)}-d(s,t)(1-3)
wherein ARR(s) represents the time when data arrives at the node s, REQ (t) represents the retention time of data at the node t, and d (s, t) represents the delay between the nodes s, t.
It should be noted that, the types of the data paths (s, t) are two, one is a data path including a gate unit, and the other is a data path including only a metal wire, the two data paths are shown in fig. 3, and fig. 3 is a schematic diagram of the two data paths in the application scenario of the signal line wiring method of the present invention; the equivalent circuit is shown in fig. 4, and fig. 4 is a schematic diagram of the equivalent circuit of two data paths of the application scenario of the signal line wiring method of the present invention.
In the figure l 1 ，l 2 Respectively data paths (s, t 1 ),(s,t 2 ) Length, c 0 ,r 0 Capacitance and resistance of metal wire per unit length, C 1 ,C 2 For node t 1 ，t 2 Load capacitance r of (2) g ,d g Is the equivalent resistance and gate delay of the gate cell in data path 1. Estimating the delay of the data path using an ELmore-based delay model, the delay d (s, t) 1 ) The calculation formula (1-4) is as follows:
delay d (s, t) of data path 2 2 ) The calculation formula (1-5) is as follows:
in specific implementation, the wiring equipment acquires a time sequence constraint file, and performs static time sequence analysis on the gate-level netlist according to the time sequence constraint file to obtain a time sequence margin of the signal line.
Step A20: and obtaining the estimated line load of the signal line from the gate-level netlist based on a line load model.
It should be noted that the Wire Load Model (Wire Load Model) is a Model that can be used to estimate the resistance, capacitance and area overhead of the interconnect. The wire load model may estimate the length of the net based on the number of fanouts, and designs or modules with different areas may select different wire load models to determine parasitics.
It will be appreciated that the estimated line load described above may include the resistive, capacitive, and area overhead imposed by the signal lines.
In a specific implementation, the routing device obtains estimated line loads of the signal lines from the gate-level netlist based on a line load model.
Step A30: and determining the estimated time sequence weight of the signal line according to the time sequence allowance of the signal line and the estimated line load of the signal line.
It should be noted that, as shown in fig. 5, fig. 5 is a reverse indication of the forward propagation of the timing margin of the data path in the application scenario of the signal line wiring method of the present invention.
Wherein s, m and t are three nodes of the data path respectively, a, b, c, d, e, f is a path name, wherein a:2/5 represents that the delay of the path a is 2, and the timing margin is 5. The timing margin of the data path (s, t) can be calculated by static timing analysis, the line delays of d, e, f can be calculated by the path delay calculation formulas (1-1) and (1-2) above, and the timing margin of the data path (s, t) is subtracted by the line delays of the three paths, respectively, to obtain the timing margins of d, e, f paths as 8,9,7, respectively. Combining (1-3) to take a path f with the smallest timing margin as the timing margin of a data path (s, m), sequentially propagating forward along a node m, and repeating the processes to obtain paths a, b and c with the timing margins of 5,4 and 3.
After the timing margin of all signals is obtained, the calculation formulas (1-6) of the timing weights of the signals are as follows:
wherein c is an adjustment parameter, s i D is the timing margin of signal i i Is the line delay of signal i. In the early stage of the back-end design, the actual metal routing is not completed, so that the line delay of the signal cannot be calculated, and the signal can be estimated through a WLM (Wire Load Model) Model.
In a specific implementation, the wiring device determines an estimated timing weight of the signal line based on the timing margin of the signal line and an estimated line load of the signal line.
According to the embodiment, a timing constraint file is obtained, static timing analysis is carried out on the gate-level netlist according to the timing constraint file, and the timing margin of a signal line is obtained; acquiring an estimated line load of the signal line from the gate-level netlist based on the line load model; an estimated timing weight of the signal line is determined based on the timing margin of the signal line and the estimated line load of the signal line. Because the timing margin of the signal line is obtained, the estimated timing weight of the signal line is determined according to the timing margin of the signal line and the estimated line load, and then the first wiring weight of the signal line is calculated according to the estimated timing weight and the power consumption weight and is used for wiring, the accuracy of the calculation of the weight of the signal line is improved.
The first wiring weight may be determined by adding a weight value of the power consumption weight of the signal line to a weight value of the estimated timing weight; the specific weight of the power consumption weight and the estimated time sequence weight in the first wiring weight may be determined in advance, and the first wiring weight may be calculated according to the obtained power consumption weight and the estimated time sequence weight, or the first wiring weight may be determined by other means, which is not limited in this embodiment.
It will be appreciated that when the first routing weight is obtained, the first routing weight may be input to the routing tool and the first routing performed by the routing tool.
In a specific implementation, the wiring device determines a first wiring weight of the signal line based on the power consumption weight and the estimated timing weight of the signal line, and performs a first wiring according to the first wiring weight.
Step S200: and when the first wiring is completed, extracting parasitic parameters of the circuit layout of the circuit in the chip based on the library file and the process file of the chip to obtain the parasitic parameters of the circuit in the chip.
It should be appreciated that the circuit layout of the on-chip circuit may be obtained at the completion of the first routing. At this time, parasitic parameters of the circuit layout of the in-chip circuit can be extracted based on the library file and the process file of the chip, and the parasitic parameters of the in-chip circuit can be obtained.
It will be appreciated that the library file is a type of file stored in the chip, and may provide some variables, function names or classes that are ready to use. Library files can be divided into static libraries and dynamic libraries, and the distinction between static libraries and dynamic libraries is embodied in the linking phase of the program: the static library is copied into the program in the linking stage of the program; the dynamic library is not copied into the program during the linking phase, but rather the program is dynamically loaded into memory by the system for program invocation at runtime.
It should be understood that the above process file is a generic term for a technical file required for guiding the steps of the production operation and the process management of the chip.
It should be noted that the parasitic parameter is an index that can be used to measure the success of a technology. The parasitic parameters may include parasitic capacitance, parasitic resistance, and parasitic inductance.
In a specific implementation, when the first wiring is completed, the wiring equipment extracts parasitic parameters of the circuit layout of the circuit in the chip based on the library file and the process file of the chip to obtain the parasitic parameters of the circuit in the chip.
Step S300: determining an actual time sequence weight of the signal line based on the parasitic parameter and the estimated time sequence weight, determining a second wiring weight of the signal line according to the actual time sequence weight and the power consumption weight, and performing second wiring according to the second wiring weight.
When the first wiring is completed, the line delay of the signal can be calculated by the obtained parasitic parameter, so as to calculate the actual time sequence weight of suspicion.
In a specific implementation, the wiring device determines an actual timing weight of the signal line based on the parasitic parameter and the estimated timing weight, determines a second wiring weight of the signal line according to the actual timing weight and the power consumption weight, and performs a second wiring according to the second wiring weight.
The embodiment determines a first wiring weight of the signal line based on the power consumption weight and the estimated time sequence weight of the signal line, and performs first wiring according to the first wiring weight; when the first wiring is completed, extracting parasitic parameters of a circuit layout of an on-chip circuit based on a library file and a process file of the chip to obtain the parasitic parameters in the chip; and determining the actual time sequence weight of the signal line based on the parasitic parameter and the estimated time sequence weight, determining the second wiring weight of the signal line according to the actual time sequence weight and the power consumption weight, and performing second wiring according to the second wiring weight. The first wiring weight of the signal line is determined through the power consumption weight and the estimated time sequence weight, then the first wiring is performed, and the parasitic parameter extraction is performed on the circuit layout of the circuit in the chip based on the library file and the process file, so that the second wiring weight of the signal line is determined, the wiring weight of the signal line is accurately obtained, the wiring length of the signal line is effectively shortened, and the power consumption and the congestion degree of the chip are reduced.
Based on the first embodiment of the signal line wiring method of the present invention as described above, a second embodiment of the signal line wiring method of the present invention is proposed. Referring to fig. 6, fig. 6 is a flowchart illustrating a second embodiment of a signal line routing method according to the present invention.
In order to obtain an accurate first routing weight, the step of determining the first routing weight of the signal line based on the power consumption weight and the estimated time sequence weight of the signal line specifically includes:
step S110: and acquiring the turnover rate and the load capacitance of the signal line, and determining the power consumption weight of the signal line according to the turnover rate and the load capacitance of the signal line.
It should be noted that, the power consumption weight depends on the quantization power consumption, and the quantization power consumption can be used to quantize the current parameter of the power consumption of the signal line, which is determined by the flip rate of the signal line and the load capacitance. Wherein the load capacitance can be found from library files of standard cells. The signal slew rate may be derived from the simulation results of the gate stage. Gate level circuits are circuits that are mapped into standard gate cell components, also known as netlists (Netlist), through a synthesis tool such as DC (Design Compiler) after the circuits are functionally described using the high level hardware language Verilog or VHDL.
In one implementation manner, the step of obtaining the turnover rate and the load capacitance of the signal line and determining the power consumption weight of the signal line according to the turnover rate and the load capacitance of the signal line specifically includes:
step S111: and acquiring a switch internal exchange format file, and acquiring the signal turnover rate of the signal line based on the switch internal exchange format file.
Note that the switch internal switching format file (Switch activity Interchange Format, SAIF) is a file that can be used for information exchange between the emulator and the power consumption analysis. The switch internal exchange format file may be generated by a simulation tool, first reading in the design file in the synthesis tool DC, generating a forward SAIF file, such as forward.
It will be appreciated that the number of logical changes of the signal is referred to as the number of turns, and that the rate of turn is the number of turns of the signal per unit time.
In a specific implementation, the wiring device acquires a switch internal switching format file, and acquires a signal inversion rate of the signal line based on the switch internal switching format file.
Step S112: and acquiring a library file of the standard gate unit, and acquiring the load capacitance of the signal line according to the library file of the standard gate unit.
The standard gate cell, i.e., the standard cell, is a method of designing an asic having a main digital logic feature.
It should be understood that the load capacitance refers to the sum of all effective capacitances of the crystal signal line, and can be regarded as a series capacitance of the crystal oscillator chip in the circuit.
In a specific implementation, the wiring device obtains a library file of the standard gate unit, and obtains a load capacitance of the signal line according to the library file of the standard gate unit.
Step S113: and determining the quantized power consumption of the signal line according to the turnover rate of the signal line and the load capacitance of the signal line, and determining the power consumption weight of the signal line based on the quantized power consumption.
It should be noted that, the calculation formula of the power consumption weight is as follows:
wherein I represents a set of all signal lines in the circuit, p e(i) Representing the quantized power consumption, alpha, of the signal i i Indicating the inversion rate of the signal line i, C wire() Is the capacitance of the signal line i, which can be obtained by parasitic parameter extraction, C pin(i) The input pin capacitance of the lower gate unit connected with the signal i can be obtained by looking up a table from a library file of the standard gate unit.
In a specific implementation, the wiring device acquires a switch internal switching format file, and acquires a signal inversion rate of the signal line based on the switch internal switching format file.
Step S120: acquiring a timing margin of the signal line and an estimated line load of the signal line, and determining an estimated timing weight of the signal line based on the timing margin of the signal line and the estimated line load of the signal line;
step S130: and determining a first wiring weight of the signal line according to the power consumption weight and the estimated time sequence weight.
In a specific implementation, a wiring device acquires a timing margin of a signal line and an estimated line load of the signal line, and determines an estimated timing weight of the signal line based on the timing margin of the signal line and the estimated line load of the signal line; and determining a first wiring weight of the signal line based on the power consumption weight and the estimated timing weight.
In order to obtain an accurate second routing weight, the step of determining an actual timing weight of the signal line based on the parasitic parameter and the estimated timing weight, and determining the second routing weight of the signal line according to the actual timing weight and the power consumption weight specifically includes:
step S121: acquiring an actual timing weight of the signal line based on the parasitic parameter and a timing margin of the signal line;
the actual line delay of the signal line can be obtained based on the parasitic parameter, and the actual time sequence weight of the signal line can be calculated according to the suspected actual line delay and the time sequence margin of the signal line.
Step S122: and confirming the second wiring weight of the signal line according to the power consumption weight and the actual time sequence weight.
In a specific implementation, the wiring device acquires an actual timing weight of the signal line based on the parasitic parameter and the timing margin of the signal line, and confirms a second wiring weight of the signal line according to the power consumption weight and the actual timing weight of the signal line.
According to the embodiment, the inversion rate and the load capacitance of the signal line are obtained, the quantization power consumption of the signal line is determined according to the inversion rate and the load capacitance of the signal line, and the power consumption weight is determined based on the quantization power consumption; acquiring a timing margin of a signal line and an estimated line load of the signal line, determining an estimated timing weight of the signal line based on the timing margin of the signal line and the estimated line load of the signal line, and determining a first wiring weight of the signal line according to the power consumption weight and the estimated timing weight; when the first wiring is completed, extracting parasitic parameters of the circuit layout, and acquiring actual time sequence weights of the signal lines according to the parasitic parameters and the time sequence allowance; and confirming the second wiring weight of the signal line according to the power consumption weight and the actual time sequence weight. The power consumption of the signal wire is quantified through the turnover rate of the signal wire and the load capacitance, the power consumption weight is determined, the first wiring weight of the signal wire is calculated by combining the estimated time sequence weight of the signal wire, when the first wiring is completed, the parasitic parameter of the circuit layout is extracted, the actual time sequence weight is obtained according to the parasitic parameter, the second wiring weight is determined, the second signal wire wiring is carried out according to the second wiring weight, the time sequence meeting requirement is ensured, the wiring length of the key signal is effectively shortened, and the switching power consumption of the chip is reduced.
It should be noted that, in order to reduce the overall congestion level in the chip, after the step of determining the actual timing weight of the signal line based on the parasitic parameter and the estimated timing weight and determining the second routing weight of the signal line according to the actual timing weight and the power consumption weight, the method further includes:
when the second wiring is completed, determining the time sequence of each signal wire in the chip circuit through static time sequence analysis, and when the signal wire with the time sequence violation exists in the chip circuit, performing time sequence repair on the signal wire;
and when no signal line with timing violations exists in the on-chip circuit, the power consumption optimization is completed.
Further, when the second routing is completed, determining the time sequence of each signal line in the on-chip circuit through static time sequence analysis, and when the signal line with the time sequence violation exists in the on-chip circuit, after the step of performing time sequence repair on the signal line, the method further comprises:
and acquiring the overall congestion degree of the chip, and when the overall congestion degree of the chip is larger than a congestion threshold value, recalculating the weight of the signal line and wiring, wherein the weight comprises the first wiring weight and the second wiring weight.
It should be explained that the congestion threshold may be a threshold preset by the user according to the requirement. The overall congestion degree of the chip can be judged through a wiring tool, and then time sequence repair is carried out through a time sequence repair tool.
Based on the first embodiment of the signal line wiring method of the present invention, the first embodiment of the signal line wiring device of the present invention is proposed, and referring to fig. 7, fig. 7 is a block diagram of the structure of the first embodiment of the signal line wiring device of the present invention.
In this embodiment, the apparatus is used for calculating a wiring weight of each signal line of an on-chip circuit, and the apparatus includes:
a first wiring module 701 for determining a first wiring weight of a signal line based on a power consumption weight and an estimated timing weight of the signal line, and performing a first wiring according to the first wiring weight;
the parameter extraction module 702 is configured to extract parasitic parameters of the circuit layout of the on-chip circuit based on the library file and the process file of the chip when the first wiring is completed, so as to obtain parasitic parameters of the on-chip circuit;
a second routing module 703, configured to determine an actual timing weight of the signal line based on the parasitic parameter and the estimated timing weight, determine a second routing weight of the signal line according to the actual timing weight and the power consumption weight, and perform a second routing according to the second routing weight.
Other embodiments or specific implementations of the signal line routing device of the present invention may refer to the above method embodiments, and are not described herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. read-only memory/random-access memory, magnetic disk, optical disk), comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (10)
1. A signal line wiring method for making signal lines reasonable by calculating a wiring weight of each signal line of an on-chip circuit, the method comprising:
determining a first wiring weight of a signal line based on the power consumption weight and the estimated time sequence weight of the signal line, and performing first wiring according to the first wiring weight;
when the first wiring is completed, extracting parasitic parameters of the circuit layout of the circuit in the chip based on a library file and a process file of the chip to obtain the parasitic parameters of the circuit in the chip;
determining an actual time sequence weight of the signal line based on the parasitic parameter and the estimated time sequence weight, determining a second wiring weight of the signal line according to the actual time sequence weight and the power consumption weight, and performing second wiring according to the second wiring weight.
2. The signal line wiring method according to claim 1, wherein the step of determining the first wiring weight of the signal line based on the power consumption weight and the estimated timing weight of the signal line, specifically comprises:
acquiring the turnover rate and the load capacitance of the signal line, and determining the power consumption weight of the signal line according to the turnover rate and the load capacitance of the signal line;
acquiring a timing margin of the signal line and an estimated line load of the signal line, and determining an estimated timing weight of the signal line based on the timing margin of the signal line and the estimated line load of the signal line;
and determining a first wiring weight of the signal line according to the power consumption weight and the estimated time sequence weight.
3. The signal line wiring method according to claim 2, wherein the step of acquiring the flip rate and the load capacitance of the signal line and determining the power consumption weight of the signal line based on the flip rate and the load capacitance of the signal line, comprises:
acquiring a switch internal exchange format file, and acquiring the signal turnover rate of the signal wire based on the switch internal exchange format file;
acquiring a library file of a standard gate unit, and acquiring a load capacitance of the signal line according to the library file of the standard gate unit;
and determining the quantized power consumption of the signal line according to the turnover rate of the signal line and the load capacitance of the signal line, and determining the power consumption weight of the signal line based on the quantized power consumption.
4. The signal line wiring method according to claim 2, wherein the step of acquiring the timing margin of the signal line and the estimated line load of the signal line, and determining the estimated timing weight of the signal line based on the timing margin of the signal line and the estimated line load of the signal line, specifically comprises:
acquiring a time sequence constraint file, and performing static time sequence analysis on a gate-level netlist according to the time sequence constraint file to acquire a time sequence margin of the signal line;
acquiring an estimated line load of the signal line from the gate-level netlist based on a line load model;
and determining the estimated time sequence weight of the signal line according to the time sequence allowance of the signal line and the estimated line load of the signal line.
5. The signal line routing method of claim 4, wherein the step of determining an actual timing weight of the signal line based on the parasitic parameter and the estimated timing weight, and determining a second routing weight of the signal line based on the actual timing weight and the power consumption weight, comprises:
acquiring an actual timing weight of the signal line based on the parasitic parameter and a timing margin of the signal line;
and confirming the second wiring weight of the signal line according to the power consumption weight and the actual time sequence weight.
6. The signal line routing method according to any one of claims 1 to 5, wherein after the step of determining an actual timing weight of the signal line based on the parasitic parameter and the estimated timing weight, and determining a second routing weight of the signal line from the actual timing weight and the power consumption weight, the method further comprises:
when the second wiring is completed, determining the time sequence of each signal wire in the chip circuit through static time sequence analysis, and when the signal wire with the time sequence violation exists in the chip circuit, performing time sequence repair on the signal wire;
and when no signal line with timing violations exists in the on-chip circuit, the power consumption optimization is completed.
7. The signal line wiring method according to claim 6, wherein the timing of each signal line in the on-chip circuit is determined by static timing analysis when the second wiring is completed, and after the step of performing timing repair on the signal line when there is a timing violation of the signal line in the on-chip circuit, the method further comprises:
and acquiring the overall congestion degree of the chip, and when the overall congestion degree of the chip is larger than a congestion threshold value, recalculating the weight of the signal line and wiring, wherein the weight comprises the first wiring weight and the second wiring weight.
8. A signal line wiring device for calculating a wiring weight of each signal line of an on-chip circuit, the device comprising:
a first wiring module for determining a first wiring weight of a signal line based on a power consumption weight and an estimated timing weight of the signal line, and performing a first wiring according to the first wiring weight;
the parameter extraction module is used for extracting parasitic parameters of the circuit layout of the circuit in the chip based on the library file and the process file of the chip when the first wiring is completed, and obtaining the parasitic parameters of the circuit in the chip;
and the second wiring module is used for determining the actual time sequence weight of the signal line based on the parasitic parameter and the estimated time sequence weight, determining the second wiring weight of the signal line according to the actual time sequence weight and the power consumption weight, and carrying out second wiring according to the second wiring weight.
9. A signal line wiring apparatus, characterized by comprising: a memory, a processor, and a signal line routing program stored on the memory and executable on the processor, the signal line routing program configured to implement the steps of the signal line routing method of any one of claims 1 to 7.
10. A storage medium having stored thereon a signal line routing program which, when executed by a processor, implements the steps of the signal line routing method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310548873.5A CN116681025A (en) | 2023-05-15 | 2023-05-15 | Signal line wiring method, device, equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310548873.5A CN116681025A (en) | 2023-05-15 | 2023-05-15 | Signal line wiring method, device, equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116681025A true CN116681025A (en) | 2023-09-01 |
Family
ID=87784486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310548873.5A Pending CN116681025A (en) | 2023-05-15 | 2023-05-15 | Signal line wiring method, device, equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116681025A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117787194A (en) * | 2023-12-28 | 2024-03-29 | 苏州异格技术有限公司 | Wiring method, wiring device, computer equipment and storage medium |
-
2023
- 2023-05-15 CN CN202310548873.5A patent/CN116681025A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117787194A (en) * | 2023-12-28 | 2024-03-29 | 苏州异格技术有限公司 | Wiring method, wiring device, computer equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10387606B2 (en) | Validating a clock tree delay | |
| CN101539958B (en) | Method and device for designing standard cell library and integrated circuit | |
| US8225248B2 (en) | Timing, noise, and power analysis of integrated circuits | |
| US20070276645A1 (en) | Power modelling in circuit designs | |
| US20090288050A1 (en) | Statistical delay and noise calculation considering cell and interconnect variations | |
| US9165105B2 (en) | Rule checking for confining waveform induced constraint variation in static timing analysis | |
| WO2021128169A1 (en) | Chip design method, chip design device, and storage medium | |
| US20210279392A1 (en) | Glitch power analysis with register transistor level vectors | |
| US9378328B2 (en) | Modeling multi-patterning variability with statistical timing | |
| CN116681025A (en) | Signal line wiring method, device, equipment and storage medium | |
| CN112560373B (en) | Burr power analysis and optimization engine | |
| US20170235868A1 (en) | Static Timing Analysis with Improved Accuracy and Efficiency | |
| US8495544B2 (en) | Statistical delay and noise calculation considering cell and interconnect variations | |
| Ramesh et al. | Artificial neural network model for arrival time computation in gate level circuits | |
| US6567960B2 (en) | System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values | |
| US7191417B1 (en) | Method and apparatus for optimization of digital integrated circuits using detection of bottlenecks | |
| Xiong et al. | Incremental criticality and yield gradients | |
| Bock et al. | Local search algorithms for timing-driven placement under arbitrary delay models | |
| CN112100950A (en) | Method, system, device and storage medium for chip design | |
| US9798843B2 (en) | Statistical timing using macro-model considering statistical timing value entry | |
| Cortadella et al. | Static timing analysis | |
| Lin et al. | Optimal wire retiming without binary search | |
| Shah et al. | Development of Static Timing Analysis Tool in Perl | |
| US8239800B2 (en) | Method and apparatus for determining a robustness metric for a circuit design | |
| US11748534B1 (en) | System and method for glitch power estimation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |