CN116681021A - Method, medium and equipment for generating coplanar waveguide graph in integrated circuit layout - Google Patents
Method, medium and equipment for generating coplanar waveguide graph in integrated circuit layout Download PDFInfo
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- CN116681021A CN116681021A CN202210170396.9A CN202210170396A CN116681021A CN 116681021 A CN116681021 A CN 116681021A CN 202210170396 A CN202210170396 A CN 202210170396A CN 116681021 A CN116681021 A CN 116681021A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
The invention discloses a method, medium and equipment for generating a coplanar waveguide graph in an integrated circuit layout. The method comprises the following steps: determining auxiliary lines for generating coplanar waveguide patterns in the integrated circuit layout; generating a coplanar waveguide pattern by taking the auxiliary line as a central line; and deleting the corresponding auxiliary line after the coplanar waveguide pattern is generated. The step of generating a coplanar waveguide pattern with the auxiliary line as a center line includes: generating a first conductor pattern with a first distance and a second conductor pattern with a second distance by taking the auxiliary line as a central line, wherein the first distance is larger than the second distance; and deleting the overlapped part of the first conductor pattern and the second conductor pattern to obtain the coplanar waveguide pattern. By the mode, the coplanar waveguide graph can be automatically generated, and the efficiency and accuracy of layout drawing are improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a method, medium, and apparatus for generating coplanar waveguide patterns in an integrated circuit layout.
Background
The coplanar waveguide is mainly used for transmitting microwave frequency signals, and is formed by two parallel transmission lines and is often applied to integrated circuits. Currently, in integrated circuit layout designs, coplanar waveguide patterns are essentially manually drawn. However, when the number of coplanar waveguide patterns is large and the distribution is dense, the work for drawing the coplanar waveguide patterns is huge, and errors are extremely easy to occur, and the drawing is hardly completed.
Disclosure of Invention
The invention aims to provide a method, medium and equipment for generating a coplanar waveguide pattern in an integrated circuit layout, so as to solve the problem of difficult drawing of the coplanar waveguide pattern in the prior art, automatically generate the coplanar waveguide pattern and improve the efficiency and accuracy of the layout drawing.
In order to solve the technical problems, the invention provides a method for generating a coplanar waveguide pattern in an integrated circuit layout, which comprises the following steps:
determining auxiliary lines for generating coplanar waveguide patterns in the integrated circuit layout;
and generating a coplanar waveguide pattern by taking the auxiliary line as a central line.
Preferably, the step of generating the coplanar waveguide pattern using the auxiliary line as a center line includes:
generating a first conductor pattern with a first distance and a second conductor pattern with a second distance by taking the auxiliary line as a central line, wherein the first distance is larger than the second distance;
and deleting the overlapped part of the first conductor pattern and the second conductor pattern to obtain a coplanar waveguide pattern.
Preferably, the step of deleting the overlapping portion of the first conductor pattern and the second conductor pattern to obtain the coplanar waveguide pattern specifically includes:
and performing non-operation of Boolean operation of the patterns on the first conductor pattern and the second conductor pattern to obtain a coplanar waveguide pattern.
Preferably, the auxiliary line is a folding line.
Preferably, before the step of generating the coplanar waveguide pattern using the auxiliary line as a center line, the method includes:
chamfering is carried out at the folding point of the auxiliary line.
Preferably, the chamfering at the folding point of the auxiliary line specifically includes:
and generating a bent transition line smoothly connected with two line segments where the folding points of the auxiliary line are located, and deleting the part between the folding points and the bent transition line on the two line segments.
Preferably, the curved transition line is an arc line with a radius of a preset length.
Preferably, the method further comprises:
and deleting the corresponding auxiliary line after the coplanar waveguide pattern is generated.
To solve the above technical problem, the present invention further provides a storage medium, in which a computer program is stored, the computer program being configured to execute the method for generating a coplanar waveguide pattern in an integrated circuit layout according to any one of the preceding claims when running.
To solve the above technical problem, the present invention further provides an electronic device, including a memory and a processor, where the memory stores a computer program, and the processor is configured to run the computer program to execute the method for generating a coplanar waveguide pattern in an integrated circuit layout according to any one of the foregoing methods.
Compared with the prior art, the method for generating the coplanar waveguide pattern in the integrated circuit layout only needs to provide the auxiliary line for generating the coplanar waveguide pattern in the integrated circuit layout, and after the auxiliary line is determined, the coplanar waveguide pattern is generated by taking the auxiliary line as a central line, so that the coplanar waveguide pattern can be automatically generated, and the efficiency and the accuracy of layout drawing are improved.
The storage medium and the electronic device provided by the invention belong to the same conception as the method for generating the coplanar waveguide pattern in the integrated circuit layout, so that the storage medium and the electronic device have the same beneficial effects and are not repeated herein.
Drawings
Fig. 1 is a flow chart of a method for generating a coplanar waveguide pattern in an integrated circuit layout according to a first embodiment of the present invention.
Fig. 2 is a schematic flowchart of step S2 in the method shown in fig. 1.
Fig. 3 is a flow chart of a method for generating a coplanar waveguide pattern in an integrated circuit layout according to a third embodiment of the present invention.
FIG. 4 is a schematic diagram of a coplanar waveguide pattern generation process in one specific application.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Referring to fig. 1, a first embodiment of the present invention provides a method for generating a coplanar waveguide pattern in an integrated circuit layout, the method comprising the steps of:
s1: auxiliary lines in the integrated circuit layout for generating the coplanar waveguide pattern are determined.
Wherein the auxiliary line may be distinguished from other traces in the integrated circuit layout by a specific identification, such as the auxiliary line being highlighted, a specific color being displayed, or the two end points of the auxiliary line being added to a specific set of coordinates. It can be determined by the specific identification whether each trace is an auxiliary line for generating the coplanar waveguide pattern.
S2: and generating a coplanar waveguide pattern by taking the auxiliary line as a central line.
The coplanar waveguide pattern consists of two conductor transmission lines with equal line widths, and the line distance between the two conductor transmission lines is fixed. The auxiliary line is used as the central line of the coplanar waveguide pattern, and the coplanar waveguide pattern can be generated according to the position of the auxiliary line, the line width of the conductor transmission line and the line distance.
Since the auxiliary line is only used for generating the coplanar waveguide pattern, the auxiliary line needs to be deleted after the coplanar waveguide pattern is generated, and in order to simplify the operation of the designer, in this embodiment, the method further includes:
s3: and deleting the corresponding auxiliary line after the coplanar waveguide pattern is generated.
By the mode, the method for generating the coplanar waveguide graph in the integrated circuit layout does not need a layout designer to directly draw the coplanar waveguide graph, only auxiliary lines are required to be drawn, and the auxiliary lines are convenient and simple to draw and are not easy to make mistakes, so that the coplanar waveguide graph can be automatically generated, and the efficiency and the accuracy of layout drawing are improved.
A second embodiment of the present invention provides a method for generating a coplanar waveguide pattern in an integrated circuit layout, where the method of the present embodiment includes all the steps of the method of the first embodiment, and is different in that, referring to fig. 2, the step of generating the coplanar waveguide pattern with an auxiliary line as a center line, that is, step S2 includes:
s21: a first conductor pattern having a first width and a second conductor pattern having a second width are generated with the auxiliary line as a center line, respectively, the first distance being greater than the second distance.
And after generating the first conductor pattern according to the position of the auxiliary line and the first distance and generating the second conductor pattern according to the position of the auxiliary line and the second distance, the first conductor pattern and the second conductor pattern are partially overlapped.
S22: and deleting the overlapped part of the first conductor pattern and the second conductor pattern to obtain the coplanar waveguide pattern.
And deleting the overlapped part of the first conductor pattern and the second conductor pattern to form two conductor transmission lines, wherein the distance between the two conductor transmission lines is a second distance, and the line width of the two conductor transmission lines is the difference value between the first distance and the second distance.
Further, in this embodiment, the step of deleting the overlapping portion of the first conductor pattern and the second conductor pattern to obtain the coplanar waveguide pattern, that is, step S22 specifically includes:
and performing non-operation of Boolean operation of the patterns on the first conductor pattern and the second conductor pattern to obtain a coplanar waveguide pattern.
Referring to fig. 3, a third embodiment of the present invention provides a method for generating a coplanar waveguide pattern in an integrated circuit layout. In this embodiment, the auxiliary line is a broken line, that is, the auxiliary line is formed by sequentially connecting a plurality of non-parallel line segments. The method comprises the following steps:
s10: auxiliary lines in the integrated circuit layout for generating the coplanar waveguide pattern are determined.
S20: chamfering is performed at the folding point of the auxiliary line.
According to the design rule of the integrated circuit layout, the coplanar waveguide cannot have sharp angles at corners, and if sharp angles exist, radiation and interference are easy to generate.
S30: and generating a coplanar waveguide pattern by taking the auxiliary line as a central line.
S40: and deleting the corresponding auxiliary line after the coplanar waveguide pattern is generated.
Steps S10, S30 and S40 are identical to steps S1, S2 and S3 in the foregoing embodiments, and have the same technical features, and are not described herein.
In this embodiment, the step of chamfering at the folding point of the auxiliary line, that is, the step S20 specifically includes:
and generating a bent transition line smoothly connected with two line segments where the folding points of the auxiliary line are located, and deleting the part between the folding points and the bent transition line on the two line segments.
Wherein, the bending transition line is an arc line with a radius of a preset length. The two ends of the bent transition line are smoothly connected with two line segments where the folding points are located, and the line segments between the connecting points and the folding points need to be deleted. That is, after the chamfering process, the auxiliary line is changed from including only the line segment to including the line segment and the circular arc line.
The method of generating the coplanar waveguide pattern in the integrated circuit layout of the third embodiment will be described in detail below by specific application.
In this particular application, referring to fig. 4, there is an auxiliary line in the integrated circuit layout, and the auxiliary line includes three line segments path1, path2, and path3. As shown in fig. 4 (a), three line segments path1, path2, and path3 form a folding line. As shown in fig. 4 (b), after chamfering is performed at the folding point of the auxiliary line, the auxiliary line includes three line segments path1, path2, path3 and two arc lines arc1, arc2 having a radius r, both ends of the arc line arc1 are smoothly connected with the line segments path1, path2, and both ends of the arc line arc2 are smoothly connected with the line segments path2, path3. As shown in fig. 4 (c), after the coplanar waveguide pattern is generated with the auxiliary line as the center line, a final coplanar waveguide pattern is formed, and the hatched portion in the figure indicates the coplanar waveguide pattern. As shown in fig. 4 (d), after the coplanar waveguide pattern is generated, the corresponding auxiliary line is deleted, and only the coplanar waveguide pattern is finally maintained.
The invention also provides a storage medium having stored therein a computer program arranged to, when run, perform the method of generating a coplanar waveguide pattern in an integrated circuit layout of any of the previous embodiments.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
The invention also provides an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the method of any of the embodiments of generating coplanar waveguide patterns in an integrated circuit layout.
In particular, the memory and the processor may be connected by a data bus. In addition, the electronic apparatus may further include a transmission device connected to the processor, and an input/output device connected to the processor.
In the description of the present specification, a description of the terms "one embodiment," "some embodiments," "examples," or "particular examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A method of generating a coplanar waveguide pattern in an integrated circuit layout, comprising:
determining auxiliary lines for generating coplanar waveguide patterns in the integrated circuit layout;
and generating a coplanar waveguide pattern by taking the auxiliary line as a central line.
2. The method of claim 1, wherein the step of generating a coplanar waveguide pattern with the auxiliary line as a center line comprises:
generating a first conductor pattern with a first distance and a second conductor pattern with a second distance by taking the auxiliary line as a central line, wherein the first distance is larger than the second distance;
and deleting the overlapped part of the first conductor pattern and the second conductor pattern to obtain a coplanar waveguide pattern.
3. The method according to claim 2, wherein the step of deleting the overlapping portion of the first conductor pattern and the second conductor pattern to obtain the coplanar waveguide pattern comprises:
and performing non-operation of Boolean operation of the patterns on the first conductor pattern and the second conductor pattern to obtain a coplanar waveguide pattern.
4. A method according to any one of claims 1 to 3, wherein the auxiliary line is a fold line.
5. The method of claim 4, wherein prior to the step of generating a coplanar waveguide pattern centered on the auxiliary line, the method comprises:
chamfering is carried out at the folding point of the auxiliary line.
6. The method according to claim 5, characterized in that said step of chamfering at the folding point of said auxiliary line comprises in particular:
and generating a bent transition line smoothly connected with two line segments where the folding points of the auxiliary line are located, and deleting the part between the folding points and the bent transition line on the two line segments.
7. The method of claim 6, wherein the curved transition line is an arc of a circle having a radius of a predetermined length.
8. A method according to any one of claims 1 to 3, further comprising:
and deleting the corresponding auxiliary line after the coplanar waveguide pattern is generated.
9. A storage medium having stored therein a computer program arranged to, when run, perform the method of generating co-planar waveguide patterns in an integrated circuit layout as claimed in any one of claims 1 to 8.
10. An electronic device comprising a memory and a processor, the memory having stored therein a computer program, the processor being arranged to run the computer program to perform the method of generating co-planar waveguide patterns in an integrated circuit layout according to any of claims 1 to 8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210170396.9A CN116681021A (en) | 2022-02-23 | 2022-02-23 | Method, medium and equipment for generating coplanar waveguide graph in integrated circuit layout |
| PCT/CN2023/077501 WO2023160556A1 (en) | 2022-02-23 | 2023-02-21 | Quantum chip layout construction method and device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210170396.9A CN116681021A (en) | 2022-02-23 | 2022-02-23 | Method, medium and equipment for generating coplanar waveguide graph in integrated circuit layout |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116681021A true CN116681021A (en) | 2023-09-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210170396.9A Pending CN116681021A (en) | 2022-02-23 | 2022-02-23 | Method, medium and equipment for generating coplanar waveguide graph in integrated circuit layout |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116681021A (en) |
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2022
- 2022-02-23 CN CN202210170396.9A patent/CN116681021A/en active Pending
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