CN116680757A - Communication method, first chip, chip assembly and replaceable accessory - Google Patents

Abstract

The embodiment of the application provides a communication method, a first chip, a second chip, a chip assembly and a replaceable accessory, wherein the method comprises the following steps: after passing the first authentication of the host device, communicating with the host device through an encryption instruction; communicating with the second chip through a plaintext instruction, or communicating with the second chip through an encrypted instruction after passing through a second authentication of the second chip; at least part of information between the first chip and the second chip is transmitted through a plaintext instruction. In an embodiment of the present application, at least part of the information between the first chip and the second chip is communicated in an unencrypted (plaintext) manner. On one hand, the increase of the second count value in the second chip can be avoided, and the service life of the second chip is prolonged; on the other hand, the encryption and decryption steps of the first chip and the second chip on the communication instruction are reduced, so that the performance cost of a communication system is saved, the communication rate is improved, and the response speed of the second chip is further improved.

Description

Communication method, first chip, chip assembly and replaceable accessory

The present application claims priority from the chinese patent office, application number 202211449300.9, application name "a grafted chip assembly" filed on day 18, 11, 2022, the entire contents of which are incorporated herein by reference.

Technical Field

The application relates to the technical field of communication, in particular to a communication method, a first chip, a chip assembly and a replaceable accessory.

Background

To enrich the host device's characteristics, the host device is often used in conjunction with some peripheral accessories. When an accessory is used on a host device, the host device often needs to authenticate the source of the accessory. On accessories, a chip for identity authentication is often included, and authentication information is stored in the chip. In addition, information such as the usage history and the service life of the accessories is stored in the chip. The host device may be an image forming apparatus, a mobile terminal, a computer, or the like, and the accessory may be a module including a chip such as a consumable cartridge, an earphone, a battery, or a peripheral, correspondingly.

For environmental and economic reasons, it is desirable in the marketplace to be able to recycle those used but not yet fully scrapped parts. Such as replacement of consumables in the fitting to repair such used fittings. If the service life information recorded in the chip cannot be modified, the used chip on the accessory needs to be replaced synchronously.

However, the used chip is not completely unusable, and if the used chip is directly replaced and discarded, the used chip is not friendly to the environment; if the used chip is used directly, part of the data in the used chip may not be recognized by the host device, resulting in an accessory abnormality. To solve this problem, one treatment scheme in the prior art is: and setting a patch chip between the host device and the used chip, and transferring information to be transmitted between the host device and the used chip by using the patch chip.

In general, due to the constraint of the communication rule of the host device, the host device and the patch chip need to communicate in an encrypted manner. However, when the patch chip communicates with the original chip, the communication rule of the host device need not be satisfied. If the patch chip and the original chip still adopt encryption mode communication, on one hand, the second count value in the original chip is increased, and the service life of the original chip is reduced; on the other hand, the encryption and decryption steps in the encryption communication not only increase the performance overhead of the communication system, but also reduce the communication rate, so that the response time of the original chip is too long.

Disclosure of Invention

In view of this, the present application provides a communication method, a first chip, a chip assembly and a replaceable accessory, so as to facilitate solving the problem that in the prior art, a patch chip and an original chip communicate in an encrypted manner, which on one hand results in an increase of a second count value in the original chip, and reduces the service life of the original chip; on the other hand, the encryption and decryption steps in the encryption communication can increase the performance overhead of the communication system and reduce the communication rate, so that the problem of overlong response time of the original chip is caused.

In a first aspect, an embodiment of the present application provides a communication method, applied to a first chip, where the method includes:

after passing the first authentication of the host device, communicating with the host device through an encryption instruction;

communicating with a second chip through a plaintext instruction, or after passing a second authentication of the second chip, communicating with the second chip through an encrypted instruction; at least part of information between the first chip and the second chip is transmitted through the plaintext instruction.

In a possible implementation manner, in the first authentication process, a first count value for authentication stored in the first chip is increased according to a preset first gradient;

in the second authentication process, a second count value for authentication stored in the second chip is increased according to a preset second gradient.

In some possible implementations, the communicating with the host device through encrypted instructions includes:

receiving a first encryption request instruction sent by the host equipment, wherein the first encryption request instruction comprises request information;

and sending a first encryption response instruction to the host device, wherein the first encryption response instruction comprises response information corresponding to the request information.

In some possible implementations, the communicating with the second chip through the plaintext instruction, or after passing the second authentication on the second chip, communicating with the second chip through the encrypted instruction, includes:

if the first chip does not contain the response information corresponding to the request information, the first chip communicates with the second chip through a plaintext instruction, or after passing through the second authentication of the second chip, the first chip communicates with the second chip through an encrypted instruction, so as to acquire the response information corresponding to the request information in the second chip.

In some possible implementations, the communicating with the second chip through a plaintext instruction or after passing through a second authentication on the second chip, the communicating with the second chip through an encrypted instruction, so as to obtain response information corresponding to the request information in the second chip, includes:

if the request information is first type request information, communicating with the second chip through a plaintext instruction to obtain response information corresponding to the request information in the second chip;

and if the request information is the second type of request information, communicating with the second chip through an encryption instruction to obtain response information corresponding to the request information in the second chip.

In some possible implementations, before the communicating with the second chip through the plaintext instruction if the request information is the first type of request information, the method further includes:

determining that the request information is first type request information or second type request information through an instruction type lookup table;

the first type request information is used for indicating communication with the second chip through a plaintext instruction, and the second type request information is used for indicating communication with the second chip through an encrypted instruction.

In some possible implementations, the communicating with the second chip through a plaintext instruction to obtain response information corresponding to the request information in the second chip includes:

sending a plaintext request instruction to the second chip, wherein the plaintext request instruction comprises the request information;

and receiving a plaintext response instruction sent by the second chip, wherein the plaintext response instruction comprises response information corresponding to the request information.

In some possible implementations, the communicating with the second chip through an encryption instruction to obtain response information corresponding to the request information in the second chip includes:

Sending a second encryption request instruction to the second chip, wherein the second encryption request instruction comprises the request information;

and receiving a second encryption response instruction sent by the second chip, wherein the second encryption response instruction comprises response information corresponding to the request information.

In some possible implementations, the communicating with the second chip through the plaintext instruction, or after passing the second authentication on the second chip, communicating with the second chip through the encrypted instruction, includes:

and communicating with a second chip through a plaintext instruction or communicating with the second chip through an encrypted instruction after passing through second authentication of the second chip so as to acquire synchronizable data in the second chip, wherein the synchronizable data is data which can be synchronized into the first chip.

In a second aspect, an embodiment of the present application provides a communication method, applied to a second chip, where the method includes:

the method comprises the steps of communicating with a first chip through a plaintext instruction or communicating with the first chip through an encrypted instruction after passing through second authentication of the first chip;

in the second authentication process, a second count value for authentication stored in the second chip is increased according to a preset second gradient, and at least part of information between the first chip and the second chip is transmitted through the plaintext instruction.

In some possible implementations, the communicating with the first chip through a plaintext instruction, or after passing through the second authentication of the first chip, communicating with the first chip through an encrypted instruction, includes:

the first chip is communicated with the second chip through a plaintext instruction so as to send response information corresponding to the request information to the second chip;

or after passing the second authentication of the first chip, communicating with the first chip through an encryption instruction to send response information corresponding to the request information to the first chip.

In some possible implementations, the communicating with the first chip through a plaintext instruction to send response information corresponding to the request information to the first chip includes:

receiving a plaintext request instruction sent by the first chip, wherein the plaintext request instruction comprises the request information;

and sending a plaintext response instruction to the first chip, wherein the plaintext response instruction comprises response information corresponding to the request information.

In some possible implementations, the communicating with the first chip through an encryption instruction to send response information corresponding to the request information to the first chip includes:

Receiving a second encryption request instruction sent by the first chip, wherein the second encryption request instruction comprises the request information;

and sending a second encryption response instruction to the first chip, wherein the second encryption response instruction comprises response information corresponding to the request information.

In some possible implementations, the communicating with the first chip through a plaintext instruction, or after passing through the second authentication of the first chip, communicating with the first chip through an encrypted instruction, includes:

and communicating with the first chip through a plaintext instruction or communicating with the first chip through an encrypted instruction after passing through second authentication of the first chip so as to send synchronizable data to the first chip, wherein the synchronizable data are data which can be synchronized into the first chip.

In a third aspect, an embodiment of the present application provides a first chip configured to perform the method of any one of the first aspects.

In a fourth aspect, embodiments of the present application provide a second chip configured to perform the method of any one of the second aspects.

In a fifth aspect, an embodiment of the present application provides a chip assembly, including: the first chip of the third aspect and the second chip of the fourth aspect are communicatively connected.

In a sixth aspect, embodiments of the present application provide a replaceable accessory comprising the chip assembly of the fifth aspect.

In the embodiment of the application, the host device and the first chip communicate in an encrypted mode, and at least part of information between the first chip and the second chip communicates in a non-encrypted (plaintext) mode. When the first chip and the second chip communicate in a non-encryption mode, on one hand, the increase of a second count value in the second chip can be avoided, and the service life of the second chip is prolonged; on the other hand, the encryption and decryption steps of the first chip and the second chip on the communication instruction are reduced, so that the performance cost of a communication system is saved, the communication rate is improved, and the response speed of the second chip is further improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a block diagram of a communication system in the related art;

fig. 2 is a block diagram of a communication system according to an embodiment of the present application;

FIG. 3 is a schematic flow chart of a communication method according to an embodiment of the present application;

fig. 4 is a flow chart of another communication method according to an embodiment of the present application;

fig. 5 is a flow chart of another communication method according to an embodiment of the present application;

fig. 6 is a flow chart of another communication method according to an embodiment of the present application;

fig. 7 is a flow chart of another communication method according to an embodiment of the present application;

fig. 8 is a flow chart of another communication method according to an embodiment of the present application;

fig. 9 is a flow chart of another communication method according to an embodiment of the present application;

FIG. 10 is a block diagram of a chip assembly according to an embodiment of the present application;

fig. 11 is a block diagram of a replaceable accessory according to an embodiment of the present application.

Detailed Description

For a better understanding of the technical solution of the present application, the following detailed description of the embodiments of the present application refers to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one way of describing an association of associated objects, meaning that there may be three relationships, e.g., a and/or b, which may represent: the first and second cases exist separately, and the first and second cases exist separately. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

In order to facilitate understanding, concepts related to the embodiments of the present application will be described first.

Original chip: the original chip on the replaceable accessory, which may also be referred to as a "used chip", "old chip", or "second chip" in some possible implementations;

patch chip: the chip, which is disposed between the host device and the original chip and provides information transfer for the host device and the original chip, may also be referred to as a "regeneration chip", "grafting chip", or "first chip" in some possible implementations.

Referring to fig. 1, a block diagram of a communication system in the related art is shown. As shown in fig. 1, the communication system includes a host device 100 and a replaceable accessory 200. For example, the host device 100 may be an image forming apparatus, a mobile terminal, a computer, or the like, and the replaceable accessory 200 may be a consumable cartridge, a headset, a battery, a peripheral, or the like, correspondingly.

In some possible implementations, the replaceable accessory 200 includes a raw chip 211, the raw chip 211 being communicatively connected to the host device 100 via a first communication link 301. It is understood that the original chip 211 and the host device 100 can transmit and receive data through the first communication link 301. Illustratively, the first communication link 301 may be an electrical, optical, infrared, or other suitable information transmission path disposed between the host device 100 and the original chip 211.

In some possible implementations, the original chip 211 has authentication information stored therein, through which the host device 100 can authenticate the replaceable accessory 200. In addition, the original chip 211 may also store information such as the usage history and the service life of the replaceable accessory 200.

In some possible implementations, the authentication information stored in the raw chip 211 includes a plurality of encrypted seed data, a plurality of count values, and a plurality of keys. Wherein each encrypted seed data is associated with a count value and a key. For convenience of distinction, the count value in the original chip 211 is referred to as "second count value". In the process of authenticating the original chip 211 by the host device 100, the host device 100 needs to acquire the encrypted seed data in the original chip 211, and the second count value is used to record the number of times the corresponding encrypted seed data in the original chip 211 is accessed.

For ease of understanding, an authentication process of the original chip 211 by the host device 100 is exemplarily described below.

Specifically, the host device 100 transmits an authentication information acquisition instruction for instructing to read the plurality of encrypted seed data in the original chip 211 and the second count value corresponding to each of the plurality of encrypted seed data to the original chip 211. After receiving the authentication information acquisition instruction, the original chip 211 transmits the information to the host device 100. For example, the authentication information obtaining instruction is used to instruct to read 4 pieces of encrypted seed data and the corresponding second count value, and the information fed back by the original chip 211 is shown in table one.

Table one:

encryption seedSub data	A second count value
		3D 02 B8 C1	00 05
3D 5A 70 C1	00 00
		3D E0 66 C1	00 FE
3D 09 0F C1	00 90

In table one, 3d XX C1 is encryption seed data (with the same prefix and suffix), and the last two bytes are a second count value used to characterize the number of times the corresponding encryption seed data is accessed. For example, the encrypted seed data [3d E0 66C1] is accessed for the number of times [00FE ].

When the host device 100 reads the above information, a new instruction is continuously issued, indicating that the encryption seed data therein needs to be selected, and communication authentication is performed with the selected encryption seed data.

Illustratively, the host device 100 sends an authentication instruction to the original chip 211, the authentication instruction indicating that the 3 rd encryption seed data [3d E0 66C1] is selected. After receiving the authentication instruction, the original chip 211 performs the following internal operations: searching a corresponding Key Key and a corresponding second count value [00FE ] according to the 3 rd encrypted seed data [3D E0 66C1 ]; 1-adding the second count value [00FE ], wherein the updated second count value is [00FF ]; and generating a session Key by using the searched Key, the updated second count value [00FF ] and the generated random number [8D DC 5F B8 ]. Thereafter, the original chip 211 may perform encrypted communication with the host device 100 based on the session key.

In addition, for the authentication instruction, information fed back to the host device 100 by the original chip 211 is: 3D E0 66C1 8DDC 5F B8 00FF. Here, [3d E0 66C1] is the encrypted seed data selected by the host device 100, [8d DC 5f B8] is the random number generated by the original chip 211, and [00FF ] is the second count value updated by the original chip 211. The host device 100 stores a Key corresponding to the encrypted seed data, and after receiving the above information fed back by the original chip 211, the host device 100 may search for the corresponding Key according to the 3 rd encrypted seed data [3d E0 66c1], and then generate a session Key (session Key) using the searched Key, the updated second count value [00FF ] and the generated random number [8d DC 5f B8 ]. Thereafter, the host device 100 can perform encrypted communication with the original chip 211 based on the session key. Note that, since the encrypted seed data and the corresponding second count value acquired in the original chip 211 are stored in the host device 100, the information fed back to the host device 100 by the original chip 211 may not include the encrypted seed data and the corresponding second count value selected by the host device 100 for the authentication instruction, which is not particularly limited in the embodiment of the present application.

If the host device 100 does not send the authentication instruction to the original chip 211, it may indicate that the host device 100 communicates with the original chip 211 in an unencrypted (e.g., clear) manner. That is, the communication between the host device 100 and the original chip 211 may be encrypted or unencrypted. In some possible implementations, the unencrypted communication may also be referred to as a plaintext communication.

It can be understood that, after each authentication instruction is executed, the original chip 211 adds 1 to the second count value corresponding to the selected encrypted seed data, so as to ensure that the session keys of each encrypted communication are different, and improve the security of the encrypted communication.

It is envisioned that if the replaceable accessory 200 is used for a long period of time, a problem may exist in that the second count value is larger for some of the encrypted seed data in the original chip 211 on the replaceable accessory 200, indicating that the original chip 211 has been encrypted and authenticated many times. In some application scenarios, when the second count value is larger, the data verification in the original chip 211 may not pass, and the original chip 211 feeds back an error code to the host device 100. It should be noted that the second count value in the original chip 211 can generally only be rewritten to a larger value and cannot be reduced.

In view of the above, the embodiment of the present application provides a patch chip 212 between the host device 100 and the original chip 211, and relays information between the host device 100 and the original chip 211 through the patch chip 212. Since the first count value corresponding to the encrypted seed data in the patch chip 212 may be set to a smaller value, the probability of passing the authentication of the host device 100 on the patch chip 212 may be improved, thereby improving the service life of the original chip 211. The detailed description is provided below in connection with specific implementations.

Referring to fig. 2, a block diagram of a communication system according to an embodiment of the present application is provided. As shown in fig. 2, the communication system includes a host device 100 and a replaceable accessory 200. For example, the host device 100 may be an image forming apparatus, a mobile terminal, a computer, or the like, and the replaceable accessory 200 may be a consumable cartridge, a headset, a battery, a peripheral, or the like, correspondingly.

In some possible implementations, the replaceable accessory 200 includes a chip assembly 210, the chip assembly 210 including a patch chip 212 and an original chip 211. Wherein host device 100 is communicatively coupled to patch chip 212 via a second communication link 302, which second communication link 302 may be an electrical, optical, infrared, or other suitable information transmission path disposed between host device 100 and patch chip 212. Patch chip 212 is communicatively coupled to original chip 211 via a third communication link 303, which third communication link 303 may be an electrical, optical, infrared or other suitable information transmission path disposed between patch chip 212 and original chip 211.

Referring to fig. 3, a flow chart of a communication method according to an embodiment of the present application is provided. The method is applicable to the communication system shown in fig. 2, and as shown in fig. 3, it mainly includes the following steps.

Step S301: the first chip sends a first data acquisition instruction to the second chip, wherein the first data acquisition instruction is used for indicating to acquire a plurality of encrypted seed data in the second chip.

In the embodiment of the application, the first chip is the patch chip, and the second chip is the original chip. The second chip typically stores a plurality of encrypted seed data, and a second count value and a key corresponding to each encrypted seed data, where the second count value is used to characterize the number of times the encrypted seed data is accessed in the second chip.

Specifically, after the first chip and the second chip are powered on, the first chip sends a first data acquisition instruction to the second chip, wherein the first data acquisition instruction is used for indicating to acquire a plurality of encrypted seed data in the second chip. It should be noted that the plurality of encrypted seed data obtained by the first chip in the second chip may be all encrypted seed data in the second chip, or may be part of encrypted seed data in the second chip (for example, 10 encrypted seed data are in the second chip, and 8 encrypted seed data are obtained by the first chip in the second chip), which is not particularly limited in this embodiment of the present application.

In some possible implementations, the first data obtaining instruction is used to instruct, in addition to obtaining the plurality of encrypted seed data in the second chip, to obtain a second count value and/or a key corresponding to each encrypted seed data in the plurality of encrypted seed data, or to obtain information such as a usage history or a service life of the replaceable accessory in the second chip, which is not limited in particular by the embodiment of the present application.

Step S302: the second chip sends a plurality of encrypted seed data to the first chip.

Specifically, after receiving the first data acquisition instruction sent by the first chip, the second chip may send a plurality of encrypted seed data to the first chip according to the first data acquisition instruction. According to the indication of the first data obtaining instruction, the plurality of encrypted seed data may be all encrypted seed data in the second chip, or may be part of encrypted seed data in the second chip, which is not particularly limited in the embodiment of the present application.

In addition, according to the indication of the first data obtaining instruction, in addition to sending the plurality of encrypted seed data to the first chip, the second count value and/or the key corresponding to each encrypted seed data in the plurality of encrypted seed data may be sent to the first chip, or the information such as the usage history or the service life of the replaceable accessory may be sent to the first chip.

In some possible implementations, after the first chip and the second chip are powered up, the second chip may actively send data (a plurality of encrypted seed data, a second count value, etc.) to the first chip, i.e. without performing step S301.

Step S303: the first chip configures a first count value for each encrypted seed data.

Specifically, after the first chip reads a plurality of encrypted seed data in the second chip, a count value may be configured for each encrypted seed data. For convenience of distinction, the count value in the first chip is referred to as a "first count value". The first count value is used to characterize the number of times the encrypted seed data is accessed in the first chip.

In some possible implementations, at least one first count value of the encryption seed data in the first chip is smaller than a second count value of the encryption seed data in the second chip. That is, the first count value in the first chip is smaller, and thus the probability of the host device passing the authentication of the first chip can be improved. It will be appreciated that, to obtain a better effect, the first count value corresponding to each encrypted seed data in the first chip may be configured to be smaller than the second count value corresponding to the encrypted seed data in the second chip. For example, the first chip reads 4 encrypted seed data and the corresponding first count value thereof in the second chip, as shown in table two.

And (II) table:

encrypting seed data	First count value
		3D 02 B8 C1	00 00
3D 5A 70 C1	00 00
		3D E0 66 C1	00 00
3D 09 0F C1	00 00

As shown in table two, the first count values corresponding to the plurality of encrypted seed data in the first chip are all [00 ], and when the host device performs encrypted authentication on the first chip, the first count value read by the host device is smaller, so the host device considers that the replaceable accessory is a new or newer accessory.

It should be noted that, in practical application, the first chip may read a plurality of encrypted seed data in advance in the second chip after the first chip and the second chip are powered on for the first time, and configure a first count value for each encrypted seed data, without executing the above steps S301 to S303 before each authentication.

Step S304: the host device sends a second data acquisition instruction to the first chip, the second data acquisition instruction being used for indicating acquisition of a plurality of encrypted seed data in the first chip.

Specifically, after the host device and the first chip are powered on, the host device sends a second data acquisition instruction to the first chip, where the second data acquisition instruction is used to instruct to acquire a plurality of encrypted seed data in the first chip. It should be noted that, the plurality of encrypted seed data obtained by the host device in the first chip may be all encrypted seed data in the first chip, or may be part of encrypted seed data in the first chip (for example, 8 encrypted seed data in the first chip, and 6 encrypted seed data are obtained by the host device in the first chip), which is not particularly limited in this embodiment of the present application.

In some possible implementations, the second data obtaining instruction is used to indicate that, in addition to obtaining the plurality of encrypted seed data in the first chip, a second count value and/or a key corresponding to each of the plurality of encrypted seed data is obtained, or to indicate that information such as a usage history or a service life of the replaceable accessory is obtained in the first chip, which is not limited in particular by the embodiment of the present application.

Step S305: the first chip sends a plurality of encrypted seed data to the host device.

Specifically, after receiving the second data acquisition instruction sent by the host device, the first chip may send a plurality of encrypted seed data to the host device according to the second data acquisition instruction. According to the indication of the second data obtaining instruction, the plurality of encrypted seed data may be all encrypted seed data in the first chip, or may be part of encrypted seed data in the first chip, which is not particularly limited in the embodiment of the present application.

In addition, according to the indication of the second data acquisition instruction, in addition to sending the plurality of encrypted seed data to the host device, a second count value and/or a key corresponding to each encrypted seed data in the plurality of encrypted seed data may be sent to the host device, or information such as a usage history or a service life of the replaceable accessory may be sent to the host device.

In some possible implementations, after the host device and the first chip are powered up, the first chip may actively send data (the plurality of encrypted seed data, the second count value, etc.) to the host device, i.e., without performing step S304.

It should be noted that, in practical applications, the host device may read a plurality of encrypted seed data and the first count value corresponding to the encrypted seed data in the first chip in advance after the host device and the first chip are powered on for the first time, without executing the steps S304 to S305 before each authentication.

Step S306: the host device sends a first authentication instruction to the first chip, wherein the first authentication instruction is used for indicating the first chip to carry out encrypted communication with the host device at least by using first target encrypted seed data in a plurality of encrypted seed data in the first chip and a first count value corresponding to the first target encrypted seed data.

Illustratively, the first chip stores the 4 encrypted seed data in table two, and the first authentication instruction is configured to instruct the first chip to perform encrypted communication with the host device using at least the 3 rd encrypted seed data [3d E0 66c1] in the 4 encrypted seed data, and the first count value [00 ] corresponding to the 3 rd encrypted seed data. That is, the first target encrypted seed data is the 3 rd encrypted seed data [3d E0 66C1] in table two.

Specifically, the first chip may search for a corresponding Key according to the first target encryption seed data, and generate a session Key using the searched Key, the first count value (or the updated first count value), and the generated random number. Thereafter, the first chip may conduct encrypted communications with the host device based on the session key.

Step S307: the first chip controls a first count value corresponding to the first target encryption seed data to be increased according to a preset first gradient.

Specifically, after receiving a first authentication instruction sent by the host device, the first chip controls a first count value corresponding to the first target encryption seed data to increment according to a preset first gradient so as to update the first count value corresponding to the first target encryption seed data, namely, update the number of times that the first target encryption seed data is accessed. Typically, the first gradient takes a value of "1". That is, after each time the first authentication instruction sent by the host device is received, the first count value corresponding to the first target encryption seed data is incremented by 1. Of course, those skilled in the art may set the first gradient to other values according to actual needs, which is not particularly limited in the embodiment of the present application.

Illustratively, the first target encrypted seed data is the 3 rd encrypted seed data [3d E0 66C1] in table two, which corresponds to the first count value of [00 ], and the first count value of [00 ] is added by 1 to obtain the updated first count value of [00 01].

In the embodiment of the application, the first count value corresponding to the encrypted seed data in the first chip is a smaller value, so that the probability of passing the authentication of the host equipment on the first chip can be improved, and the service life of the second chip can be further prolonged.

In practical applications, the first chip may store a portion of the data acquired in the second chip. After the first chip receives the request information sent by the host equipment, if the response information corresponding to the request information is stored in the first chip, the first chip directly feeds back the response information to the host equipment; if the response information corresponding to the request information is not stored in the first chip, the first chip needs to acquire the response information corresponding to the request information in the second chip, and then the response information is fed back to the host device. Therefore, the first chip also needs to perform communication authentication with the second chip.

Referring to fig. 4, a flow chart of another communication method according to an embodiment of the present application is shown. As shown in fig. 4, the method further comprises the following steps on the basis of the embodiment shown in fig. 3.

Step S401: the first chip sends a second authentication instruction to the second chip, wherein the second authentication instruction is used for indicating the second chip to carry out encrypted communication with the first chip at least by using second target encrypted seed data in a plurality of encrypted seed data in the second chip and a second count value corresponding to the second target encrypted seed data.

Illustratively, the second chip stores the 4 encrypted seed data in table one, and the second authentication instruction is configured to instruct the second chip to use at least the 4 th encrypted seed data [3d 09 f 0f C1] in the 4 th encrypted seed data, and the second count value [00 ] corresponding to the 4 th encrypted seed data to perform encrypted communication with the first chip. That is, the second target encryption seed data is the 4 th encryption seed data [3d 09 f 0f C1] in table one.

Specifically, the second chip may search for a corresponding Key according to the second target encryption seed data, and generate the session Key using the searched Key, the second count value (or the updated second count value), and the generated random number. Thereafter, the second chip may perform encrypted communication with the first chip based on the session key.

In practical applications, the second count values corresponding to different encrypted seed data in the second chip may be different. For example, in table one, the second count value corresponding to the 1 st encrypted seed data [3d 02b8 C1] is [00 ] 05; the second count value corresponding to the 2 nd encrypted seed data [3D 5A 70 C1] is [00 ]; the second count value corresponding to the 3 rd encryption seed data [3D E0 66 C1] is [00FE ]; the second count value corresponding to the 4 th encrypted seed data [3D 09F C1] is [00 ] 90]. If the 3 rd encrypted seed data [3d E0 66 C1] is selected as the second target encrypted seed data, the second count value [00FE ] corresponding to the 3 rd encrypted seed data [3d E0 66 C1] may be larger, so that the data verification in the second chip is not passed, and the second chip feeds back an error code to the first chip, thereby making the second chip unusable. Therefore, in order to increase the probability of the first chip identifying the second chip and utilize the second count value resource in the second chip as much as possible, in some possible implementations, the encrypted seed data with the smaller second count value may be selected for communication authentication. Specifically, according to a second count value corresponding to each piece of encrypted seed data, encrypted seed data with a smaller second count value in a plurality of pieces of encrypted seed data in a second chip is determined, and the encrypted seed data with the smaller second count value is used as second target encrypted seed data. The "encrypted seed data with smaller second count value" may be N encrypted seed data with the smallest second count value, where N may take a value of 1, 2 or 3, etc., which is not particularly limited in the embodiment of the present application.

Illustratively, among the 4 encrypted seed data shown in table one, the second count value [00 ] corresponding to the 2 nd encrypted seed data [3d 5a 70 C1] is smallest, and therefore, the 2 nd encrypted seed data [3d 5a 70 C1] is taken as the second target encrypted seed data. It will be appreciated that an increase in the number of accesses to the 2 nd encrypted seed data [3d 5a 70 C1] (an increase in the second count value [00 ]) does not immediately result in the second chip being unusable, thereby ensuring that the second chip can continue to be used.

Step S402: the second chip controls a second count value corresponding to the second target encryption seed data to be increased according to a preset second gradient.

Specifically, after receiving the second authentication instruction sent by the first chip, the second chip controls the second count value corresponding to the second target encryption seed data to increment according to a preset second gradient so as to update the second count value corresponding to the second target encryption seed data, namely, update the number of times that the second target encryption seed data is accessed. Typically, the second gradient takes a value of "1". That is, after each time the second authentication instruction sent by the first chip is received, the second count value corresponding to the second target encryption seed data is incremented by 1. Of course, those skilled in the art may set the second gradient to other values according to actual needs, which are not particularly limited in the embodiment of the present application.

Illustratively, the second target encrypted seed data is the 2 nd encrypted seed data [3d 5a 70 C1] in table one, the corresponding second count value is [00 ], the second count value is [00 ] and 1 is added to the second count value to obtain an updated second count value is [00 01].

It should be noted that, in the embodiment of the present application, a session key generated when the host device and the first chip perform communication authentication (the session key is referred to as a "first session key" for convenience of description) may be different from a session key generated when the first chip and the second chip perform communication authentication (the session key is referred to as a "second session key" for convenience of description), and there may be the following two cases: first, a first count value corresponding to a first session key and a second count value corresponding to a second session key are different, resulting in the first session key and the second session key being different; second, the encrypted seed data corresponding to the first session key and the second session key are different, resulting in the first session key and the second session key being different.

It can be understood that, when the first chip and the second chip need to perform encrypted communication, the first chip needs to perform encrypted authentication on the second chip, that is, needs to perform the steps S401 to S403. The encryption authentication of the first chip to the second chip has the following two processing occasions.

First, after the first chip and the second chip are powered on, the second chip is immediately subjected to encryption authentication (a second authentication instruction is sent to the second chip), namely, the second chip is subjected to advanced authentication. Because the second chip does not need to be encrypted and authenticated temporarily when the encryption instruction is needed to be sent later, the response speed of the first chip can be quickened later.

Second, when the encryption command needs to be sent, encryption authentication is performed on the second chip (the second authentication command is sent to the second chip). Specifically, before the first chip sends an encryption instruction to the second chip, the second chip is subjected to encryption authentication. The authentication mode does not need the second chip to be in a power supply and standby state all the time, so that the overall power consumption of the chip assembly can be reduced.

Typically, due to constraints of communication rules of the host device, encrypted communication is required between the host device and the first chip. However, when the first chip communicates with the second chip, the communication rule of the host device need not be satisfied. If the first chip and the second chip still communicate in an encrypted mode, on one hand, the second count value in the second chip is increased, and the service life of the second chip is reduced; on the other hand, the encryption and decryption steps in the encryption communication not only increase the performance overhead of the communication system, but also reduce the communication rate, so that the response time of the second chip is too long.

In view of the above, an embodiment of the present application provides a communication method, in which a host device and a first chip communicate in an encrypted manner, and at least part of information between the first chip and a second chip communicates in an unencrypted (plaintext) manner. When the first chip and the second chip communicate in a non-encryption mode, on one hand, the increase of a second count value in the second chip can be avoided, and the service life of the second chip is prolonged; on the other hand, the encryption and decryption steps of the first chip and the second chip on the communication instruction are reduced, so that the performance cost of a communication system is saved, the communication rate is improved, and the response speed of the second chip is further improved. The detailed description is provided below in connection with specific implementations.

Referring to fig. 5, a flow chart of another communication method according to an embodiment of the present application is shown. The method is applicable to the communication system shown in fig. 2, and as shown in fig. 5, it mainly includes the following steps.

Step S501: after passing the first authentication of the first chip, the host device communicates with the first chip through the encryption instruction.

Typically, due to constraints of communication rules of the host device, encrypted communication is required between the host device and the first chip. Prior to the encrypted communication, the host device needs to perform communication authentication for the first chip, which is referred to as "first authentication" for convenience of distinction.

In some possible implementations, the first authentication includes the authentication process of the embodiment shown in fig. 3 described above. As described above, after the host device passes the first authentication on the first chip, the first count value corresponding to a certain encrypted seed data in the first chip is increased, the first session key is generated in the host device and the first chip, and the host device and the first chip can generate the encrypted instruction through the first session key, so as to communicate through the encrypted instruction. For details of the first authentication, reference may be made to the description of the above embodiments, and for brevity of description, details are not repeated here.

Step S502: the first chip and the second chip communicate through plaintext instructions; or after passing the second authentication of the second chip, the first chip and the second chip communicate through the encryption instruction.

In the embodiment of the application, the first chip and the second chip can communicate through the plaintext instruction and can communicate through the encrypted instruction as the communication rule of the host equipment is not required to be satisfied when the first chip and the second chip communicate.

When the first chip and the second chip communicate by an encryption instruction, the first chip needs to perform communication authentication on the second chip before encrypting communication, and this communication authentication is referred to as "second authentication" for convenience of distinction. In some possible implementations, the second authentication includes the authentication process of the embodiment shown in fig. 4 described above. As described above, after the first chip passes the second authentication of the second chip, the second count value corresponding to a certain encrypted seed data in the second chip is increased, and the second session keys are generated in the first chip and the second chip respectively, so that the first chip and the second chip can generate the encrypted command through the second session keys, and further communicate through the encrypted command. For details of the second authentication, reference may be made to the description of the above embodiments, and for brevity of description, details are not repeated here.

When the first chip and the second chip communicate through the plaintext instruction, on one hand, the first chip does not need to carry out communication authentication on the second chip, so that the second count value in the second chip is not increased, and the service life of the second chip is further prolonged; on the other hand, the encryption and decryption steps of the first chip and the second chip on the communication instruction are reduced, so that the performance cost of a communication system is saved, the communication rate is improved, and the response speed of the second chip is further improved.

It should be noted that in the embodiment of the present application, at least part of the information between the first chip and the second chip is transmitted by a plaintext instruction.

For ease of understanding, the communication method shown in fig. 5 is described in detail below in connection with a specific communication flow.

Referring to fig. 6, a flow chart of another communication method according to an embodiment of the present application is shown. The method is applicable to the communication system shown in fig. 2, and as shown in fig. 6, it mainly includes the following steps.

Step S601: the host device sends a first encryption request instruction to the first chip, wherein the first encryption request instruction contains request information.

Specifically, the host device may generate a first encryption request instruction based on the first session key after passing the first authentication of the first chip, and then transmit the first encryption request instruction to the first chip. The request information in the first encryption request instruction is used to characterize information that the host device needs to acquire.

Step S602: if the first chip does not contain the response information corresponding to the request information, the first chip communicates with the second chip through a plaintext instruction, or after passing through the second authentication of the second chip, the first chip communicates with the second chip through an encrypted instruction, so as to acquire the response information corresponding to the request information in the second chip.

Specifically, after receiving the first encryption request instruction, the first chip may parse the first encryption request instruction to obtain the request information in the first encryption request instruction. If the first chip does not contain the response information corresponding to the request information, the first chip needs to communicate with the second chip, and the response information corresponding to the request information is acquired from the second chip.

The first chip and the second chip may communicate directly through a plaintext instruction, and response information corresponding to the request information is obtained from the second chip; it is also possible to communicate with the second chip through an encryption instruction after the second authentication of the second chip, and obtain response information corresponding to the request information in the second chip, which will be described in detail below.

Step S603: the first chip sends a first encryption response instruction to the host device, wherein the first encryption response instruction contains response information corresponding to the request information.

Specifically, after the first chip obtains the response information corresponding to the request information from the second chip, a first encrypted response instruction may be generated based on the first session key, and then the first encrypted response instruction is sent to the first chip, where the first encrypted response instruction includes the response information corresponding to the request information.

It should be noted that, if the first chip stores the response information corresponding to the request information, the first chip does not need to communicate with the second chip, that is, step S602 is skipped, and the first chip directly sends the first encryption response instruction to the host device. It can be understood that the information processing manner can enable the response speed of the first chip to be faster. Therefore, in order to increase the response speed of the first chip, the data in the second chip should be stored in the first chip as synchronously as possible, and the first chip directly feeds back information to the host device. Of course, due to the different architecture of the first chip and the second chip, or communication protocol limitations, etc., some data in the second chip may not be synchronized into the first chip, i.e. information feedback to the host device must be performed by the second chip.

In a specific implementation, the data in the second chip may be divided into synchronizable data and unsynchronizable data. The synchronizable data refers to data which can be synchronized into the first chip and can be fed back to the host device by the first chip; the unsynchronizable data refers to data that cannot be synchronized into the first chip or fed back to the host device by the first chip. The second chip sends the synchronous data to the first chip and stores the synchronous data in the first chip so as to enable the first chip to directly feed back information to the host equipment as much as possible, and the response speed of the first chip is improved.

As described above, when the first chip does not include the response information corresponding to the request information, the first chip may communicate with the second chip directly through the plaintext instruction, and obtain the response information corresponding to the request information in the second chip; it is also possible to obtain response information corresponding to the request information in the second chip by communicating with the second chip through the encrypted instruction. If the communication is carried out in an encrypted mode, on one hand, a second count value in the second chip is increased, and the service life of the second chip is reduced; on the other hand, the encryption and decryption steps in the encryption communication not only increase the performance overhead of the communication system, but also reduce the communication rate, so that the response time of the second chip is too long. Thus, the first chip should communicate with the second chip in a preferential, non-encrypted manner.

However, since the types of data stored in the second chip are different, a plaintext instruction may be employed for transmission of some types of data, such as encryption seed data, a second count value, etc.; for other types of data, encryption instructions must be used for transmission, e.g., keys, etc. Therefore, the first chip needs to distinguish the communication type (encrypted communication or unencrypted communication) with the second chip, which will be described in detail below.

Referring to fig. 7, a flow chart of another communication method according to an embodiment of the present application is shown. As shown in fig. 7, step S602 shown in fig. 6 specifically includes the following steps.

Step S701: the first chip determines the request information to be the first type request information or the second type request information through the instruction type lookup table.

In the embodiment of the application, the mapping relation between the request information type and the communication type can be preset in the instruction type lookup table. The request information type comprises first type request information and second type request information, the communication type comprises encrypted communication and non-encrypted communication, the first type request information corresponds to the non-encrypted communication, and the second type request information corresponds to the encrypted communication. Therefore, after the first chip obtains the request information, the type of the request information can be determined through the instruction type lookup table, and the communication type with the second chip is further determined.

It should be noted that the first chip may determine the type of the request information in other manners, which is not particularly limited by the embodiment of the present application. For example, the type flag of the request information may be carried in the request information sent by the host device to the first chip.

Step S702: if the request information is the first type request information, the request information is communicated with the second chip through a plaintext instruction so as to obtain response information corresponding to the request information in the second chip.

As shown in fig. 8, the communication with the second chip through the plaintext instruction specifically includes the following steps.

Step S7021: if the request information is the first type request information, the first chip sends a plaintext request instruction to the second chip, wherein the plaintext request instruction contains the request information.

Step S7022: the second chip sends a plaintext response instruction to the first chip, wherein the plaintext response instruction comprises response information corresponding to the request information.

Step S703: if the request information is the second type request information, the second chip is communicated with the request information through the encryption instruction so as to obtain response information corresponding to the request information in the second chip.

As shown in fig. 9, the communication with the second chip through the encryption instruction specifically includes the following steps.

Step S7031: if the request information is the second type request information, the first chip sends a second encryption request instruction to the second chip, and the second encryption request instruction contains the request information.

Specifically, after determining that the request information is the second type of request information, the first chip may generate a second encryption request instruction based on the second session key, where the second encryption request instruction includes the request information.

Step S7032: the second chip sends a second encryption response instruction to the first chip, wherein the second encryption response instruction comprises response information corresponding to the request information.

Specifically, after receiving the second encryption request instruction, the second chip may parse the second encryption request instruction based on the second session key to obtain request information in the second encryption request instruction; then, searching corresponding response information in the second chip according to the request information; and finally, generating a second encryption response instruction based on the second session key, wherein the second encryption response instruction comprises response information corresponding to the request information, and sending the second encryption response instruction to the first chip.

In the embodiment of the application, the first chip communicates with the second chip in a non-encryption mode preferentially, so that the service life of the second chip can be further prolonged, the performance cost of a communication system is saved, the communication rate is improved, and the response speed of the second chip is further improved.

Corresponding to the above embodiment, the embodiment of the present application further provides a first chip, where the first chip is configured to perform a part or all of the methods on the first chip side in the above method embodiment, and the specific content of the first chip may be referred to the description of the above method embodiment, which is not repeated herein for brevity of description.

Corresponding to the above embodiment, the embodiment of the present application further provides a second chip, where the second chip is configured to perform a part or all of the methods on the second chip side in the above method embodiment, and the specific content of the second chip may be referred to the description of the above method embodiment, which is not repeated herein for brevity of description.

Corresponding to the above embodiment, the embodiment of the application also provides a chip assembly.

Referring to fig. 10, a block diagram of a chip assembly according to an embodiment of the present application is provided. As shown in fig. 10, the chip assembly 1010 includes a first chip 1011 and a second chip 1012, and the first chip 1011 and the second chip 1012 are communicatively connected. For details of the first chip 1011 and the second chip 1012, reference may be made to the description of the above embodiments, and for brevity of description, details are not repeated here.

Corresponding to the above embodiments, the embodiments of the present application also provide a replaceable accessory.

Referring to fig. 11, a block diagram of a replaceable accessory is provided in accordance with an embodiment of the present application. As shown in fig. 11, the replaceable accessory 1000 includes a chip assembly 1010. For details of the chip assembly 1010, reference may be made to the description of the above embodiments, and for brevity of description, details are not repeated here.

Corresponding to the above embodiment, the embodiment of the present application further provides a computer readable storage medium, where the computer readable storage medium may store a program, where when the program runs, the device where the computer readable storage medium is located may be controlled to execute some or all of the steps in the above method embodiment. In particular, the computer readable storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (random access memory, RAM), or the like.

Corresponding to the above embodiments, the present application also provides a computer program product comprising executable instructions which, when executed on a computer, cause the computer to perform some or all of the steps of the above method embodiments.

In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relation of association objects, and indicates that there may be three kinds of relations, for example, a and/or B, and may indicate that a alone exists, a and B together, and B alone exists. Wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of the following" and the like means any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

Those of ordinary skill in the art will appreciate that the various elements and algorithm steps described in the embodiments disclosed herein can be implemented as a combination of electronic hardware, computer software, and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In several embodiments provided by the present application, any of the functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely exemplary embodiments of the present application, and any person skilled in the art may easily conceive of changes or substitutions within the technical scope of the present application, which should be covered by the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims (12)

1. A communication method applied to a first chip, the method comprising:

after passing the first authentication of the host device, communicating with the host device through an encryption instruction;

communicating with a second chip through a plaintext instruction, or after passing a second authentication of the second chip, communicating with the second chip through an encrypted instruction; at least part of information between the first chip and the second chip is transmitted through the plaintext instruction.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

in the first authentication process, a first count value for authentication stored in the first chip is increased according to a preset first gradient;

in the second authentication process, a second count value for authentication stored in the second chip is increased according to a preset second gradient.

3. The method of claim 1, wherein the communicating with the host device via encrypted instructions comprises:

receiving a first encryption request instruction sent by the host equipment, wherein the first encryption request instruction comprises request information;

and sending a first encryption response instruction to the host device, wherein the first encryption response instruction comprises response information corresponding to the request information.

4. A method according to claim 3, wherein said communicating with the second chip via a plaintext instruction or, after passing a second authentication of the second chip, via an encrypted instruction, comprises:

if the first chip does not contain the response information corresponding to the request information, the first chip communicates with the second chip through a plaintext instruction, or after passing through the second authentication of the second chip, the first chip communicates with the second chip through an encrypted instruction, so as to acquire the response information corresponding to the request information in the second chip.

5. The method of claim 4, wherein the communicating with the second chip through a plaintext instruction or after passing through a second authentication of the second chip, communicating with the second chip through an encrypted instruction to obtain response information corresponding to the request information in the second chip, comprises:

If the request information is first type request information, communicating with the second chip through a plaintext instruction to obtain response information corresponding to the request information in the second chip;

and if the request information is the second type of request information, communicating with the second chip through an encryption instruction to obtain response information corresponding to the request information in the second chip.

6. The method of claim 5, wherein prior to said communicating with the second chip via the plain instruction if the request message is of the first type, the method further comprises:

determining that the request information is first type request information or second type request information through an instruction type lookup table;

the first type request information is used for indicating communication with the second chip through a plaintext instruction, and the second type request information is used for indicating communication with the second chip through an encrypted instruction.

7. The method of claim 5, wherein the communicating with the second chip via a plaintext instruction to obtain response information corresponding to the request information in the second chip comprises:

Sending a plaintext request instruction to the second chip, wherein the plaintext request instruction comprises the request information;

and receiving a plaintext response instruction sent by the second chip, wherein the plaintext response instruction comprises response information corresponding to the request information.

8. The method of claim 5, wherein the communicating with the second chip via an encrypted instruction to obtain response information corresponding to the request information in the second chip comprises:

sending a second encryption request instruction to the second chip, wherein the second encryption request instruction comprises the request information;

and receiving a second encryption response instruction sent by the second chip, wherein the second encryption response instruction comprises response information corresponding to the request information.

9. The method of claim 1, wherein the communicating with the second chip via the plaintext instruction or, after passing the second authentication of the second chip, the communicating with the second chip via the encrypted instruction comprises:

and communicating with a second chip through a plaintext instruction or communicating with the second chip through an encrypted instruction after passing through second authentication of the second chip so as to acquire synchronizable data in the second chip, wherein the synchronizable data is data which can be synchronized into the first chip.

10. A first chip, characterized in that it is configured to perform the method of any of claims 1-9.

11. A chip assembly, comprising:

the first chip of claim 10;

and the first chip is in communication connection with the second chip.

12. A replaceable accessory comprising the chip assembly of claim 11.