CN116679875A - Redundant disk array controller switching system, method, electronic device and medium - Google Patents
Redundant disk array controller switching system, method, electronic device and medium Download PDFInfo
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Abstract
The application provides a redundant disk array controller switching system, a method, electronic equipment and a medium, comprising the following steps: the system comprises a main disk array controller, a standby disk array controller, an expansion chip, a first CPU, a second CPU and a baseboard management controller which are respectively connected with the main disk array controller, the standby disk array controller and the expansion chip; the first uplink port of the expansion chip is connected to the main disk array controller, and the second uplink port of the expansion chip is connected to the spare disk array controller; the first CPU is connected to the uplink interface of the main disk array controller, and the second CPU is connected to the uplink interface of the spare disk array controller; the baseboard management controller is used for switching the working disk array controller from the main disk array controller to the standby disk array controller when the main disk array controller fails. The method realizes the effective switching of the disk array controller in the state of not shutting down, thereby ensuring the normal data access operation of the server and no downtime of the upper layer service.
Description
Technical Field
The application relates to the technical field of computers, in particular to a redundant array of inexpensive disks controller switching system, a redundant array of inexpensive disks controller switching method, electronic equipment and a medium.
Background
Disk array ((RedundantArraysofIndependentDrives, RAID))
In the current market, how to improve server quality, reduce failure rate, and improve after-market efficiency is a focus of attention for many server enterprises in order to improve competitiveness. The technology of disk arrays (redundancy array of IndependentDrives, RAID) is widely applied to the field of servers, and multiple hard disks on a hard disk backboard are formed into different RAID levels through RAID cards, so that the storage space can be increased, the data storage speed can be increased, and the data storage stability can be improved.
However, most of the servers at present adopt a design of a single disk array controller (RAIDcontroller), the redundant function of the hard disk level is realized by directly connecting the hard disk in a downlink manner through the disk array controller or connecting the hard disk through an expansion chip, if a single hard disk is damaged, the damaged hard disk is replaced and the disk array logical volume is reconstructed when the server is electrified to work, the lost hard disk data can be recovered to a newly inserted hard disk, and the integrity of the data is ensured. Therefore, since only one disk array controller exists in the server system, when the disk array controller is abnormal, the connected hard disk array also fails together, and the whole storage array is paralyzed when serious, even if the whole storage array can be repaired, the whole system is required to be powered off and then the disk array controller is replaced, and the running stability of the system is difficult to ensure.
Therefore, a method for switching redundant array controllers is needed to solve the above-mentioned problems.
Disclosure of Invention
Based on this, it is necessary to provide a method, a system and an electronic device for optimizing the health degree of a storage system, so as to improve the health degree of the storage system, thereby enabling the storage system to always keep running with higher health degree.
In a first aspect, the present application provides a redundant array of inexpensive disk controller switching system, the system comprising:
the system comprises a main disk array controller, a standby disk array controller, an expansion chip, a first CPU, a second CPU and a baseboard management controller which are respectively connected with the main disk array controller, the standby disk array controller and the expansion chip, wherein the main disk array controller is set as a working disk array controller;
the first uplink port of the expansion chip is connected to the main disk array controller, the second uplink port of the expansion chip is connected to the standby disk array controller, and the expansion chip is also connected with a plurality of hard disks, wherein the second uplink port is set to be in a closed state by default;
the first CPU is connected to an uplink interface of the main disk array controller, and the second CPU is connected to an uplink interface of the spare disk array controller, wherein the uplink interface of the spare disk array controller is set to be in a disabled state by default;
The baseboard management controller is used for closing the connection state of the uplink interfaces of the main disk array controller and the standby disk array controller and expanding the closing state of the first uplink port and the second uplink port of the chip when the main disk array controller fails so as to realize the switching of the working disk array controller from the main disk array controller to the standby disk array controller.
As an improvement, the system further comprises:
and the complex programmable logic device is connected with the main disk array controller, the standby disk array controller and the baseboard management controller and is used for realizing that the baseboard management controller switches the SGPIO signal line for controlling the state of the hard disk indicator lamp from the main disk array controller to the standby disk array controller when the main disk array controller fails.
As an improved scheme, the baseboard management controller is connected to the main disk array controller through a first I2C bus, is connected to the spare disk array controller through a second I2C bus, and is connected to the expansion chip through a third I2C bus;
the first CPU is connected to the uplink interface of the main disk array controller through a first PCIE bus, and the second CPU is connected to the uplink interface of the main disk array controller through a second PCIE bus.
As an improvement, the baseboard management controller is connected to the complex programmable logic device through a fourth I2C bus.
In a second aspect, the present application provides a method for switching redundant array of independent disks controllers, which is characterized in that the method includes:
the baseboard management controller detects whether the main disk array controller set as the working disk array controller fails or not at regular time;
if the main disk array controller fails, the baseboard management controller changes the connection state of the uplink interfaces of the main disk array controller and the spare disk array controller and expands the closing state of the first uplink port and the second uplink port of the chip so as to realize the switching of the working disk array controller from the main disk array controller to the spare disk array controller.
As an improved solution, the baseboard management controller changes the connection state of the uplink interfaces of the main disk array controller and the spare disk array controller and expands the closing state of the first uplink port and the second uplink port of the chip, including:
the baseboard management controller transmits a first switching signal to the main disk array controller and the standby disk array controller, and transmits a second switching signal to the expansion chip;
After the main disk array controller receives the first switching signal, modifying the state of a first register in the main disk array controller to close an uplink interface of the main disk array controller;
after the spare disk array controller receives the first switching signal, modifying the state of a second register in the main disk array controller to enable an uplink interface of the spare disk array controller which is set to be in a disabled state by default;
and after the expansion chip receives the second switching signal, closing the first uplink port and opening the second uplink port of the expansion chip.
As an improvement, the method further comprises:
when the main disk array controller fails, the baseboard management controller issues a third switching command to the complex programmable logic device;
and after the complex programmable logic device receives the third switching command, changing the state of a third register in the complex programmable logic device to realize switching of an SGPIO signal line for controlling the state of the hard disk indicator lamp from the main disk array controller to the standby disk array controller.
As an improvement, the method further comprises:
After the working disk array controller is switched from the main disk controller to the spare disk array controller, the operating system detects the spare disk controller and a plurality of hard disks connected with the spare disk array controller through the expansion chip so as to ensure that the spare disk array controller works normally.
In a third aspect, the present application provides an electronic device, including:
one or more processors;
and a memory associated with the one or more processors, the memory for storing program instructions that, when read for execution by the one or more processors, perform the following:
the baseboard management controller detects whether the main disk array controller set as the working disk array controller fails or not at regular time;
if the main disk array controller fails, the baseboard management controller changes the connection state of the uplink interfaces of the main disk array controller and the spare disk array controller and expands the closing state of the first uplink port and the second uplink port of the chip so as to realize the switching of the working disk array controller from the main disk array controller to the spare disk array controller.
In a fourth aspect, the present application also provides a computer-readable storage medium having stored thereon a computer program that causes a computer to perform the operations of:
the baseboard management controller detects whether the main disk array controller set as the working disk array controller fails or not at regular time;
if the main disk array controller fails, the baseboard management controller changes the connection state of the uplink interfaces of the main disk array controller and the spare disk array controller and expands the closing state of the first uplink port and the second uplink port of the chip so as to realize the switching of the working disk array controller from the main disk array controller to the spare disk array controller.
The beneficial effects achieved by the application are as follows:
the application provides a redundant disk array controller switching system, which comprises a main disk array controller, a spare disk array controller, an expansion chip, a first CPU, a second CPU and a baseboard management controller respectively connected with the main disk array controller, the spare disk array controller and the expansion chip, wherein the main disk array controller is set as a working disk array controller; the first uplink port of the expansion chip is connected to the main disk array controller, the second uplink port of the expansion chip is connected to the standby disk array controller, and the expansion chip is also connected with a plurality of hard disks, wherein the second uplink port is set to be in a closed state by default; the first CPU is connected to an uplink interface of the main disk array controller, and the second CPU is connected to an uplink interface of the spare disk array controller, wherein the uplink interface of the spare disk array controller is set to be in a disabled state by default; the baseboard management controller is used for closing the connection state of the uplink interfaces of the main disk array controller and the standby disk array controller and expanding the closing state of the first uplink port and the second uplink port of the chip when the main disk array controller fails so as to realize the switching of the working disk array controller from the main disk array controller to the standby disk array controller. The working state of the main disk array controller is detected through the timing cycle of the substrate management controller, when the main disk array controller fails, a command is issued to close the main disk array controller, an uplink port of an expansion chip connected with the disk array controller is switched to the standby disk array controller, and the standby disk array controller is opened, so that the server system re-detects the standby disk array controller and the storage device. The method realizes the effective switching of the disk array controller in the state of no shutdown, thereby ensuring that the data access of the server works normally and the upper layer service is not down; and the loss caused by service interruption when the disk array controller works abnormally is avoided.
Drawings
For a clearer description of the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a schematic diagram of a switching system architecture of a redundant array of inexpensive disks controller according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a switching method of a redundant array of inexpensive disks controller according to an embodiment of the present application;
FIG. 3 is a flowchart of a method for switching redundant array of inexpensive disks controller according to an embodiment of the present application;
fig. 4 is a block diagram of an electronic device according to an embodiment of the present application.
Description of the drawings the reference numerals: 1. a primary disk array controller; 2. a spare disk array controller; 3. expanding the chip; 4. a baseboard management controller; 5. complex editable logic devices; 6. a first CPU; 7. and a second CPU.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be understood that throughout this specification and the claims, unless the context clearly requires otherwise, the words "comprise", "comprising", and the like, are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".
It should also be appreciated that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
It should be noted that the terms "S1", "S2", and the like are used for the purpose of describing the steps only, and are not intended to be construed to be specific as to the order or sequence of steps, nor are they intended to limit the present application, which is merely used to facilitate the description of the method of the present application, and are not to be construed as indicating the sequence of steps. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present application.
As described in the background art, most of the existing servers only support a single disk array controller design, the disk array controller is directly connected with the CPU in the uplink direction, the disk array controller is connected with the backplane through an MCIOX8 or minissas connector in the downlink direction, and is communicated with the HDD Hard disk (Hard disk drive) through SAS (serial attached SCSI) signals, and transmits SGPIO (serial general-purpose-input/output) signals to the backplane CPLD (complex programmable logic device) to control the indicator lamp to display the read/write states of the HDD. Meanwhile, the BMC (Baseboard ManagementController ) is respectively connected to the RAID card and the hard disk backboard CPLD through a group of I2C, reads the asset information of the RAIDcontroller, and realizes the functions of logical disk parameter setting, RAID level setting, RAID state information display, hard disk positioning and the like. The design mode realizes the simple logic disk control access and the redundant backup function of the hard disk, but lacks the disk array controller redundancy of the disk controller, so that the disk array becomes a weak point in a server storage link, once the disk array controller is abnormally misplaced or damaged, the server needs to be closed to replace a problematic RAID card, and at the moment, service interruption can be caused, and unpredictable loss is caused.
Therefore, a set of redundant design of the disk array controller level is needed to be designed, when the disk array controller is abnormally reported to be wrong, the preparation state of the disk array controller and SGPIO signals are automatically switched, the redundant function of the disk array controller is realized, and the loss caused by service interruption due to the abnormal operation of the disk array controller is avoided.
Example 1
The embodiment of the application provides a switching system of a redundant array of inexpensive disks controller, and fig. 1 is a schematic diagram of the switching system of redundant array of inexpensive disks controller, the switching system of redundant array of inexpensive disks controller specifically comprises the following components:
the system comprises a main disk array controller 1, a spare disk array controller 2, an expansion chip 3, a first CPU6, a second CPU7 and a baseboard management controller 4 respectively connected with the main disk array controller 1, the spare disk array controller 2 and the expansion chip 3, wherein the main disk array controller 1 is set as a working disk array controller; the first uplink port of the expansion chip 3 is connected to the main disk array controller 1, the second uplink port of the expansion chip 3 is connected to the spare disk array controller 2, and the expansion chip 3 is also connected with a plurality of hard disks, wherein the second uplink port is set to be in a closed state by default; the first CPU6 is connected to the uplink interface of the main disk array controller 1, the second CPU7 is connected to the uplink interface of the spare disk array controller 2, and the uplink interface of the spare disk array controller 2 is set to be in a disabled state by default; the baseboard management controller 4 is used for closing the uplink interface of the main disk array controller 1 and enabling the uplink interface of the standby disk array controller 2 set to be in a disabled state when the main disk array controller 1 fails, and closing the first uplink port of the expansion chip 3 and opening the second uplink port of the expansion chip 3 so as to switch the working disk array controller from the main disk array controller to the standby disk array controller 2.
Further, the baseboard management controller 4 issues a first switching command to the main disk array controller 1 and the spare disk array controller 2, so that the main disk array controller 1 and the spare disk array controller 2 respectively modify states of a first register inside the main disk array controller 1 and a second register inside the spare disk array controller 2 to modify uplink interface states of the main disk array controller 1 and the spare disk array controller 2; the baseboard management controller 4 also issues a second switching command to the expansion chip 3, and after the expansion chip 3 receives the second switching command, the first uplink port is closed and the second uplink port of the expansion chip 3 is opened; to effect switching of the active disk array controller from the primary disk controller to the standby disk array controller 2.
Wherein, the connection mode of each part is: the baseboard management controller 4 is connected to the main disk array controller 1 through a first I2C bus, is connected to the spare disk array controller 2 through a second I2C bus, and is connected to the expansion chip 3 through a third I2C bus; the first CPU6 is connected to an uplink interface of the main disk array controller 1 through a first PCIE bus, and the second CPU7 is connected to the uplink interface of the main disk array controller 1 through a second PCIE bus; the baseboard management controller 4 is connected to the complex editable logic device 5 via a fourth I2C bus.
The redundant array controller switching system further comprises a complex editable logic device 5, the complex editable logic device 5 is respectively connected with the main array controller 1, the spare array controller 2 and the baseboard management controller 4, and depending on the complex editable logic device 5, the baseboard management controller 4 can switch the SGPIO signal line for controlling the state of the hard disk indicator lamp from the main array controller 1 to the spare array controller 2 when the main array controller 1 fails, specifically, the baseboard management controller 4 sends a third switching command to the complex programmable logic device, and after the complex programmable logic device receives the third switching command, the complex programmable logic device is realized by changing the state of a third register in the complex programmable logic device. After the error is reported by the main disk array controller 1, the spare disk array controller 2 is coupled with a control indicator lamp to display the read-write state (including the bit state, the read-write state, the reconstruction state, the dislocation state and the like) of the hard disk.
Example two
The embodiment of the application also provides a switching method of the redundant array controller, as shown in the flow chart of fig. 2, based on the switching system of the redundant array controller disclosed by the application, when the working main array controller fails, the switching of the spare array controller comprises the following steps:
S1, detecting whether a working main disk array controller fails or not by the baseboard management controller.
Specifically, in the method disclosed in this embodiment, the baseboard management controller detects the status information of the main disk array controller set as the working disk array controller at regular time, where the status information at least includes error reporting information, if the baseboard management controller detects that the status information includes error reporting information, the baseboard management controller determines that the main disk array controller fails, and if the baseboard management controller does not detect that the status information includes error reporting information, the baseboard management controller confirms that the Zhu Cipan array controller works normally.
S2, after the main disk array controller fails, the baseboard management controller switches the working disk array controller from the main disk controller to the standby disk array controller.
In the method disclosed by the embodiment of the application, a main disk array controller and a standby disk array controller are respectively connected to two CPUs of a multipath server, namely, the main disk array controller is connected to a first CPU, and the standby disk array controller is connected to a second CPU; under the default condition, the main disk array controller is set as a working disk array controller, and the uplink interface of the spare disk array controller is set as a disabled state, namely the main disk array controller which participates in the operation of the server at the moment is ensured, so that the connection state of the main disk array controller and the spare disk array controller is required to be changed when the main disk array controller and the spare disk array controller are switched. In addition, the main disk array controller and the standby disk array controller are respectively connected with the first uplink port and the second uplink port of the expansion chip, and under the default, the second uplink port of the expansion chip, which is connected with the standby disk array controller, is set to be in a closed state, and the first uplink port, which is connected with the main disk array controller, is set to be in an open state, so that the main disk array controller can control the hard disk. Therefore, when the baseboard management controller switches the working disk array controller from the main disk controller to the standby disk array controller, the connection state of the uplink interfaces of the main disk array controller and the standby disk array controller needs to be changed, and the closing state of the first uplink port and the second uplink port of the chip is expanded.
Specifically, the baseboard management controller issues a first switching command to the main disk array controller and the spare disk array controller through the I2C bus, and after the main disk array controller receives the first switching command, the state of a first register in the main disk array controller is modified to close an uplink interface of the main disk array controller. Specifically, an enabling signal bit corresponding to the uplink interface is set in a first register in the main disk array controller, and after a first switching command is received, the enabling signal bit originally set to be in an enabling state is set to zero, so that connection between the main disk array controller and the first CPU is stopped, namely, use of the main disk array controller is stopped. After receiving the first switching command, the spare disk array controller modifies the state of a second register in the main disk array controller to enable an uplink interface of the spare disk array controller which is set as a disabled state by default, specifically, an enabling signal bit corresponding to the uplink interface is set in the second register in the spare disk array controller, and an enabling signal which is set to be zero first is set as an enabling state after receiving the first switching command, so that the spare disk array controller is normally connected with a second CPU, namely the spare disk array controller is enabled; the baseboard management controller also issues a second switching command to the expansion chip through the I2C bus, and after the expansion chip receives the second switching signal, the first uplink port is closed and the second uplink port of the expansion chip is opened. At this time, the disk array controller participating in the operation is replaced with the spare disk array controller from the main disk array controller.
S3, after the main disk array controller fails, the baseboard management controller switches the SGPIO signal line for controlling the state of the hard disk indicator lamp from the main disk array controller to the standby disk array controller.
Specifically, after the baseboard management controller detects that the main disk array controller fails, a third switching command is issued to a complex programmable logic device through an I2C bus, and the complex programmable logic device is connected with the main disk array controller through a first interface and is connected with the spare disk array controller through a second interface; after the complex programmable logic device receives the third switching command, changing the state of a third register in the complex programmable logic device to realize switching of an SGPIO signal line for controlling the state of the hard disk indicator lamp from the main disk array controller to the standby disk array controller: setting an enabling signal bit corresponding to the first interface and the second interface in a third register in the complex programmable logic device, setting the enabling signal bit corresponding to the first interface in an enabling state after receiving a third switching command, and setting the enabling signal bit corresponding to the second interface in the enabling state after the enabling signal bit is set to zero. After switching, the complex programmable logic device analyzes SGPIO signals of the spare disk array controller and lights up and displays the working state of the hard disk.
S4, after the working disk array controller is switched from the main disk controller to the spare disk array controller, the operating system detects the spare disk controller and a plurality of hard disks connected with the spare disk controller through the expansion chip so as to ensure that the spare disk array controller works normally.
According to the switching method of the redundant disk array controller, the working state of the main disk array controller is periodically detected through the substrate management controller, when the main disk array controller fails, a command is issued to close the main disk array controller, an uplink port of an expansion chip connected with the disk array controller is switched to the spare disk array controller, the spare disk array controller is started, and the spare disk array controller and the storage equipment are re-detected by the server system. The method realizes the effective switching of the disk array controller in the state of no shutdown, thereby ensuring that the data access of the server works normally and the upper layer service is not down.
In addition, the embodiment of the application also provides a testing method, which specifically comprises the following steps: the redundant disk array controller switching system provided in the first embodiment is built in a test prototype, and comprises a main board, a back board, BMC firmware, a complex programmable logic device and the like; after the server is started, logging in a BMC management control interface; based on the BMC, checking the working state of the disk array controller working in the current server (namely the main disk array controller), and displaying that the main disk array controller works normally and the standby disk array controller does not work at the moment; closing the server and replacing the main disk array controller with a fault disk array controller with faults; starting the server again after replacement and logging in the BMC management control interface; and checking the working state of the disk array controller in the current server, and if the main disk array controller reports errors and the standby disk array controller is in the working state, constructing a redundant disk array controller switching system and normally using the redundant disk array controller switching system.
Example III
Corresponding to the second embodiment, the embodiment of the present application further provides a redundant array controller switching method, as shown in fig. 3, which specifically includes the following steps:
310. the baseboard management controller detects whether the main disk array controller set as the working disk array controller fails or not at regular time;
320. if the main disk array controller fails, the baseboard management controller changes the connection state of the uplink interfaces of the main disk array controller and the spare disk array controller and expands the closing state of the first uplink port and the second uplink port of the chip so as to realize the switching of the working disk array controller from the main disk array controller to the spare disk array controller.
Preferably, the baseboard management controller changes a connection state of an uplink interface of the main disk array controller and the spare disk array controller and expands a closing state of a first uplink port and a second uplink port of the chip, including:
321. the baseboard management controller transmits a first switching signal to the main disk array controller and the standby disk array controller, and transmits a second switching signal to the expansion chip;
322. after the main disk array controller receives the first switching signal, modifying the state of a first register in the main disk array controller to close an uplink interface of the main disk array controller;
323. After the spare disk array controller receives the first switching signal, modifying the state of a second register in the main disk array controller to enable an uplink interface of the spare disk array controller which is set to be in a disabled state by default;
324. and after the expansion chip receives the second switching signal, closing the first uplink port and opening the second uplink port of the expansion chip.
Preferably, the method further comprises:
330. when the main disk array controller fails, the baseboard management controller issues a third switching command to the complex programmable logic device;
340. and after the complex programmable logic device receives the third switching command, changing the state of a third register in the complex programmable logic device to realize switching of an SGPIO signal line for controlling the state of the hard disk indicator lamp from the main disk array controller to the standby disk array controller.
Preferably, the method further comprises:
350. after the working disk array controller is switched from the main disk controller to the spare disk array controller, the operating system detects the spare disk controller and a plurality of hard disks connected with the spare disk array controller through the expansion chip so as to ensure that the spare disk array controller works normally.
Example IV
Corresponding to all the embodiments described above, an embodiment of the present application provides an electronic device, including:
one or more processors; and a memory associated with the one or more processors, the memory for storing program instructions that, when read for execution by the one or more processors, perform the following:
the baseboard management controller detects whether the main disk array controller set as the working disk array controller fails or not at regular time;
if the main disk array controller fails, the baseboard management controller changes the connection state of the uplink interfaces of the main disk array controller and the spare disk array controller and expands the closing state of the first uplink port and the second uplink port of the chip so as to realize the switching of the working disk array controller from the main disk array controller to the spare disk array controller.
In some implementations, the following operations are also performed:
the baseboard management controller transmits a first switching signal to the main disk array controller and the standby disk array controller, and transmits a second switching signal to the expansion chip;
after the main disk array controller receives the first switching signal, modifying the state of a first register in the main disk array controller to close an uplink interface of the main disk array controller;
After the spare disk array controller receives the first switching signal, modifying the state of a second register in the main disk array controller to enable an uplink interface of the spare disk array controller which is set to be in a disabled state by default;
and after the expansion chip receives the second switching signal, closing the first uplink port and opening the second uplink port of the expansion chip.
In some implementations, the following operations are also performed:
when the main disk array controller fails, the baseboard management controller issues a third switching command to the complex programmable logic device;
and after the complex programmable logic device receives the third switching command, changing the state of a third register in the complex programmable logic device to realize switching of an SGPIO signal line for controlling the state of the hard disk indicator lamp from the main disk array controller to the standby disk array controller.
In some implementations, the following operations are also performed:
after the working disk array controller is switched from the main disk controller to the spare disk array controller, the operating system detects the spare disk controller and a plurality of hard disks connected with the spare disk array controller through the expansion chip so as to ensure that the spare disk array controller works normally.
Fig. 4 illustrates an architecture of an electronic device, which may include a processor 410, a video display adapter 411, a disk drive 412, an input/output interface 413, a network interface 414, and a memory 420, among others. The processor 410, video display adapter 411, disk drive 412, input/output interface 413, network interface 414, and memory 420 may be communicatively coupled via bus 430.
The processor 410 may be implemented by a general-purpose CPU (central processing unit), a microprocessor, an application-specific integrated circuit (ApplicationSpecificIntegratedCircuit, ASIC), or one or more integrated circuits, etc. for executing related programs to implement the technical solution provided by the present application.
The memory 420 may be implemented in the form of ROM (read only memory), RAM (random access memory), a static storage device, a dynamic storage device, or the like. The memory 420 may store an operating system 421 for controlling the execution of the electronic device 400, and a Basic Input Output System (BIOS) 422 for controlling the low-level operation of the electronic device 400. In addition, a web browser 423, a data storage management system 424, an icon font processing system 425, and the like may also be stored. The icon font processing system 425 may be an application program that implements the operations of the foregoing steps in embodiments of the present application. In general, when the technical solution provided by the present application is implemented by software or firmware, relevant program codes are stored in the memory 420 and invoked by the processor 410 for execution.
The input/output interface 413 is used to connect to an input/output module to realize information input and output. The input/output module may be configured as a component in a device (not shown) or may be external to the device to provide corresponding functionality. Wherein the input devices may include a keyboard, mouse, touch screen, microphone, various types of sensors, etc., and the output devices may include a display, speaker, vibrator, indicator lights, etc.
The network interface 414 is used to connect communication modules (not shown) to enable communication interactions of the device with other devices. The communication module may implement communication through a wired manner (such as USB, network cable, etc.), or may implement communication through a wireless manner (such as mobile network, WIFI, bluetooth, etc.).
Bus 430 includes a path to transfer information between various components of the device (e.g., processor 410, video display adapter 411, disk drive 412, input/output interface 413, network interface 414, and memory 420).
In addition, the electronic device 400 may also obtain information of specific acquisition conditions from the virtual resource object acquisition condition information database, for performing condition judgment, and so on.
It should be noted that although the above devices only show the processor 410, the video display adapter 411, the disk drive 412, the input/output interface 413, the network interface 414, the memory 420, the bus 430, and the like, in the specific implementation, the device may further include other components necessary to achieve normal execution. Furthermore, it will be appreciated by those skilled in the art that the apparatus may include only the components necessary to implement the present application, and not all of the components shown in the drawings.
From the above description of embodiments, it will be apparent to those skilled in the art that the present application may be implemented in software plus a necessary general hardware platform. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., and includes several instructions for causing a computer device (which may be a personal computer, a cloud server, or a network device, etc.) to execute the method described in the embodiments or some parts of the embodiments of the present application.
Example five
Corresponding to all the above embodiments, the embodiments of the present application further provide a computer-readable storage medium, characterized in that it stores a computer program that causes a computer to perform the operations of:
the baseboard management controller detects whether the main disk array controller set as the working disk array controller fails or not at regular time;
if the main disk array controller fails, the baseboard management controller changes the connection state of the uplink interfaces of the main disk array controller and the spare disk array controller and expands the closing state of the first uplink port and the second uplink port of the chip so as to realize the switching of the working disk array controller from the main disk array controller to the spare disk array controller.
In some embodiments, the computer program causes the computer to further perform the following:
the baseboard management controller transmits a first switching signal to the main disk array controller and the standby disk array controller, and transmits a second switching signal to the expansion chip;
after the main disk array controller receives the first switching signal, modifying the state of a first register in the main disk array controller to close an uplink interface of the main disk array controller;
after the spare disk array controller receives the first switching signal, modifying the state of a second register in the main disk array controller to enable an uplink interface of the spare disk array controller which is set to be in a disabled state by default;
and after the expansion chip receives the second switching signal, closing the first uplink port and opening the second uplink port of the expansion chip.
In some embodiments, the computer program causes the computer to further perform the following:
when the main disk array controller fails, the baseboard management controller issues a third switching command to the complex programmable logic device;
and after the complex programmable logic device receives the third switching command, changing the state of a third register in the complex programmable logic device to realize switching of an SGPIO signal line for controlling the state of the hard disk indicator lamp from the main disk array controller to the standby disk array controller.
In some embodiments, the computer program causes the computer to further perform the following:
after the working disk array controller is switched from the main disk controller to the spare disk array controller, the operating system detects the spare disk controller and a plurality of hard disks connected with the spare disk array controller through the expansion chip so as to ensure that the spare disk array controller works normally.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for a system or system embodiment, since it is substantially similar to a method embodiment, the description is relatively simple, with reference to the description of the method embodiment being made in part. The systems and system embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The foregoing description of the preferred embodiments of the application is not intended to limit the application to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the application are intended to be included within the scope of the application.
Claims (10)
1. A redundant array of disk controller switching system, the system comprising: the system comprises a main disk array controller, a standby disk array controller, an expansion chip, a first CPU, a second CPU and a baseboard management controller which are respectively connected with the main disk array controller, the standby disk array controller and the expansion chip, wherein the main disk array controller is set as a working disk array controller;
the first uplink port of the expansion chip is connected to the main disk array controller, the second uplink port of the expansion chip is connected to the standby disk array controller, and the expansion chip is also connected with a plurality of hard disks, wherein the second uplink port is set to be in a closed state by default;
the first CPU is connected to an uplink interface of the main disk array controller, and the second CPU is connected to an uplink interface of the spare disk array controller, wherein the uplink interface of the spare disk array controller is set to be in a disabled state by default;
The baseboard management controller is used for closing the connection state of the uplink interfaces of the main disk array controller and the standby disk array controller and expanding the closing state of the first uplink port and the second uplink port of the chip when the main disk array controller fails so as to realize the switching of the working disk array controller from the main disk array controller to the standby disk array controller.
2. The system of claim 1, wherein the system further comprises:
and the complex programmable logic device is connected with the main disk array controller, the standby disk array controller and the baseboard management controller and is used for realizing that the baseboard management controller switches the SGPIO signal line for controlling the state of the hard disk indicator lamp from the main disk array controller to the standby disk array controller when the main disk array controller fails.
3. The system according to claim 1 or 2, wherein,
the baseboard management controller is connected to the main disk array controller through a first I2C bus, is connected to the standby disk array controller through a second I2C bus and is connected to the expansion chip through a third I2C bus;
The first CPU is connected to the uplink interface of the main disk array controller through a first PCIE bus, and the second CPU is connected to the uplink interface of the main disk array controller through a second PCIE bus.
4. The system of claim 2, wherein the baseboard management controller is connected to the complex programmable logic device through a fourth I2C bus.
5. A redundant array of independent disks controller switching method based on the redundant array of independent disks controller switching system of claim 1, the method comprising:
the baseboard management controller detects whether the main disk array controller set as the working disk array controller fails or not at regular time;
if the main disk array controller fails, the baseboard management controller changes the connection state of the uplink interfaces of the main disk array controller and the spare disk array controller and expands the closing state of the first uplink port and the second uplink port of the chip so as to realize the switching of the working disk array controller from the main disk array controller to the spare disk array controller.
6. The method of claim 5, wherein the baseboard management controller changing the connection state of the upstream interfaces of the main disk array controller and the spare disk array controller and expanding the closed state of the first upstream port and the second upstream port of the chip comprises:
The baseboard management controller transmits a first switching signal to the main disk array controller and the standby disk array controller, and transmits a second switching signal to the expansion chip;
after the main disk array controller receives the first switching signal, modifying the state of a first register in the main disk array controller to close an uplink interface of the main disk array controller;
after the spare disk array controller receives the first switching signal, modifying the state of a second register in the main disk array controller to enable an uplink interface of the spare disk array controller which is set to be in a disabled state by default;
and after the expansion chip receives the second switching signal, closing the first uplink port and opening the second uplink port of the expansion chip.
7. The method of claim 5, wherein the method further comprises:
when the main disk array controller fails, the baseboard management controller issues a third switching command to the complex programmable logic device;
and after the complex programmable logic device receives the third switching command, changing the state of a third register in the complex programmable logic device to realize switching of an SGPIO signal line for controlling the state of the hard disk indicator lamp from the main disk array controller to the standby disk array controller.
8. The method of claim 5, wherein the method further comprises:
after the working disk array controller is switched from the main disk controller to the spare disk array controller, the operating system detects the spare disk controller and a plurality of hard disks connected with the spare disk array controller through the expansion chip so as to ensure that the spare disk array controller works normally.
9. An electronic device, the electronic device comprising:
one or more processors;
and a memory associated with the one or more processors, the memory for storing program instructions that, when read for execution by the one or more processors, perform the method of any of claims 5-8.
10. A computer-readable storage medium, characterized in that it stores a computer program, which causes a computer to perform the method of any one of claims 5-8.
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| CN202310568894.3A CN116679875A (en) | 2023-05-19 | 2023-05-19 | Redundant disk array controller switching system, method, electronic device and medium |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310568894.3A CN116679875A (en) | 2023-05-19 | 2023-05-19 | Redundant disk array controller switching system, method, electronic device and medium |
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